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You searched for subject:(traverse time). Showing records 1 – 2 of 2 total matches.

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Queensland University of Technology

1. Mat Isa, Zaiton. Mathematical modelling of fumigant transport in stored grain.

Degree: 2014, Queensland University of Technology

Computational fluid dynamics, analytical solutions, and mathematical modelling approaches are used to gain insights into the distribution of fumigant gas within farm-scale, grain storage silos. Both fan-forced and tablet fumigation are considered in this work, which develops new models for use by researchers, primary producers and silo manufacturers to assist in the eradication grain storage pests.

Subjects/Keywords: porous media; Darcy's Law; Laplace equation; mathematical modelling; fumigation; computational fluid dynamics; phosphine; grain storage; traverse time; silo

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mat Isa, Z. (2014). Mathematical modelling of fumigant transport in stored grain. (Thesis). Queensland University of Technology. Retrieved from https://eprints.qut.edu.au/75420/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mat Isa, Zaiton. “Mathematical modelling of fumigant transport in stored grain.” 2014. Thesis, Queensland University of Technology. Accessed July 23, 2019. https://eprints.qut.edu.au/75420/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mat Isa, Zaiton. “Mathematical modelling of fumigant transport in stored grain.” 2014. Web. 23 Jul 2019.

Vancouver:

Mat Isa Z. Mathematical modelling of fumigant transport in stored grain. [Internet] [Thesis]. Queensland University of Technology; 2014. [cited 2019 Jul 23]. Available from: https://eprints.qut.edu.au/75420/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mat Isa Z. Mathematical modelling of fumigant transport in stored grain. [Thesis]. Queensland University of Technology; 2014. Available from: https://eprints.qut.edu.au/75420/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Tech

2. Drayer, Thomas Hudson. A Design Methodology for Creating Programmable Logic-based Real-time Image Processing Hardware.

Degree: PhD, Electrical and Computer Engineering, 1997, Virginia Tech

A new design methodology that produces hardware solutions for performing real-time image processing is presented here. This design methodology provides significant advantages over traditional hardware design approaches by translating real-time image processing tasks into the gate-level resources of programmable logic-based hardware architectures. The use of programmable logic allows high-performance solutions to be realized with very efficient utilization of available logic and interconnection resources. These implementations provide comparable performance at a lower cost than other available programmable logic-based hardware architectures. This new design methodology is based on two components: a programmable logic-based destination hardware architecture and a suite of development system software. The destination hardware architecture is a Custom Computing Machine (CCM) that contains multiple Field Programmable Gate Array (FPGA) chips. FPGA chips provide gate-level programmability for the hardware architecture. Sophisticated software development tools, called the TRAVERSE development system software, are created to overcome the significant amount of time and expertise required to manually utilize this gate-level programmability. The new hardware architecture and development system software combine to establish a unique design methodology. There are several distinct contributions provided by this dissertation. The new flexible MORRPH hardware architecture provides a more efficient solution for creating real-time image processing computing machines than current commercial hardware architectures. The TRAVERSE development system software is the first integrated development system specifically for creating real-time image processing designs with multiple FPGA-based CCMs. New standards and design conventions are defined specifically for creating solutions to low-level image processing tasks, using the MORRPH architecture for verification. The circuit partitioning and global routing programs of the TRAVERSE development system software enable automated translation of image processing designs into the resources of multiple FPGA chips in the hardware architecture. In a broad sense, the individual contributions of this dissertation combine to create a new design methodology that will change the way hardware solutions are created for real-time image processing in the future. Advisors/Committee Members: Tront, Joseph G. (committeechair), Abbott, A. Lynn (committee member), Kline, D. Earl (committee member), Nunnally, Charles E. (committee member), Conners, Richard W. (committeecochair).

Subjects/Keywords: real-time image processing; FPGA-based computing; design methodology; reconfigurable computing; MORRPH; TRAVERSE; LD5655.V856 1997.D739

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Drayer, T. H. (1997). A Design Methodology for Creating Programmable Logic-based Real-time Image Processing Hardware. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/30619

Chicago Manual of Style (16th Edition):

Drayer, Thomas Hudson. “A Design Methodology for Creating Programmable Logic-based Real-time Image Processing Hardware.” 1997. Doctoral Dissertation, Virginia Tech. Accessed July 23, 2019. http://hdl.handle.net/10919/30619.

MLA Handbook (7th Edition):

Drayer, Thomas Hudson. “A Design Methodology for Creating Programmable Logic-based Real-time Image Processing Hardware.” 1997. Web. 23 Jul 2019.

Vancouver:

Drayer TH. A Design Methodology for Creating Programmable Logic-based Real-time Image Processing Hardware. [Internet] [Doctoral dissertation]. Virginia Tech; 1997. [cited 2019 Jul 23]. Available from: http://hdl.handle.net/10919/30619.

Council of Science Editors:

Drayer TH. A Design Methodology for Creating Programmable Logic-based Real-time Image Processing Hardware. [Doctoral Dissertation]. Virginia Tech; 1997. Available from: http://hdl.handle.net/10919/30619

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