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You searched for subject:(threshold voltage). Showing records 1 – 30 of 77 total matches.

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University of Illinois – Urbana-Champaign

1. Min, David. Synthesis constraint optimization for near-threshold voltage design.

Degree: MS, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 Near-threshold voltage (NTV) design is a viable solution to many embedded systems which require high energy efficiencies and low performances, but it makes them vulnerable… (more)

Subjects/Keywords: Near-threshold voltage; Low-energy; Embedded systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Min, D. (2017). Synthesis constraint optimization for near-threshold voltage design. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/97551

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Min, David. “Synthesis constraint optimization for near-threshold voltage design.” 2017. Thesis, University of Illinois – Urbana-Champaign. Accessed August 08, 2020. http://hdl.handle.net/2142/97551.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Min, David. “Synthesis constraint optimization for near-threshold voltage design.” 2017. Web. 08 Aug 2020.

Vancouver:

Min D. Synthesis constraint optimization for near-threshold voltage design. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2017. [cited 2020 Aug 08]. Available from: http://hdl.handle.net/2142/97551.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Min D. Synthesis constraint optimization for near-threshold voltage design. [Thesis]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/97551

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

2. Scaff, Robson. Caracterização elétrica de dispositivos tipo ISFET com estrutura Si/SiO2/Si3N4 para medição de pH utilizando pseudoeletrodos de Pt, Ag e Au.

Degree: Mestrado, Microeletrônica, 2008, University of São Paulo

Neste trabalho, foi realizado um estudo da caracterização elétrica dos ISFETs com estrutura Si/SiO2/Si3N4, utilizando pseudoeletrodos de Pt, Ag e Au como alternativas aos eletrodos… (more)

Subjects/Keywords: Circuitos integrados MOS; Eletroquímica; ISFET; Microeletrônica; pH; Pseudoelectrode; Si3N4; Threshold voltage

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APA (6th Edition):

Scaff, R. (2008). Caracterização elétrica de dispositivos tipo ISFET com estrutura Si/SiO2/Si3N4 para medição de pH utilizando pseudoeletrodos de Pt, Ag e Au. (Masters Thesis). University of São Paulo. Retrieved from http://www.teses.usp.br/teses/disponiveis/3/3140/tde-01102008-142910/ ;

Chicago Manual of Style (16th Edition):

Scaff, Robson. “Caracterização elétrica de dispositivos tipo ISFET com estrutura Si/SiO2/Si3N4 para medição de pH utilizando pseudoeletrodos de Pt, Ag e Au.” 2008. Masters Thesis, University of São Paulo. Accessed August 08, 2020. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-01102008-142910/ ;.

MLA Handbook (7th Edition):

Scaff, Robson. “Caracterização elétrica de dispositivos tipo ISFET com estrutura Si/SiO2/Si3N4 para medição de pH utilizando pseudoeletrodos de Pt, Ag e Au.” 2008. Web. 08 Aug 2020.

Vancouver:

Scaff R. Caracterização elétrica de dispositivos tipo ISFET com estrutura Si/SiO2/Si3N4 para medição de pH utilizando pseudoeletrodos de Pt, Ag e Au. [Internet] [Masters thesis]. University of São Paulo; 2008. [cited 2020 Aug 08]. Available from: http://www.teses.usp.br/teses/disponiveis/3/3140/tde-01102008-142910/ ;.

Council of Science Editors:

Scaff R. Caracterização elétrica de dispositivos tipo ISFET com estrutura Si/SiO2/Si3N4 para medição de pH utilizando pseudoeletrodos de Pt, Ag e Au. [Masters Thesis]. University of São Paulo; 2008. Available from: http://www.teses.usp.br/teses/disponiveis/3/3140/tde-01102008-142910/ ;


Universidade do Rio Grande do Sul

3. Stangherlin, Kleber Hugo. Energy and speed exploration in digital CMOS circuits in the near-threshold regime for very-wide voltage-frequency scaling.

Degree: 2013, Universidade do Rio Grande do Sul

This thesis assesses the benefits and drawbacks associated with a very wide range of frequency when operation at near-threshold is considered. Scaling down the supply… (more)

Subjects/Keywords: Voltage-frequency scaling; Microeletrônica; Energy-efficiency; Cmos; Power savings; Near-threshold

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APA (6th Edition):

Stangherlin, K. H. (2013). Energy and speed exploration in digital CMOS circuits in the near-threshold regime for very-wide voltage-frequency scaling. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/96974

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Stangherlin, Kleber Hugo. “Energy and speed exploration in digital CMOS circuits in the near-threshold regime for very-wide voltage-frequency scaling.” 2013. Thesis, Universidade do Rio Grande do Sul. Accessed August 08, 2020. http://hdl.handle.net/10183/96974.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Stangherlin, Kleber Hugo. “Energy and speed exploration in digital CMOS circuits in the near-threshold regime for very-wide voltage-frequency scaling.” 2013. Web. 08 Aug 2020.

Vancouver:

Stangherlin KH. Energy and speed exploration in digital CMOS circuits in the near-threshold regime for very-wide voltage-frequency scaling. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2013. [cited 2020 Aug 08]. Available from: http://hdl.handle.net/10183/96974.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Stangherlin KH. Energy and speed exploration in digital CMOS circuits in the near-threshold regime for very-wide voltage-frequency scaling. [Thesis]. Universidade do Rio Grande do Sul; 2013. Available from: http://hdl.handle.net/10183/96974

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

4. Tseng, Hsin-Yuan. Mixed-Voltage Output Buffers with Slew Rate Compensation Based on PVT Variation Detection.

Degree: Master, Electrical Engineering, 2012, NSYSU

 This thesis is composed of two designs: a PT (process, temperature) detector for 2ÃVDD output buffer with slew rate compensation, and a slew rate self-adjusting… (more)

Subjects/Keywords: PVT compensation; slew rate; output buffer; 2ÃVDD; threshold voltage

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APA (6th Edition):

Tseng, H. (2012). Mixed-Voltage Output Buffers with Slew Rate Compensation Based on PVT Variation Detection. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0710112-144122

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tseng, Hsin-Yuan. “Mixed-Voltage Output Buffers with Slew Rate Compensation Based on PVT Variation Detection.” 2012. Thesis, NSYSU. Accessed August 08, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0710112-144122.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tseng, Hsin-Yuan. “Mixed-Voltage Output Buffers with Slew Rate Compensation Based on PVT Variation Detection.” 2012. Web. 08 Aug 2020.

Vancouver:

Tseng H. Mixed-Voltage Output Buffers with Slew Rate Compensation Based on PVT Variation Detection. [Internet] [Thesis]. NSYSU; 2012. [cited 2020 Aug 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0710112-144122.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tseng H. Mixed-Voltage Output Buffers with Slew Rate Compensation Based on PVT Variation Detection. [Thesis]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0710112-144122

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Texas – Austin

5. Arora, Manisha. Analog model parameter extraction-circuits for process monitoring.

Degree: MSin Engineering, Electrical and Computer Engineering, 2019, University of Texas – Austin

 A method for extracting the three parameters of the well-known level-2 Spice MOSFET-model namely threshold voltage, transconductance parameter, and channel length modulation is presented. Currently… (more)

Subjects/Keywords: Model parameter; MOSFET; Threshold voltage; Channel length modulation

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APA (6th Edition):

Arora, M. (2019). Analog model parameter extraction-circuits for process monitoring. (Masters Thesis). University of Texas – Austin. Retrieved from http://dx.doi.org/10.26153/tsw/8928

Chicago Manual of Style (16th Edition):

Arora, Manisha. “Analog model parameter extraction-circuits for process monitoring.” 2019. Masters Thesis, University of Texas – Austin. Accessed August 08, 2020. http://dx.doi.org/10.26153/tsw/8928.

MLA Handbook (7th Edition):

Arora, Manisha. “Analog model parameter extraction-circuits for process monitoring.” 2019. Web. 08 Aug 2020.

Vancouver:

Arora M. Analog model parameter extraction-circuits for process monitoring. [Internet] [Masters thesis]. University of Texas – Austin; 2019. [cited 2020 Aug 08]. Available from: http://dx.doi.org/10.26153/tsw/8928.

Council of Science Editors:

Arora M. Analog model parameter extraction-circuits for process monitoring. [Masters Thesis]. University of Texas – Austin; 2019. Available from: http://dx.doi.org/10.26153/tsw/8928


Universidade do Rio Grande do Sul

6. Caicedo, Jhon Alexander Gomez. CMOS low-power threshold voltage monitors circuits and applications.

Degree: 2016, Universidade do Rio Grande do Sul

A threshold voltage (VT0) monitor is a circuit that ideally delivers the estimated VT0 value as a voltage at its output, for a given temperature… (more)

Subjects/Keywords: Microeletrônica; Threshold voltage; CMOS analog design; Cmos; Threshold voltage monitor circuit; Microeletrônica; High-PSRR; Resistorless; Ultra-low-power; Voltage reference; Process compensation

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APA (6th Edition):

Caicedo, J. A. G. (2016). CMOS low-power threshold voltage monitors circuits and applications. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/144080

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Caicedo, Jhon Alexander Gomez. “CMOS low-power threshold voltage monitors circuits and applications.” 2016. Thesis, Universidade do Rio Grande do Sul. Accessed August 08, 2020. http://hdl.handle.net/10183/144080.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Caicedo, Jhon Alexander Gomez. “CMOS low-power threshold voltage monitors circuits and applications.” 2016. Web. 08 Aug 2020.

Vancouver:

Caicedo JAG. CMOS low-power threshold voltage monitors circuits and applications. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2016. [cited 2020 Aug 08]. Available from: http://hdl.handle.net/10183/144080.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Caicedo JAG. CMOS low-power threshold voltage monitors circuits and applications. [Thesis]. Universidade do Rio Grande do Sul; 2016. Available from: http://hdl.handle.net/10183/144080

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


UCLA

7. Conos, Nathaniel Alcala. Energy Minimization under Uncertainty using Coordinated Multi-phase Synthesis Techniques.

Degree: Computer Science, 2014, UCLA

 Energy minimization is one of the premiere design objectives in modern inte-grated circuits (ICs). Currently, there is a pressing need to reduce energy con-sumption in… (more)

Subjects/Keywords: Computer science; Computer engineering; Dynamic Voltage Scaling; Energy Minimization; Gate Sizing; Integrated Circuit Synthesis; Power Gating; Threshold Voltage Selection

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APA (6th Edition):

Conos, N. A. (2014). Energy Minimization under Uncertainty using Coordinated Multi-phase Synthesis Techniques. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/0m13d0wq

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Conos, Nathaniel Alcala. “Energy Minimization under Uncertainty using Coordinated Multi-phase Synthesis Techniques.” 2014. Thesis, UCLA. Accessed August 08, 2020. http://www.escholarship.org/uc/item/0m13d0wq.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Conos, Nathaniel Alcala. “Energy Minimization under Uncertainty using Coordinated Multi-phase Synthesis Techniques.” 2014. Web. 08 Aug 2020.

Vancouver:

Conos NA. Energy Minimization under Uncertainty using Coordinated Multi-phase Synthesis Techniques. [Internet] [Thesis]. UCLA; 2014. [cited 2020 Aug 08]. Available from: http://www.escholarship.org/uc/item/0m13d0wq.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Conos NA. Energy Minimization under Uncertainty using Coordinated Multi-phase Synthesis Techniques. [Thesis]. UCLA; 2014. Available from: http://www.escholarship.org/uc/item/0m13d0wq

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

8. Colombo, Dalton Martini. Design of analog integrated circuits aiming characterization of radiation and noise.

Degree: 2015, Universidade do Rio Grande do Sul

This thesis is focused on two challenges faced by analog integrated circuit designers when predicting the reliability of transistors implemented in modern CMOS processes: radiation… (more)

Subjects/Keywords: Microeletrônica; Flicker noise; Radiação; RTS noise; Circuitos integrados; Radiation; Total dose effects; Voltage reference; Oscillators; LC-tank; Bandgap; Threshold voltage

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APA (6th Edition):

Colombo, D. M. (2015). Design of analog integrated circuits aiming characterization of radiation and noise. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/133731

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Colombo, Dalton Martini. “Design of analog integrated circuits aiming characterization of radiation and noise.” 2015. Thesis, Universidade do Rio Grande do Sul. Accessed August 08, 2020. http://hdl.handle.net/10183/133731.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Colombo, Dalton Martini. “Design of analog integrated circuits aiming characterization of radiation and noise.” 2015. Web. 08 Aug 2020.

Vancouver:

Colombo DM. Design of analog integrated circuits aiming characterization of radiation and noise. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2015. [cited 2020 Aug 08]. Available from: http://hdl.handle.net/10183/133731.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Colombo DM. Design of analog integrated circuits aiming characterization of radiation and noise. [Thesis]. Universidade do Rio Grande do Sul; 2015. Available from: http://hdl.handle.net/10183/133731

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

9. Lin, Kun-Yao. Investigation of the Hot Carrier and Self-Heating Effects in InGaZnO Thin Film Transistor with U- and I-shaped structure for Advanced Displays.

Degree: Master, Physics, 2014, NSYSU

 In the first section, we investigate the hot-carrier effect in indiumâgalliumâzinc oxide (IGZO) thin film transistors with symmetric and asymmetric source/drain structures. The different degradation… (more)

Subjects/Keywords: Threshold voltage; charge trapping; Thin Film Transistors; Hot Carrier Effect; InGaZnO; Self-Heating Effect; kick back voltage

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APA (6th Edition):

Lin, K. (2014). Investigation of the Hot Carrier and Self-Heating Effects in InGaZnO Thin Film Transistor with U- and I-shaped structure for Advanced Displays. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0518114-165953

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Kun-Yao. “Investigation of the Hot Carrier and Self-Heating Effects in InGaZnO Thin Film Transistor with U- and I-shaped structure for Advanced Displays.” 2014. Thesis, NSYSU. Accessed August 08, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0518114-165953.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Kun-Yao. “Investigation of the Hot Carrier and Self-Heating Effects in InGaZnO Thin Film Transistor with U- and I-shaped structure for Advanced Displays.” 2014. Web. 08 Aug 2020.

Vancouver:

Lin K. Investigation of the Hot Carrier and Self-Heating Effects in InGaZnO Thin Film Transistor with U- and I-shaped structure for Advanced Displays. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Aug 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0518114-165953.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin K. Investigation of the Hot Carrier and Self-Heating Effects in InGaZnO Thin Film Transistor with U- and I-shaped structure for Advanced Displays. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0518114-165953

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

10. Lin, Chung-Ming. Fundamental Studies on Electrical Pitting Mechanism of Lubricated Metal Surface.

Degree: PhD, Mechanical and Electro-Mechanical Engineering, 2003, NSYSU

 Abstract The electrical pitting often occurs at the bearing of the ro-tating machinery due to the actions of the shaft voltage and the shaft current… (more)

Subjects/Keywords: threshold voltage; shaft current; shaft voltage; electrical pitting; MoS2

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APA (6th Edition):

Lin, C. (2003). Fundamental Studies on Electrical Pitting Mechanism of Lubricated Metal Surface. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725103-095936

Chicago Manual of Style (16th Edition):

Lin, Chung-Ming. “Fundamental Studies on Electrical Pitting Mechanism of Lubricated Metal Surface.” 2003. Doctoral Dissertation, NSYSU. Accessed August 08, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725103-095936.

MLA Handbook (7th Edition):

Lin, Chung-Ming. “Fundamental Studies on Electrical Pitting Mechanism of Lubricated Metal Surface.” 2003. Web. 08 Aug 2020.

Vancouver:

Lin C. Fundamental Studies on Electrical Pitting Mechanism of Lubricated Metal Surface. [Internet] [Doctoral dissertation]. NSYSU; 2003. [cited 2020 Aug 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725103-095936.

Council of Science Editors:

Lin C. Fundamental Studies on Electrical Pitting Mechanism of Lubricated Metal Surface. [Doctoral Dissertation]. NSYSU; 2003. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725103-095936


NSYSU

11. Hung, Pei-Hua. Investigation of Gate Bias Stress-induced Instability and High Sputter Rate SiAl-based Passivation Layer Applied to Amorphous InGaZnO Thin-Film Transistors.

Degree: Master, Electro-Optical Engineering, 2015, NSYSU

 Thin film transistors (TFTs) based on amorphous InGaZn oxide (a-IGZO) have been studied extensively for potential application in next-generation flat-panel displays. Although a-IGZO TFTs exhibit… (more)

Subjects/Keywords: Charge trapping; InGaZnO; Thin Film Transistors; Gate bias stress; Threshold voltage; Hydrolysis effect

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APA (6th Edition):

Hung, P. (2015). Investigation of Gate Bias Stress-induced Instability and High Sputter Rate SiAl-based Passivation Layer Applied to Amorphous InGaZnO Thin-Film Transistors. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623115-160429

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hung, Pei-Hua. “Investigation of Gate Bias Stress-induced Instability and High Sputter Rate SiAl-based Passivation Layer Applied to Amorphous InGaZnO Thin-Film Transistors.” 2015. Thesis, NSYSU. Accessed August 08, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623115-160429.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hung, Pei-Hua. “Investigation of Gate Bias Stress-induced Instability and High Sputter Rate SiAl-based Passivation Layer Applied to Amorphous InGaZnO Thin-Film Transistors.” 2015. Web. 08 Aug 2020.

Vancouver:

Hung P. Investigation of Gate Bias Stress-induced Instability and High Sputter Rate SiAl-based Passivation Layer Applied to Amorphous InGaZnO Thin-Film Transistors. [Internet] [Thesis]. NSYSU; 2015. [cited 2020 Aug 08]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623115-160429.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hung P. Investigation of Gate Bias Stress-induced Instability and High Sputter Rate SiAl-based Passivation Layer Applied to Amorphous InGaZnO Thin-Film Transistors. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623115-160429

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Vanderbilt University

12. Kou, Lingbo. Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region.

Degree: MS, Electrical Engineering, 2014, Vanderbilt University

 Power consumption has become a major concern of integrated circuit (IC) design. Reducing the supply voltage to the near-threshold region is one method to reduce… (more)

Subjects/Keywords: flip-flop; radiation-induced soft errors; sram; near-threshold voltage; critical charge; process variations; reliability

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APA (6th Edition):

Kou, L. (2014). Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-04082014-141041/ ;

Chicago Manual of Style (16th Edition):

Kou, Lingbo. “Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region.” 2014. Masters Thesis, Vanderbilt University. Accessed August 08, 2020. http://etd.library.vanderbilt.edu/available/etd-04082014-141041/ ;.

MLA Handbook (7th Edition):

Kou, Lingbo. “Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region.” 2014. Web. 08 Aug 2020.

Vancouver:

Kou L. Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region. [Internet] [Masters thesis]. Vanderbilt University; 2014. [cited 2020 Aug 08]. Available from: http://etd.library.vanderbilt.edu/available/etd-04082014-141041/ ;.

Council of Science Editors:

Kou L. Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region. [Masters Thesis]. Vanderbilt University; 2014. Available from: http://etd.library.vanderbilt.edu/available/etd-04082014-141041/ ;


University of Michigan

13. Pinckney, Nathaniel Ross. Near-Threshold Computing: Past, Present, and Future.

Degree: PhD, Electrical Engineering, 2015, University of Michigan

 Transistor threshold voltages have stagnated in recent years, deviating from constant-voltage scaling theory and directly limiting supply voltage scaling. To overcome the resulting energy and… (more)

Subjects/Keywords: Near Threshold Computing; Energy Efficiency; Low Power; Voltage Boosting; Electrical Engineering; Engineering

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APA (6th Edition):

Pinckney, N. R. (2015). Near-Threshold Computing: Past, Present, and Future. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/113600

Chicago Manual of Style (16th Edition):

Pinckney, Nathaniel Ross. “Near-Threshold Computing: Past, Present, and Future.” 2015. Doctoral Dissertation, University of Michigan. Accessed August 08, 2020. http://hdl.handle.net/2027.42/113600.

MLA Handbook (7th Edition):

Pinckney, Nathaniel Ross. “Near-Threshold Computing: Past, Present, and Future.” 2015. Web. 08 Aug 2020.

Vancouver:

Pinckney NR. Near-Threshold Computing: Past, Present, and Future. [Internet] [Doctoral dissertation]. University of Michigan; 2015. [cited 2020 Aug 08]. Available from: http://hdl.handle.net/2027.42/113600.

Council of Science Editors:

Pinckney NR. Near-Threshold Computing: Past, Present, and Future. [Doctoral Dissertation]. University of Michigan; 2015. Available from: http://hdl.handle.net/2027.42/113600


Arizona State University

14. Gummalla, Samatha. An Analytical Approach to Efficient Circuit Variability Analysis in Scaled CMOS Design.

Degree: MS, Electrical Engineering, 2011, Arizona State University

 Process variations have become increasingly important for scaled technologies starting at 45nm. The increased variations are primarily due to random dopant fluctuations, line-edge roughness and… (more)

Subjects/Keywords: Electrical Engineering; Analytical Modeling; Delay Model; Modeling and performance analysis; Threshold voltage variation; Variability

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APA (6th Edition):

Gummalla, S. (2011). An Analytical Approach to Efficient Circuit Variability Analysis in Scaled CMOS Design. (Masters Thesis). Arizona State University. Retrieved from http://repository.asu.edu/items/9288

Chicago Manual of Style (16th Edition):

Gummalla, Samatha. “An Analytical Approach to Efficient Circuit Variability Analysis in Scaled CMOS Design.” 2011. Masters Thesis, Arizona State University. Accessed August 08, 2020. http://repository.asu.edu/items/9288.

MLA Handbook (7th Edition):

Gummalla, Samatha. “An Analytical Approach to Efficient Circuit Variability Analysis in Scaled CMOS Design.” 2011. Web. 08 Aug 2020.

Vancouver:

Gummalla S. An Analytical Approach to Efficient Circuit Variability Analysis in Scaled CMOS Design. [Internet] [Masters thesis]. Arizona State University; 2011. [cited 2020 Aug 08]. Available from: http://repository.asu.edu/items/9288.

Council of Science Editors:

Gummalla S. An Analytical Approach to Efficient Circuit Variability Analysis in Scaled CMOS Design. [Masters Thesis]. Arizona State University; 2011. Available from: http://repository.asu.edu/items/9288


Universidade do Rio Grande do Sul

15. Paniz, Vitor. Simulação elétrica do efeito de dose total em células de memória estática (SRAM).

Degree: 2010, Universidade do Rio Grande do Sul

Nesta dissertação é apresentado o estudo da célula SRAM estática de 6 transistores, com tecnologia CMOS, sendo utilizada em ambiente exposto à radiação. Foi verificado,… (more)

Subjects/Keywords: Transistores; SRAM; CMOS; Circuitos eletrônicos; Dose effect; Simulação numérica; Total ionization dose; Read noise margin; Threshold voltage; Leakage current

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APA (6th Edition):

Paniz, V. (2010). Simulação elétrica do efeito de dose total em células de memória estática (SRAM). (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/27264

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Paniz, Vitor. “Simulação elétrica do efeito de dose total em células de memória estática (SRAM).” 2010. Thesis, Universidade do Rio Grande do Sul. Accessed August 08, 2020. http://hdl.handle.net/10183/27264.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Paniz, Vitor. “Simulação elétrica do efeito de dose total em células de memória estática (SRAM).” 2010. Web. 08 Aug 2020.

Vancouver:

Paniz V. Simulação elétrica do efeito de dose total em células de memória estática (SRAM). [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2010. [cited 2020 Aug 08]. Available from: http://hdl.handle.net/10183/27264.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Paniz V. Simulação elétrica do efeito de dose total em células de memória estática (SRAM). [Thesis]. Universidade do Rio Grande do Sul; 2010. Available from: http://hdl.handle.net/10183/27264

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Akron

16. Mulpuri, Vamsi. Failure Analysis and High Temperature Characterization of Silicon Carbide Power MOSFETs.

Degree: MSin Engineering, Electrical Engineering, 2017, University of Akron

 The reliability of power semiconductor switches is important when considering their vital role in power electronic converters for aerospace, railway, hybrid electric vehicle, and power… (more)

Subjects/Keywords: Engineering; Silicon Carbide, Threshold Voltage, On state Resistance, Gate leakage Current, Gate Oxide, Metallization, Bond wire

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APA (6th Edition):

Mulpuri, V. (2017). Failure Analysis and High Temperature Characterization of Silicon Carbide Power MOSFETs. (Masters Thesis). University of Akron. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=akron151076214366849

Chicago Manual of Style (16th Edition):

Mulpuri, Vamsi. “Failure Analysis and High Temperature Characterization of Silicon Carbide Power MOSFETs.” 2017. Masters Thesis, University of Akron. Accessed August 08, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=akron151076214366849.

MLA Handbook (7th Edition):

Mulpuri, Vamsi. “Failure Analysis and High Temperature Characterization of Silicon Carbide Power MOSFETs.” 2017. Web. 08 Aug 2020.

Vancouver:

Mulpuri V. Failure Analysis and High Temperature Characterization of Silicon Carbide Power MOSFETs. [Internet] [Masters thesis]. University of Akron; 2017. [cited 2020 Aug 08]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=akron151076214366849.

Council of Science Editors:

Mulpuri V. Failure Analysis and High Temperature Characterization of Silicon Carbide Power MOSFETs. [Masters Thesis]. University of Akron; 2017. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=akron151076214366849


University of Cincinnati

17. Ravi, Ajaay. Run-Time Active Leakage Control Mechanism based on a Light Threshold Voltage Hopping Technique (LITHE).

Degree: MS, Engineering and Applied Science: Computer Engineering, 2011, University of Cincinnati

  Leakage aware designs are an indispensable part of the design and manufacturing process in today’s deep sub-micron technologies. Technology scaling continues to be a… (more)

Subjects/Keywords: Computer Engineering; Leakage Power Reduction; Run-Time Active Leakage Control; Threshold Voltage Hopping; Substrate Biasing; LITHE; Steady state leakage current reduction

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APA (6th Edition):

Ravi, A. (2011). Run-Time Active Leakage Control Mechanism based on a Light Threshold Voltage Hopping Technique (LITHE). (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1302550444

Chicago Manual of Style (16th Edition):

Ravi, Ajaay. “Run-Time Active Leakage Control Mechanism based on a Light Threshold Voltage Hopping Technique (LITHE).” 2011. Masters Thesis, University of Cincinnati. Accessed August 08, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1302550444.

MLA Handbook (7th Edition):

Ravi, Ajaay. “Run-Time Active Leakage Control Mechanism based on a Light Threshold Voltage Hopping Technique (LITHE).” 2011. Web. 08 Aug 2020.

Vancouver:

Ravi A. Run-Time Active Leakage Control Mechanism based on a Light Threshold Voltage Hopping Technique (LITHE). [Internet] [Masters thesis]. University of Cincinnati; 2011. [cited 2020 Aug 08]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1302550444.

Council of Science Editors:

Ravi A. Run-Time Active Leakage Control Mechanism based on a Light Threshold Voltage Hopping Technique (LITHE). [Masters Thesis]. University of Cincinnati; 2011. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1302550444


Wright State University

18. Gopalakrishnan, Harish. Energy Reduction for Asynchronous Circuits in SoC Applications.

Degree: PhD, Engineering PhD, 2011, Wright State University

  As complexity increases and gate sizes shrink for monolithic, mixed-signal integrated circuit (IC) technologies, two problems become dominant: substrate noise caused by digital clocks… (more)

Subjects/Keywords: Electrical Engineering; Asynchronous Circuits; Asynchronous Threshold Network Circuits; NULL Convention Logic (NCL); energy reduction; gate sizing; dual voltage scaling

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APA (6th Edition):

Gopalakrishnan, H. (2011). Energy Reduction for Asynchronous Circuits in SoC Applications. (Doctoral Dissertation). Wright State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=wright1324264498

Chicago Manual of Style (16th Edition):

Gopalakrishnan, Harish. “Energy Reduction for Asynchronous Circuits in SoC Applications.” 2011. Doctoral Dissertation, Wright State University. Accessed August 08, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=wright1324264498.

MLA Handbook (7th Edition):

Gopalakrishnan, Harish. “Energy Reduction for Asynchronous Circuits in SoC Applications.” 2011. Web. 08 Aug 2020.

Vancouver:

Gopalakrishnan H. Energy Reduction for Asynchronous Circuits in SoC Applications. [Internet] [Doctoral dissertation]. Wright State University; 2011. [cited 2020 Aug 08]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1324264498.

Council of Science Editors:

Gopalakrishnan H. Energy Reduction for Asynchronous Circuits in SoC Applications. [Doctoral Dissertation]. Wright State University; 2011. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1324264498


Universidade do Rio Grande do Sul

19. Cardoso, Guilherme Schwanke. Impacto dos desvios de tensão de limiar induzidos por radiação ionizante no desempenho dos blocos básicos de dois amplificadores operacionais complementares.

Degree: 2012, Universidade do Rio Grande do Sul

Este trabalho estuda os efeitos de dose total ionizante (TID – Total Ionizing Dose) em amplificadores operacionais e em seus blocos básicos de construção. A… (more)

Subjects/Keywords: Total ionizing dose (TID); Microeletrônica; Circuitos integrados; Radiation effects in analog circuits; Analog building blocks; Operational amplifiers; Threshold voltage deviations

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cardoso, G. S. (2012). Impacto dos desvios de tensão de limiar induzidos por radiação ionizante no desempenho dos blocos básicos de dois amplificadores operacionais complementares. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/61871

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Cardoso, Guilherme Schwanke. “Impacto dos desvios de tensão de limiar induzidos por radiação ionizante no desempenho dos blocos básicos de dois amplificadores operacionais complementares.” 2012. Thesis, Universidade do Rio Grande do Sul. Accessed August 08, 2020. http://hdl.handle.net/10183/61871.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Cardoso, Guilherme Schwanke. “Impacto dos desvios de tensão de limiar induzidos por radiação ionizante no desempenho dos blocos básicos de dois amplificadores operacionais complementares.” 2012. Web. 08 Aug 2020.

Vancouver:

Cardoso GS. Impacto dos desvios de tensão de limiar induzidos por radiação ionizante no desempenho dos blocos básicos de dois amplificadores operacionais complementares. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2012. [cited 2020 Aug 08]. Available from: http://hdl.handle.net/10183/61871.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Cardoso GS. Impacto dos desvios de tensão de limiar induzidos por radiação ionizante no desempenho dos blocos básicos de dois amplificadores operacionais complementares. [Thesis]. Universidade do Rio Grande do Sul; 2012. Available from: http://hdl.handle.net/10183/61871

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

20. Rosa, André Luís Rodeghiero. Projeto de células e circuitos VLSI digitais CMOS para operação em baixa tensão.

Degree: 2015, Universidade do Rio Grande do Sul

Este trabalho propõe uma estratégia para projeto de circuitos VLSI operando em amplo ajuste de tensão e frequência (VFS), desde o regime em Near-threshold, onde… (more)

Subjects/Keywords: Microeletrônica; Digital CMOS; Voltage-frequency scaling; Cmos; Vlsi; CMOS energy-efficiency; Near-threshold; Multi-VT MOSFET transistors

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APA (6th Edition):

Rosa, A. L. R. (2015). Projeto de células e circuitos VLSI digitais CMOS para operação em baixa tensão. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/118526

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Rosa, André Luís Rodeghiero. “Projeto de células e circuitos VLSI digitais CMOS para operação em baixa tensão.” 2015. Thesis, Universidade do Rio Grande do Sul. Accessed August 08, 2020. http://hdl.handle.net/10183/118526.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Rosa, André Luís Rodeghiero. “Projeto de células e circuitos VLSI digitais CMOS para operação em baixa tensão.” 2015. Web. 08 Aug 2020.

Vancouver:

Rosa ALR. Projeto de células e circuitos VLSI digitais CMOS para operação em baixa tensão. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2015. [cited 2020 Aug 08]. Available from: http://hdl.handle.net/10183/118526.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Rosa ALR. Projeto de células e circuitos VLSI digitais CMOS para operação em baixa tensão. [Thesis]. Universidade do Rio Grande do Sul; 2015. Available from: http://hdl.handle.net/10183/118526

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

21. Reimann, Tiago Jose. Cell selection to minimize power in high-performance industrial microprocessor designs.

Degree: 2016, Universidade do Rio Grande do Sul

This work addresses the gate sizing and Vt assignment problem for power, area and timing optimization in modern integrated circuits (IC). The proposed flow is… (more)

Subjects/Keywords: Gate sizing; Microeletrônica; Threshold voltage assignment; Portas logicas; Microprocessadores; Lagrangian relaxation; Processamento : Alto desempenho; EDA; Microelectronics

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APA (6th Edition):

Reimann, T. J. (2016). Cell selection to minimize power in high-performance industrial microprocessor designs. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/158131

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Reimann, Tiago Jose. “Cell selection to minimize power in high-performance industrial microprocessor designs.” 2016. Thesis, Universidade do Rio Grande do Sul. Accessed August 08, 2020. http://hdl.handle.net/10183/158131.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Reimann, Tiago Jose. “Cell selection to minimize power in high-performance industrial microprocessor designs.” 2016. Web. 08 Aug 2020.

Vancouver:

Reimann TJ. Cell selection to minimize power in high-performance industrial microprocessor designs. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2016. [cited 2020 Aug 08]. Available from: http://hdl.handle.net/10183/158131.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Reimann TJ. Cell selection to minimize power in high-performance industrial microprocessor designs. [Thesis]. Universidade do Rio Grande do Sul; 2016. Available from: http://hdl.handle.net/10183/158131

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

22. Grisales, Catalina Aguirre. Análises dos transistores de porta flutuante : modelamento e impacto do efeito de doses total ionizante.

Degree: 2013, Universidade do Rio Grande do Sul

Nesta dissertação é apresentado o estudo dos transistores de porta flutuante (Floating Gate Transistor - FG Transistor), sua modelagem, e a análise do efeito da… (more)

Subjects/Keywords: Floating gate transistor; Transistores; MOS transistor; Simulação numérica; Total ionizing dose; Threshold voltage; Charge retention; Capacitive coupling coefficient

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APA (6th Edition):

Grisales, C. A. (2013). Análises dos transistores de porta flutuante : modelamento e impacto do efeito de doses total ionizante. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/96480

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Grisales, Catalina Aguirre. “Análises dos transistores de porta flutuante : modelamento e impacto do efeito de doses total ionizante.” 2013. Thesis, Universidade do Rio Grande do Sul. Accessed August 08, 2020. http://hdl.handle.net/10183/96480.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Grisales, Catalina Aguirre. “Análises dos transistores de porta flutuante : modelamento e impacto do efeito de doses total ionizante.” 2013. Web. 08 Aug 2020.

Vancouver:

Grisales CA. Análises dos transistores de porta flutuante : modelamento e impacto do efeito de doses total ionizante. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2013. [cited 2020 Aug 08]. Available from: http://hdl.handle.net/10183/96480.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Grisales CA. Análises dos transistores de porta flutuante : modelamento e impacto do efeito de doses total ionizante. [Thesis]. Universidade do Rio Grande do Sul; 2013. Available from: http://hdl.handle.net/10183/96480

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Vanderbilt University

23. Ni, Kai. A fully embedded Silicon On Insulator Total Ionizing Dose monitor.

Degree: MS, Electrical Engineering, 2013, Vanderbilt University

 Total ionizing dose (TID) effect is a kind of radiation effects. Itâs related with the charge build up in the insulator caused by the radiation.… (more)

Subjects/Keywords: silicon on insulator; buried oxide; threshold voltage shift; leakage current; current controlled oscillator; total ionizing dose

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APA (6th Edition):

Ni, K. (2013). A fully embedded Silicon On Insulator Total Ionizing Dose monitor. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-07302013-093909/ ;

Chicago Manual of Style (16th Edition):

Ni, Kai. “A fully embedded Silicon On Insulator Total Ionizing Dose monitor.” 2013. Masters Thesis, Vanderbilt University. Accessed August 08, 2020. http://etd.library.vanderbilt.edu/available/etd-07302013-093909/ ;.

MLA Handbook (7th Edition):

Ni, Kai. “A fully embedded Silicon On Insulator Total Ionizing Dose monitor.” 2013. Web. 08 Aug 2020.

Vancouver:

Ni K. A fully embedded Silicon On Insulator Total Ionizing Dose monitor. [Internet] [Masters thesis]. Vanderbilt University; 2013. [cited 2020 Aug 08]. Available from: http://etd.library.vanderbilt.edu/available/etd-07302013-093909/ ;.

Council of Science Editors:

Ni K. A fully embedded Silicon On Insulator Total Ionizing Dose monitor. [Masters Thesis]. Vanderbilt University; 2013. Available from: http://etd.library.vanderbilt.edu/available/etd-07302013-093909/ ;

24. Γιάννακας, Γεώργιος. Σχεδίαση ολοκληρωμένων μετατροπέων ισχύος ραδιοσυχνοτήτων (RF) σε ισχύ συνεχούς (DC).

Degree: 2012, University of Thessaly (UTH); Πανεπιστήμιο Θεσσαλίας

 A major problem in designing wireless sensor networks (WSN) is the very limited energy supply of its nodes. Although there are plenty of energy conservation… (more)

Subjects/Keywords: Ενεργειακή συγκομιδή; Ασύρματη ταυτοποίηση; Ανορθωτές; RFIDs; WSN; RF energy harvesting; RF to DC conversion; Voltage threshold reduction; Loaded quality factor

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APA (6th Edition):

Γιάννακας, . . (2012). Σχεδίαση ολοκληρωμένων μετατροπέων ισχύος ραδιοσυχνοτήτων (RF) σε ισχύ συνεχούς (DC). (Thesis). University of Thessaly (UTH); Πανεπιστήμιο Θεσσαλίας. Retrieved from http://hdl.handle.net/10442/hedi/26583

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Γιάννακας, Γεώργιος. “Σχεδίαση ολοκληρωμένων μετατροπέων ισχύος ραδιοσυχνοτήτων (RF) σε ισχύ συνεχούς (DC).” 2012. Thesis, University of Thessaly (UTH); Πανεπιστήμιο Θεσσαλίας. Accessed August 08, 2020. http://hdl.handle.net/10442/hedi/26583.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Γιάννακας, Γεώργιος. “Σχεδίαση ολοκληρωμένων μετατροπέων ισχύος ραδιοσυχνοτήτων (RF) σε ισχύ συνεχούς (DC).” 2012. Web. 08 Aug 2020.

Vancouver:

Γιάννακας . Σχεδίαση ολοκληρωμένων μετατροπέων ισχύος ραδιοσυχνοτήτων (RF) σε ισχύ συνεχούς (DC). [Internet] [Thesis]. University of Thessaly (UTH); Πανεπιστήμιο Θεσσαλίας; 2012. [cited 2020 Aug 08]. Available from: http://hdl.handle.net/10442/hedi/26583.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Γιάννακας . Σχεδίαση ολοκληρωμένων μετατροπέων ισχύος ραδιοσυχνοτήτων (RF) σε ισχύ συνεχούς (DC). [Thesis]. University of Thessaly (UTH); Πανεπιστήμιο Θεσσαλίας; 2012. Available from: http://hdl.handle.net/10442/hedi/26583

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Cornell University

25. Fried, David. The Design, Fabrication and Characterization of Independent-Gate FinFETs .

Degree: 2004, Cornell University

 The Independent-Gate FinFET is introduced as a novel device structure that combines several innovative aspects of the FinFET and planar double-gate FETs. The IG-FinFET addresses… (more)

Subjects/Keywords: FinFET; Independent-Gate; Threshold Voltage Control; Double-Gate; Fabrication

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APA (6th Edition):

Fried, D. (2004). The Design, Fabrication and Characterization of Independent-Gate FinFETs . (Thesis). Cornell University. Retrieved from http://hdl.handle.net/1813/100

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fried, David. “The Design, Fabrication and Characterization of Independent-Gate FinFETs .” 2004. Thesis, Cornell University. Accessed August 08, 2020. http://hdl.handle.net/1813/100.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fried, David. “The Design, Fabrication and Characterization of Independent-Gate FinFETs .” 2004. Web. 08 Aug 2020.

Vancouver:

Fried D. The Design, Fabrication and Characterization of Independent-Gate FinFETs . [Internet] [Thesis]. Cornell University; 2004. [cited 2020 Aug 08]. Available from: http://hdl.handle.net/1813/100.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fried D. The Design, Fabrication and Characterization of Independent-Gate FinFETs . [Thesis]. Cornell University; 2004. Available from: http://hdl.handle.net/1813/100

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Ohio University

26. Bhamidipati, Padmaja. RETUNES: Reliable and Energy-Ecient Network-on-Chip Architecture using Adaptive Routing and Approximate Communication.

Degree: MS, Electrical Engineering & Computer Science (Engineering and Technology), 2019, Ohio University

 As the number of processing cores are increasing in a chip multiprocessor (CMP), demand for an energy-efficient and reliable Network-on-Chip (NoC) architecture is increasing. However,… (more)

Subjects/Keywords: Electrical Engineering; Network-on-Chip; Energy efficiency; Reliability; Aging; Adaptive routing algorithm; Approximate communication; Near Threshold Voltage; NBTI; HCI

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APA (6th Edition):

Bhamidipati, P. (2019). RETUNES: Reliable and Energy-Ecient Network-on-Chip Architecture using Adaptive Routing and Approximate Communication. (Masters Thesis). Ohio University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1554914045111913

Chicago Manual of Style (16th Edition):

Bhamidipati, Padmaja. “RETUNES: Reliable and Energy-Ecient Network-on-Chip Architecture using Adaptive Routing and Approximate Communication.” 2019. Masters Thesis, Ohio University. Accessed August 08, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1554914045111913.

MLA Handbook (7th Edition):

Bhamidipati, Padmaja. “RETUNES: Reliable and Energy-Ecient Network-on-Chip Architecture using Adaptive Routing and Approximate Communication.” 2019. Web. 08 Aug 2020.

Vancouver:

Bhamidipati P. RETUNES: Reliable and Energy-Ecient Network-on-Chip Architecture using Adaptive Routing and Approximate Communication. [Internet] [Masters thesis]. Ohio University; 2019. [cited 2020 Aug 08]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1554914045111913.

Council of Science Editors:

Bhamidipati P. RETUNES: Reliable and Energy-Ecient Network-on-Chip Architecture using Adaptive Routing and Approximate Communication. [Masters Thesis]. Ohio University; 2019. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1554914045111913


Université Catholique de Louvain

27. Botman, François. Towards the design of a pseudo-synchronous multi-processor system-on-chip for processing-intensive ultra-low-power applications.

Degree: 2014, Université Catholique de Louvain

The Internet-of-Things (IoT) is an emerging paradigm that aims to integrate technology into the human environment, rather than the reverse. By connecting together a multitude… (more)

Subjects/Keywords: CMOS digital integrated circuits; VLSI; Embedded microcontroller; Near-threshold/subthreshold logic; System-on-Chip (SoC); Ultralow power; Ultralow voltage; Variability mitigation

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APA (6th Edition):

Botman, F. (2014). Towards the design of a pseudo-synchronous multi-processor system-on-chip for processing-intensive ultra-low-power applications. (Thesis). Université Catholique de Louvain. Retrieved from http://hdl.handle.net/2078.1/152487

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Botman, François. “Towards the design of a pseudo-synchronous multi-processor system-on-chip for processing-intensive ultra-low-power applications.” 2014. Thesis, Université Catholique de Louvain. Accessed August 08, 2020. http://hdl.handle.net/2078.1/152487.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Botman, François. “Towards the design of a pseudo-synchronous multi-processor system-on-chip for processing-intensive ultra-low-power applications.” 2014. Web. 08 Aug 2020.

Vancouver:

Botman F. Towards the design of a pseudo-synchronous multi-processor system-on-chip for processing-intensive ultra-low-power applications. [Internet] [Thesis]. Université Catholique de Louvain; 2014. [cited 2020 Aug 08]. Available from: http://hdl.handle.net/2078.1/152487.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Botman F. Towards the design of a pseudo-synchronous multi-processor system-on-chip for processing-intensive ultra-low-power applications. [Thesis]. Université Catholique de Louvain; 2014. Available from: http://hdl.handle.net/2078.1/152487

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

28. Barč, Andrej. Tvarovače a omezovače signálu pro laboratorní výuku: Shaping networks and limiters for educational laboratory purposes.

Degree: 2019, Brno University of Technology

 This bachelor thesis deals with design and implementation of shaping diode circuits and double - sided diode limiter of sinusoidal signal for laboratory use in… (more)

Subjects/Keywords: Prevodná charakteristika; obmedzovač; prahové napätie; operačný zosilňovač; simulácia; Transmission characteristic; limiter; threshold voltage; operational amplifier; simulation

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APA (6th Edition):

Barč, A. (2019). Tvarovače a omezovače signálu pro laboratorní výuku: Shaping networks and limiters for educational laboratory purposes. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/173649

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Barč, Andrej. “Tvarovače a omezovače signálu pro laboratorní výuku: Shaping networks and limiters for educational laboratory purposes.” 2019. Thesis, Brno University of Technology. Accessed August 08, 2020. http://hdl.handle.net/11012/173649.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Barč, Andrej. “Tvarovače a omezovače signálu pro laboratorní výuku: Shaping networks and limiters for educational laboratory purposes.” 2019. Web. 08 Aug 2020.

Vancouver:

Barč A. Tvarovače a omezovače signálu pro laboratorní výuku: Shaping networks and limiters for educational laboratory purposes. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2020 Aug 08]. Available from: http://hdl.handle.net/11012/173649.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Barč A. Tvarovače a omezovače signálu pro laboratorní výuku: Shaping networks and limiters for educational laboratory purposes. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/173649

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Iowa State University

29. Lee, Sheng Huang. Multi-threshold transistors cell for low voltage integrated temperature sensing application in digital deep submicron process.

Degree: 2011, Iowa State University

 The rapid shrinking of feature sizes in CMOS processes has enabled high density integration of multi-core systems. However, the corresponding increase in component and local… (more)

Subjects/Keywords: analog mixed-signal vlsi; low voltage; multiple threshold; reference circuit; stable equilibrium point; temperature sensor; Electrical and Computer Engineering

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APA (6th Edition):

Lee, S. H. (2011). Multi-threshold transistors cell for low voltage integrated temperature sensing application in digital deep submicron process. (Thesis). Iowa State University. Retrieved from https://lib.dr.iastate.edu/etd/10253

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lee, Sheng Huang. “Multi-threshold transistors cell for low voltage integrated temperature sensing application in digital deep submicron process.” 2011. Thesis, Iowa State University. Accessed August 08, 2020. https://lib.dr.iastate.edu/etd/10253.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lee, Sheng Huang. “Multi-threshold transistors cell for low voltage integrated temperature sensing application in digital deep submicron process.” 2011. Web. 08 Aug 2020.

Vancouver:

Lee SH. Multi-threshold transistors cell for low voltage integrated temperature sensing application in digital deep submicron process. [Internet] [Thesis]. Iowa State University; 2011. [cited 2020 Aug 08]. Available from: https://lib.dr.iastate.edu/etd/10253.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lee SH. Multi-threshold transistors cell for low voltage integrated temperature sensing application in digital deep submicron process. [Thesis]. Iowa State University; 2011. Available from: https://lib.dr.iastate.edu/etd/10253

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

30. Fontaine, Charly. Analyse par XPS d'empilements High-K Metal Gate de transistors CMOS et corrélation des décalages d'énergie de liaison aux tensions de seuil : XPs analysis of High K Metal Gate transistors and relationship between binding energy shift and threshold voltage.

Degree: Docteur es, Nano electronique et nano technologies, 2019, Université Grenoble Alpes (ComUE)

Les dernières technologies microélectroniques embarquent des transistors dont les isolants de grille sont des isolants à forte constante diélectrique (high-k en anglais) associés à des… (more)

Subjects/Keywords: Xps; Tension de seuil; High K metal gate; Xps; Threshold voltage; High K metal gate; 540; 620

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Fontaine, C. (2019). Analyse par XPS d'empilements High-K Metal Gate de transistors CMOS et corrélation des décalages d'énergie de liaison aux tensions de seuil : XPs analysis of High K Metal Gate transistors and relationship between binding energy shift and threshold voltage. (Doctoral Dissertation). Université Grenoble Alpes (ComUE). Retrieved from http://www.theses.fr/2019GREAT011

Chicago Manual of Style (16th Edition):

Fontaine, Charly. “Analyse par XPS d'empilements High-K Metal Gate de transistors CMOS et corrélation des décalages d'énergie de liaison aux tensions de seuil : XPs analysis of High K Metal Gate transistors and relationship between binding energy shift and threshold voltage.” 2019. Doctoral Dissertation, Université Grenoble Alpes (ComUE). Accessed August 08, 2020. http://www.theses.fr/2019GREAT011.

MLA Handbook (7th Edition):

Fontaine, Charly. “Analyse par XPS d'empilements High-K Metal Gate de transistors CMOS et corrélation des décalages d'énergie de liaison aux tensions de seuil : XPs analysis of High K Metal Gate transistors and relationship between binding energy shift and threshold voltage.” 2019. Web. 08 Aug 2020.

Vancouver:

Fontaine C. Analyse par XPS d'empilements High-K Metal Gate de transistors CMOS et corrélation des décalages d'énergie de liaison aux tensions de seuil : XPs analysis of High K Metal Gate transistors and relationship between binding energy shift and threshold voltage. [Internet] [Doctoral dissertation]. Université Grenoble Alpes (ComUE); 2019. [cited 2020 Aug 08]. Available from: http://www.theses.fr/2019GREAT011.

Council of Science Editors:

Fontaine C. Analyse par XPS d'empilements High-K Metal Gate de transistors CMOS et corrélation des décalages d'énergie de liaison aux tensions de seuil : XPs analysis of High K Metal Gate transistors and relationship between binding energy shift and threshold voltage. [Doctoral Dissertation]. Université Grenoble Alpes (ComUE); 2019. Available from: http://www.theses.fr/2019GREAT011

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