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You searched for subject:(thread level parallelism). Showing records 1 – 11 of 11 total matches.

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Texas A&M University

1. Fatehi, Ehsan. ILP and TLP in Shared Memory Applications: A Limit Study.

Degree: 2015, Texas A&M University

 The work in this dissertation explores the limits of Chip-multiprocessors (CMPs) with respect to shared-memory, multi-threaded benchmarks, which will help aid in identifying microarchitectural bottlenecks.… (more)

Subjects/Keywords: instruction-level parallelism; limits parallelism; concurrency pthreads; thread-level parallelism

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APA (6th Edition):

Fatehi, E. (2015). ILP and TLP in Shared Memory Applications: A Limit Study. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/155119

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fatehi, Ehsan. “ILP and TLP in Shared Memory Applications: A Limit Study.” 2015. Thesis, Texas A&M University. Accessed October 14, 2019. http://hdl.handle.net/1969.1/155119.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fatehi, Ehsan. “ILP and TLP in Shared Memory Applications: A Limit Study.” 2015. Web. 14 Oct 2019.

Vancouver:

Fatehi E. ILP and TLP in Shared Memory Applications: A Limit Study. [Internet] [Thesis]. Texas A&M University; 2015. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/1969.1/155119.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fatehi E. ILP and TLP in Shared Memory Applications: A Limit Study. [Thesis]. Texas A&M University; 2015. Available from: http://hdl.handle.net/1969.1/155119

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Texas – Austin

2. Khubaib. Performance and energy efficiency via an adaptive MorphCore architecture.

Degree: PhD, Electrical and Computer Engineering, 2014, University of Texas – Austin

 The level of Thread-Level Parallelism (TLP), Instruction-Level Parallelism (ILP), and Memory-Level Parallelism (MLP) varies across programs and across program phases. Hence, every program requires different… (more)

Subjects/Keywords: Computer architecture; Microprocessor; Thread-level parallelism; Instruction-level parallelism; Memory-level parallelism; Adaptive microprocessor; Energy efficiency; High performance; Power efficiency; Chip-multiprocessor; Heterogeneous computing

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APA (6th Edition):

Khubaib. (2014). Performance and energy efficiency via an adaptive MorphCore architecture. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/25092

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

Khubaib. “Performance and energy efficiency via an adaptive MorphCore architecture.” 2014. Doctoral Dissertation, University of Texas – Austin. Accessed October 14, 2019. http://hdl.handle.net/2152/25092.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

Khubaib. “Performance and energy efficiency via an adaptive MorphCore architecture.” 2014. Web. 14 Oct 2019.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

Khubaib. Performance and energy efficiency via an adaptive MorphCore architecture. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2014. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/2152/25092.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

Khubaib. Performance and energy efficiency via an adaptive MorphCore architecture. [Doctoral Dissertation]. University of Texas – Austin; 2014. Available from: http://hdl.handle.net/2152/25092

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete


Loughborough University

3. Stevens, David. On the automated compilation of UML notation to a VLIW chip multiprocessor.

Degree: PhD, 2013, Loughborough University

 With the availability of more and more cores within architectures the process of extracting implicit and explicit parallelism in applications to fully utilise these cores… (more)

Subjects/Keywords: 621.3; Very long instruction word; VLIW; Unified modelling language; UML; Thread level parallelism; Hardware threading

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APA (6th Edition):

Stevens, D. (2013). On the automated compilation of UML notation to a VLIW chip multiprocessor. (Doctoral Dissertation). Loughborough University. Retrieved from https://dspace.lboro.ac.uk/2134/13746 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.588060

Chicago Manual of Style (16th Edition):

Stevens, David. “On the automated compilation of UML notation to a VLIW chip multiprocessor.” 2013. Doctoral Dissertation, Loughborough University. Accessed October 14, 2019. https://dspace.lboro.ac.uk/2134/13746 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.588060.

MLA Handbook (7th Edition):

Stevens, David. “On the automated compilation of UML notation to a VLIW chip multiprocessor.” 2013. Web. 14 Oct 2019.

Vancouver:

Stevens D. On the automated compilation of UML notation to a VLIW chip multiprocessor. [Internet] [Doctoral dissertation]. Loughborough University; 2013. [cited 2019 Oct 14]. Available from: https://dspace.lboro.ac.uk/2134/13746 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.588060.

Council of Science Editors:

Stevens D. On the automated compilation of UML notation to a VLIW chip multiprocessor. [Doctoral Dissertation]. Loughborough University; 2013. Available from: https://dspace.lboro.ac.uk/2134/13746 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.588060


Universidade do Rio Grande do Sul

4. Rutzig, Mateus Beck. A transparent and energy aware reconfigurable multiprocessor platform for efficient ILP and TLP exploitation.

Degree: 2012, Universidade do Rio Grande do Sul

 As the number of embedded applications is increasing, the current strategy of several companies is to launch a new platform within short periods, to execute… (more)

Subjects/Keywords: Multiprocessadores; Multiprocessors; Microeletrônica; Reconfigurable architectures; Instruction and thread level parallelism; Sistemas embarcados

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APA (6th Edition):

Rutzig, M. B. (2012). A transparent and energy aware reconfigurable multiprocessor platform for efficient ILP and TLP exploitation. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/37178

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Rutzig, Mateus Beck. “A transparent and energy aware reconfigurable multiprocessor platform for efficient ILP and TLP exploitation.” 2012. Thesis, Universidade do Rio Grande do Sul. Accessed October 14, 2019. http://hdl.handle.net/10183/37178.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Rutzig, Mateus Beck. “A transparent and energy aware reconfigurable multiprocessor platform for efficient ILP and TLP exploitation.” 2012. Web. 14 Oct 2019.

Vancouver:

Rutzig MB. A transparent and energy aware reconfigurable multiprocessor platform for efficient ILP and TLP exploitation. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2012. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/10183/37178.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Rutzig MB. A transparent and energy aware reconfigurable multiprocessor platform for efficient ILP and TLP exploitation. [Thesis]. Universidade do Rio Grande do Sul; 2012. Available from: http://hdl.handle.net/10183/37178

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Loughborough University

5. Stevens, David. On the automated compilation of UML notation to a VLIW chip multiprocessor.

Degree: PhD, 2013, Loughborough University

 With the availability of more and more cores within architectures the process of extracting implicit and explicit parallelism in applications to fully utilise these cores… (more)

Subjects/Keywords: 621.3; Very long instruction word; VLIW; Unified modelling language; UML; Thread level parallelism; Hardware threading

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Stevens, D. (2013). On the automated compilation of UML notation to a VLIW chip multiprocessor. (Doctoral Dissertation). Loughborough University. Retrieved from http://hdl.handle.net/2134/13746

Chicago Manual of Style (16th Edition):

Stevens, David. “On the automated compilation of UML notation to a VLIW chip multiprocessor.” 2013. Doctoral Dissertation, Loughborough University. Accessed October 14, 2019. http://hdl.handle.net/2134/13746.

MLA Handbook (7th Edition):

Stevens, David. “On the automated compilation of UML notation to a VLIW chip multiprocessor.” 2013. Web. 14 Oct 2019.

Vancouver:

Stevens D. On the automated compilation of UML notation to a VLIW chip multiprocessor. [Internet] [Doctoral dissertation]. Loughborough University; 2013. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/2134/13746.

Council of Science Editors:

Stevens D. On the automated compilation of UML notation to a VLIW chip multiprocessor. [Doctoral Dissertation]. Loughborough University; 2013. Available from: http://hdl.handle.net/2134/13746

6. Ioannou, Nikolas. Complementing user-level coarse-grain parallelism with implicit speculative parallelism.

Degree: PhD, 2012, University of Edinburgh

 Multi-core and many-core systems are the norm in contemporary processor technology and are expected to remain so for the foreseeable future. Parallel programming is, thus,… (more)

Subjects/Keywords: 005.2; many-core architecture; thread-level speculation; thread-level parallelism; power management

…extracting thread-level parallelism between whatever dynamic dependences actually exist at runtime… …Complementing User-Level Coarse-Grain Parallelism with Implicit Speculative Parallelism” Nikolas… …Thread-Level Speculation . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.1 Example… …Example of Thread-Level Speculation execution: (a) pseudo-code of a loop with… …hardware. By running implicit speculative threads 3 through thread-level speculation (TLS… 

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APA (6th Edition):

Ioannou, N. (2012). Complementing user-level coarse-grain parallelism with implicit speculative parallelism. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/7900

Chicago Manual of Style (16th Edition):

Ioannou, Nikolas. “Complementing user-level coarse-grain parallelism with implicit speculative parallelism.” 2012. Doctoral Dissertation, University of Edinburgh. Accessed October 14, 2019. http://hdl.handle.net/1842/7900.

MLA Handbook (7th Edition):

Ioannou, Nikolas. “Complementing user-level coarse-grain parallelism with implicit speculative parallelism.” 2012. Web. 14 Oct 2019.

Vancouver:

Ioannou N. Complementing user-level coarse-grain parallelism with implicit speculative parallelism. [Internet] [Doctoral dissertation]. University of Edinburgh; 2012. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/1842/7900.

Council of Science Editors:

Ioannou N. Complementing user-level coarse-grain parallelism with implicit speculative parallelism. [Doctoral Dissertation]. University of Edinburgh; 2012. Available from: http://hdl.handle.net/1842/7900


North Carolina State University

7. So, Won. Software Thread Integration for Instruction Level Parallelism.

Degree: PhD, Computer Engineering, 2007, North Carolina State University

 Multimedia applications require a significantly higher level of performance than previous workloads of embedded systems. They have driven digital signal processor (DSP) makers to adopt… (more)

Subjects/Keywords: StreamIt; VLIW; DSP; digital signal processor; stream programming; Itanium; software thread integration; very long instruction word; TI C6000; instruction level parallelism; thread level parallelism

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APA (6th Edition):

So, W. (2007). Software Thread Integration for Instruction Level Parallelism. (Doctoral Dissertation). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/5930

Chicago Manual of Style (16th Edition):

So, Won. “Software Thread Integration for Instruction Level Parallelism.” 2007. Doctoral Dissertation, North Carolina State University. Accessed October 14, 2019. http://www.lib.ncsu.edu/resolver/1840.16/5930.

MLA Handbook (7th Edition):

So, Won. “Software Thread Integration for Instruction Level Parallelism.” 2007. Web. 14 Oct 2019.

Vancouver:

So W. Software Thread Integration for Instruction Level Parallelism. [Internet] [Doctoral dissertation]. North Carolina State University; 2007. [cited 2019 Oct 14]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/5930.

Council of Science Editors:

So W. Software Thread Integration for Instruction Level Parallelism. [Doctoral Dissertation]. North Carolina State University; 2007. Available from: http://www.lib.ncsu.edu/resolver/1840.16/5930


Université Paris-Sud – Paris XI

8. Bahi, Mouad. High Performance by Exploiting Information Locality through Reverse Computing : Hautes Performances en Exploitant la Localité de l'Information via le Calcul Réversible.

Degree: Docteur es, Informatique, 2011, Université Paris-Sud – Paris XI

Les trois principales ressources du calcul sont le temps, l'espace et l'énergie, les minimiser constitue un des défis les plus importants de la recherche de… (more)

Subjects/Keywords: Compilation; Calcul réversible; Localité de l'information; Optimisation des performances; Allocation de registres; Rematérialisation; Vidage en mémoire; Parallélisme d'instructions; Parallélisme de threads; GPU; Cell BE; LQCD; Reversible computing; Performance optimization; Information locality; Rematerialization; Register allocation; Spill code; Instruction-level parallelism; Thread-l

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bahi, M. (2011). High Performance by Exploiting Information Locality through Reverse Computing : Hautes Performances en Exploitant la Localité de l'Information via le Calcul Réversible. (Doctoral Dissertation). Université Paris-Sud – Paris XI. Retrieved from http://www.theses.fr/2011PA112327

Chicago Manual of Style (16th Edition):

Bahi, Mouad. “High Performance by Exploiting Information Locality through Reverse Computing : Hautes Performances en Exploitant la Localité de l'Information via le Calcul Réversible.” 2011. Doctoral Dissertation, Université Paris-Sud – Paris XI. Accessed October 14, 2019. http://www.theses.fr/2011PA112327.

MLA Handbook (7th Edition):

Bahi, Mouad. “High Performance by Exploiting Information Locality through Reverse Computing : Hautes Performances en Exploitant la Localité de l'Information via le Calcul Réversible.” 2011. Web. 14 Oct 2019.

Vancouver:

Bahi M. High Performance by Exploiting Information Locality through Reverse Computing : Hautes Performances en Exploitant la Localité de l'Information via le Calcul Réversible. [Internet] [Doctoral dissertation]. Université Paris-Sud – Paris XI; 2011. [cited 2019 Oct 14]. Available from: http://www.theses.fr/2011PA112327.

Council of Science Editors:

Bahi M. High Performance by Exploiting Information Locality through Reverse Computing : Hautes Performances en Exploitant la Localité de l'Information via le Calcul Réversible. [Doctoral Dissertation]. Université Paris-Sud – Paris XI; 2011. Available from: http://www.theses.fr/2011PA112327


Universitat Politècnica de Catalunya

9. Pericàs Gleim, Miquel. Affordable kilo-instruction processors.

Degree: Departament d'Arquitectura de Computadors, 2008, Universitat Politècnica de Catalunya

 Several motives explain the slowdown of high-performance single-thread processor development. On the one hand, aggressive techniques such as superpipelining or out-of-order execution have a considerable… (more)

Subjects/Keywords: load-store queues; thread scheduling; decoupled processors; memory level parallelism; kilo-instruction processors; 004

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APA (6th Edition):

Pericàs Gleim, M. (2008). Affordable kilo-instruction processors. (Thesis). Universitat Politècnica de Catalunya. Retrieved from http://hdl.handle.net/10803/6025

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pericàs Gleim, Miquel. “Affordable kilo-instruction processors.” 2008. Thesis, Universitat Politècnica de Catalunya. Accessed October 14, 2019. http://hdl.handle.net/10803/6025.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pericàs Gleim, Miquel. “Affordable kilo-instruction processors.” 2008. Web. 14 Oct 2019.

Vancouver:

Pericàs Gleim M. Affordable kilo-instruction processors. [Internet] [Thesis]. Universitat Politècnica de Catalunya; 2008. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/10803/6025.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pericàs Gleim M. Affordable kilo-instruction processors. [Thesis]. Universitat Politècnica de Catalunya; 2008. Available from: http://hdl.handle.net/10803/6025

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Tech

10. Dickenson, William Wesley. High Performance Applications for the Single-Chip Message-Passing Parallel Computer.

Degree: MS, Electrical and Computer Engineering, 2004, Virginia Tech

 Computer architects continue to push the limits of modern microprocessors. By using techniques such as out-of-order execution, branch prediction, and dynamic scheduling, designers have found… (more)

Subjects/Keywords: Chip Multiprocessors; Message-Passing Systems; Parallel Applications; Parallel Architectures; Single-Chip Systems; Thread Level Parallelism

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APA (6th Edition):

Dickenson, W. W. (2004). High Performance Applications for the Single-Chip Message-Passing Parallel Computer. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/32023

Chicago Manual of Style (16th Edition):

Dickenson, William Wesley. “High Performance Applications for the Single-Chip Message-Passing Parallel Computer.” 2004. Masters Thesis, Virginia Tech. Accessed October 14, 2019. http://hdl.handle.net/10919/32023.

MLA Handbook (7th Edition):

Dickenson, William Wesley. “High Performance Applications for the Single-Chip Message-Passing Parallel Computer.” 2004. Web. 14 Oct 2019.

Vancouver:

Dickenson WW. High Performance Applications for the Single-Chip Message-Passing Parallel Computer. [Internet] [Masters thesis]. Virginia Tech; 2004. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/10919/32023.

Council of Science Editors:

Dickenson WW. High Performance Applications for the Single-Chip Message-Passing Parallel Computer. [Masters Thesis]. Virginia Tech; 2004. Available from: http://hdl.handle.net/10919/32023

11. Alwan, Esraa. Enhancing the performance of decoupled software pipeline through backward slicing.

Degree: PhD, 2014, University of Bath

 The rapidly increasing number of cores available in multicore processors does not necessarily lead directly to a commensurate increase in performance: programs written in conventional… (more)

Subjects/Keywords: 004.35; decoupled software pipeline; slicing; multicore; thread-level parallelism; automatic restructuring

parallelism where multiple low-level instructions are executed at the same time, parallelizing… …underlying architecture, just as instruction-level parallelism(ILP) optimizations relieve… …been used to enhance the performance of single thread applications in a highly effective way… …thread programs has become clear especially due to recent increases in processor clock speed… …no gains have been made from this strategy for single thread application. Various… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Alwan, E. (2014). Enhancing the performance of decoupled software pipeline through backward slicing. (Doctoral Dissertation). University of Bath. Retrieved from https://researchportal.bath.ac.uk/en/studentthesis/enhancing-the-performance-of-decoupled-software-pipeline-through-backward-slicing(2ebd660d-9ee8-4429-85e6-cb21031fb64f).html ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.616651

Chicago Manual of Style (16th Edition):

Alwan, Esraa. “Enhancing the performance of decoupled software pipeline through backward slicing.” 2014. Doctoral Dissertation, University of Bath. Accessed October 14, 2019. https://researchportal.bath.ac.uk/en/studentthesis/enhancing-the-performance-of-decoupled-software-pipeline-through-backward-slicing(2ebd660d-9ee8-4429-85e6-cb21031fb64f).html ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.616651.

MLA Handbook (7th Edition):

Alwan, Esraa. “Enhancing the performance of decoupled software pipeline through backward slicing.” 2014. Web. 14 Oct 2019.

Vancouver:

Alwan E. Enhancing the performance of decoupled software pipeline through backward slicing. [Internet] [Doctoral dissertation]. University of Bath; 2014. [cited 2019 Oct 14]. Available from: https://researchportal.bath.ac.uk/en/studentthesis/enhancing-the-performance-of-decoupled-software-pipeline-through-backward-slicing(2ebd660d-9ee8-4429-85e6-cb21031fb64f).html ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.616651.

Council of Science Editors:

Alwan E. Enhancing the performance of decoupled software pipeline through backward slicing. [Doctoral Dissertation]. University of Bath; 2014. Available from: https://researchportal.bath.ac.uk/en/studentthesis/enhancing-the-performance-of-decoupled-software-pipeline-through-backward-slicing(2ebd660d-9ee8-4429-85e6-cb21031fb64f).html ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.616651

.