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You searched for subject:(successive approximation). Showing records 1 – 30 of 59 total matches.

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Oregon State University

1. Leung, Jerry. Data driven optimization in SAR ADC.

Degree: MS, Electrical and Computer Engineering, 2014, Oregon State University

 Recent publications show that successive approximation register (SAR) analog to digital converters (ADC) are capable of achieving high efficiency over other ADC topologies. Furthermore, techniques… (more)

Subjects/Keywords: SAR; Successive approximation analog-to-digital converters

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APA (6th Edition):

Leung, J. (2014). Data driven optimization in SAR ADC. (Masters Thesis). Oregon State University. Retrieved from http://hdl.handle.net/1957/54631

Chicago Manual of Style (16th Edition):

Leung, Jerry. “Data driven optimization in SAR ADC.” 2014. Masters Thesis, Oregon State University. Accessed October 22, 2019. http://hdl.handle.net/1957/54631.

MLA Handbook (7th Edition):

Leung, Jerry. “Data driven optimization in SAR ADC.” 2014. Web. 22 Oct 2019.

Vancouver:

Leung J. Data driven optimization in SAR ADC. [Internet] [Masters thesis]. Oregon State University; 2014. [cited 2019 Oct 22]. Available from: http://hdl.handle.net/1957/54631.

Council of Science Editors:

Leung J. Data driven optimization in SAR ADC. [Masters Thesis]. Oregon State University; 2014. Available from: http://hdl.handle.net/1957/54631


Texas A&M University

2. Gao, Yang. An Energy Efficient Asynchronous Time-Domain Comparator.

Degree: 2013, Texas A&M University

 In energy-limited applications, such as wearable battery powered systems and implantable circuits for biological applications, ultra-low power analog-to-digital converters (ADCs) are essential for sustaining long… (more)

Subjects/Keywords: Analog-to-digital converter; asynchronous circuits; comparator; successive approximation

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APA (6th Edition):

Gao, Y. (2013). An Energy Efficient Asynchronous Time-Domain Comparator. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/149314

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gao, Yang. “An Energy Efficient Asynchronous Time-Domain Comparator.” 2013. Thesis, Texas A&M University. Accessed October 22, 2019. http://hdl.handle.net/1969.1/149314.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gao, Yang. “An Energy Efficient Asynchronous Time-Domain Comparator.” 2013. Web. 22 Oct 2019.

Vancouver:

Gao Y. An Energy Efficient Asynchronous Time-Domain Comparator. [Internet] [Thesis]. Texas A&M University; 2013. [cited 2019 Oct 22]. Available from: http://hdl.handle.net/1969.1/149314.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gao Y. An Energy Efficient Asynchronous Time-Domain Comparator. [Thesis]. Texas A&M University; 2013. Available from: http://hdl.handle.net/1969.1/149314

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

3. Li, Sz-Hsien. A Wide-Range and Harmonic-Free 10-bit SAR All-Digital Delay-Locked Loop.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 This delay locked loop uses TSMC 90nm process. It uses the shift-counting type successive approximation register to control the digital delay line, which can solve… (more)

Subjects/Keywords: successive approximation register; harmonic locking; resolution; complementary; delay locked loop

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APA (6th Edition):

Li, S. (2014). A Wide-Range and Harmonic-Free 10-bit SAR All-Digital Delay-Locked Loop. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0022114-120427

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Li, Sz-Hsien. “A Wide-Range and Harmonic-Free 10-bit SAR All-Digital Delay-Locked Loop.” 2014. Thesis, NSYSU. Accessed October 22, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0022114-120427.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Li, Sz-Hsien. “A Wide-Range and Harmonic-Free 10-bit SAR All-Digital Delay-Locked Loop.” 2014. Web. 22 Oct 2019.

Vancouver:

Li S. A Wide-Range and Harmonic-Free 10-bit SAR All-Digital Delay-Locked Loop. [Internet] [Thesis]. NSYSU; 2014. [cited 2019 Oct 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0022114-120427.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li S. A Wide-Range and Harmonic-Free 10-bit SAR All-Digital Delay-Locked Loop. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0022114-120427

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

4. Huang, Hui-wen. A 10-bit 250MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

 This thesis presents the architecture of a 10-bit 250-MS/s two-step pipelined analog-to-digital converter for reducing power consumption in TSMC 90nm CMOS technology. The first stage… (more)

Subjects/Keywords: Dynamic Comparator; Bootstrapped Switch; Successive Approximation ADC; Binary Search ADC

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APA (6th Edition):

Huang, H. (2015). A 10-bit 250MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183824

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Hui-wen. “A 10-bit 250MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.” 2015. Thesis, NSYSU. Accessed October 22, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183824.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Hui-wen. “A 10-bit 250MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.” 2015. Web. 22 Oct 2019.

Vancouver:

Huang H. A 10-bit 250MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. [Internet] [Thesis]. NSYSU; 2015. [cited 2019 Oct 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183824.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang H. A 10-bit 250MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183824

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Southern Illinois University

5. Sekar, Ramgopal. LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS.

Degree: MS, Electrical and Computer Engineering, 2010, Southern Illinois University

  In this work, we investigate circuit techniques to reduce the power consumption of Successive Approximation Register Analog-to-Digital Converter (SAR-ADC). We developed four low-power SAR-ADC… (more)

Subjects/Keywords: Analog to Digital Converters; Low Power Design; Successive Approximation Register ADC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sekar, R. (2010). LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS. (Masters Thesis). Southern Illinois University. Retrieved from http://opensiuc.lib.siu.edu/theses/350

Chicago Manual of Style (16th Edition):

Sekar, Ramgopal. “LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS.” 2010. Masters Thesis, Southern Illinois University. Accessed October 22, 2019. http://opensiuc.lib.siu.edu/theses/350.

MLA Handbook (7th Edition):

Sekar, Ramgopal. “LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS.” 2010. Web. 22 Oct 2019.

Vancouver:

Sekar R. LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS. [Internet] [Masters thesis]. Southern Illinois University; 2010. [cited 2019 Oct 22]. Available from: http://opensiuc.lib.siu.edu/theses/350.

Council of Science Editors:

Sekar R. LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS. [Masters Thesis]. Southern Illinois University; 2010. Available from: http://opensiuc.lib.siu.edu/theses/350


University of Texas – Austin

6. Fontaine, Robert Alexander. Investigation of 10-bit SAR ADC using flip-flip bypass circuit.

Degree: MSin Engineering, Electrical and Computer Engineering, 2013, University of Texas – Austin

 The Successive Approximation Register (SAR) Analog to Digital Converter (ADC) is power efficient and operates at moderate resolution. However, the conversion speed is limited by… (more)

Subjects/Keywords: SAR; Successive Approximation Register; ADC; Flip-flop bypass

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APA (6th Edition):

Fontaine, R. A. (2013). Investigation of 10-bit SAR ADC using flip-flip bypass circuit. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/24011

Chicago Manual of Style (16th Edition):

Fontaine, Robert Alexander. “Investigation of 10-bit SAR ADC using flip-flip bypass circuit.” 2013. Masters Thesis, University of Texas – Austin. Accessed October 22, 2019. http://hdl.handle.net/2152/24011.

MLA Handbook (7th Edition):

Fontaine, Robert Alexander. “Investigation of 10-bit SAR ADC using flip-flip bypass circuit.” 2013. Web. 22 Oct 2019.

Vancouver:

Fontaine RA. Investigation of 10-bit SAR ADC using flip-flip bypass circuit. [Internet] [Masters thesis]. University of Texas – Austin; 2013. [cited 2019 Oct 22]. Available from: http://hdl.handle.net/2152/24011.

Council of Science Editors:

Fontaine RA. Investigation of 10-bit SAR ADC using flip-flip bypass circuit. [Masters Thesis]. University of Texas – Austin; 2013. Available from: http://hdl.handle.net/2152/24011


University of Minnesota

7. Razaviyayn, Meisam. Successive convex approximation: analysis and applications.

Degree: PhD, Electrical Engineering, 2014, University of Minnesota

 The block coordinate descent (BCD) method is widely used for minimizing a continuous function f of several block variables. At each iteration of this method,… (more)

Subjects/Keywords: Beamformer Design; Convex Optimization; Heterogeneous Networks; Sparse Dictionary Leaning; Successive Convex Approximation; Successive Upper-bound Minimization

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APA (6th Edition):

Razaviyayn, M. (2014). Successive convex approximation: analysis and applications. (Doctoral Dissertation). University of Minnesota. Retrieved from http://hdl.handle.net/11299/163884

Chicago Manual of Style (16th Edition):

Razaviyayn, Meisam. “Successive convex approximation: analysis and applications.” 2014. Doctoral Dissertation, University of Minnesota. Accessed October 22, 2019. http://hdl.handle.net/11299/163884.

MLA Handbook (7th Edition):

Razaviyayn, Meisam. “Successive convex approximation: analysis and applications.” 2014. Web. 22 Oct 2019.

Vancouver:

Razaviyayn M. Successive convex approximation: analysis and applications. [Internet] [Doctoral dissertation]. University of Minnesota; 2014. [cited 2019 Oct 22]. Available from: http://hdl.handle.net/11299/163884.

Council of Science Editors:

Razaviyayn M. Successive convex approximation: analysis and applications. [Doctoral Dissertation]. University of Minnesota; 2014. Available from: http://hdl.handle.net/11299/163884


NSYSU

8. Wang, Deng-Shian. A High-Voltage Multiplexer and A Successive-Approximation Register Analog to Digital Converter for BMS.

Degree: Master, Electrical Engineering, 2013, NSYSU

 This thesis includes two designs: A high-voltage (HV) multiplexer and a successive-approximation register ADC for Battery Management Systems (BMS). The proposed designs are implemented by… (more)

Subjects/Keywords: BMS; high-voltage multiplexer; charge redistribution architecture; successive-approximation register ADC; high-voltage switch

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APA (6th Edition):

Wang, D. (2013). A High-Voltage Multiplexer and A Successive-Approximation Register Analog to Digital Converter for BMS. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0608113-213119

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Deng-Shian. “A High-Voltage Multiplexer and A Successive-Approximation Register Analog to Digital Converter for BMS.” 2013. Thesis, NSYSU. Accessed October 22, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0608113-213119.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Deng-Shian. “A High-Voltage Multiplexer and A Successive-Approximation Register Analog to Digital Converter for BMS.” 2013. Web. 22 Oct 2019.

Vancouver:

Wang D. A High-Voltage Multiplexer and A Successive-Approximation Register Analog to Digital Converter for BMS. [Internet] [Thesis]. NSYSU; 2013. [cited 2019 Oct 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0608113-213119.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang D. A High-Voltage Multiplexer and A Successive-Approximation Register Analog to Digital Converter for BMS. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0608113-213119

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

9. Lo, Ching-Wen. High Speed SAR Analog to Digital Converter Design.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 In this thesis, the circuits are designing with TSMC 90nm CMOS process and 1.2V of supply voltage. The speed and resolution of ADC are 8-bit… (more)

Subjects/Keywords: Bootstrapped switch; Dynamic Comparator; Successive Approximation; Low power; Analog-to-Digital Converter

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lo, C. (2014). High Speed SAR Analog to Digital Converter Design. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0022114-122004

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lo, Ching-Wen. “High Speed SAR Analog to Digital Converter Design.” 2014. Thesis, NSYSU. Accessed October 22, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0022114-122004.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lo, Ching-Wen. “High Speed SAR Analog to Digital Converter Design.” 2014. Web. 22 Oct 2019.

Vancouver:

Lo C. High Speed SAR Analog to Digital Converter Design. [Internet] [Thesis]. NSYSU; 2014. [cited 2019 Oct 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0022114-122004.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lo C. High Speed SAR Analog to Digital Converter Design. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0022114-122004

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

10. Liou, Shih-Hao. All-Digital SAR-Controlled Delay-Locked Loop with Tracking System Based on Thermometer Code.

Degree: Master, Computer Science and Engineering, 2016, NSYSU

 This All-Digital delay-locked loop uses TSMC90nm process. It uses digital phase detector and successive approximation register to control the digital delay line as well as… (more)

Subjects/Keywords: binary-weighted code; successive approximation register; delay lock loop; thermometer code; low power

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APA (6th Edition):

Liou, S. (2016). All-Digital SAR-Controlled Delay-Locked Loop with Tracking System Based on Thermometer Code. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729116-130544

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liou, Shih-Hao. “All-Digital SAR-Controlled Delay-Locked Loop with Tracking System Based on Thermometer Code.” 2016. Thesis, NSYSU. Accessed October 22, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729116-130544.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liou, Shih-Hao. “All-Digital SAR-Controlled Delay-Locked Loop with Tracking System Based on Thermometer Code.” 2016. Web. 22 Oct 2019.

Vancouver:

Liou S. All-Digital SAR-Controlled Delay-Locked Loop with Tracking System Based on Thermometer Code. [Internet] [Thesis]. NSYSU; 2016. [cited 2019 Oct 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729116-130544.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liou S. All-Digital SAR-Controlled Delay-Locked Loop with Tracking System Based on Thermometer Code. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729116-130544

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

11. Liao, Yen-Qun. High Speed Low Power Two-Stage Pipelined-SAR Analog-to-Digital Converter.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

 In this thesis, the circuits are designing with TSMC.18μm CMOS process and 1.8V of supply voltage. The speed and resolution of ADC are 100MS/s and… (more)

Subjects/Keywords: Symmetry Bootstrap-switch; Dynamic comparator; Switched-Opamp; Successive Approximation ADC; Pipelined ADC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liao, Y. (2013). High Speed Low Power Two-Stage Pipelined-SAR Analog-to-Digital Converter. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0626113-144731

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liao, Yen-Qun. “High Speed Low Power Two-Stage Pipelined-SAR Analog-to-Digital Converter.” 2013. Thesis, NSYSU. Accessed October 22, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0626113-144731.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liao, Yen-Qun. “High Speed Low Power Two-Stage Pipelined-SAR Analog-to-Digital Converter.” 2013. Web. 22 Oct 2019.

Vancouver:

Liao Y. High Speed Low Power Two-Stage Pipelined-SAR Analog-to-Digital Converter. [Internet] [Thesis]. NSYSU; 2013. [cited 2019 Oct 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0626113-144731.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liao Y. High Speed Low Power Two-Stage Pipelined-SAR Analog-to-Digital Converter. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0626113-144731

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

12. Huang, Kai-chi. A 0.5 V 10-bit 500KS/s SAR ADC With MergeãSplit and Tri-Level Switching in 90 nm CMOS.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

 This thesis presents a 10-bit 500KS/s Successive Approximation Analog-to-Digital Converter (SAR ADC) for biomedical applications with a 0.5 V supply voltage which is implemented by… (more)

Subjects/Keywords: Successive Approximation ADC; Low Voltage; Low Speed; Merge and Split Switching; Tri-level Switching

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Huang, K. (2017). A 0.5 V 10-bit 500KS/s SAR ADC With MergeãSplit and Tri-Level Switching in 90 nm CMOS. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0012117-163328

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Kai-chi. “A 0.5 V 10-bit 500KS/s SAR ADC With MergeãSplit and Tri-Level Switching in 90 nm CMOS.” 2017. Thesis, NSYSU. Accessed October 22, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0012117-163328.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Kai-chi. “A 0.5 V 10-bit 500KS/s SAR ADC With MergeãSplit and Tri-Level Switching in 90 nm CMOS.” 2017. Web. 22 Oct 2019.

Vancouver:

Huang K. A 0.5 V 10-bit 500KS/s SAR ADC With MergeãSplit and Tri-Level Switching in 90 nm CMOS. [Internet] [Thesis]. NSYSU; 2017. [cited 2019 Oct 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0012117-163328.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang K. A 0.5 V 10-bit 500KS/s SAR ADC With MergeãSplit and Tri-Level Switching in 90 nm CMOS. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0012117-163328

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

13. Chen , Hsin-cheng. Implementation a Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

 A high speed and low power Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter is proposed in this thesis. Using only two stage in the proposed ADC… (more)

Subjects/Keywords: Successive Approximation ADC; Error correction; Dynamic comparator; Pipelined ADC; Additional comparator for MSB

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APA (6th Edition):

Chen , H. (2015). Implementation a Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0616115-104146

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen , Hsin-cheng. “Implementation a Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter.” 2015. Thesis, NSYSU. Accessed October 22, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0616115-104146.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen , Hsin-cheng. “Implementation a Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter.” 2015. Web. 22 Oct 2019.

Vancouver:

Chen H. Implementation a Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter. [Internet] [Thesis]. NSYSU; 2015. [cited 2019 Oct 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0616115-104146.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen H. Implementation a Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0616115-104146

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

14. Chen, Guan-Ting. A 10-bit High Speed Successive Approximation Register Analog to Digital Converter with Non-binary Error Correction, 2b/Cycle Combine with Alternate 1b/Cycle.

Degree: Master, Computer Science and Engineering, 2018, NSYSU

 In this thesis, a 10-bit resolution analog-to-digital converter with 100MHz sampling frequency is proposed. In terms of design, in order to improve the conversion speed,… (more)

Subjects/Keywords: 2b/Cycle; Non-binary Error Correction; Alternate Technique; Successive Approximation Register; Analog to Digital Converter

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, G. (2018). A 10-bit High Speed Successive Approximation Register Analog to Digital Converter with Non-binary Error Correction, 2b/Cycle Combine with Alternate 1b/Cycle. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0612118-155240

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Guan-Ting. “A 10-bit High Speed Successive Approximation Register Analog to Digital Converter with Non-binary Error Correction, 2b/Cycle Combine with Alternate 1b/Cycle.” 2018. Thesis, NSYSU. Accessed October 22, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0612118-155240.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Guan-Ting. “A 10-bit High Speed Successive Approximation Register Analog to Digital Converter with Non-binary Error Correction, 2b/Cycle Combine with Alternate 1b/Cycle.” 2018. Web. 22 Oct 2019.

Vancouver:

Chen G. A 10-bit High Speed Successive Approximation Register Analog to Digital Converter with Non-binary Error Correction, 2b/Cycle Combine with Alternate 1b/Cycle. [Internet] [Thesis]. NSYSU; 2018. [cited 2019 Oct 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0612118-155240.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen G. A 10-bit High Speed Successive Approximation Register Analog to Digital Converter with Non-binary Error Correction, 2b/Cycle Combine with Alternate 1b/Cycle. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0612118-155240

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Tech

15. Ojha, Abhi. Coupled Natural Gas and Electric Power Systems.

Degree: MS, Electrical and Computer Engineering, 2017, Virginia Tech

 Decreasing gas prices and the pressing need for fast-responding electric power generators are currently transforming natural gas networks. The intermittent operation of gas-fired plants to… (more)

Subjects/Keywords: Successive convex approximation; semidefinite programming; feasible point pursuit; alternating direction method of multipliers

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ojha, A. (2017). Coupled Natural Gas and Electric Power Systems. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/78666

Chicago Manual of Style (16th Edition):

Ojha, Abhi. “Coupled Natural Gas and Electric Power Systems.” 2017. Masters Thesis, Virginia Tech. Accessed October 22, 2019. http://hdl.handle.net/10919/78666.

MLA Handbook (7th Edition):

Ojha, Abhi. “Coupled Natural Gas and Electric Power Systems.” 2017. Web. 22 Oct 2019.

Vancouver:

Ojha A. Coupled Natural Gas and Electric Power Systems. [Internet] [Masters thesis]. Virginia Tech; 2017. [cited 2019 Oct 22]. Available from: http://hdl.handle.net/10919/78666.

Council of Science Editors:

Ojha A. Coupled Natural Gas and Electric Power Systems. [Masters Thesis]. Virginia Tech; 2017. Available from: http://hdl.handle.net/10919/78666


NSYSU

16. Chen, Yan-Lin. A Low Power 10-bit Dual-Mode Successive Approximation Register Analog to Digital Converter with the Image Correction Ability for the CMOS Image Sensor.

Degree: Master, Computer Science and Engineering, 2018, NSYSU

 In this thesis, a 10-bit, 10 MS/s dual-mode analog-to-digital converter with a 1.8 V supply voltage is implemented by using the TSMC 0.18ï­m process technology.… (more)

Subjects/Keywords: Dual-Mode; Edge Image; Image Sensor; Analog to Digital Converter; Successive Approximation Register

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, Y. (2018). A Low Power 10-bit Dual-Mode Successive Approximation Register Analog to Digital Converter with the Image Correction Ability for the CMOS Image Sensor. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-132437

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Yan-Lin. “A Low Power 10-bit Dual-Mode Successive Approximation Register Analog to Digital Converter with the Image Correction Ability for the CMOS Image Sensor.” 2018. Thesis, NSYSU. Accessed October 22, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-132437.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Yan-Lin. “A Low Power 10-bit Dual-Mode Successive Approximation Register Analog to Digital Converter with the Image Correction Ability for the CMOS Image Sensor.” 2018. Web. 22 Oct 2019.

Vancouver:

Chen Y. A Low Power 10-bit Dual-Mode Successive Approximation Register Analog to Digital Converter with the Image Correction Ability for the CMOS Image Sensor. [Internet] [Thesis]. NSYSU; 2018. [cited 2019 Oct 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-132437.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen Y. A Low Power 10-bit Dual-Mode Successive Approximation Register Analog to Digital Converter with the Image Correction Ability for the CMOS Image Sensor. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0729118-132437

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

17. Shah, Aarti Mahesh Kumar. Successive-approximation-register based quantizer design for high-speed delta-sigma modulators.

Degree: MS, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 High-speed delta-sigma modulators are in high demand for applications such as wire-line and wireless communications, medical imaging, RF receivers and high-definition video processing. A high-speed… (more)

Subjects/Keywords: Analog-to-digital converters; High speed successive approximation register (SAR); Delta-sigma modulators; Quantizer; Medium resolution successive approximation register (SAR); Time-interleaved successive approximation register (TI SAR); Time-interleaved analog-to-digital converter (ADC); Higher order delta-sigma modulator design; Delta-sigma simulink models; Successive approximation register analog-to-digital converter (SAR ADC) design

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APA (6th Edition):

Shah, A. M. K. (2017). Successive-approximation-register based quantizer design for high-speed delta-sigma modulators. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/97465

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shah, Aarti Mahesh Kumar. “Successive-approximation-register based quantizer design for high-speed delta-sigma modulators.” 2017. Thesis, University of Illinois – Urbana-Champaign. Accessed October 22, 2019. http://hdl.handle.net/2142/97465.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shah, Aarti Mahesh Kumar. “Successive-approximation-register based quantizer design for high-speed delta-sigma modulators.” 2017. Web. 22 Oct 2019.

Vancouver:

Shah AMK. Successive-approximation-register based quantizer design for high-speed delta-sigma modulators. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2017. [cited 2019 Oct 22]. Available from: http://hdl.handle.net/2142/97465.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shah AMK. Successive-approximation-register based quantizer design for high-speed delta-sigma modulators. [Thesis]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/97465

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Michigan

18. Fredenburg, Jeffrey Alan. Noise-Shaping SAR ADCs.

Degree: PhD, Electrical Engineering, 2015, University of Michigan

 This work investigates hybrid analog-to-digital converters (ADCs) that combine the phenomenal energy efficiency of successive-approximation (SAR) ADCs with the resolution enhancement strategies used by noise-shaping… (more)

Subjects/Keywords: Analog-to-Digital Converter; Noise-shaping SAR; Successive-approximation ADC; Analog Circuits; Electrical Engineering; Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Fredenburg, J. A. (2015). Noise-Shaping SAR ADCs. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/113647

Chicago Manual of Style (16th Edition):

Fredenburg, Jeffrey Alan. “Noise-Shaping SAR ADCs.” 2015. Doctoral Dissertation, University of Michigan. Accessed October 22, 2019. http://hdl.handle.net/2027.42/113647.

MLA Handbook (7th Edition):

Fredenburg, Jeffrey Alan. “Noise-Shaping SAR ADCs.” 2015. Web. 22 Oct 2019.

Vancouver:

Fredenburg JA. Noise-Shaping SAR ADCs. [Internet] [Doctoral dissertation]. University of Michigan; 2015. [cited 2019 Oct 22]. Available from: http://hdl.handle.net/2027.42/113647.

Council of Science Editors:

Fredenburg JA. Noise-Shaping SAR ADCs. [Doctoral Dissertation]. University of Michigan; 2015. Available from: http://hdl.handle.net/2027.42/113647


University of Toronto

19. Cheeseman, Alison. Adaptive Waveform Design and CFAR Processing for High Frequency Surface Wave Radar.

Degree: 2017, University of Toronto

High frequency surface wave radar (HFSWR), used for coastal surveillance, operates in a challenging environment as the clutter signals returned from the ocean surface can… (more)

Subjects/Keywords: alternating projections; CFAR; radar; sea clutter; spectral coexistence; successive convex approximation; 0544

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APA (6th Edition):

Cheeseman, A. (2017). Adaptive Waveform Design and CFAR Processing for High Frequency Surface Wave Radar. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/79106

Chicago Manual of Style (16th Edition):

Cheeseman, Alison. “Adaptive Waveform Design and CFAR Processing for High Frequency Surface Wave Radar.” 2017. Masters Thesis, University of Toronto. Accessed October 22, 2019. http://hdl.handle.net/1807/79106.

MLA Handbook (7th Edition):

Cheeseman, Alison. “Adaptive Waveform Design and CFAR Processing for High Frequency Surface Wave Radar.” 2017. Web. 22 Oct 2019.

Vancouver:

Cheeseman A. Adaptive Waveform Design and CFAR Processing for High Frequency Surface Wave Radar. [Internet] [Masters thesis]. University of Toronto; 2017. [cited 2019 Oct 22]. Available from: http://hdl.handle.net/1807/79106.

Council of Science Editors:

Cheeseman A. Adaptive Waveform Design and CFAR Processing for High Frequency Surface Wave Radar. [Masters Thesis]. University of Toronto; 2017. Available from: http://hdl.handle.net/1807/79106


University of Michigan

20. Collins, Nicholas. Mismatch-Immune Successive-Approximation Techniques for Nanometer CMOS ADCs.

Degree: PhD, Electrical Engineering, 2017, University of Michigan

 During the past decade, SAR ADCs have enjoyed increasing prominence due to their inherently scaling-friendly architecture. Several recent SAR ADC innovations focus on decreasing power… (more)

Subjects/Keywords: Mismatch in SAR ADCs; Mismatch in Successive Approximation Analog-to-Digital Converters; Electrical Engineering; Engineering

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APA (6th Edition):

Collins, N. (2017). Mismatch-Immune Successive-Approximation Techniques for Nanometer CMOS ADCs. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/138630

Chicago Manual of Style (16th Edition):

Collins, Nicholas. “Mismatch-Immune Successive-Approximation Techniques for Nanometer CMOS ADCs.” 2017. Doctoral Dissertation, University of Michigan. Accessed October 22, 2019. http://hdl.handle.net/2027.42/138630.

MLA Handbook (7th Edition):

Collins, Nicholas. “Mismatch-Immune Successive-Approximation Techniques for Nanometer CMOS ADCs.” 2017. Web. 22 Oct 2019.

Vancouver:

Collins N. Mismatch-Immune Successive-Approximation Techniques for Nanometer CMOS ADCs. [Internet] [Doctoral dissertation]. University of Michigan; 2017. [cited 2019 Oct 22]. Available from: http://hdl.handle.net/2027.42/138630.

Council of Science Editors:

Collins N. Mismatch-Immune Successive-Approximation Techniques for Nanometer CMOS ADCs. [Doctoral Dissertation]. University of Michigan; 2017. Available from: http://hdl.handle.net/2027.42/138630


University of Pretoria

21. Motsamai, O.S. (Oboetswe Seraga). Optimisation techniques for combustor design.

Degree: Mechanical and Aeronautical Engineering, 2009, University of Pretoria

 For gas turbines, the demand for high-performance, more efficient and longer-life turbine blades is increasing. This is especially so, now that there is a need… (more)

Subjects/Keywords: Successive approximation algorithm; Mathematical optimisation; Computational fluid dynamics; Gradient-based optimisation algorithm; Combustor exit temperature profile; Temperature profile; Design methodology; UCTD

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Motsamai, O. S. (. (2009). Optimisation techniques for combustor design. (Doctoral Dissertation). University of Pretoria. Retrieved from http://hdl.handle.net/2263/23827

Chicago Manual of Style (16th Edition):

Motsamai, O S (Oboetswe. “Optimisation techniques for combustor design.” 2009. Doctoral Dissertation, University of Pretoria. Accessed October 22, 2019. http://hdl.handle.net/2263/23827.

MLA Handbook (7th Edition):

Motsamai, O S (Oboetswe. “Optimisation techniques for combustor design.” 2009. Web. 22 Oct 2019.

Vancouver:

Motsamai OS(. Optimisation techniques for combustor design. [Internet] [Doctoral dissertation]. University of Pretoria; 2009. [cited 2019 Oct 22]. Available from: http://hdl.handle.net/2263/23827.

Council of Science Editors:

Motsamai OS(. Optimisation techniques for combustor design. [Doctoral Dissertation]. University of Pretoria; 2009. Available from: http://hdl.handle.net/2263/23827


NSYSU

22. Bai, Je-Wei. A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction.

Degree: Master, Computer Science and Engineering, 2016, NSYSU

 In this thesis, a 10-bit, 80 MS/s analog-to-digital converter with a 1 V supply voltage is implemented by using the TSMC 90nm process technology. This… (more)

Subjects/Keywords: non-binary digital error correction; digital error correction; 2b/Cycle; Successive Approximation Register; Analog to Digital Converter

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bai, J. (2016). A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725116-155819

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bai, Je-Wei. “A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction.” 2016. Thesis, NSYSU. Accessed October 22, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725116-155819.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bai, Je-Wei. “A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction.” 2016. Web. 22 Oct 2019.

Vancouver:

Bai J. A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction. [Internet] [Thesis]. NSYSU; 2016. [cited 2019 Oct 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725116-155819.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bai J. A 10-bit high speed Successive Approximation Register Analog to Digital Converter with 2 bit per cycle and non-binary digital error correction. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725116-155819

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

23. Chung, Meng-hsun. A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

 In this thesis, a 10-bit binary search assisted time-interleaved SAR ADC operating in 250Ms/s sampling rate with 1.2 supply voltage is presented. The ADC adopt… (more)

Subjects/Keywords: Analog-to-Digital Converter; ADC; Binary-Search ADC; Successive Approximation; SAR ADC; Time-Interleaved; Non-overlapping circuit

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APA (6th Edition):

Chung, M. (2015). A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183859

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chung, Meng-hsun. “A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.” 2015. Thesis, NSYSU. Accessed October 22, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183859.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chung, Meng-hsun. “A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.” 2015. Web. 22 Oct 2019.

Vancouver:

Chung M. A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. [Internet] [Thesis]. NSYSU; 2015. [cited 2019 Oct 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183859.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chung M. A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183859

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

24. Juan, Sung-lin. Low Power/Wideband With Tracking System All-Digital Phase Locked Loop Research.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

 This All-Digital phase-locked loop uses TSMC90nm process. It uses digital frequency detector and successive approximation register to control the digitally controlled oscillator as well as… (more)

Subjects/Keywords: low power; digitally controlled oscillator; successive approximation register; digital frequency detector; all digital phase-locked loop

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APA (6th Edition):

Juan, S. (2015). Low Power/Wideband With Tracking System All-Digital Phase Locked Loop Research. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623115-163614

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Juan, Sung-lin. “Low Power/Wideband With Tracking System All-Digital Phase Locked Loop Research.” 2015. Thesis, NSYSU. Accessed October 22, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623115-163614.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Juan, Sung-lin. “Low Power/Wideband With Tracking System All-Digital Phase Locked Loop Research.” 2015. Web. 22 Oct 2019.

Vancouver:

Juan S. Low Power/Wideband With Tracking System All-Digital Phase Locked Loop Research. [Internet] [Thesis]. NSYSU; 2015. [cited 2019 Oct 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623115-163614.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Juan S. Low Power/Wideband With Tracking System All-Digital Phase Locked Loop Research. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0623115-163614

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Pretoria

25. [No author]. Optimisation techniques for combustor design .

Degree: 2009, University of Pretoria

 For gas turbines, the demand for high-performance, more efficient and longer-life turbine blades is increasing. This is especially so, now that there is a need… (more)

Subjects/Keywords: Successive approximation algorithm; Mathematical optimisation; Computational fluid dynamics; Gradient-based optimisation algorithm; Combustor exit temperature profile; Temperature profile; Design methodology; UCTD

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

author], [. (2009). Optimisation techniques for combustor design . (Doctoral Dissertation). University of Pretoria. Retrieved from http://upetd.up.ac.za/thesis/available/etd-04072009-222336/

Chicago Manual of Style (16th Edition):

author], [No. “Optimisation techniques for combustor design .” 2009. Doctoral Dissertation, University of Pretoria. Accessed October 22, 2019. http://upetd.up.ac.za/thesis/available/etd-04072009-222336/.

MLA Handbook (7th Edition):

author], [No. “Optimisation techniques for combustor design .” 2009. Web. 22 Oct 2019.

Vancouver:

author] [. Optimisation techniques for combustor design . [Internet] [Doctoral dissertation]. University of Pretoria; 2009. [cited 2019 Oct 22]. Available from: http://upetd.up.ac.za/thesis/available/etd-04072009-222336/.

Council of Science Editors:

author] [. Optimisation techniques for combustor design . [Doctoral Dissertation]. University of Pretoria; 2009. Available from: http://upetd.up.ac.za/thesis/available/etd-04072009-222336/


Universidade do Rio Grande do Sul

26. Lanot, Alisson Jamie Cruz. Estudo de falhas transientes e técnicas de tolerância a falhas em conversores de dados do tipo SAR baseados em redistribuição de carga.

Degree: 2014, Universidade do Rio Grande do Sul

Conversores A/D do tipo aproximações sucessivas (SAR) baseados em redistribuição de carga são frequentemente utilizados em aplicações envolvendo a aquisição de sinais, principalmente as que… (more)

Subjects/Keywords: Analog to digital converters; Conversor analogico/digital; Circuitos integrados; Successive approximation register; Single event effects; Single event transients; Fault mitigation techniques

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lanot, A. J. C. (2014). Estudo de falhas transientes e técnicas de tolerância a falhas em conversores de dados do tipo SAR baseados em redistribuição de carga. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/114478

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lanot, Alisson Jamie Cruz. “Estudo de falhas transientes e técnicas de tolerância a falhas em conversores de dados do tipo SAR baseados em redistribuição de carga.” 2014. Thesis, Universidade do Rio Grande do Sul. Accessed October 22, 2019. http://hdl.handle.net/10183/114478.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lanot, Alisson Jamie Cruz. “Estudo de falhas transientes e técnicas de tolerância a falhas em conversores de dados do tipo SAR baseados em redistribuição de carga.” 2014. Web. 22 Oct 2019.

Vancouver:

Lanot AJC. Estudo de falhas transientes e técnicas de tolerância a falhas em conversores de dados do tipo SAR baseados em redistribuição de carga. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2014. [cited 2019 Oct 22]. Available from: http://hdl.handle.net/10183/114478.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lanot AJC. Estudo de falhas transientes e técnicas de tolerância a falhas em conversores de dados do tipo SAR baseados em redistribuição de carga. [Thesis]. Universidade do Rio Grande do Sul; 2014. Available from: http://hdl.handle.net/10183/114478

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

27. Xie, Shan-yang. Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop.

Degree: Master, Computer Science and Engineering, 2018, NSYSU

 This All-Digital phase-locked loop uses TSMC90nm process. It uses digital frequency detector and successive approximation register to control the digitally controlled oscillator as well as… (more)

Subjects/Keywords: low power schmitt trigger inverter; digitally controlled oscillator; all digital phase-locked loop; digital frequency detector; successive approximation register

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Xie, S. (2018). Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0101118-101614

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Xie, Shan-yang. “Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop.” 2018. Thesis, NSYSU. Accessed October 22, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0101118-101614.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Xie, Shan-yang. “Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop.” 2018. Web. 22 Oct 2019.

Vancouver:

Xie S. Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop. [Internet] [Thesis]. NSYSU; 2018. [cited 2019 Oct 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0101118-101614.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Xie S. Low Resolution/ Power With Tracking System All-Digital Phase Locked Loop. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0101118-101614

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Linköping University

28. Zhang, Dai. Design and Evaluation of an Ultra-Low Power Successive Approximation ADC.

Degree: Electrical Engineering, 2009, Linköping University

  Analog-to-digital converters (ADC) targeted for use in medical implant devices serve an important role as the interface between analog signal and digital processing system.… (more)

Subjects/Keywords: Analog-to-digital converter (ADC); charge redistribution; CMOS; low power; low supply voltage; successive approximation; latched comparator; Electrical engineering; Elektroteknik

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhang, D. (2009). Design and Evaluation of an Ultra-Low Power Successive Approximation ADC. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18219

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhang, Dai. “Design and Evaluation of an Ultra-Low Power Successive Approximation ADC.” 2009. Thesis, Linköping University. Accessed October 22, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18219.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhang, Dai. “Design and Evaluation of an Ultra-Low Power Successive Approximation ADC.” 2009. Web. 22 Oct 2019.

Vancouver:

Zhang D. Design and Evaluation of an Ultra-Low Power Successive Approximation ADC. [Internet] [Thesis]. Linköping University; 2009. [cited 2019 Oct 22]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18219.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhang D. Design and Evaluation of an Ultra-Low Power Successive Approximation ADC. [Thesis]. Linköping University; 2009. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18219

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

29. Wu, Ching-Feng. Implementation of a 10-bit SAR ADC With Merge, Split, and Tri-Level Switching using Mortise-Tenon Structure Capacitor.

Degree: Master, Computer Science and Engineering, 2018, NSYSU

 This thesis presents a 10-bit 500 KS/s Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for biomedical application with a 0.5 V supply voltage which is… (more)

Subjects/Keywords: Successive Approximation Register ADC; Merge and Split Switching; Dummy Input Pair; Parasitic Minimization; Low Voltage; Mortise-Tenon structure; Tri-level Switching

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu, C. (2018). Implementation of a 10-bit SAR ADC With Merge, Split, and Tri-Level Switching using Mortise-Tenon Structure Capacitor. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0520118-082221

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Ching-Feng. “Implementation of a 10-bit SAR ADC With Merge, Split, and Tri-Level Switching using Mortise-Tenon Structure Capacitor.” 2018. Thesis, NSYSU. Accessed October 22, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0520118-082221.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Ching-Feng. “Implementation of a 10-bit SAR ADC With Merge, Split, and Tri-Level Switching using Mortise-Tenon Structure Capacitor.” 2018. Web. 22 Oct 2019.

Vancouver:

Wu C. Implementation of a 10-bit SAR ADC With Merge, Split, and Tri-Level Switching using Mortise-Tenon Structure Capacitor. [Internet] [Thesis]. NSYSU; 2018. [cited 2019 Oct 22]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0520118-082221.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu C. Implementation of a 10-bit SAR ADC With Merge, Split, and Tri-Level Switching using Mortise-Tenon Structure Capacitor. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0520118-082221

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

30. Wu, Chao ECE. A single-channel high-speed pipelined-SAR ADC with an open-loop MDAC.

Degree: 2018, Hong Kong University of Science and Technology

 High-speed high-precision analog-to-digital converters (ADCs) are widely used in the fields of image processing, information storage and wireless communication. To achieve high speed and high… (more)

Subjects/Keywords: Analog-to-digital converters; Successive approximation analog-to-digital converters; Signal processing; Digital techniques; Real-time data processing; Electronic data processing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu, C. E. (2018). A single-channel high-speed pipelined-SAR ADC with an open-loop MDAC. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-991012615563203412 ; http://repository.ust.hk/ir/bitstream/1783.1-93162/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Chao ECE. “A single-channel high-speed pipelined-SAR ADC with an open-loop MDAC.” 2018. Thesis, Hong Kong University of Science and Technology. Accessed October 22, 2019. https://doi.org/10.14711/thesis-991012615563203412 ; http://repository.ust.hk/ir/bitstream/1783.1-93162/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Chao ECE. “A single-channel high-speed pipelined-SAR ADC with an open-loop MDAC.” 2018. Web. 22 Oct 2019.

Vancouver:

Wu CE. A single-channel high-speed pipelined-SAR ADC with an open-loop MDAC. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2018. [cited 2019 Oct 22]. Available from: https://doi.org/10.14711/thesis-991012615563203412 ; http://repository.ust.hk/ir/bitstream/1783.1-93162/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu CE. A single-channel high-speed pipelined-SAR ADC with an open-loop MDAC. [Thesis]. Hong Kong University of Science and Technology; 2018. Available from: https://doi.org/10.14711/thesis-991012615563203412 ; http://repository.ust.hk/ir/bitstream/1783.1-93162/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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