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You searched for subject:(successive approximation ADC). Showing records 1 – 26 of 26 total matches.

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NSYSU

1. Huang, Hui-wen. A 10-bit 250MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

 This thesis presents the architecture of a 10-bit 250-MS/s two-step pipelined analog-to-digital converter for reducing power consumption in TSMC 90nm CMOS technology. The first stage… (more)

Subjects/Keywords: Dynamic Comparator; Bootstrapped Switch; Successive Approximation ADC; Binary Search ADC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Huang, H. (2015). A 10-bit 250MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183824

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Hui-wen. “A 10-bit 250MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.” 2015. Thesis, NSYSU. Accessed April 18, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183824.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Hui-wen. “A 10-bit 250MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.” 2015. Web. 18 Apr 2021.

Vancouver:

Huang H. A 10-bit 250MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. [Internet] [Thesis]. NSYSU; 2015. [cited 2021 Apr 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183824.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang H. A 10-bit 250MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183824

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

2. Liao, Yen-Qun. High Speed Low Power Two-Stage Pipelined-SAR Analog-to-Digital Converter.

Degree: Master, Computer Science and Engineering, 2013, NSYSU

 In this thesis, the circuits are designing with TSMC.18μm CMOS process and 1.8V of supply voltage. The speed and resolution of ADC are 100MS/s and… (more)

Subjects/Keywords: Symmetry Bootstrap-switch; Dynamic comparator; Switched-Opamp; Successive Approximation ADC; Pipelined ADC

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APA (6th Edition):

Liao, Y. (2013). High Speed Low Power Two-Stage Pipelined-SAR Analog-to-Digital Converter. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0626113-144731

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liao, Yen-Qun. “High Speed Low Power Two-Stage Pipelined-SAR Analog-to-Digital Converter.” 2013. Thesis, NSYSU. Accessed April 18, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0626113-144731.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liao, Yen-Qun. “High Speed Low Power Two-Stage Pipelined-SAR Analog-to-Digital Converter.” 2013. Web. 18 Apr 2021.

Vancouver:

Liao Y. High Speed Low Power Two-Stage Pipelined-SAR Analog-to-Digital Converter. [Internet] [Thesis]. NSYSU; 2013. [cited 2021 Apr 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0626113-144731.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liao Y. High Speed Low Power Two-Stage Pipelined-SAR Analog-to-Digital Converter. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0626113-144731

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

3. Chen , Hsin-cheng. Implementation a Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

 A high speed and low power Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter is proposed in this thesis. Using only two stage in the proposed ADC(more)

Subjects/Keywords: Successive Approximation ADC; Error correction; Dynamic comparator; Pipelined ADC; Additional comparator for MSB

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen , H. (2015). Implementation a Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0616115-104146

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen , Hsin-cheng. “Implementation a Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter.” 2015. Thesis, NSYSU. Accessed April 18, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0616115-104146.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen , Hsin-cheng. “Implementation a Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter.” 2015. Web. 18 Apr 2021.

Vancouver:

Chen H. Implementation a Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter. [Internet] [Thesis]. NSYSU; 2015. [cited 2021 Apr 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0616115-104146.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen H. Implementation a Two-Stage Pipelined Successive Approximation Analog-to-Digital Converter. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0616115-104146

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Texas – Austin

4. Fontaine, Robert Alexander. Investigation of 10-bit SAR ADC using flip-flip bypass circuit.

Degree: MSin Engineering, Electrical and Computer Engineering, 2013, University of Texas – Austin

 The Successive Approximation Register (SAR) Analog to Digital Converter (ADC) is power efficient and operates at moderate resolution. However, the conversion speed is limited by… (more)

Subjects/Keywords: SAR; Successive Approximation Register; ADC; Flip-flop bypass

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APA (6th Edition):

Fontaine, R. A. (2013). Investigation of 10-bit SAR ADC using flip-flip bypass circuit. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/24011

Chicago Manual of Style (16th Edition):

Fontaine, Robert Alexander. “Investigation of 10-bit SAR ADC using flip-flip bypass circuit.” 2013. Masters Thesis, University of Texas – Austin. Accessed April 18, 2021. http://hdl.handle.net/2152/24011.

MLA Handbook (7th Edition):

Fontaine, Robert Alexander. “Investigation of 10-bit SAR ADC using flip-flip bypass circuit.” 2013. Web. 18 Apr 2021.

Vancouver:

Fontaine RA. Investigation of 10-bit SAR ADC using flip-flip bypass circuit. [Internet] [Masters thesis]. University of Texas – Austin; 2013. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/2152/24011.

Council of Science Editors:

Fontaine RA. Investigation of 10-bit SAR ADC using flip-flip bypass circuit. [Masters Thesis]. University of Texas – Austin; 2013. Available from: http://hdl.handle.net/2152/24011


NSYSU

5. Chung, Meng-hsun. A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

 In this thesis, a 10-bit binary search assisted time-interleaved SAR ADC operating in 250Ms/s sampling rate with 1.2 supply voltage is presented. The ADC adopt… (more)

Subjects/Keywords: Analog-to-Digital Converter; ADC; Binary-Search ADC; Successive Approximation; SAR ADC; Time-Interleaved; Non-overlapping circuit

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chung, M. (2015). A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183859

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chung, Meng-hsun. “A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.” 2015. Thesis, NSYSU. Accessed April 18, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183859.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chung, Meng-hsun. “A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC.” 2015. Web. 18 Apr 2021.

Vancouver:

Chung M. A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. [Internet] [Thesis]. NSYSU; 2015. [cited 2021 Apr 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183859.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chung M. A High-Speed Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0622115-183859

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

6. Wang, Deng-Shian. A High-Voltage Multiplexer and A Successive-Approximation Register Analog to Digital Converter for BMS.

Degree: Master, Electrical Engineering, 2013, NSYSU

 This thesis includes two designs: A high-voltage (HV) multiplexer and a successive-approximation register ADC for Battery Management Systems (BMS). The proposed designs are implemented by… (more)

Subjects/Keywords: BMS; high-voltage multiplexer; charge redistribution architecture; successive-approximation register ADC; high-voltage switch

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APA (6th Edition):

Wang, D. (2013). A High-Voltage Multiplexer and A Successive-Approximation Register Analog to Digital Converter for BMS. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0608113-213119

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Deng-Shian. “A High-Voltage Multiplexer and A Successive-Approximation Register Analog to Digital Converter for BMS.” 2013. Thesis, NSYSU. Accessed April 18, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0608113-213119.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Deng-Shian. “A High-Voltage Multiplexer and A Successive-Approximation Register Analog to Digital Converter for BMS.” 2013. Web. 18 Apr 2021.

Vancouver:

Wang D. A High-Voltage Multiplexer and A Successive-Approximation Register Analog to Digital Converter for BMS. [Internet] [Thesis]. NSYSU; 2013. [cited 2021 Apr 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0608113-213119.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang D. A High-Voltage Multiplexer and A Successive-Approximation Register Analog to Digital Converter for BMS. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0608113-213119

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

7. Huang, Kai-chi. A 0.5 V 10-bit 500KS/s SAR ADC With MergeãSplit and Tri-Level Switching in 90 nm CMOS.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

 This thesis presents a 10-bit 500KS/s Successive Approximation Analog-to-Digital Converter (SAR ADC) for biomedical applications with a 0.5 V supply voltage which is implemented by… (more)

Subjects/Keywords: Successive Approximation ADC; Low Voltage; Low Speed; Merge and Split Switching; Tri-level Switching

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Huang, K. (2017). A 0.5 V 10-bit 500KS/s SAR ADC With MergeãSplit and Tri-Level Switching in 90 nm CMOS. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0012117-163328

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Kai-chi. “A 0.5 V 10-bit 500KS/s SAR ADC With MergeãSplit and Tri-Level Switching in 90 nm CMOS.” 2017. Thesis, NSYSU. Accessed April 18, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0012117-163328.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Kai-chi. “A 0.5 V 10-bit 500KS/s SAR ADC With MergeãSplit and Tri-Level Switching in 90 nm CMOS.” 2017. Web. 18 Apr 2021.

Vancouver:

Huang K. A 0.5 V 10-bit 500KS/s SAR ADC With MergeãSplit and Tri-Level Switching in 90 nm CMOS. [Internet] [Thesis]. NSYSU; 2017. [cited 2021 Apr 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0012117-163328.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang K. A 0.5 V 10-bit 500KS/s SAR ADC With MergeãSplit and Tri-Level Switching in 90 nm CMOS. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0012117-163328

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Michigan

8. Fredenburg, Jeffrey Alan. Noise-Shaping SAR ADCs.

Degree: PhD, Electrical Engineering, 2015, University of Michigan

 This work investigates hybrid analog-to-digital converters (ADCs) that combine the phenomenal energy efficiency of successive-approximation (SAR) ADCs with the resolution enhancement strategies used by noise-shaping… (more)

Subjects/Keywords: Analog-to-Digital Converter; Noise-shaping SAR; Successive-approximation ADC; Analog Circuits; Electrical Engineering; Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Fredenburg, J. A. (2015). Noise-Shaping SAR ADCs. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/113647

Chicago Manual of Style (16th Edition):

Fredenburg, Jeffrey Alan. “Noise-Shaping SAR ADCs.” 2015. Doctoral Dissertation, University of Michigan. Accessed April 18, 2021. http://hdl.handle.net/2027.42/113647.

MLA Handbook (7th Edition):

Fredenburg, Jeffrey Alan. “Noise-Shaping SAR ADCs.” 2015. Web. 18 Apr 2021.

Vancouver:

Fredenburg JA. Noise-Shaping SAR ADCs. [Internet] [Doctoral dissertation]. University of Michigan; 2015. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/2027.42/113647.

Council of Science Editors:

Fredenburg JA. Noise-Shaping SAR ADCs. [Doctoral Dissertation]. University of Michigan; 2015. Available from: http://hdl.handle.net/2027.42/113647


University of Illinois – Urbana-Champaign

9. Shah, Aarti Mahesh Kumar. Successive-approximation-register based quantizer design for high-speed delta-sigma modulators.

Degree: MS, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 High-speed delta-sigma modulators are in high demand for applications such as wire-line and wireless communications, medical imaging, RF receivers and high-definition video processing. A high-speed… (more)

Subjects/Keywords: Analog-to-digital converters; High speed successive approximation register (SAR); Delta-sigma modulators; Quantizer; Medium resolution successive approximation register (SAR); Time-interleaved successive approximation register (TI SAR); Time-interleaved analog-to-digital converter (ADC); Higher order delta-sigma modulator design; Delta-sigma simulink models; Successive approximation register analog-to-digital converter (SAR ADC) design

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shah, A. M. K. (2017). Successive-approximation-register based quantizer design for high-speed delta-sigma modulators. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/97465

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shah, Aarti Mahesh Kumar. “Successive-approximation-register based quantizer design for high-speed delta-sigma modulators.” 2017. Thesis, University of Illinois – Urbana-Champaign. Accessed April 18, 2021. http://hdl.handle.net/2142/97465.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shah, Aarti Mahesh Kumar. “Successive-approximation-register based quantizer design for high-speed delta-sigma modulators.” 2017. Web. 18 Apr 2021.

Vancouver:

Shah AMK. Successive-approximation-register based quantizer design for high-speed delta-sigma modulators. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/2142/97465.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shah AMK. Successive-approximation-register based quantizer design for high-speed delta-sigma modulators. [Thesis]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/97465

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Texas – Austin

10. Li, Shaolan. High-performance oversampling A/D converter design techniques in scaled CMOS technologies.

Degree: PhD, Electrical and Computer Engineering, 2018, University of Texas – Austin

 Oversampling analog-to-digital converters (ADCs) are specialists in digitizing real-word signals in high resolution. They have been crucial building blocks in many modern electronic systems, and… (more)

Subjects/Keywords: Analog-to-digital converters (ADC); Oversampling ADC; Delta-Sigma ADC; Successive approximation register (SAR) ADC; Noise-shaping SAR ADC; Voltage-controlled-oscillator (VCO); VCO-based ADC; Dynamic amplifier; Mixed-signal integrated circuit

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Li, S. (2018). High-performance oversampling A/D converter design techniques in scaled CMOS technologies. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://dx.doi.org/10.26153/tsw/11686

Chicago Manual of Style (16th Edition):

Li, Shaolan. “High-performance oversampling A/D converter design techniques in scaled CMOS technologies.” 2018. Doctoral Dissertation, University of Texas – Austin. Accessed April 18, 2021. http://dx.doi.org/10.26153/tsw/11686.

MLA Handbook (7th Edition):

Li, Shaolan. “High-performance oversampling A/D converter design techniques in scaled CMOS technologies.” 2018. Web. 18 Apr 2021.

Vancouver:

Li S. High-performance oversampling A/D converter design techniques in scaled CMOS technologies. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2018. [cited 2021 Apr 18]. Available from: http://dx.doi.org/10.26153/tsw/11686.

Council of Science Editors:

Li S. High-performance oversampling A/D converter design techniques in scaled CMOS technologies. [Doctoral Dissertation]. University of Texas – Austin; 2018. Available from: http://dx.doi.org/10.26153/tsw/11686


NSYSU

11. Wu, Ching-Feng. Implementation of a 10-bit SAR ADC With Merge, Split, and Tri-Level Switching using Mortise-Tenon Structure Capacitor.

Degree: Master, Computer Science and Engineering, 2018, NSYSU

 This thesis presents a 10-bit 500 KS/s Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for biomedical application with a 0.5 V supply voltage which is… (more)

Subjects/Keywords: Successive Approximation Register ADC; Merge and Split Switching; Dummy Input Pair; Parasitic Minimization; Low Voltage; Mortise-Tenon structure; Tri-level Switching

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu, C. (2018). Implementation of a 10-bit SAR ADC With Merge, Split, and Tri-Level Switching using Mortise-Tenon Structure Capacitor. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0520118-082221

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Ching-Feng. “Implementation of a 10-bit SAR ADC With Merge, Split, and Tri-Level Switching using Mortise-Tenon Structure Capacitor.” 2018. Thesis, NSYSU. Accessed April 18, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0520118-082221.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Ching-Feng. “Implementation of a 10-bit SAR ADC With Merge, Split, and Tri-Level Switching using Mortise-Tenon Structure Capacitor.” 2018. Web. 18 Apr 2021.

Vancouver:

Wu C. Implementation of a 10-bit SAR ADC With Merge, Split, and Tri-Level Switching using Mortise-Tenon Structure Capacitor. [Internet] [Thesis]. NSYSU; 2018. [cited 2021 Apr 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0520118-082221.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu C. Implementation of a 10-bit SAR ADC With Merge, Split, and Tri-Level Switching using Mortise-Tenon Structure Capacitor. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0520118-082221

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Boston University

12. Yang, Jiao. Design of a low power 8-bit A/D converter for wireless neural recorder applications.

Degree: MS, Electrical & Computer Engineering, 2017, Boston University

 Human brain and related topics like neuron spikes and their active potentials have become more and more attractive to people these days, as these issues… (more)

Subjects/Keywords: Electrical engineering; Energy-saving capacitor array; Low power design; Neural recorder applications; Successive approximation register analog-to-digital converter (SAR-ADC)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yang, J. (2017). Design of a low power 8-bit A/D converter for wireless neural recorder applications. (Masters Thesis). Boston University. Retrieved from http://hdl.handle.net/2144/23685

Chicago Manual of Style (16th Edition):

Yang, Jiao. “Design of a low power 8-bit A/D converter for wireless neural recorder applications.” 2017. Masters Thesis, Boston University. Accessed April 18, 2021. http://hdl.handle.net/2144/23685.

MLA Handbook (7th Edition):

Yang, Jiao. “Design of a low power 8-bit A/D converter for wireless neural recorder applications.” 2017. Web. 18 Apr 2021.

Vancouver:

Yang J. Design of a low power 8-bit A/D converter for wireless neural recorder applications. [Internet] [Masters thesis]. Boston University; 2017. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/2144/23685.

Council of Science Editors:

Yang J. Design of a low power 8-bit A/D converter for wireless neural recorder applications. [Masters Thesis]. Boston University; 2017. Available from: http://hdl.handle.net/2144/23685


Brno University of Technology

13. Paštěka, Richard. Osciloskop v systému Android: Oscilloscope with the Android Operating System.

Degree: 2019, Brno University of Technology

 Bachelor thesis deals with the design of digital oscilloscope using the Arduino development kit. The theoretical part of the thesis discusses the basic parameters of… (more)

Subjects/Keywords: digitální osciloskop; Arduino ADK; Matlab; A/D převodník s postupnou aproximací; digital oscilloscope; Arduino ADK; Matlab; successive approximation ADC

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APA (6th Edition):

Paštěka, R. (2019). Osciloskop v systému Android: Oscilloscope with the Android Operating System. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/33266

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Paštěka, Richard. “Osciloskop v systému Android: Oscilloscope with the Android Operating System.” 2019. Thesis, Brno University of Technology. Accessed April 18, 2021. http://hdl.handle.net/11012/33266.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Paštěka, Richard. “Osciloskop v systému Android: Oscilloscope with the Android Operating System.” 2019. Web. 18 Apr 2021.

Vancouver:

Paštěka R. Osciloskop v systému Android: Oscilloscope with the Android Operating System. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/11012/33266.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Paštěka R. Osciloskop v systému Android: Oscilloscope with the Android Operating System. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/33266

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

14. Dornelas, Helga Uchoa. Low power SAR analog-to-digital converter for internet-of-things RF receivers.

Degree: 2018, Brazil

 The "Internet of Things" (IoT) has been a topic of intensive research in industry, technological centers and academic community, being data communication one aspect of… (more)

Subjects/Keywords: Microeletrônica; Cmos; Internet das coisas; CMOS Analog Design; Internet of Things; Successive Approximation ADC; Low Power Design; Analog to Digital Converter

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APA (6th Edition):

Dornelas, H. U. (2018). Low power SAR analog-to-digital converter for internet-of-things RF receivers. (Masters Thesis). Brazil. Retrieved from http://hdl.handle.net/10183/186015

Chicago Manual of Style (16th Edition):

Dornelas, Helga Uchoa. “Low power SAR analog-to-digital converter for internet-of-things RF receivers.” 2018. Masters Thesis, Brazil. Accessed April 18, 2021. http://hdl.handle.net/10183/186015.

MLA Handbook (7th Edition):

Dornelas, Helga Uchoa. “Low power SAR analog-to-digital converter for internet-of-things RF receivers.” 2018. Web. 18 Apr 2021.

Vancouver:

Dornelas HU. Low power SAR analog-to-digital converter for internet-of-things RF receivers. [Internet] [Masters thesis]. Brazil; 2018. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/10183/186015.

Council of Science Editors:

Dornelas HU. Low power SAR analog-to-digital converter for internet-of-things RF receivers. [Masters Thesis]. Brazil; 2018. Available from: http://hdl.handle.net/10183/186015

15. Lin, Jiaming. Design techniques for low power high speed successive approximation analog-to-digital converters.

Degree: PhD, Electrical and Computer Engineering, 2013, Oregon State University

 This dissertation presents two high-speed pipeline successive approximation analog-to-digital converters (SAR ADCs). Capacitive DACs and resistive DACs are utilized in these two pipeline SAR ADCs,… (more)

Subjects/Keywords: successive approximation ADC; Successive approximation analog-to-digital converters  – Design and construction

…architecture. 3 For low power application, successive approximation ADC (SAR ADC) is a… …69 Design Techniques for Low Power High Speed Successive Approximation Analog-to-Digital… …54 4 The Design of a Low-Power Multi-Step Capacitor-Splitting SAR ADC ................. 56… …56 4.2 Multi-Step Capacitor-Splitting SAR ADC… …72 LIST OF FIGURES Figure Page Fig. 1-1. The existing ADC architecture… 

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APA (6th Edition):

Lin, J. (2013). Design techniques for low power high speed successive approximation analog-to-digital converters. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/40996

Chicago Manual of Style (16th Edition):

Lin, Jiaming. “Design techniques for low power high speed successive approximation analog-to-digital converters.” 2013. Doctoral Dissertation, Oregon State University. Accessed April 18, 2021. http://hdl.handle.net/1957/40996.

MLA Handbook (7th Edition):

Lin, Jiaming. “Design techniques for low power high speed successive approximation analog-to-digital converters.” 2013. Web. 18 Apr 2021.

Vancouver:

Lin J. Design techniques for low power high speed successive approximation analog-to-digital converters. [Internet] [Doctoral dissertation]. Oregon State University; 2013. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1957/40996.

Council of Science Editors:

Lin J. Design techniques for low power high speed successive approximation analog-to-digital converters. [Doctoral Dissertation]. Oregon State University; 2013. Available from: http://hdl.handle.net/1957/40996

16. Li, Wei. Low-power successive approximation analog to digital converter with digital calibration.

Degree: PhD, Electrical and Computer Engineering, 2014, Oregon State University

 IC designers are continuously facing the challenges from reduced CMOS feature sizes and supply voltages. ADCs that deliver satisfactory resolutions/speeds while utilizing the state-of-the-art technologies… (more)

Subjects/Keywords: ADC; Successive approximation analog-to-digital converters  – Calibration

…usually operates at low-to-medium speed. Successive approximation register (SAR) ADC… …parameters of the whole ADC. 2.1 SAR Algorithm The basic successive approximation process in SAR… …10b 20MSample/s non-binary successive approximation ADC in 0.13μm CMOS," ISSCC 2002, pp… …x22;A 1 GS/s 6 bit 6.7 mW successive approximation ADC using asynchronous processing,"… …70 Low-Power Successive Approximation Analog to Digital Converter with Digital… 

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APA (6th Edition):

Li, W. (2014). Low-power successive approximation analog to digital converter with digital calibration. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/46788

Chicago Manual of Style (16th Edition):

Li, Wei. “Low-power successive approximation analog to digital converter with digital calibration.” 2014. Doctoral Dissertation, Oregon State University. Accessed April 18, 2021. http://hdl.handle.net/1957/46788.

MLA Handbook (7th Edition):

Li, Wei. “Low-power successive approximation analog to digital converter with digital calibration.” 2014. Web. 18 Apr 2021.

Vancouver:

Li W. Low-power successive approximation analog to digital converter with digital calibration. [Internet] [Doctoral dissertation]. Oregon State University; 2014. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1957/46788.

Council of Science Editors:

Li W. Low-power successive approximation analog to digital converter with digital calibration. [Doctoral Dissertation]. Oregon State University; 2014. Available from: http://hdl.handle.net/1957/46788


Southern Illinois University

17. Sekar, Ramgopal. LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS.

Degree: MS, Electrical and Computer Engineering, 2010, Southern Illinois University

  In this work, we investigate circuit techniques to reduce the power consumption of Successive Approximation Register Analog-to-Digital Converter (SAR-ADC). We developed four low-power SAR-ADC(more)

Subjects/Keywords: Analog to Digital Converters; Low Power Design; Successive Approximation Register ADC

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APA (6th Edition):

Sekar, R. (2010). LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS. (Masters Thesis). Southern Illinois University. Retrieved from https://opensiuc.lib.siu.edu/theses/350

Chicago Manual of Style (16th Edition):

Sekar, Ramgopal. “LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS.” 2010. Masters Thesis, Southern Illinois University. Accessed April 18, 2021. https://opensiuc.lib.siu.edu/theses/350.

MLA Handbook (7th Edition):

Sekar, Ramgopal. “LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS.” 2010. Web. 18 Apr 2021.

Vancouver:

Sekar R. LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS. [Internet] [Masters thesis]. Southern Illinois University; 2010. [cited 2021 Apr 18]. Available from: https://opensiuc.lib.siu.edu/theses/350.

Council of Science Editors:

Sekar R. LOW-POWER TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TO-DIGITAL CONVERTERS. [Masters Thesis]. Southern Illinois University; 2010. Available from: https://opensiuc.lib.siu.edu/theses/350


Texas A&M University

18. Shafik, Ayman Osama Amin Mohamed. Equalization Architectures for High Speed ADC-Based Serial I/O Receivers.

Degree: PhD, Electrical Engineering, 2016, Texas A&M University

 The growth in worldwide network traffic due to the rise of cloud computing and wireless video consumption has required servers and routers to support increased… (more)

Subjects/Keywords: ADC-Based Receiver; Analog-To-Digital Converter (ADC); Bit-Error Rate (BER); Decision Feedback Equalizer (DFE); Digital Equalization; Embedded Equalization; Feed-Forward Equalizer (FFE); Statistical Modeling; Successive Approximation Register (SAR); Time Interleaving

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APA (6th Edition):

Shafik, A. O. A. M. (2016). Equalization Architectures for High Speed ADC-Based Serial I/O Receivers. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/156875

Chicago Manual of Style (16th Edition):

Shafik, Ayman Osama Amin Mohamed. “Equalization Architectures for High Speed ADC-Based Serial I/O Receivers.” 2016. Doctoral Dissertation, Texas A&M University. Accessed April 18, 2021. http://hdl.handle.net/1969.1/156875.

MLA Handbook (7th Edition):

Shafik, Ayman Osama Amin Mohamed. “Equalization Architectures for High Speed ADC-Based Serial I/O Receivers.” 2016. Web. 18 Apr 2021.

Vancouver:

Shafik AOAM. Equalization Architectures for High Speed ADC-Based Serial I/O Receivers. [Internet] [Doctoral dissertation]. Texas A&M University; 2016. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1969.1/156875.

Council of Science Editors:

Shafik AOAM. Equalization Architectures for High Speed ADC-Based Serial I/O Receivers. [Doctoral Dissertation]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/156875


University of Illinois – Urbana-Champaign

19. Liu, Wenbo. Low-power high-performance SAR ADC design with digital calibration techniques.

Degree: PhD, 1200, 2011, University of Illinois – Urbana-Champaign

 This dissertation presents the design of three high-performance successive-approximation-register (SAR) analog-to-digital converters (ADCs) using distinct digital background calibration techniques under the framework of a generalized… (more)

Subjects/Keywords: successive-approximation-register (SAR) analog-to-digital converters (ADC); redundancy; sub-radix-2; Nonlinearity; digital calibration; linear equalizer; generalized linear equalizer; perturbation; bit-wise correlation; channel mismatch; time-interleaved analog-to-digital converters (ADC)

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APA (6th Edition):

Liu, W. (2011). Low-power high-performance SAR ADC design with digital calibration techniques. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/18623

Chicago Manual of Style (16th Edition):

Liu, Wenbo. “Low-power high-performance SAR ADC design with digital calibration techniques.” 2011. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 18, 2021. http://hdl.handle.net/2142/18623.

MLA Handbook (7th Edition):

Liu, Wenbo. “Low-power high-performance SAR ADC design with digital calibration techniques.” 2011. Web. 18 Apr 2021.

Vancouver:

Liu W. Low-power high-performance SAR ADC design with digital calibration techniques. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2011. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/2142/18623.

Council of Science Editors:

Liu W. Low-power high-performance SAR ADC design with digital calibration techniques. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/18623

20. Moorthy, Sriram. Characterizing Distortion in Successive-Approx imation Analog-to-Digital Converters due to Off-Chip Capacitors within the Voltage Reference Circuit.

Degree: 2014, University of Waterloo

 The Successive Approximation Analog-to-Digital converter (SAR-ADC) is a popular architecture due to its low power, simple design, and reasonable resolution and speed. Due to the… (more)

Subjects/Keywords: ADC SAR-ADC Analog-to-Digital Converters Voltage-Referece Successive Approximation

…3.1.1 Matlab Code for an Ideal Successive Approximation ADC . . . . . . . . . . 18 3.1.2… …32 3.4.1 Matlab Code for a Non-Ideal Successive Approximation ADC . . . . . . . . 34… …For the AD7276 Successive Approximation ADC [7] . . . . . . 37 4.1.3 Overall… …types of ADCs for a designer to choose from. One such ADC is the Successive Approximation ADC… …Specifications and Measurements It is important to note that the Successive Approximation ADC has a… 

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APA (6th Edition):

Moorthy, S. (2014). Characterizing Distortion in Successive-Approx imation Analog-to-Digital Converters due to Off-Chip Capacitors within the Voltage Reference Circuit. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/9011

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Moorthy, Sriram. “Characterizing Distortion in Successive-Approx imation Analog-to-Digital Converters due to Off-Chip Capacitors within the Voltage Reference Circuit.” 2014. Thesis, University of Waterloo. Accessed April 18, 2021. http://hdl.handle.net/10012/9011.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Moorthy, Sriram. “Characterizing Distortion in Successive-Approx imation Analog-to-Digital Converters due to Off-Chip Capacitors within the Voltage Reference Circuit.” 2014. Web. 18 Apr 2021.

Vancouver:

Moorthy S. Characterizing Distortion in Successive-Approx imation Analog-to-Digital Converters due to Off-Chip Capacitors within the Voltage Reference Circuit. [Internet] [Thesis]. University of Waterloo; 2014. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/10012/9011.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Moorthy S. Characterizing Distortion in Successive-Approx imation Analog-to-Digital Converters due to Off-Chip Capacitors within the Voltage Reference Circuit. [Thesis]. University of Waterloo; 2014. Available from: http://hdl.handle.net/10012/9011

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

21. Chaturvedi, Vikram. Low Power and Low Area Techniques for Neural Recording Application.

Degree: PhD, Faculty of Engineering, 2018, Indian Institute of Science

 Chronic recording of neural signals is indispensable in designing efficient brain machine interfaces and to elucidate human neurophysiology. The advent of multi-channel micro-electrode arrays has… (more)

Subjects/Keywords: Neural Signal Processing; Nervous System - Electric Signals; Brain Machine Interface; Neural Recording System; Neural Recording Front End; Neural Low Noise Amplifiers; Successive Approximation Analog to Digital Converter; Neural Recording Application; Neural Recording Front End (NRFE).; FlipDAC; Quaternary Capacitor Switching; ANALOG-TO-DIGITAL Converter (ADC); SAR ADC Design; Neural Physiology

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APA (6th Edition):

Chaturvedi, V. (2018). Low Power and Low Area Techniques for Neural Recording Application. (Doctoral Dissertation). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/3167

Chicago Manual of Style (16th Edition):

Chaturvedi, Vikram. “Low Power and Low Area Techniques for Neural Recording Application.” 2018. Doctoral Dissertation, Indian Institute of Science. Accessed April 18, 2021. http://etd.iisc.ac.in/handle/2005/3167.

MLA Handbook (7th Edition):

Chaturvedi, Vikram. “Low Power and Low Area Techniques for Neural Recording Application.” 2018. Web. 18 Apr 2021.

Vancouver:

Chaturvedi V. Low Power and Low Area Techniques for Neural Recording Application. [Internet] [Doctoral dissertation]. Indian Institute of Science; 2018. [cited 2021 Apr 18]. Available from: http://etd.iisc.ac.in/handle/2005/3167.

Council of Science Editors:

Chaturvedi V. Low Power and Low Area Techniques for Neural Recording Application. [Doctoral Dissertation]. Indian Institute of Science; 2018. Available from: http://etd.iisc.ac.in/handle/2005/3167


Linköping University

22. Zhang, Dai. Design and Evaluation of an Ultra-Low Power Successive Approximation ADC.

Degree: Electrical Engineering, 2009, Linköping University

  Analog-to-digital converters (ADC) targeted for use in medical implant devices serve an important role as the interface between analog signal and digital processing system.… (more)

Subjects/Keywords: Analog-to-digital converter (ADC); charge redistribution; CMOS; low power; low supply voltage; successive approximation; latched comparator; Electrical engineering; Elektroteknik

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APA (6th Edition):

Zhang, D. (2009). Design and Evaluation of an Ultra-Low Power Successive Approximation ADC. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18219

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhang, Dai. “Design and Evaluation of an Ultra-Low Power Successive Approximation ADC.” 2009. Thesis, Linköping University. Accessed April 18, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18219.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhang, Dai. “Design and Evaluation of an Ultra-Low Power Successive Approximation ADC.” 2009. Web. 18 Apr 2021.

Vancouver:

Zhang D. Design and Evaluation of an Ultra-Low Power Successive Approximation ADC. [Internet] [Thesis]. Linköping University; 2009. [cited 2021 Apr 18]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18219.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhang D. Design and Evaluation of an Ultra-Low Power Successive Approximation ADC. [Thesis]. Linköping University; 2009. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-18219

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

23. Parsons, Colton A. Variable Precision Tandem Analog-to-Digital Converter (ADC).

Degree: MS, Electrical Engineering, 2014, Cal Poly

  This paper describes an analog-to-digital signal converter which varies its precision as a function of input slew rate (maximum signal rate of change), in… (more)

Subjects/Keywords: ADC; A2D; Variable Precision; Successive Approximation; Controls and Control Theory; Electrical and Electronics; Signal Processing

…4 Figure 1.2: Successive Approximation ADC… …1.2 – Successive Approximation ADC Successive Approximation ADCs work by an iterative… …down. Unlike the Flash ADC, a Successive Approximation ADC requires only minor size growth if… …errors as does a Pipelined or Subranging ADC. In this proposal the Successive Approximation… …fundamental concept for the implementation is to use a Flash ADC and Successive Approximation ADC in… 

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APA (6th Edition):

Parsons, C. A. (2014). Variable Precision Tandem Analog-to-Digital Converter (ADC). (Masters Thesis). Cal Poly. Retrieved from https://digitalcommons.calpoly.edu/theses/1255 ; 10.15368/theses.2014.100

Chicago Manual of Style (16th Edition):

Parsons, Colton A. “Variable Precision Tandem Analog-to-Digital Converter (ADC).” 2014. Masters Thesis, Cal Poly. Accessed April 18, 2021. https://digitalcommons.calpoly.edu/theses/1255 ; 10.15368/theses.2014.100.

MLA Handbook (7th Edition):

Parsons, Colton A. “Variable Precision Tandem Analog-to-Digital Converter (ADC).” 2014. Web. 18 Apr 2021.

Vancouver:

Parsons CA. Variable Precision Tandem Analog-to-Digital Converter (ADC). [Internet] [Masters thesis]. Cal Poly; 2014. [cited 2021 Apr 18]. Available from: https://digitalcommons.calpoly.edu/theses/1255 ; 10.15368/theses.2014.100.

Council of Science Editors:

Parsons CA. Variable Precision Tandem Analog-to-Digital Converter (ADC). [Masters Thesis]. Cal Poly; 2014. Available from: https://digitalcommons.calpoly.edu/theses/1255 ; 10.15368/theses.2014.100

24. Zeloufi, Mohamed. Développement d’un convertisseur analogique-numérique innovant dans le cadre des projets d’amélioration des systèmes d’acquisition de l’expérience ATLAS au LHC : Development of an innovative analog-digital converter chip in the scope of the upgrade of data acquisition infrastructure of the ATLAS experiment at the LHC.

Degree: Docteur es, Nanoélectronique et nanotechnologie, 2016, Université Grenoble Alpes (ComUE)

 À l’horizon 2024, l’expérience ATLAS prévoit de fonctionner à des luminosités 10 fois supérieures à la configuration actuelle. Par conséquent, l’électronique actuelle de lecture ne… (more)

Subjects/Keywords: Convertisseur Analogique-Numérique (CAN); Conversion à approximations successives (SAR); Redondance; Algorithme de commutation; Correction numérique; Tensions de référence; Analog-Digital Converter (ADC); Successive Approximation Register (SAR); Redundancy; Switching algorithm; Digital calibration; Reference voltages; 620

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APA (6th Edition):

Zeloufi, M. (2016). Développement d’un convertisseur analogique-numérique innovant dans le cadre des projets d’amélioration des systèmes d’acquisition de l’expérience ATLAS au LHC : Development of an innovative analog-digital converter chip in the scope of the upgrade of data acquisition infrastructure of the ATLAS experiment at the LHC. (Doctoral Dissertation). Université Grenoble Alpes (ComUE). Retrieved from http://www.theses.fr/2016GREAT115

Chicago Manual of Style (16th Edition):

Zeloufi, Mohamed. “Développement d’un convertisseur analogique-numérique innovant dans le cadre des projets d’amélioration des systèmes d’acquisition de l’expérience ATLAS au LHC : Development of an innovative analog-digital converter chip in the scope of the upgrade of data acquisition infrastructure of the ATLAS experiment at the LHC.” 2016. Doctoral Dissertation, Université Grenoble Alpes (ComUE). Accessed April 18, 2021. http://www.theses.fr/2016GREAT115.

MLA Handbook (7th Edition):

Zeloufi, Mohamed. “Développement d’un convertisseur analogique-numérique innovant dans le cadre des projets d’amélioration des systèmes d’acquisition de l’expérience ATLAS au LHC : Development of an innovative analog-digital converter chip in the scope of the upgrade of data acquisition infrastructure of the ATLAS experiment at the LHC.” 2016. Web. 18 Apr 2021.

Vancouver:

Zeloufi M. Développement d’un convertisseur analogique-numérique innovant dans le cadre des projets d’amélioration des systèmes d’acquisition de l’expérience ATLAS au LHC : Development of an innovative analog-digital converter chip in the scope of the upgrade of data acquisition infrastructure of the ATLAS experiment at the LHC. [Internet] [Doctoral dissertation]. Université Grenoble Alpes (ComUE); 2016. [cited 2021 Apr 18]. Available from: http://www.theses.fr/2016GREAT115.

Council of Science Editors:

Zeloufi M. Développement d’un convertisseur analogique-numérique innovant dans le cadre des projets d’amélioration des systèmes d’acquisition de l’expérience ATLAS au LHC : Development of an innovative analog-digital converter chip in the scope of the upgrade of data acquisition infrastructure of the ATLAS experiment at the LHC. [Doctoral Dissertation]. Université Grenoble Alpes (ComUE); 2016. Available from: http://www.theses.fr/2016GREAT115


Brno University of Technology

25. Lembard, Tomáš. Speciální aplikace VoIP: Special application of VoIP.

Degree: 2019, Brno University of Technology

 The aim of this master's thesis is suggestion and following realization of voice transmission over the local network equipment and a description of used circuits… (more)

Subjects/Keywords: Přenos hlasu v lokální síti; VoIP; Ethernet; LAN; IP; UDP; Digitalizace nízkofrekvenčních signálů; PCM; A/D převod s postupnou aproximací; RMII; TCP/IP stack cIPS; Voice transmission over the local network; VoIP; Ethernet; LAN; IP; UDP; Digitization of low-frequency signals; PCM; Successive approximation ADC; RMII; TCP/IP stack cIPS

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APA (6th Edition):

Lembard, T. (2019). Speciální aplikace VoIP: Special application of VoIP. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/2345

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lembard, Tomáš. “Speciální aplikace VoIP: Special application of VoIP.” 2019. Thesis, Brno University of Technology. Accessed April 18, 2021. http://hdl.handle.net/11012/2345.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lembard, Tomáš. “Speciální aplikace VoIP: Special application of VoIP.” 2019. Web. 18 Apr 2021.

Vancouver:

Lembard T. Speciální aplikace VoIP: Special application of VoIP. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/11012/2345.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lembard T. Speciální aplikace VoIP: Special application of VoIP. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/2345

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

26. Zhian Tabasy, Ehsan. Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications.

Degree: PhD, Electrical Engineering, 2015, Texas A&M University

 As the data rates of wireline communication links increases, channel impairments such as skin effect, dielectric loss, fiber dispersion, reflections and cross-talk become more pronounced.… (more)

Subjects/Keywords: Analog to Digital Converter (ADC); Embedded Equalization; ADC-Based Receiver; Decision Feedback Equalizer (DFE); Embedded Equalization; Feed-Forward Equalizer (FFE); Serial Link; Successive Approximation Register (SAR); Time Interleaving; Wireline

…architectures are briefly introduced and successive approximation register (SAR) topology… …Implementation . . . . ADC Design . . . . . . . . . . . . . . . . . . . . . 3.3.1 Time-Interleaved… …Architecture . . . . . . . 3.3.2 Unit ADC with Embedded 1-Tap DFE . . 3.3.3 Front-End Track-and-Hold… …3.4.1 Core ADC Characterization . . . . . . . . 3.4.2 Embedded DFE Functionality… …60 62 64 65 67 67 68 72 73 77 77 79 84 . . . . . . . 87 A 6-Bit 10GS/s ADC with Embedded… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhian Tabasy, E. (2015). Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/155223

Chicago Manual of Style (16th Edition):

Zhian Tabasy, Ehsan. “Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications.” 2015. Doctoral Dissertation, Texas A&M University. Accessed April 18, 2021. http://hdl.handle.net/1969.1/155223.

MLA Handbook (7th Edition):

Zhian Tabasy, Ehsan. “Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications.” 2015. Web. 18 Apr 2021.

Vancouver:

Zhian Tabasy E. Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications. [Internet] [Doctoral dissertation]. Texas A&M University; 2015. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1969.1/155223.

Council of Science Editors:

Zhian Tabasy E. Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications. [Doctoral Dissertation]. Texas A&M University; 2015. Available from: http://hdl.handle.net/1969.1/155223

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