subject:(stuck at faults)

University of Iowa

1. Yang, Fan. New tests and test methodologies for scan cell internal faults.

Degree: PhD, Electrical and Computer Engineering, 2009, University of Iowa

► Semiconductor industry goals for the quality of shipped products continue to get higher to satisfy customer requirements. Higher quality of shipped electronic devices can… (more)

▼ Semiconductor industry goals for the quality of shipped products continue to get higher to satisfy customer requirements. Higher quality of shipped electronic devices can only be obtained by thorough tests of the manufactured components. Scan chains are universally used in large industrial designs in order to cost effectively test manufactured electronic devices. They contain nearly half of the logic transistors in large industrial designs. Yet, faults in the scan cells are not directly targeted by the existing tests. The main objective of this thesis is to investigate the detectability of the faults internal to scan cells. In this thesis, we analyze the detection of line stuck-at, transistor stuck-on, resistive opens and bridging faults in scan cells. Both synchronous and asynchronous scan cells are considered. We define the notion of half-speed flush test and demonstrate that such new tests increase coverage of internal faults in scan cells. A new set of flush tests is proposed and such tests are applied at higher temperatures to detect scan cell internal opens with a wider range of resistances. We also propose new scan based tests to further increase the coverage of those opens. The proposed tests are shown to achieve the maximum possible coverage of opens in transistors internal to scan cells. For an asynchronous scan cell considered, two new flush tests are added to cover the faults that are not detected by the tests for synchronous scan cells. An analysis of detection of a set of scan cell internal bridging faults is described. Both zero-resistance and nonzero-resistance bridging fault models are considered. We show that the detection of some zero-resistance non-feedback bridging faults requires two-pattern tests. We classify the undetectable faults based on the reasons for their undetectability. We also propose an enhanced logic BIST architecture that accomplishes the new flush tests we propose to detect scan cell internal opens. The effectiveness of these new methods to detect scan cell internal faults is demonstrated by experimental results using some standard scan cells from a large industrial design. Advisors/Committee Members: Reddy, Sudhakar M. (supervisor).

Subjects/Keywords: bridging faults; faults in scan cell; faults in scan chain; stuck-at faults; stuck-on faults; stuck-open faults; Electrical and Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Yang, F. (2009). New tests and test methodologies for scan cell internal faults. (Doctoral Dissertation). University of Iowa. Retrieved from https://ir.uiowa.edu/etd/452

Chicago Manual of Style (16^th Edition):

Yang, Fan. “New tests and test methodologies for scan cell internal faults.” 2009. Doctoral Dissertation, University of Iowa. Accessed April 20, 2021. https://ir.uiowa.edu/etd/452.

MLA Handbook (7^th Edition):

Yang, Fan. “New tests and test methodologies for scan cell internal faults.” 2009. Web. 20 Apr 2021.

Vancouver:

Yang F. New tests and test methodologies for scan cell internal faults. [Internet] [Doctoral dissertation]. University of Iowa; 2009. [cited 2021 Apr 20]. Available from: https://ir.uiowa.edu/etd/452.

Council of Science Editors:

Yang F. New tests and test methodologies for scan cell internal faults. [Doctoral Dissertation]. University of Iowa; 2009. Available from: https://ir.uiowa.edu/etd/452

2. Kuentzer, Felipe Augusto. More than a timing resilient template : a case study on reliability-oriented improvements on blade.

Degree: 2018, Pontifical Catholic University of Rio Grande do Sul

URL: http://tede2.pucrs.br/tede2/handle/tede/8093

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Made available in DSpace on 2018-06-01T12:33:57Z (GMT). No. of bitstreams: 1 FELIPE_AUGUSTO_KUENTZER_TES.pdf: 3277301 bytes, checksum: 7e77c5eb72299302d091329bde56b953 (MD5) Previous issue date: 2018-03-28

? medida que o projeto de VLSI avan?a para tecnologias ultra submicron, as margens de atraso adicionadas para compensar variabilidades de processo de fabrica??o, temperatura de opera??o e tens?o de alimenta??o, tornam-se uma parte significativa do per?odo de rel?gio em circuitos s?ncronos tradicionais. As arquiteturas resilientes a varia??es de atraso surgiram como uma solu??o promissora para aliviar essas margens de tempo projetadas para o pior caso, melhorando o desempenho do sistema e reduzindo o consumo de energia. Essas arquiteturas incorporam circuitos adicionais para detec??o e recupera??o de viola??es de atraso que podem surgir ao projetar o circuito com margens de tempo menores. Os sistemas ass?ncronos apresentam potencial para melhorar a efici?ncia energ?tica e o desempenho devido ? aus?ncia de um sinal de rel?gio global. Al?m disso, os circuitos ass?ncronos s?o conhecidos por serem robustos a varia??es de processo, tens?o e temperatura. Blade ? um modelo que incorpora as vantagens de projeto ass?ncrono e resilientes a varia??es de atraso. No entanto, o Blade ainda apresenta desafios em rela??o ? sua testabilidade, o que dificulta sua aplica??o comercial ou em larga escala. Embora o projeto visando testabilidade com Scan seja amplamente utilizado na ind?stria, os altos custos de sil?cio associados com o seu uso no Blade podem ser proibitivos. Por outro lado, os circuitos ass?ncronos podem apresentar vantagens para testes funcionais, enquanto o circuito resiliente fornece feedback cont?nuo durante o funcionamento normal do circuito, uma caracter?stica que pode ser aplicada para testes concorrentes. Nesta Tese, a testabilidade do Blade ? avaliada sob uma perspectiva diferente, onde o circuito implementado com o Blade apresenta propriedades de confiabilidade que podem ser exploradas para testes. Inicialmente, um m?todo de classifica??o de falhas que relaciona padr?es comportamentais com falhas estruturais dentro da l?gica de detec??o de erro e uma nova implementa??o orientada para teste desse m?dulo de detec??o s?o propostos. A parte de controle ? analisada para falhas internas, e um novo projeto ? proposto, onde o teste ? melhorado e o circuito pode ser otimizado pelo fluxo de projeto. Um m?todo original de medi??o de tempo das linhas de atraso tamb?m ? abordado. Finalmente, o teste de falhas de atrasos em caminhos cr?ticos do caminho de dados ? explorado como uma consequ?ncia…

Advisors/Committee Members: Amory, Alexandre de Morais.

Subjects/Keywords: Projeto Resiliente a Varia??es de Atraso; Projeto Ass?ncrono; Projeto Visando Testabilidade; Teste Funcional; Falhas de Stuck-at; Falhas de Atraso; Blade; Timing Resilient Design; Asynchronous Design; Design for Testability; Functional Testing; Stuck-at Faults; Delay Faults; CIENCIA DA COMPUTACAO::TEORIA DA COMPUTACAO

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Kuentzer, F. A. (2018). More than a timing resilient template : a case study on reliability-oriented improvements on blade. (Doctoral Dissertation). Pontifical Catholic University of Rio Grande do Sul. Retrieved from http://tede2.pucrs.br/tede2/handle/tede/8093

Chicago Manual of Style (16^th Edition):

Kuentzer, Felipe Augusto. “More than a timing resilient template : a case study on reliability-oriented improvements on blade.” 2018. Doctoral Dissertation, Pontifical Catholic University of Rio Grande do Sul. Accessed April 20, 2021. http://tede2.pucrs.br/tede2/handle/tede/8093.

MLA Handbook (7^th Edition):

Kuentzer, Felipe Augusto. “More than a timing resilient template : a case study on reliability-oriented improvements on blade.” 2018. Web. 20 Apr 2021.

Vancouver:

Kuentzer FA. More than a timing resilient template : a case study on reliability-oriented improvements on blade. [Internet] [Doctoral dissertation]. Pontifical Catholic University of Rio Grande do Sul; 2018. [cited 2021 Apr 20]. Available from: http://tede2.pucrs.br/tede2/handle/tede/8093.

Council of Science Editors:

Kuentzer FA. More than a timing resilient template : a case study on reliability-oriented improvements on blade. [Doctoral Dissertation]. Pontifical Catholic University of Rio Grande do Sul; 2018. Available from: http://tede2.pucrs.br/tede2/handle/tede/8093

3. Lawrence, Ignatius Praveen. Improving Power, Performance and Area with Test: A Case Study.

Degree: MS, Computer Engineering, 2018, Texas A&M University

URL: http://hdl.handle.net/1969.1/173669

► As more low power devices are needed for applications such as Internet of Things, reducing power and area is becoming more critical. Reducing power consumption… (more)

Subjects/Keywords: partial scan; stuck-at faults; transition; delay faults; PPA; ATPG; frequency; TNS; near-threshold technology

…at faults (SAFs) in a partial scan design. In Figure 3, we can see that two… …faults captured by the first non-scan DFF need N + 1 capture cycles to be observed at an SDFF… …stuck-at 1 (SA1) fault in Figure 6, we need the output values of FF4 and FF5 (… …control and observe at every DFF. We determine sequentially redundant faults as those that are… …low fan-in, the non-scan DFF has at least one easy path to propagate captured faults. Here…

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Lawrence, I. P. (2018). Improving Power, Performance and Area with Test: A Case Study. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/173669

Chicago Manual of Style (16^th Edition):

Lawrence, Ignatius Praveen. “Improving Power, Performance and Area with Test: A Case Study.” 2018. Masters Thesis, Texas A&M University. Accessed April 20, 2021. http://hdl.handle.net/1969.1/173669.

MLA Handbook (7^th Edition):

Lawrence, Ignatius Praveen. “Improving Power, Performance and Area with Test: A Case Study.” 2018. Web. 20 Apr 2021.

Vancouver:

Lawrence IP. Improving Power, Performance and Area with Test: A Case Study. [Internet] [Masters thesis]. Texas A&M University; 2018. [cited 2021 Apr 20]. Available from: http://hdl.handle.net/1969.1/173669.

Council of Science Editors:

Lawrence IP. Improving Power, Performance and Area with Test: A Case Study. [Masters Thesis]. Texas A&M University; 2018. Available from: http://hdl.handle.net/1969.1/173669

4. Marques, Felipe de Souza. Um algoritmo formal para remoção de redundâncias.

Degree: 2003, Brazil

URL: http://hdl.handle.net/10183/8498

► Os algoritmos para síntese de circuitos digitais em geral visam a melhoria de uma função de custo composta de quatro critérios: área, desempenho, potência e… (more)

▼ Os algoritmos para síntese de circuitos digitais em geral visam a melhoria de uma função de custo composta de quatro critérios: área, desempenho, potência e testabilidade. Normalmente estes algoritmos conseguem uma relação de compromisso para a otimização de dois critérios. Efeitos indesejáveis também podem surgir com a otimização de um destes critérios. Por exemplo, as otimizações de desempenho podem introduzir falhas de colagem não testáveis (redundâncias) em um circuito, reduzindo a sua testabilidade. Muitos algoritmos de síntese lógica exploram propriedades específicas de determinadas funções a serem sintetizadas. Um exemplo de função com propriedades específicas são as funções ditas unate. Um exemplo deste tipo de função é o sinal de carry de um somador completo. Este tipo de função exige cuidados especiais para evitar a introdução de redundâncias. Muitos dos algoritmos para síntese lógica empregam a decomposição de Shannon para melhorar o desempenho de um circuito. A equação geral da decomposição de Shannon é expressa através de uma função binate. As redundâncias sempre serão introduzidas nos circuitos quando uma equação binate é utilizada para representar uma função unate. Diagramas de Decisão Binária (BDDs) são um tipo estruturas de dados muito utilizadas em algoritmos para síntese lógica. A decomposição de Shannon também é utilizada para derivar circuitos a partir de BDDs. Este tipo de estrutura representa uma função lógica, mas não mantém uma representação sem redundâncias da mesma. Infelizmente, os circuitos derivados a partir desta estrutura poderão ser redundantes, principalmente quando a decomposição de Shannon for utilizada. Existem estruturas de dados capazes de representar uma função sem redundâncias. Este é o caso dos VPBDDs , que possuem propriedades especiais que preservam características de testabilidade da função representada. Baseando-se nas propriedades dos VPBDDs, um novo algoritmo para remoção de redundâncias foi proposto. Este algoritmo é capaz de gerar circuitos sem redundâncias, mesmo quando a função, que é representada pelo VPBDD, é unate. Além da geração de circuitos sem redundâncias, o algoritmo garante que o atraso do circuito não aumenta após a remoção de redundâncias. A área dos circuitos resultantes pode aumentar, diminuir ou permanecer a mesma, considerando o número de portas lógicas utilizadas. Todos os resultados obtidos neste trabalho mostram que o algoritmo consegue realizar a remoção de redundâncias, sem prejudicar o atraso do circuito. Além disso, todos os caminhos redundantes do circuito têm seu atraso reduzido, pois com a remoção de redundâncias o número de portas lógicas em série é reduzido. A aplicação deste algoritmo apresenta bons resultados para circuitos aritméticos. Isto se deve principalmente ao fato do carry ser uma função unate, o que pode introduzir redundâncias no circuito se esta propriedade (de ser unate) não for tratada adequadamente. O algoritmo proposto também abre possibilidades para a criação de outras ferramentas de CAD, como por exemplo: uma… Advisors/Committee Members: Reis, Andre Inacio.

Subjects/Keywords: Microeletrônica; BBDs; Remocao : Redundancias; Redundancy removal; False paths; Stuck-at faults; Path delay faults; BDD; VPBDD; Unate functions

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Marques, F. d. S. (2003). Um algoritmo formal para remoção de redundâncias. (Masters Thesis). Brazil. Retrieved from http://hdl.handle.net/10183/8498

Chicago Manual of Style (16^th Edition):

Marques, Felipe de Souza. “Um algoritmo formal para remoção de redundâncias.” 2003. Masters Thesis, Brazil. Accessed April 20, 2021. http://hdl.handle.net/10183/8498.

MLA Handbook (7^th Edition):

Marques, Felipe de Souza. “Um algoritmo formal para remoção de redundâncias.” 2003. Web. 20 Apr 2021.

Vancouver:

Marques FdS. Um algoritmo formal para remoção de redundâncias. [Internet] [Masters thesis]. Brazil; 2003. [cited 2021 Apr 20]. Available from: http://hdl.handle.net/10183/8498.

Council of Science Editors:

Marques FdS. Um algoritmo formal para remoção de redundâncias. [Masters Thesis]. Brazil; 2003. Available from: http://hdl.handle.net/10183/8498

Texas A&M University

5. Layek, Ritwik. Pathways, Networks and Therapy: A Boolean Approach to Systems Biology.

Degree: PhD, Electrical Engineering, 2012, Texas A&M University

URL: http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-10829

► The area of systems biology evolved in an attempt to introduce mathematical systems theory principles in biology. Although we believe that all biological processes are… (more)

▼ The area of systems biology evolved in an attempt to introduce mathematical systems theory principles in biology. Although we believe that all biological processes are essentially chemical reactions, describing those using precise mathematical rules is not easy, primarily due to the complexity and enormity of biological systems. Here we introduce a formal approach for modeling biological dynamical relationships and diseases such as cancer. The immediate motivation behind this research is the urgency to find a practicable cure of cancer, the emperor of all maladies. Unlike other deadly endemic diseases such as plague, dengue and AIDS, cancer is characteristically heterogenic and hence requires a closer look into the genesis of the disease. The actual cause of cancer lies within our physiology. The process of cell division holds the clue to unravel the mysteries surrounding this disease. In normal scenario, all control mechanisms work in tandem and cell divides only when the division is required, for instance, to heal a wound platelet derived growth factor triggers cell division. The control mechanism is tightly regulated by several biochemical interactions commonly known as signal transduction pathways. However, from mathematical point of view, these pathways are marginal in nature and unable to cope with the multi-variability of a heterogenic disease like cancer. The present research is possibly one first attempt towards unraveling the mysteries surrounding the dynamics of a proliferating cell. A novel yet simple methodology is developed to bring all the marginal knowledge of the signaling pathways together to form the simplest mathematical abstract known as the Boolean Network. The malfunctioning in the cell by genetic mutations is formally modeled as stuck-at faults in the underlying Network. Finally a mathematical methodology is discovered to optimally find out the possible best combination drug therapy which can drive the cell from an undesirable condition of proliferation to a desirable condition of quiescence or apoptosis. Although, the complete biological validation was beyond the scope of the current research, the process of in-vitro validation has been already initiated by our collaborators. Once validated, this research will lead to a bright future in the field on personalized cancer therapy. Advisors/Committee Members: Datta, Aniruddha (advisor), Dougherty, Edward R. (advisor), Bhattacharyya, Shankar P. (committee member), Sivakumar, N (committee member).

Subjects/Keywords: Systems Biology; Boolean Network; Probabilistic Boolean Network; Markov Chain; State transition diagram; Dynamic Programming; Therapeutic Intervention; Karnaugh Map; Signal Transduction Pathways; Regulatory Networks; DNA damage pathways; P53; Cancer; Cell Cycle; Growth Factor Mediated Pathways; Targeted Therapy; Combination Drug; Genetic Mutation; Stuck-at Faults; Fault Detection; Fault Classification

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Layek, R. (2012). Pathways, Networks and Therapy: A Boolean Approach to Systems Biology. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-10829

Chicago Manual of Style (16^th Edition):

Layek, Ritwik. “Pathways, Networks and Therapy: A Boolean Approach to Systems Biology.” 2012. Doctoral Dissertation, Texas A&M University. Accessed April 20, 2021. http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-10829.

MLA Handbook (7^th Edition):

Layek, Ritwik. “Pathways, Networks and Therapy: A Boolean Approach to Systems Biology.” 2012. Web. 20 Apr 2021.

Vancouver:

Layek R. Pathways, Networks and Therapy: A Boolean Approach to Systems Biology. [Internet] [Doctoral dissertation]. Texas A&M University; 2012. [cited 2021 Apr 20]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-10829.

Council of Science Editors:

Layek R. Pathways, Networks and Therapy: A Boolean Approach to Systems Biology. [Doctoral Dissertation]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-10829

6. Vissa, Pranay. Toward high-level synthesis of reliable circuits through low-cost modulo shadow datapaths.

Degree: MS, Electrical & Computer Engr, 2015, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/78571

► With transistor dimensions shrinking to the atomic scale, a plethora of new reliability problems presents a barrier to continued Moore’s law scaling. Traditional modular redundancy… (more)

Subjects/Keywords: high-level synthesis; automation; error detection; scheduling; binding; optimization; pipelining; modulo arithmetic; logic optimization; state machine; datapath; shadow logic; low cost; high performance; electrical faults; Aliasing; stuck-at faults; soft errors; timing errors; checkpointing; rollback recovery

…stuck-at faults, transient errors, and timing errors. Stuck-at faults are the result of… …stuck-at faults to affect both redundant datapaths in the same way. Further state machine… …inject stuck-at faults, the netlist transform inserts AND (for stuck-at 0) or OR… …faults [9]. For unmasked errors with mod-5 units, we observe an average stuck-at… …fabrication defects that leave a gate output stuck at either 0 or 1 regardless of the input…

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Vissa, P. (2015). Toward high-level synthesis of reliable circuits through low-cost modulo shadow datapaths. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/78571

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Vissa, Pranay. “Toward high-level synthesis of reliable circuits through low-cost modulo shadow datapaths.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed April 20, 2021. http://hdl.handle.net/2142/78571.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Vissa, Pranay. “Toward high-level synthesis of reliable circuits through low-cost modulo shadow datapaths.” 2015. Web. 20 Apr 2021.

Vancouver:

Vissa P. Toward high-level synthesis of reliable circuits through low-cost modulo shadow datapaths. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2021 Apr 20]. Available from: http://hdl.handle.net/2142/78571.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vissa P. Toward high-level synthesis of reliable circuits through low-cost modulo shadow datapaths. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/78571

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

7. Campbell, Keith A. Low-cost error detection through high-level synthesis.

Degree: MS, Electrical & Computer Engineering, 2015, University of Illinois – Urbana-Champaign

URL: http://hdl.handle.net/2142/89068

► System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling and complexity has resulted in a… (more)

▼ System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling and complexity has resulted in a variety of reliability and validation challenges including logic bugs, hot spots, wear-out, and soft errors. To make matters worse, as we reach the limits of Dennard scaling, efforts to improve system performance and energy efficiency have resulted in the integration of a wide variety of complex hardware accelerators in SoCs. Thus the challenge is to design complex, custom hardware that is efficient, but also correct and reliable. High-level synthesis shows promise to address the problem of complex hardware design by providing a bridge from the high-productivity software domain to the hardware design process. Much research has been done on high-level synthesis efficiency optimizations. This thesis shows that high-level synthesis also has the power to address validation and reliability challenges through two solutions. One solution for circuit reliability is modulo-3 shadow datapaths: performing lightweight shadow computations in modulo-3 space for each main computation. We leverage the binding and scheduling flexibility of high-level synthesis to detect control errors through diverse binding and minimize area cost through intelligent checkpoint scheduling and modulo-3 reducer sharing. We introduce logic and dataflow optimizations to further reduce cost. We evaluated our technique with 12 high-level synthesis benchmarks from the arithmetic-oriented PolyBench benchmark suite using FPGA emulated netlist-level error injection. We observe coverages of 99.1% for stuck-at faults, 99.5% for soft errors, and 99.6% for timing errors with a 25.7% area cost and negligible performance impact. Leveraging a mean error detection latency of 12.75 cycles (4150x faster than end result check) for soft errors, we also explore a rollback recovery method with an additional area cost of 28.0%, observing a 175x increase in reliability against soft errors. Another solution for rapid post-silicon validation of accelerator designs is Hybrid Quick Error Detection (H-QED): inserting signature generation logic in a hardware design to create a heavily compressed signature stream that captures the internal behavior of the design at a fine temporal and spatial granularity for comparison with a reference set of signatures generated by high-level simulation to detect bugs. Using H-QED, we demonstrate an improvement in error detection latency (time elapsed from when a bug is activated to when it manifests as an observable failure) of two orders of magnitude and a threefold improvement in bug coverage compared to traditional post-silicon validation techniques. H-QED also uncovered previously unknown bugs in the CHStone benchmark suite, which is widely used by the HLS community. H-QED incurs less than 10% area overhead for the accelerator it validates with negligible performance impact, and we also introduce techniques to minimize any possible intrusiveness introduced by H-QED. Advisors/Committee Members: Chen, Deming (advisor).

Subjects/Keywords: High-level synthesis; Automation; error detection; scheduling; binding; compiler transformation; compiler optimization; pipelining; modulo arithmetic; logic optimization; state machine; datapath, control logic; shadow logic; low cost; high performance; electrical bugs; Aliasing; stuck-at faults; soft errors; timing errors; checkpointing; rollback; recovery; post-silicon validation; Accelerators; system on a chip; signature generation; execution signatures; execution hashing; logic bugs; nondeterministic bugs; masked errors; circuit reliability; hot spots; wear out; silent data corruption; observability; detection latency; mixed datapath; diversity; checkpoint corruption; error injection; error removal; Quick Error Detection (QED); Hybrid Quick Error Detection (H-QED); hybrid hardware/software; execution tracing; address conversion; undefined behavior; High-Level Synthesis (HLS) engine bugs; detection coverage

…transistor fabrication failures. These permanent defects typically manifest as stuck-at faults… …arrives too late. 1.2.2 Stuck-at Faults Fabrication defects result in gate outputs being stuck… …errors and stuck-at faults to a↵ect both redundant datapaths in the same way. Further state… …wires that are supposed to be the output of a logic gate are stuck at logic 0 or logic 1 and… …original driver and connect it to a constant logic 0 or 1 instead. Stuck-at 0 (1)…

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6^th Edition):

Campbell, K. A. (2015). Low-cost error detection through high-level synthesis. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/89068

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16^th Edition):

Campbell, Keith A. “Low-cost error detection through high-level synthesis.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed April 20, 2021. http://hdl.handle.net/2142/89068.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7^th Edition):

Campbell, Keith A. “Low-cost error detection through high-level synthesis.” 2015. Web. 20 Apr 2021.

Vancouver:

Campbell KA. Low-cost error detection through high-level synthesis. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2021 Apr 20]. Available from: http://hdl.handle.net/2142/89068.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Campbell KA. Low-cost error detection through high-level synthesis. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/89068

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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