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You searched for subject:(stuck at faults). Showing records 1 – 7 of 7 total matches.

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University of Iowa

1. Yang, Fan. New tests and test methodologies for scan cell internal faults.

Degree: PhD, Electrical and Computer Engineering, 2009, University of Iowa

  Semiconductor industry goals for the quality of shipped products continue to get higher to satisfy customer requirements. Higher quality of shipped electronic devices can… (more)

Subjects/Keywords: bridging faults; faults in scan cell; faults in scan chain; stuck-at faults; stuck-on faults; stuck-open faults; Electrical and Computer Engineering

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APA (6th Edition):

Yang, F. (2009). New tests and test methodologies for scan cell internal faults. (Doctoral Dissertation). University of Iowa. Retrieved from https://ir.uiowa.edu/etd/452

Chicago Manual of Style (16th Edition):

Yang, Fan. “New tests and test methodologies for scan cell internal faults.” 2009. Doctoral Dissertation, University of Iowa. Accessed April 20, 2021. https://ir.uiowa.edu/etd/452.

MLA Handbook (7th Edition):

Yang, Fan. “New tests and test methodologies for scan cell internal faults.” 2009. Web. 20 Apr 2021.

Vancouver:

Yang F. New tests and test methodologies for scan cell internal faults. [Internet] [Doctoral dissertation]. University of Iowa; 2009. [cited 2021 Apr 20]. Available from: https://ir.uiowa.edu/etd/452.

Council of Science Editors:

Yang F. New tests and test methodologies for scan cell internal faults. [Doctoral Dissertation]. University of Iowa; 2009. Available from: https://ir.uiowa.edu/etd/452

2. Kuentzer, Felipe Augusto. More than a timing resilient template : a case study on reliability-oriented improvements on blade.

Degree: 2018, Pontifical Catholic University of Rio Grande do Sul

Submitted by PPG Ci?ncia da Computa??o ([email protected]) on 2018-05-21T13:19:36Z No. of bitstreams: 1 FELIPE_AUGUSTO_KUENTZER_TES.pdf: 3277301 bytes, checksum: 7e77c5eb72299302d091329bde56b953 (MD5)

Approved for entry into archive by… (more)

Subjects/Keywords: Projeto Resiliente a Varia??es de Atraso; Projeto Ass?ncrono; Projeto Visando Testabilidade; Teste Funcional; Falhas de Stuck-at; Falhas de Atraso; Blade; Timing Resilient Design; Asynchronous Design; Design for Testability; Functional Testing; Stuck-at Faults; Delay Faults; CIENCIA DA COMPUTACAO::TEORIA DA COMPUTACAO

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APA (6th Edition):

Kuentzer, F. A. (2018). More than a timing resilient template : a case study on reliability-oriented improvements on blade. (Doctoral Dissertation). Pontifical Catholic University of Rio Grande do Sul. Retrieved from http://tede2.pucrs.br/tede2/handle/tede/8093

Chicago Manual of Style (16th Edition):

Kuentzer, Felipe Augusto. “More than a timing resilient template : a case study on reliability-oriented improvements on blade.” 2018. Doctoral Dissertation, Pontifical Catholic University of Rio Grande do Sul. Accessed April 20, 2021. http://tede2.pucrs.br/tede2/handle/tede/8093.

MLA Handbook (7th Edition):

Kuentzer, Felipe Augusto. “More than a timing resilient template : a case study on reliability-oriented improvements on blade.” 2018. Web. 20 Apr 2021.

Vancouver:

Kuentzer FA. More than a timing resilient template : a case study on reliability-oriented improvements on blade. [Internet] [Doctoral dissertation]. Pontifical Catholic University of Rio Grande do Sul; 2018. [cited 2021 Apr 20]. Available from: http://tede2.pucrs.br/tede2/handle/tede/8093.

Council of Science Editors:

Kuentzer FA. More than a timing resilient template : a case study on reliability-oriented improvements on blade. [Doctoral Dissertation]. Pontifical Catholic University of Rio Grande do Sul; 2018. Available from: http://tede2.pucrs.br/tede2/handle/tede/8093

3. Lawrence, Ignatius Praveen. Improving Power, Performance and Area with Test: A Case Study.

Degree: MS, Computer Engineering, 2018, Texas A&M University

 As more low power devices are needed for applications such as Internet of Things, reducing power and area is becoming more critical. Reducing power consumption… (more)

Subjects/Keywords: partial scan; stuck-at faults; transition; delay faults; PPA; ATPG; frequency; TNS; near-threshold technology

at faults (SAFs) in a partial scan design. In Figure 3, we can see that two… …faults captured by the first non-scan DFF need N + 1 capture cycles to be observed at an SDFF… …stuck-at 1 (SA1) fault in Figure 6, we need the output values of FF4 and FF5 (… …control and observe at every DFF. We determine sequentially redundant faults as those that are… …low fan-in, the non-scan DFF has at least one easy path to propagate captured faults. Here… 

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APA (6th Edition):

Lawrence, I. P. (2018). Improving Power, Performance and Area with Test: A Case Study. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/173669

Chicago Manual of Style (16th Edition):

Lawrence, Ignatius Praveen. “Improving Power, Performance and Area with Test: A Case Study.” 2018. Masters Thesis, Texas A&M University. Accessed April 20, 2021. http://hdl.handle.net/1969.1/173669.

MLA Handbook (7th Edition):

Lawrence, Ignatius Praveen. “Improving Power, Performance and Area with Test: A Case Study.” 2018. Web. 20 Apr 2021.

Vancouver:

Lawrence IP. Improving Power, Performance and Area with Test: A Case Study. [Internet] [Masters thesis]. Texas A&M University; 2018. [cited 2021 Apr 20]. Available from: http://hdl.handle.net/1969.1/173669.

Council of Science Editors:

Lawrence IP. Improving Power, Performance and Area with Test: A Case Study. [Masters Thesis]. Texas A&M University; 2018. Available from: http://hdl.handle.net/1969.1/173669

4. Marques, Felipe de Souza. Um algoritmo formal para remoção de redundâncias.

Degree: 2003, Brazil

 Os algoritmos para síntese de circuitos digitais em geral visam a melhoria de uma função de custo composta de quatro critérios: área, desempenho, potência e… (more)

Subjects/Keywords: Microeletrônica; BBDs; Remocao : Redundancias; Redundancy removal; False paths; Stuck-at faults; Path delay faults; BDD; VPBDD; Unate functions

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APA (6th Edition):

Marques, F. d. S. (2003). Um algoritmo formal para remoção de redundâncias. (Masters Thesis). Brazil. Retrieved from http://hdl.handle.net/10183/8498

Chicago Manual of Style (16th Edition):

Marques, Felipe de Souza. “Um algoritmo formal para remoção de redundâncias.” 2003. Masters Thesis, Brazil. Accessed April 20, 2021. http://hdl.handle.net/10183/8498.

MLA Handbook (7th Edition):

Marques, Felipe de Souza. “Um algoritmo formal para remoção de redundâncias.” 2003. Web. 20 Apr 2021.

Vancouver:

Marques FdS. Um algoritmo formal para remoção de redundâncias. [Internet] [Masters thesis]. Brazil; 2003. [cited 2021 Apr 20]. Available from: http://hdl.handle.net/10183/8498.

Council of Science Editors:

Marques FdS. Um algoritmo formal para remoção de redundâncias. [Masters Thesis]. Brazil; 2003. Available from: http://hdl.handle.net/10183/8498


Texas A&M University

5. Layek, Ritwik. Pathways, Networks and Therapy: A Boolean Approach to Systems Biology.

Degree: PhD, Electrical Engineering, 2012, Texas A&M University

 The area of systems biology evolved in an attempt to introduce mathematical systems theory principles in biology. Although we believe that all biological processes are… (more)

Subjects/Keywords: Systems Biology; Boolean Network; Probabilistic Boolean Network; Markov Chain; State transition diagram; Dynamic Programming; Therapeutic Intervention; Karnaugh Map; Signal Transduction Pathways; Regulatory Networks; DNA damage pathways; P53; Cancer; Cell Cycle; Growth Factor Mediated Pathways; Targeted Therapy; Combination Drug; Genetic Mutation; Stuck-at Faults; Fault Detection; Fault Classification

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Layek, R. (2012). Pathways, Networks and Therapy: A Boolean Approach to Systems Biology. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-10829

Chicago Manual of Style (16th Edition):

Layek, Ritwik. “Pathways, Networks and Therapy: A Boolean Approach to Systems Biology.” 2012. Doctoral Dissertation, Texas A&M University. Accessed April 20, 2021. http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-10829.

MLA Handbook (7th Edition):

Layek, Ritwik. “Pathways, Networks and Therapy: A Boolean Approach to Systems Biology.” 2012. Web. 20 Apr 2021.

Vancouver:

Layek R. Pathways, Networks and Therapy: A Boolean Approach to Systems Biology. [Internet] [Doctoral dissertation]. Texas A&M University; 2012. [cited 2021 Apr 20]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-10829.

Council of Science Editors:

Layek R. Pathways, Networks and Therapy: A Boolean Approach to Systems Biology. [Doctoral Dissertation]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-05-10829

6. Vissa, Pranay. Toward high-level synthesis of reliable circuits through low-cost modulo shadow datapaths.

Degree: MS, Electrical & Computer Engr, 2015, University of Illinois – Urbana-Champaign

 With transistor dimensions shrinking to the atomic scale, a plethora of new reliability problems presents a barrier to continued Moore’s law scaling. Traditional modular redundancy… (more)

Subjects/Keywords: high-level synthesis; automation; error detection; scheduling; binding; optimization; pipelining; modulo arithmetic; logic optimization; state machine; datapath; shadow logic; low cost; high performance; electrical faults; Aliasing; stuck-at faults; soft errors; timing errors; checkpointing; rollback recovery

stuck-at faults, transient errors, and timing errors. Stuck-at faults are the result of… …stuck-at faults to affect both redundant datapaths in the same way. Further state machine… …inject stuck-at faults, the netlist transform inserts AND (for stuck-at 0) or OR… …faults [9]. For unmasked errors with mod-5 units, we observe an average stuck-at… …fabrication defects that leave a gate output stuck at either 0 or 1 regardless of the input… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vissa, P. (2015). Toward high-level synthesis of reliable circuits through low-cost modulo shadow datapaths. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/78571

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vissa, Pranay. “Toward high-level synthesis of reliable circuits through low-cost modulo shadow datapaths.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed April 20, 2021. http://hdl.handle.net/2142/78571.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vissa, Pranay. “Toward high-level synthesis of reliable circuits through low-cost modulo shadow datapaths.” 2015. Web. 20 Apr 2021.

Vancouver:

Vissa P. Toward high-level synthesis of reliable circuits through low-cost modulo shadow datapaths. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2021 Apr 20]. Available from: http://hdl.handle.net/2142/78571.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vissa P. Toward high-level synthesis of reliable circuits through low-cost modulo shadow datapaths. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/78571

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

7. Campbell, Keith A. Low-cost error detection through high-level synthesis.

Degree: MS, Electrical & Computer Engineering, 2015, University of Illinois – Urbana-Champaign

 System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling and complexity has resulted in a… (more)

Subjects/Keywords: High-level synthesis; Automation; error detection; scheduling; binding; compiler transformation; compiler optimization; pipelining; modulo arithmetic; logic optimization; state machine; datapath, control logic; shadow logic; low cost; high performance; electrical bugs; Aliasing; stuck-at faults; soft errors; timing errors; checkpointing; rollback; recovery; post-silicon validation; Accelerators; system on a chip; signature generation; execution signatures; execution hashing; logic bugs; nondeterministic bugs; masked errors; circuit reliability; hot spots; wear out; silent data corruption; observability; detection latency; mixed datapath; diversity; checkpoint corruption; error injection; error removal; Quick Error Detection (QED); Hybrid Quick Error Detection (H-QED); hybrid hardware/software; execution tracing; address conversion; undefined behavior; High-Level Synthesis (HLS) engine bugs; detection coverage

…transistor fabrication failures. These permanent defects typically manifest as stuck-at faults… …arrives too late. 1.2.2 Stuck-at Faults Fabrication defects result in gate outputs being stuck… …errors and stuck-at faults to a↵ect both redundant datapaths in the same way. Further state… …wires that are supposed to be the output of a logic gate are stuck at logic 0 or logic 1 and… …original driver and connect it to a constant logic 0 or 1 instead. Stuck-at 0 (1)… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Campbell, K. A. (2015). Low-cost error detection through high-level synthesis. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/89068

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Campbell, Keith A. “Low-cost error detection through high-level synthesis.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed April 20, 2021. http://hdl.handle.net/2142/89068.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Campbell, Keith A. “Low-cost error detection through high-level synthesis.” 2015. Web. 20 Apr 2021.

Vancouver:

Campbell KA. Low-cost error detection through high-level synthesis. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2021 Apr 20]. Available from: http://hdl.handle.net/2142/89068.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Campbell KA. Low-cost error detection through high-level synthesis. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/89068

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

.