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You searched for subject:(soft error). Showing records 1 – 30 of 110 total matches.

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University of Waterloo

1. Ghaznavi, Solmaz. Soft Error Resistant Design of the AES Cipher Using SRAM-based FPGA.

Degree: 2011, University of Waterloo

 This thesis presents a new architecture for the reliable implementation of the symmetric-key algorithm Advanced Encryption Standard (AES) in Field Programmable Gate Arrays (FPGAs). Since… (more)

Subjects/Keywords: soft error; AES

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ghaznavi, S. (2011). Soft Error Resistant Design of the AES Cipher Using SRAM-based FPGA. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/5792

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ghaznavi, Solmaz. “Soft Error Resistant Design of the AES Cipher Using SRAM-based FPGA.” 2011. Thesis, University of Waterloo. Accessed April 12, 2021. http://hdl.handle.net/10012/5792.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ghaznavi, Solmaz. “Soft Error Resistant Design of the AES Cipher Using SRAM-based FPGA.” 2011. Web. 12 Apr 2021.

Vancouver:

Ghaznavi S. Soft Error Resistant Design of the AES Cipher Using SRAM-based FPGA. [Internet] [Thesis]. University of Waterloo; 2011. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10012/5792.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ghaznavi S. Soft Error Resistant Design of the AES Cipher Using SRAM-based FPGA. [Thesis]. University of Waterloo; 2011. Available from: http://hdl.handle.net/10012/5792

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Vanderbilt University

2. Ossi, Edward John. Soft-error mitigation at the architecture-level using Berger codes for error detection.

Degree: ME, Electrical Engineering, 2011, Vanderbilt University

Soft-error mitigation using design techniques at the architecture-level can overcome the limitations of process and circuit-level mitigation techniques in advanced technologies. This thesis presents two… (more)

Subjects/Keywords: berger code; architecture; soft error

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APA (6th Edition):

Ossi, E. J. (2011). Soft-error mitigation at the architecture-level using Berger codes for error detection. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/15019

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ossi, Edward John. “Soft-error mitigation at the architecture-level using Berger codes for error detection.” 2011. Thesis, Vanderbilt University. Accessed April 12, 2021. http://hdl.handle.net/1803/15019.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ossi, Edward John. “Soft-error mitigation at the architecture-level using Berger codes for error detection.” 2011. Web. 12 Apr 2021.

Vancouver:

Ossi EJ. Soft-error mitigation at the architecture-level using Berger codes for error detection. [Internet] [Thesis]. Vanderbilt University; 2011. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/1803/15019.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ossi EJ. Soft-error mitigation at the architecture-level using Berger codes for error detection. [Thesis]. Vanderbilt University; 2011. Available from: http://hdl.handle.net/1803/15019

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Saskatchewan

3. Xie, Hao 1988-. Study of Single Event Transient Error Mitigation.

Degree: 2017, University of Saskatchewan

 Single Event Transient (SET) errors in ground-level electronic devices are a growing concern in the radiation hardening field. However, effective SET mitigation technologies which satisfy… (more)

Subjects/Keywords: Single Event Transient; Soft Error Mitigation

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APA (6th Edition):

Xie, H. 1. (2017). Study of Single Event Transient Error Mitigation. (Thesis). University of Saskatchewan. Retrieved from http://hdl.handle.net/10388/8025

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Xie, Hao 1988-. “Study of Single Event Transient Error Mitigation.” 2017. Thesis, University of Saskatchewan. Accessed April 12, 2021. http://hdl.handle.net/10388/8025.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Xie, Hao 1988-. “Study of Single Event Transient Error Mitigation.” 2017. Web. 12 Apr 2021.

Vancouver:

Xie H1. Study of Single Event Transient Error Mitigation. [Internet] [Thesis]. University of Saskatchewan; 2017. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10388/8025.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Xie H1. Study of Single Event Transient Error Mitigation. [Thesis]. University of Saskatchewan; 2017. Available from: http://hdl.handle.net/10388/8025

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

4. Bangalore Srinivasmurthy, Sowmyalatha. Impact of soft errors on scientific simulations .

Degree: 2011, Penn State University

 The trends in computing processor technology are driving toward multicores through miniaturization that can pack many processors in a given chip area. This miniaturization has… (more)

Subjects/Keywords: sparse matrix; iterative linear solvers; soft error

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APA (6th Edition):

Bangalore Srinivasmurthy, S. (2011). Impact of soft errors on scientific simulations . (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/12404

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bangalore Srinivasmurthy, Sowmyalatha. “Impact of soft errors on scientific simulations .” 2011. Thesis, Penn State University. Accessed April 12, 2021. https://submit-etda.libraries.psu.edu/catalog/12404.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bangalore Srinivasmurthy, Sowmyalatha. “Impact of soft errors on scientific simulations .” 2011. Web. 12 Apr 2021.

Vancouver:

Bangalore Srinivasmurthy S. Impact of soft errors on scientific simulations . [Internet] [Thesis]. Penn State University; 2011. [cited 2021 Apr 12]. Available from: https://submit-etda.libraries.psu.edu/catalog/12404.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bangalore Srinivasmurthy S. Impact of soft errors on scientific simulations . [Thesis]. Penn State University; 2011. Available from: https://submit-etda.libraries.psu.edu/catalog/12404

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Southern California

5. Suh, Jinho. Models for soft errors in low-level caches.

Degree: PhD, Computer Engineering, 2012, University of Southern California

 Benchmarking the FIT (failures in time of 1E9 hours) rates of caches due to soft errors is critical to evaluate the relative merits of various… (more)

Subjects/Keywords: cache; modeling; reliability; sampling; simulation; soft error

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APA (6th Edition):

Suh, J. (2012). Models for soft errors in low-level caches. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/200536/rec/4161

Chicago Manual of Style (16th Edition):

Suh, Jinho. “Models for soft errors in low-level caches.” 2012. Doctoral Dissertation, University of Southern California. Accessed April 12, 2021. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/200536/rec/4161.

MLA Handbook (7th Edition):

Suh, Jinho. “Models for soft errors in low-level caches.” 2012. Web. 12 Apr 2021.

Vancouver:

Suh J. Models for soft errors in low-level caches. [Internet] [Doctoral dissertation]. University of Southern California; 2012. [cited 2021 Apr 12]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/200536/rec/4161.

Council of Science Editors:

Suh J. Models for soft errors in low-level caches. [Doctoral Dissertation]. University of Southern California; 2012. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/200536/rec/4161


Louisiana State University

6. Chen, Sui. Enhancing Program Soft Error Resilience through Algorithmic Approaches.

Degree: MSEE, Electrical and Computer Engineering, 2016, Louisiana State University

 The rising count and shrinking feature size of transistors within modern computers is making them increasingly vulnerable to various types of soft faults. This problem… (more)

Subjects/Keywords: Soft Error; Algorithmic Fault Resilience; Fault Injection

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APA (6th Edition):

Chen, S. (2016). Enhancing Program Soft Error Resilience through Algorithmic Approaches. (Masters Thesis). Louisiana State University. Retrieved from etd-09262016-115601 ; https://digitalcommons.lsu.edu/gradschool_theses/4411

Chicago Manual of Style (16th Edition):

Chen, Sui. “Enhancing Program Soft Error Resilience through Algorithmic Approaches.” 2016. Masters Thesis, Louisiana State University. Accessed April 12, 2021. etd-09262016-115601 ; https://digitalcommons.lsu.edu/gradschool_theses/4411.

MLA Handbook (7th Edition):

Chen, Sui. “Enhancing Program Soft Error Resilience through Algorithmic Approaches.” 2016. Web. 12 Apr 2021.

Vancouver:

Chen S. Enhancing Program Soft Error Resilience through Algorithmic Approaches. [Internet] [Masters thesis]. Louisiana State University; 2016. [cited 2021 Apr 12]. Available from: etd-09262016-115601 ; https://digitalcommons.lsu.edu/gradschool_theses/4411.

Council of Science Editors:

Chen S. Enhancing Program Soft Error Resilience through Algorithmic Approaches. [Masters Thesis]. Louisiana State University; 2016. Available from: etd-09262016-115601 ; https://digitalcommons.lsu.edu/gradschool_theses/4411

7. Golnari, Pareesa Ameneh. Computing on Large, Sparse Datasets and Error-Prone Fabrics .

Degree: PhD, 2018, Princeton University

 In this dissertation we study problems arising from two trends: computation on large and sparse datasets and computing on error-prone fabrics. Every year the dataset… (more)

Subjects/Keywords: crs; error-tolerant computing; reliability; soft error; sparse formats; spmm

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APA (6th Edition):

Golnari, P. A. (2018). Computing on Large, Sparse Datasets and Error-Prone Fabrics . (Doctoral Dissertation). Princeton University. Retrieved from http://arks.princeton.edu/ark:/88435/dsp01m039k7603

Chicago Manual of Style (16th Edition):

Golnari, Pareesa Ameneh. “Computing on Large, Sparse Datasets and Error-Prone Fabrics .” 2018. Doctoral Dissertation, Princeton University. Accessed April 12, 2021. http://arks.princeton.edu/ark:/88435/dsp01m039k7603.

MLA Handbook (7th Edition):

Golnari, Pareesa Ameneh. “Computing on Large, Sparse Datasets and Error-Prone Fabrics .” 2018. Web. 12 Apr 2021.

Vancouver:

Golnari PA. Computing on Large, Sparse Datasets and Error-Prone Fabrics . [Internet] [Doctoral dissertation]. Princeton University; 2018. [cited 2021 Apr 12]. Available from: http://arks.princeton.edu/ark:/88435/dsp01m039k7603.

Council of Science Editors:

Golnari PA. Computing on Large, Sparse Datasets and Error-Prone Fabrics . [Doctoral Dissertation]. Princeton University; 2018. Available from: http://arks.princeton.edu/ark:/88435/dsp01m039k7603

8. Batagin Armelin, Fábio. Stratégie d'estimation de la vulnérabilité aux erreurs `soft' basée sur la susceptibilité aux événements transitoires de chaque porte logique : A strategy for soft-error vulnerability estimation using the single-event transient susceptibilities of each gate.

Degree: Docteur es, Réseaux, information et communications, 2019, Université Paris-Saclay (ComUE); Instituto tecnólogico de aeronáutica (São José dos Campos, Brésil)

La vulnérabilité aux erreurs récupérables (SEV - Soft Error Vulnerability) est un paramètre estimé qui, associé aux caractéristiques de l’environnement de rayonnement, permet d’obtenir le… (more)

Subjects/Keywords: Taux d'erreur soft; Vulnérabilité aux erreurs soft; Injection de défauts; Transitoires d'événements uniques; FPGA; Soft error rate; Soft-Error Vulnerability; Fault injection; Single-Event Transient; FPGA

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APA (6th Edition):

Batagin Armelin, F. (2019). Stratégie d'estimation de la vulnérabilité aux erreurs `soft' basée sur la susceptibilité aux événements transitoires de chaque porte logique : A strategy for soft-error vulnerability estimation using the single-event transient susceptibilities of each gate. (Doctoral Dissertation). Université Paris-Saclay (ComUE); Instituto tecnólogico de aeronáutica (São José dos Campos, Brésil). Retrieved from http://www.theses.fr/2019SACLT035

Chicago Manual of Style (16th Edition):

Batagin Armelin, Fábio. “Stratégie d'estimation de la vulnérabilité aux erreurs `soft' basée sur la susceptibilité aux événements transitoires de chaque porte logique : A strategy for soft-error vulnerability estimation using the single-event transient susceptibilities of each gate.” 2019. Doctoral Dissertation, Université Paris-Saclay (ComUE); Instituto tecnólogico de aeronáutica (São José dos Campos, Brésil). Accessed April 12, 2021. http://www.theses.fr/2019SACLT035.

MLA Handbook (7th Edition):

Batagin Armelin, Fábio. “Stratégie d'estimation de la vulnérabilité aux erreurs `soft' basée sur la susceptibilité aux événements transitoires de chaque porte logique : A strategy for soft-error vulnerability estimation using the single-event transient susceptibilities of each gate.” 2019. Web. 12 Apr 2021.

Vancouver:

Batagin Armelin F. Stratégie d'estimation de la vulnérabilité aux erreurs `soft' basée sur la susceptibilité aux événements transitoires de chaque porte logique : A strategy for soft-error vulnerability estimation using the single-event transient susceptibilities of each gate. [Internet] [Doctoral dissertation]. Université Paris-Saclay (ComUE); Instituto tecnólogico de aeronáutica (São José dos Campos, Brésil); 2019. [cited 2021 Apr 12]. Available from: http://www.theses.fr/2019SACLT035.

Council of Science Editors:

Batagin Armelin F. Stratégie d'estimation de la vulnérabilité aux erreurs `soft' basée sur la susceptibilité aux événements transitoires de chaque porte logique : A strategy for soft-error vulnerability estimation using the single-event transient susceptibilities of each gate. [Doctoral Dissertation]. Université Paris-Saclay (ComUE); Instituto tecnólogico de aeronáutica (São José dos Campos, Brésil); 2019. Available from: http://www.theses.fr/2019SACLT035


The Ohio State University

9. Liu, Jiaqi. Handling Soft and Hard Errors for Scientific Applications.

Degree: PhD, Computer Science and Engineering, 2017, The Ohio State University

 Due to the rapid decrease in Mean Time Between Failure (MTBF) in High Performance Computing, fault tolerance emerged as a critical topic to improve overall… (more)

Subjects/Keywords: Computer Engineering; Computer Science; hard error; soft error; scientific application; fault tolerance; resilience

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APA (6th Edition):

Liu, J. (2017). Handling Soft and Hard Errors for Scientific Applications. (Doctoral Dissertation). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1483632126075067

Chicago Manual of Style (16th Edition):

Liu, Jiaqi. “Handling Soft and Hard Errors for Scientific Applications.” 2017. Doctoral Dissertation, The Ohio State University. Accessed April 12, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=osu1483632126075067.

MLA Handbook (7th Edition):

Liu, Jiaqi. “Handling Soft and Hard Errors for Scientific Applications.” 2017. Web. 12 Apr 2021.

Vancouver:

Liu J. Handling Soft and Hard Errors for Scientific Applications. [Internet] [Doctoral dissertation]. The Ohio State University; 2017. [cited 2021 Apr 12]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1483632126075067.

Council of Science Editors:

Liu J. Handling Soft and Hard Errors for Scientific Applications. [Doctoral Dissertation]. The Ohio State University; 2017. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1483632126075067


NSYSU

10. Chih, Tsung-Liang. Design and Implementation of A Defect and Soft-Error Tolerable Cache.

Degree: Master, Electrical Engineering, 2015, NSYSU

 When the feature size of transistors becomes smaller, chips are more sensitive to process defects and variation, which may result in low yield and reliability.… (more)

Subjects/Keywords: cache; performance degradation tolerance; performance degrading faults; defect; soft-error

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APA (6th Edition):

Chih, T. (2015). Design and Implementation of A Defect and Soft-Error Tolerable Cache. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-142034

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chih, Tsung-Liang. “Design and Implementation of A Defect and Soft-Error Tolerable Cache.” 2015. Thesis, NSYSU. Accessed April 12, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-142034.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chih, Tsung-Liang. “Design and Implementation of A Defect and Soft-Error Tolerable Cache.” 2015. Web. 12 Apr 2021.

Vancouver:

Chih T. Design and Implementation of A Defect and Soft-Error Tolerable Cache. [Internet] [Thesis]. NSYSU; 2015. [cited 2021 Apr 12]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-142034.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chih T. Design and Implementation of A Defect and Soft-Error Tolerable Cache. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-142034

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


UCLA

11. Feng, Zhe. Logic Synthesis for FPGA Reliability.

Degree: Electrical Engineering, 2013, UCLA

 Logic synthesis is one of the key stages in the computer-aided design (CAD) flow for a field programmable gate array (FPGA) based design. It usually… (more)

Subjects/Keywords: Electrical engineering; FPGA; Logic synthesis; Reliability; Soft error

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APA (6th Edition):

Feng, Z. (2013). Logic Synthesis for FPGA Reliability. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/7w7602f5

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Feng, Zhe. “Logic Synthesis for FPGA Reliability.” 2013. Thesis, UCLA. Accessed April 12, 2021. http://www.escholarship.org/uc/item/7w7602f5.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Feng, Zhe. “Logic Synthesis for FPGA Reliability.” 2013. Web. 12 Apr 2021.

Vancouver:

Feng Z. Logic Synthesis for FPGA Reliability. [Internet] [Thesis]. UCLA; 2013. [cited 2021 Apr 12]. Available from: http://www.escholarship.org/uc/item/7w7602f5.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Feng Z. Logic Synthesis for FPGA Reliability. [Thesis]. UCLA; 2013. Available from: http://www.escholarship.org/uc/item/7w7602f5

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Vanderbilt University

12. Sierawski, Brian David. The Role of Singly-Charged Particles in Microelectronics Reliability.

Degree: PhD, Electrical Engineering, 2011, Vanderbilt University

 Lightly ionizing particles in any radiation environment have the potential to induce single event upsets in scaled CMOS technologies. As microelectronic devices become smaller and… (more)

Subjects/Keywords: proton; muon; direct ionization; single event upset; soft error; memory

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APA (6th Edition):

Sierawski, B. D. (2011). The Role of Singly-Charged Particles in Microelectronics Reliability. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/14976

Chicago Manual of Style (16th Edition):

Sierawski, Brian David. “The Role of Singly-Charged Particles in Microelectronics Reliability.” 2011. Doctoral Dissertation, Vanderbilt University. Accessed April 12, 2021. http://hdl.handle.net/1803/14976.

MLA Handbook (7th Edition):

Sierawski, Brian David. “The Role of Singly-Charged Particles in Microelectronics Reliability.” 2011. Web. 12 Apr 2021.

Vancouver:

Sierawski BD. The Role of Singly-Charged Particles in Microelectronics Reliability. [Internet] [Doctoral dissertation]. Vanderbilt University; 2011. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/1803/14976.

Council of Science Editors:

Sierawski BD. The Role of Singly-Charged Particles in Microelectronics Reliability. [Doctoral Dissertation]. Vanderbilt University; 2011. Available from: http://hdl.handle.net/1803/14976


Vanderbilt University

13. Gaspard, Nelson Joseph III. Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS.

Degree: PhD, Electrical Engineering, 2017, Vanderbilt University

 Alpha, heavy-ion, neutron, and proton experimental results from 130-nm to 28-nm technology nodes are establish single-event upset cross section trends in soft and hardened flip-flop… (more)

Subjects/Keywords: single event upset; CMOS; flip-flop; soft error

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APA (6th Edition):

Gaspard, N. J. I. (2017). Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/10824

Chicago Manual of Style (16th Edition):

Gaspard, Nelson Joseph III. “Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS.” 2017. Doctoral Dissertation, Vanderbilt University. Accessed April 12, 2021. http://hdl.handle.net/1803/10824.

MLA Handbook (7th Edition):

Gaspard, Nelson Joseph III. “Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS.” 2017. Web. 12 Apr 2021.

Vancouver:

Gaspard NJI. Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS. [Internet] [Doctoral dissertation]. Vanderbilt University; 2017. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/1803/10824.

Council of Science Editors:

Gaspard NJI. Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS. [Doctoral Dissertation]. Vanderbilt University; 2017. Available from: http://hdl.handle.net/1803/10824


Penn State University

14. Barth, Michael Judson. SB-BASED MATERIALS FOR BEYOND SI FIELD EFFECT TRANSISTOR DEVICES.

Degree: 2016, Penn State University

 Antimonide based (Sb) compound semiconductors owing to their superior electron and hole transport properties over Si are an attractive option as a channel replacement material… (more)

Subjects/Keywords: InAsSb; GaSb; InGaSb; Soft Error; Heavy Ion; Atomic Layer Deposition

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APA (6th Edition):

Barth, M. J. (2016). SB-BASED MATERIALS FOR BEYOND SI FIELD EFFECT TRANSISTOR DEVICES. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/13195mjb590

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Barth, Michael Judson. “SB-BASED MATERIALS FOR BEYOND SI FIELD EFFECT TRANSISTOR DEVICES.” 2016. Thesis, Penn State University. Accessed April 12, 2021. https://submit-etda.libraries.psu.edu/catalog/13195mjb590.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Barth, Michael Judson. “SB-BASED MATERIALS FOR BEYOND SI FIELD EFFECT TRANSISTOR DEVICES.” 2016. Web. 12 Apr 2021.

Vancouver:

Barth MJ. SB-BASED MATERIALS FOR BEYOND SI FIELD EFFECT TRANSISTOR DEVICES. [Internet] [Thesis]. Penn State University; 2016. [cited 2021 Apr 12]. Available from: https://submit-etda.libraries.psu.edu/catalog/13195mjb590.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Barth MJ. SB-BASED MATERIALS FOR BEYOND SI FIELD EFFECT TRANSISTOR DEVICES. [Thesis]. Penn State University; 2016. Available from: https://submit-etda.libraries.psu.edu/catalog/13195mjb590

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


McMaster University

15. Zuzarte, Marvin. A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits.

Degree: MASc, 2014, McMaster University

Safety and mission critical systems are currently deployed in many different fields where there is a greater presence of high energy particles (e.g. aerospace). The… (more)

Subjects/Keywords: FPGA; Fault injection; Field programmable gate array; runtime; soft error

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zuzarte, M. (2014). A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits. (Masters Thesis). McMaster University. Retrieved from http://hdl.handle.net/11375/16500

Chicago Manual of Style (16th Edition):

Zuzarte, Marvin. “A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits.” 2014. Masters Thesis, McMaster University. Accessed April 12, 2021. http://hdl.handle.net/11375/16500.

MLA Handbook (7th Edition):

Zuzarte, Marvin. “A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits.” 2014. Web. 12 Apr 2021.

Vancouver:

Zuzarte M. A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits. [Internet] [Masters thesis]. McMaster University; 2014. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/11375/16500.

Council of Science Editors:

Zuzarte M. A Tool For Run Time Soft Error Fault Injection Into FPGA Circuits. [Masters Thesis]. McMaster University; 2014. Available from: http://hdl.handle.net/11375/16500

16. Zhang, Kuiyuan. A Study to Evaluate and Project Soft Error Tolerance in Radiation-hardened Circuits Using Device and Physical Level Simulations : デバイスレベルと物理レベルシミュレーションを用いた対放射線回路のソフトエラー耐性の評価手法と予測手法に関する研究.

Degree: 博士(工学), 2016, Kyoto Institute of Technology / 京都工芸繊維大学

 My thesis focuses on projection and evaluation for soft error tolerance in the radiation-hardened circuit by device and physics level simulations. The SERs of various… (more)

Subjects/Keywords: Soft Error; Radiation-hard; VLSI; Simulation; TCAD; PHITS

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APA (6th Edition):

Zhang, K. (2016). A Study to Evaluate and Project Soft Error Tolerance in Radiation-hardened Circuits Using Device and Physical Level Simulations : デバイスレベルと物理レベルシミュレーションを用いた対放射線回路のソフトエラー耐性の評価手法と予測手法に関する研究. (Thesis). Kyoto Institute of Technology / 京都工芸繊維大学. Retrieved from http://hdl.handle.net/10212/2312

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhang, Kuiyuan. “A Study to Evaluate and Project Soft Error Tolerance in Radiation-hardened Circuits Using Device and Physical Level Simulations : デバイスレベルと物理レベルシミュレーションを用いた対放射線回路のソフトエラー耐性の評価手法と予測手法に関する研究.” 2016. Thesis, Kyoto Institute of Technology / 京都工芸繊維大学. Accessed April 12, 2021. http://hdl.handle.net/10212/2312.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhang, Kuiyuan. “A Study to Evaluate and Project Soft Error Tolerance in Radiation-hardened Circuits Using Device and Physical Level Simulations : デバイスレベルと物理レベルシミュレーションを用いた対放射線回路のソフトエラー耐性の評価手法と予測手法に関する研究.” 2016. Web. 12 Apr 2021.

Vancouver:

Zhang K. A Study to Evaluate and Project Soft Error Tolerance in Radiation-hardened Circuits Using Device and Physical Level Simulations : デバイスレベルと物理レベルシミュレーションを用いた対放射線回路のソフトエラー耐性の評価手法と予測手法に関する研究. [Internet] [Thesis]. Kyoto Institute of Technology / 京都工芸繊維大学; 2016. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10212/2312.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhang K. A Study to Evaluate and Project Soft Error Tolerance in Radiation-hardened Circuits Using Device and Physical Level Simulations : デバイスレベルと物理レベルシミュレーションを用いた対放射線回路のソフトエラー耐性の評価手法と予測手法に関する研究. [Thesis]. Kyoto Institute of Technology / 京都工芸繊維大学; 2016. Available from: http://hdl.handle.net/10212/2312

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

17. Luong, Dinh Hung. Soft-Error Tolerant Cache Architectures : 耐ソフト・エラーのキャッシュ・アーキテクチャ.

Degree: 博士(情報理工学), 2017, The University of Tokyo / 東京大学

 The problem of soft errors caused by radiation events are expected to get worse with technology scaling. This thesis focuses on mitigation of soft errors… (more)

Subjects/Keywords: soft error; defect; cache; reliability

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Luong, D. H. (2017). Soft-Error Tolerant Cache Architectures : 耐ソフト・エラーのキャッシュ・アーキテクチャ. (Thesis). The University of Tokyo / 東京大学. Retrieved from http://hdl.handle.net/2261/25849

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Luong, Dinh Hung. “Soft-Error Tolerant Cache Architectures : 耐ソフト・エラーのキャッシュ・アーキテクチャ.” 2017. Thesis, The University of Tokyo / 東京大学. Accessed April 12, 2021. http://hdl.handle.net/2261/25849.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Luong, Dinh Hung. “Soft-Error Tolerant Cache Architectures : 耐ソフト・エラーのキャッシュ・アーキテクチャ.” 2017. Web. 12 Apr 2021.

Vancouver:

Luong DH. Soft-Error Tolerant Cache Architectures : 耐ソフト・エラーのキャッシュ・アーキテクチャ. [Internet] [Thesis]. The University of Tokyo / 東京大学; 2017. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/2261/25849.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Luong DH. Soft-Error Tolerant Cache Architectures : 耐ソフト・エラーのキャッシュ・アーキテクチャ. [Thesis]. The University of Tokyo / 東京大学; 2017. Available from: http://hdl.handle.net/2261/25849

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Arizona State University

18. Jeyapaul, Reiley. Smart Compilers for Reliable and Power-efficient Embedded Computing.

Degree: PhD, Computer Science, 2012, Arizona State University

 Thanks to continuous technology scaling, intelligent, fast and smaller digital systems are now available at affordable costs. As a result, digital systems have found use… (more)

Subjects/Keywords: Computer science; cgra; compiler; computer architecture; power efficiency; reliability; soft error

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jeyapaul, R. (2012). Smart Compilers for Reliable and Power-efficient Embedded Computing. (Doctoral Dissertation). Arizona State University. Retrieved from http://repository.asu.edu/items/14766

Chicago Manual of Style (16th Edition):

Jeyapaul, Reiley. “Smart Compilers for Reliable and Power-efficient Embedded Computing.” 2012. Doctoral Dissertation, Arizona State University. Accessed April 12, 2021. http://repository.asu.edu/items/14766.

MLA Handbook (7th Edition):

Jeyapaul, Reiley. “Smart Compilers for Reliable and Power-efficient Embedded Computing.” 2012. Web. 12 Apr 2021.

Vancouver:

Jeyapaul R. Smart Compilers for Reliable and Power-efficient Embedded Computing. [Internet] [Doctoral dissertation]. Arizona State University; 2012. [cited 2021 Apr 12]. Available from: http://repository.asu.edu/items/14766.

Council of Science Editors:

Jeyapaul R. Smart Compilers for Reliable and Power-efficient Embedded Computing. [Doctoral Dissertation]. Arizona State University; 2012. Available from: http://repository.asu.edu/items/14766

19. Isaza-González, José. Aportaciones a la tolerancia a fallos en microprocesadores bajo efectos de la radiación .

Degree: 2018, University of Alicante

 El funcionamiento correcto de un sistema electrónico, aún bajo perturbaciones y fallos causados por la radiación, ha sido siempre un factor crucial en aplicaciones aeroespaciales,… (more)

Subjects/Keywords: Microprocessor reliability; Fault injection; Soft error; Radiation effects fault tolerance

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APA (6th Edition):

Isaza-González, J. (2018). Aportaciones a la tolerancia a fallos en microprocesadores bajo efectos de la radiación . (Thesis). University of Alicante. Retrieved from http://hdl.handle.net/10045/90359

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Isaza-González, José. “Aportaciones a la tolerancia a fallos en microprocesadores bajo efectos de la radiación .” 2018. Thesis, University of Alicante. Accessed April 12, 2021. http://hdl.handle.net/10045/90359.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Isaza-González, José. “Aportaciones a la tolerancia a fallos en microprocesadores bajo efectos de la radiación .” 2018. Web. 12 Apr 2021.

Vancouver:

Isaza-González J. Aportaciones a la tolerancia a fallos en microprocesadores bajo efectos de la radiación . [Internet] [Thesis]. University of Alicante; 2018. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10045/90359.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Isaza-González J. Aportaciones a la tolerancia a fallos en microprocesadores bajo efectos de la radiación . [Thesis]. University of Alicante; 2018. Available from: http://hdl.handle.net/10045/90359

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Minnesota

20. Kumar, Saurabh. Circuit Techniques For Characterization Of Radiation-Induced Soft Errors In Advanced Cmos Processes.

Degree: PhD, Electrical Engineering, 2018, University of Minnesota

Soft errors induced by particle strikes have been a major concern in reliability critical applications such as defense, space, medicine and finance etc. A number… (more)

Subjects/Keywords: FinFET; MBU; Radiation strike; SET; SEU; Soft Error

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kumar, S. (2018). Circuit Techniques For Characterization Of Radiation-Induced Soft Errors In Advanced Cmos Processes. (Doctoral Dissertation). University of Minnesota. Retrieved from http://hdl.handle.net/11299/215201

Chicago Manual of Style (16th Edition):

Kumar, Saurabh. “Circuit Techniques For Characterization Of Radiation-Induced Soft Errors In Advanced Cmos Processes.” 2018. Doctoral Dissertation, University of Minnesota. Accessed April 12, 2021. http://hdl.handle.net/11299/215201.

MLA Handbook (7th Edition):

Kumar, Saurabh. “Circuit Techniques For Characterization Of Radiation-Induced Soft Errors In Advanced Cmos Processes.” 2018. Web. 12 Apr 2021.

Vancouver:

Kumar S. Circuit Techniques For Characterization Of Radiation-Induced Soft Errors In Advanced Cmos Processes. [Internet] [Doctoral dissertation]. University of Minnesota; 2018. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/11299/215201.

Council of Science Editors:

Kumar S. Circuit Techniques For Characterization Of Radiation-Induced Soft Errors In Advanced Cmos Processes. [Doctoral Dissertation]. University of Minnesota; 2018. Available from: http://hdl.handle.net/11299/215201


Northeastern University

21. Shazli, Syed Zafar. High level modeling and mitigation of transient errors in nano-scale systems.

Degree: PhD, Department of Electrical and Computer Engineering, 2011, Northeastern University

Soft errors, due to cosmic radiations, are a major reliability barrier for VLSI designs. The vulnerability of such systems to soft errors grows exponentially with… (more)

Subjects/Keywords: Error Recovery; Field Analysis; Online Error Detection; SER Estimation; Soft Errors; Transient Errors; Electrical and Computer Engineering; Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shazli, S. Z. (2011). High level modeling and mitigation of transient errors in nano-scale systems. (Doctoral Dissertation). Northeastern University. Retrieved from http://hdl.handle.net/2047/d20002793

Chicago Manual of Style (16th Edition):

Shazli, Syed Zafar. “High level modeling and mitigation of transient errors in nano-scale systems.” 2011. Doctoral Dissertation, Northeastern University. Accessed April 12, 2021. http://hdl.handle.net/2047/d20002793.

MLA Handbook (7th Edition):

Shazli, Syed Zafar. “High level modeling and mitigation of transient errors in nano-scale systems.” 2011. Web. 12 Apr 2021.

Vancouver:

Shazli SZ. High level modeling and mitigation of transient errors in nano-scale systems. [Internet] [Doctoral dissertation]. Northeastern University; 2011. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/2047/d20002793.

Council of Science Editors:

Shazli SZ. High level modeling and mitigation of transient errors in nano-scale systems. [Doctoral Dissertation]. Northeastern University; 2011. Available from: http://hdl.handle.net/2047/d20002793

22. Rhod, Eduardo Luis. Quaternary CLB a falul tolerant quaternary FPGA.

Degree: 2012, Brazil

A diminuição no tamanho dos transistores vem aumentando cada vez mais o número de funções que os dispositivos eletrônicos podem realizar. Apesar da diminuição do… (more)

Subjects/Keywords: Microeletrônica; Tolerancia : Falhas; Sistemas digitais; Fault tolerant architectures; Quaternary circuits; Error detection techniques; Soft error rate; FPGAs

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Rhod, E. L. (2012). Quaternary CLB a falul tolerant quaternary FPGA. (Doctoral Dissertation). Brazil. Retrieved from http://hdl.handle.net/10183/72925

Chicago Manual of Style (16th Edition):

Rhod, Eduardo Luis. “Quaternary CLB a falul tolerant quaternary FPGA.” 2012. Doctoral Dissertation, Brazil. Accessed April 12, 2021. http://hdl.handle.net/10183/72925.

MLA Handbook (7th Edition):

Rhod, Eduardo Luis. “Quaternary CLB a falul tolerant quaternary FPGA.” 2012. Web. 12 Apr 2021.

Vancouver:

Rhod EL. Quaternary CLB a falul tolerant quaternary FPGA. [Internet] [Doctoral dissertation]. Brazil; 2012. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10183/72925.

Council of Science Editors:

Rhod EL. Quaternary CLB a falul tolerant quaternary FPGA. [Doctoral Dissertation]. Brazil; 2012. Available from: http://hdl.handle.net/10183/72925

23. Lackmann-Zimpeck, Alexandra. Circuit-level approaches to mitigate the process variability and soft errors in FinFET logic cells : Approches au niveau du circuit pour atténuer la variabilité de fabrication et les soft errors dans les cellules logiques FinFET.

Degree: Docteur es, Micro et Nanosystèmes, 2019, Toulouse, ISAE; Universidade Federal do Rio Grande do Sul (Porto Alegre, Brésil)

 Les contraintes imposées par la roadmap technologique nanométrique imposent aux fabricants de microélectronique une réduction de la variabilité de fabrication mais également de durcissement vis-à-vis… (more)

Subjects/Keywords: Microélectronique; Design au niveau circuit; Variabilité de fabrication; Fiabilité; Soft error; FinFET; Microelectronics; Circuit-Level design; Process variability; Reliability; Soft error; FinFET

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APA (6th Edition):

Lackmann-Zimpeck, A. (2019). Circuit-level approaches to mitigate the process variability and soft errors in FinFET logic cells : Approches au niveau du circuit pour atténuer la variabilité de fabrication et les soft errors dans les cellules logiques FinFET. (Doctoral Dissertation). Toulouse, ISAE; Universidade Federal do Rio Grande do Sul (Porto Alegre, Brésil). Retrieved from http://www.theses.fr/2019ESAE0026

Chicago Manual of Style (16th Edition):

Lackmann-Zimpeck, Alexandra. “Circuit-level approaches to mitigate the process variability and soft errors in FinFET logic cells : Approches au niveau du circuit pour atténuer la variabilité de fabrication et les soft errors dans les cellules logiques FinFET.” 2019. Doctoral Dissertation, Toulouse, ISAE; Universidade Federal do Rio Grande do Sul (Porto Alegre, Brésil). Accessed April 12, 2021. http://www.theses.fr/2019ESAE0026.

MLA Handbook (7th Edition):

Lackmann-Zimpeck, Alexandra. “Circuit-level approaches to mitigate the process variability and soft errors in FinFET logic cells : Approches au niveau du circuit pour atténuer la variabilité de fabrication et les soft errors dans les cellules logiques FinFET.” 2019. Web. 12 Apr 2021.

Vancouver:

Lackmann-Zimpeck A. Circuit-level approaches to mitigate the process variability and soft errors in FinFET logic cells : Approches au niveau du circuit pour atténuer la variabilité de fabrication et les soft errors dans les cellules logiques FinFET. [Internet] [Doctoral dissertation]. Toulouse, ISAE; Universidade Federal do Rio Grande do Sul (Porto Alegre, Brésil); 2019. [cited 2021 Apr 12]. Available from: http://www.theses.fr/2019ESAE0026.

Council of Science Editors:

Lackmann-Zimpeck A. Circuit-level approaches to mitigate the process variability and soft errors in FinFET logic cells : Approches au niveau du circuit pour atténuer la variabilité de fabrication et les soft errors dans les cellules logiques FinFET. [Doctoral Dissertation]. Toulouse, ISAE; Universidade Federal do Rio Grande do Sul (Porto Alegre, Brésil); 2019. Available from: http://www.theses.fr/2019ESAE0026


Vanderbilt University

24. Jiang, Hui. Design of soft-error-aware sequential circuits with power and speed optimization.

Degree: PhD, Electrical Engineering, 2018, Vanderbilt University

 A single-event effect (SEE) of circuits is strongly dependent on the supply voltage and the physical capacitance. Reduction in supply voltage as well as technology… (more)

Subjects/Keywords: power optimization; sequential circuit; soft error rate; Single event effects; empirical model

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APA (6th Edition):

Jiang, H. (2018). Design of soft-error-aware sequential circuits with power and speed optimization. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/10911

Chicago Manual of Style (16th Edition):

Jiang, Hui. “Design of soft-error-aware sequential circuits with power and speed optimization.” 2018. Doctoral Dissertation, Vanderbilt University. Accessed April 12, 2021. http://hdl.handle.net/1803/10911.

MLA Handbook (7th Edition):

Jiang, Hui. “Design of soft-error-aware sequential circuits with power and speed optimization.” 2018. Web. 12 Apr 2021.

Vancouver:

Jiang H. Design of soft-error-aware sequential circuits with power and speed optimization. [Internet] [Doctoral dissertation]. Vanderbilt University; 2018. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/1803/10911.

Council of Science Editors:

Jiang H. Design of soft-error-aware sequential circuits with power and speed optimization. [Doctoral Dissertation]. Vanderbilt University; 2018. Available from: http://hdl.handle.net/1803/10911


Penn State University

25. Liu, Huichu. Device Circuit Interactions for Steep Switching Slope Devices.

Degree: 2015, Penn State University

 Energy efficiency limit has becomes the main obstacle for the power-constrained applications using the conventional silicon complementary metal-oxide-semiconductor (CMOS) technology. In particular, the supply voltage… (more)

Subjects/Keywords: Tunneling-field-effect-transistor; device-circuit interaction; steep subthreshold slope; energy efficiency; soft error reliability

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liu, H. (2015). Device Circuit Interactions for Steep Switching Slope Devices. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/23759

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Huichu. “Device Circuit Interactions for Steep Switching Slope Devices.” 2015. Thesis, Penn State University. Accessed April 12, 2021. https://submit-etda.libraries.psu.edu/catalog/23759.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Huichu. “Device Circuit Interactions for Steep Switching Slope Devices.” 2015. Web. 12 Apr 2021.

Vancouver:

Liu H. Device Circuit Interactions for Steep Switching Slope Devices. [Internet] [Thesis]. Penn State University; 2015. [cited 2021 Apr 12]. Available from: https://submit-etda.libraries.psu.edu/catalog/23759.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu H. Device Circuit Interactions for Steep Switching Slope Devices. [Thesis]. Penn State University; 2015. Available from: https://submit-etda.libraries.psu.edu/catalog/23759

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Stellenbosch University

26. Babalola, Oluwaseyi Paul. Soft-decision decoding of moderate length binary cycle codes based on parity-check transformation.

Degree: PhD, Electrical and Electronic Engineering, 2020, Stellenbosch University

 ENGLISH ABSTRACT: This thesis focuses on obtaining low complexity soft-decision (SD) decoding of binary cyclic codes with coding performance close to the optimal decoding algorithm.… (more)

Subjects/Keywords: Parity check; Digital communication; Error-correcting codes (Information theory); UCTD; Soft-decision decoding

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APA (6th Edition):

Babalola, O. P. (2020). Soft-decision decoding of moderate length binary cycle codes based on parity-check transformation. (Doctoral Dissertation). Stellenbosch University. Retrieved from http://hdl.handle.net/10019.1/107932

Chicago Manual of Style (16th Edition):

Babalola, Oluwaseyi Paul. “Soft-decision decoding of moderate length binary cycle codes based on parity-check transformation.” 2020. Doctoral Dissertation, Stellenbosch University. Accessed April 12, 2021. http://hdl.handle.net/10019.1/107932.

MLA Handbook (7th Edition):

Babalola, Oluwaseyi Paul. “Soft-decision decoding of moderate length binary cycle codes based on parity-check transformation.” 2020. Web. 12 Apr 2021.

Vancouver:

Babalola OP. Soft-decision decoding of moderate length binary cycle codes based on parity-check transformation. [Internet] [Doctoral dissertation]. Stellenbosch University; 2020. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10019.1/107932.

Council of Science Editors:

Babalola OP. Soft-decision decoding of moderate length binary cycle codes based on parity-check transformation. [Doctoral Dissertation]. Stellenbosch University; 2020. Available from: http://hdl.handle.net/10019.1/107932


University of Waterloo

27. Shah, Jaspal Singh. Low-Power Soft-Error-Robust Embedded SRAM.

Degree: 2013, University of Waterloo

Soft errors are radiation-induced ionization events (induced by energetic particles like alpha particles, cosmic neutron, etc.) that cause transient errors in integrated circuits. The circuit… (more)

Subjects/Keywords: VLSI; Embedded SRAM; Cache; Soft Error; Offset cancellation; Sense amplifier; Low Power

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shah, J. S. (2013). Low-Power Soft-Error-Robust Embedded SRAM. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/7186

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shah, Jaspal Singh. “Low-Power Soft-Error-Robust Embedded SRAM.” 2013. Thesis, University of Waterloo. Accessed April 12, 2021. http://hdl.handle.net/10012/7186.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shah, Jaspal Singh. “Low-Power Soft-Error-Robust Embedded SRAM.” 2013. Web. 12 Apr 2021.

Vancouver:

Shah JS. Low-Power Soft-Error-Robust Embedded SRAM. [Internet] [Thesis]. University of Waterloo; 2013. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10012/7186.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shah JS. Low-Power Soft-Error-Robust Embedded SRAM. [Thesis]. University of Waterloo; 2013. Available from: http://hdl.handle.net/10012/7186

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Vanderbilt University

28. Limbrick, Daniel Brian. Impact of Logic Synthesis on the Soft Error Rate of Digital Integrated Circuits.

Degree: PhD, Electrical Engineering, 2012, Vanderbilt University

 Radiation-induced soft errors are becoming a dominant reliability-failure mechanism in modern CMOS technologies. In nanometer technologies, the effects are not limited to the storage elements… (more)

Subjects/Keywords: reliability-aware synthesis; single event transient; pulse width; combinational logic; soft error; logic synthesis

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APA (6th Edition):

Limbrick, D. B. (2012). Impact of Logic Synthesis on the Soft Error Rate of Digital Integrated Circuits. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/14920

Chicago Manual of Style (16th Edition):

Limbrick, Daniel Brian. “Impact of Logic Synthesis on the Soft Error Rate of Digital Integrated Circuits.” 2012. Doctoral Dissertation, Vanderbilt University. Accessed April 12, 2021. http://hdl.handle.net/1803/14920.

MLA Handbook (7th Edition):

Limbrick, Daniel Brian. “Impact of Logic Synthesis on the Soft Error Rate of Digital Integrated Circuits.” 2012. Web. 12 Apr 2021.

Vancouver:

Limbrick DB. Impact of Logic Synthesis on the Soft Error Rate of Digital Integrated Circuits. [Internet] [Doctoral dissertation]. Vanderbilt University; 2012. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/1803/14920.

Council of Science Editors:

Limbrick DB. Impact of Logic Synthesis on the Soft Error Rate of Digital Integrated Circuits. [Doctoral Dissertation]. Vanderbilt University; 2012. Available from: http://hdl.handle.net/1803/14920


University of Texas – Austin

29. Mirkhani, Shahrzad. Statistical methods for rapid system evaluation under transient and permanent faults.

Degree: PhD, Electrical and Computer Engineering, 2014, University of Texas – Austin

 Traditional solutions for test and reliability do not scale well for modern designs with their size and complexity increasing with every technology generation. Therefore, in… (more)

Subjects/Keywords: Functional fault grading; VLSI testing; Fault coverage estimation; Soft error; Vulnerability factors

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mirkhani, S. (2014). Statistical methods for rapid system evaluation under transient and permanent faults. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/28393

Chicago Manual of Style (16th Edition):

Mirkhani, Shahrzad. “Statistical methods for rapid system evaluation under transient and permanent faults.” 2014. Doctoral Dissertation, University of Texas – Austin. Accessed April 12, 2021. http://hdl.handle.net/2152/28393.

MLA Handbook (7th Edition):

Mirkhani, Shahrzad. “Statistical methods for rapid system evaluation under transient and permanent faults.” 2014. Web. 12 Apr 2021.

Vancouver:

Mirkhani S. Statistical methods for rapid system evaluation under transient and permanent faults. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2014. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/2152/28393.

Council of Science Editors:

Mirkhani S. Statistical methods for rapid system evaluation under transient and permanent faults. [Doctoral Dissertation]. University of Texas – Austin; 2014. Available from: http://hdl.handle.net/2152/28393

30. Zimpeck, Alexandra Lackmann. Circuit-level approaches to mitigate the process variability and soft errors in finFET logic cells.

Degree: 2019, Brazil

 A variabilidade de processo e a resistência a radiação são requisitos de confiabilidade relevantes à medida que a fabricação de chips avança mais a fundo… (more)

Subjects/Keywords: Microeletrônica; Circuitos digitais; circuit-level design; process variability; reliability; soft error; FinFET

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zimpeck, A. L. (2019). Circuit-level approaches to mitigate the process variability and soft errors in finFET logic cells. (Doctoral Dissertation). Brazil. Retrieved from http://hdl.handle.net/10183/201310

Chicago Manual of Style (16th Edition):

Zimpeck, Alexandra Lackmann. “Circuit-level approaches to mitigate the process variability and soft errors in finFET logic cells.” 2019. Doctoral Dissertation, Brazil. Accessed April 12, 2021. http://hdl.handle.net/10183/201310.

MLA Handbook (7th Edition):

Zimpeck, Alexandra Lackmann. “Circuit-level approaches to mitigate the process variability and soft errors in finFET logic cells.” 2019. Web. 12 Apr 2021.

Vancouver:

Zimpeck AL. Circuit-level approaches to mitigate the process variability and soft errors in finFET logic cells. [Internet] [Doctoral dissertation]. Brazil; 2019. [cited 2021 Apr 12]. Available from: http://hdl.handle.net/10183/201310.

Council of Science Editors:

Zimpeck AL. Circuit-level approaches to mitigate the process variability and soft errors in finFET logic cells. [Doctoral Dissertation]. Brazil; 2019. Available from: http://hdl.handle.net/10183/201310

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