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You searched for subject:(single event transient SET ). Showing records 1 – 30 of 15687 total matches.

[1] [2] [3] [4] [5] … [523]

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Universidade do Rio Grande do Sul

1. Ribeiro, Ivandro da Silva. Modelagem e caracterização da propagação de pulsos transientes causados por radiação ionizante.

Degree: 2010, Universidade do Rio Grande do Sul

A propagação de eventos transientes na lógica combinacional é estudada através da simulação elétrica do circuito, utilizando-se o simulador Hspice. Uma das fontes de falhas… (more)

Subjects/Keywords: Single event transient; Microeletrônica; SET broadening; Circuitos integrados; Electrical model

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APA (6th Edition):

Ribeiro, I. d. S. (2010). Modelagem e caracterização da propagação de pulsos transientes causados por radiação ionizante. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/31119

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ribeiro, Ivandro da Silva. “Modelagem e caracterização da propagação de pulsos transientes causados por radiação ionizante.” 2010. Thesis, Universidade do Rio Grande do Sul. Accessed November 22, 2019. http://hdl.handle.net/10183/31119.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ribeiro, Ivandro da Silva. “Modelagem e caracterização da propagação de pulsos transientes causados por radiação ionizante.” 2010. Web. 22 Nov 2019.

Vancouver:

Ribeiro IdS. Modelagem e caracterização da propagação de pulsos transientes causados por radiação ionizante. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2010. [cited 2019 Nov 22]. Available from: http://hdl.handle.net/10183/31119.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ribeiro IdS. Modelagem e caracterização da propagação de pulsos transientes causados por radiação ionizante. [Thesis]. Universidade do Rio Grande do Sul; 2010. Available from: http://hdl.handle.net/10183/31119

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Saskatchewan

2. Liu, Rui. Study of Radiation Effects on 28nm UTBB FDSOI Technology.

Degree: 2017, University of Saskatchewan

 With the evolution of modern Complementary Metal-Oxide-Semiconductor (CMOS) technology, transistor feature size has been scaled down to nanometers. The scaling has resulted in tremendous advantages… (more)

Subjects/Keywords: Single Event Transient; FDSOI

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APA (6th Edition):

Liu, R. (2017). Study of Radiation Effects on 28nm UTBB FDSOI Technology. (Thesis). University of Saskatchewan. Retrieved from http://hdl.handle.net/10388/8259

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Rui. “Study of Radiation Effects on 28nm UTBB FDSOI Technology.” 2017. Thesis, University of Saskatchewan. Accessed November 22, 2019. http://hdl.handle.net/10388/8259.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Rui. “Study of Radiation Effects on 28nm UTBB FDSOI Technology.” 2017. Web. 22 Nov 2019.

Vancouver:

Liu R. Study of Radiation Effects on 28nm UTBB FDSOI Technology. [Internet] [Thesis]. University of Saskatchewan; 2017. [cited 2019 Nov 22]. Available from: http://hdl.handle.net/10388/8259.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu R. Study of Radiation Effects on 28nm UTBB FDSOI Technology. [Thesis]. University of Saskatchewan; 2017. Available from: http://hdl.handle.net/10388/8259

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Vanderbilt University

3. Harrington, Rachel Christine. Models for Characterizing Single-Event Effects in Advanced Technology Circuits.

Degree: PhD, Electrical Engineering, 2019, Vanderbilt University

 At each emerging technology node, characterization of single-event transients and upsets is crucial to accurately predict soft error rates for circuits operating in radiation environments.… (more)

Subjects/Keywords: modeling; single-event transient; single-event upset; single-event effects

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APA (6th Edition):

Harrington, R. C. (2019). Models for Characterizing Single-Event Effects in Advanced Technology Circuits. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-05152019-100307/ ;

Chicago Manual of Style (16th Edition):

Harrington, Rachel Christine. “Models for Characterizing Single-Event Effects in Advanced Technology Circuits.” 2019. Doctoral Dissertation, Vanderbilt University. Accessed November 22, 2019. http://etd.library.vanderbilt.edu/available/etd-05152019-100307/ ;.

MLA Handbook (7th Edition):

Harrington, Rachel Christine. “Models for Characterizing Single-Event Effects in Advanced Technology Circuits.” 2019. Web. 22 Nov 2019.

Vancouver:

Harrington RC. Models for Characterizing Single-Event Effects in Advanced Technology Circuits. [Internet] [Doctoral dissertation]. Vanderbilt University; 2019. [cited 2019 Nov 22]. Available from: http://etd.library.vanderbilt.edu/available/etd-05152019-100307/ ;.

Council of Science Editors:

Harrington RC. Models for Characterizing Single-Event Effects in Advanced Technology Circuits. [Doctoral Dissertation]. Vanderbilt University; 2019. Available from: http://etd.library.vanderbilt.edu/available/etd-05152019-100307/ ;


Universidade do Rio Grande do Sul

4. Franck, Helen de Souza. Avaliação de atraso, consumo e proteção de somadores tolerantes a falhas.

Degree: 2011, Universidade do Rio Grande do Sul

Nos últimos anos, os sistemas integrados em silício (SOCs - Systems-on-Chip) têm se tornado menos imunes a ruído, em decorrência dos ajustes necessários na tecnologia… (more)

Subjects/Keywords: Fault tolerance; Microeletrônica; SET (single-event transient); Tolerancia : Falhas; Binary-signed digit number system; Adder architectures

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APA (6th Edition):

Franck, H. d. S. (2011). Avaliação de atraso, consumo e proteção de somadores tolerantes a falhas. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/49071

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Franck, Helen de Souza. “Avaliação de atraso, consumo e proteção de somadores tolerantes a falhas.” 2011. Thesis, Universidade do Rio Grande do Sul. Accessed November 22, 2019. http://hdl.handle.net/10183/49071.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Franck, Helen de Souza. “Avaliação de atraso, consumo e proteção de somadores tolerantes a falhas.” 2011. Web. 22 Nov 2019.

Vancouver:

Franck HdS. Avaliação de atraso, consumo e proteção de somadores tolerantes a falhas. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2011. [cited 2019 Nov 22]. Available from: http://hdl.handle.net/10183/49071.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Franck HdS. Avaliação de atraso, consumo e proteção de somadores tolerantes a falhas. [Thesis]. Universidade do Rio Grande do Sul; 2011. Available from: http://hdl.handle.net/10183/49071

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Vanderbilt University

5. Assis, Thiago Rocha de. Soft error aware physical synthesis.

Degree: PhD, Electrical Engineering, 2015, Vanderbilt University

 To allow accurate analysis of Soft Errors by Electronic Design Automation (EDA) tools, analytical models were developed to estimate electrical characteristics of the single event.… (more)

Subjects/Keywords: single event transient; set pulse width; collected charge; radiation effects; electronic design automation; physical synthesis; soft error; reliability

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APA (6th Edition):

Assis, T. R. d. (2015). Soft error aware physical synthesis. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-11242015-013303/ ;

Chicago Manual of Style (16th Edition):

Assis, Thiago Rocha de. “Soft error aware physical synthesis.” 2015. Doctoral Dissertation, Vanderbilt University. Accessed November 22, 2019. http://etd.library.vanderbilt.edu/available/etd-11242015-013303/ ;.

MLA Handbook (7th Edition):

Assis, Thiago Rocha de. “Soft error aware physical synthesis.” 2015. Web. 22 Nov 2019.

Vancouver:

Assis TRd. Soft error aware physical synthesis. [Internet] [Doctoral dissertation]. Vanderbilt University; 2015. [cited 2019 Nov 22]. Available from: http://etd.library.vanderbilt.edu/available/etd-11242015-013303/ ;.

Council of Science Editors:

Assis TRd. Soft error aware physical synthesis. [Doctoral Dissertation]. Vanderbilt University; 2015. Available from: http://etd.library.vanderbilt.edu/available/etd-11242015-013303/ ;


University of Saskatchewan

6. Xie, Hao 1988-. Study of Single Event Transient Error Mitigation.

Degree: 2017, University of Saskatchewan

Single Event Transient (SET) errors in ground-level electronic devices are a growing concern in the radiation hardening field. However, effective SET mitigation technologies which satisfy… (more)

Subjects/Keywords: Single Event Transient; Soft Error Mitigation

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APA (6th Edition):

Xie, H. 1. (2017). Study of Single Event Transient Error Mitigation. (Thesis). University of Saskatchewan. Retrieved from http://hdl.handle.net/10388/8025

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Xie, Hao 1988-. “Study of Single Event Transient Error Mitigation.” 2017. Thesis, University of Saskatchewan. Accessed November 22, 2019. http://hdl.handle.net/10388/8025.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Xie, Hao 1988-. “Study of Single Event Transient Error Mitigation.” 2017. Web. 22 Nov 2019.

Vancouver:

Xie H1. Study of Single Event Transient Error Mitigation. [Internet] [Thesis]. University of Saskatchewan; 2017. [cited 2019 Nov 22]. Available from: http://hdl.handle.net/10388/8025.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Xie H1. Study of Single Event Transient Error Mitigation. [Thesis]. University of Saskatchewan; 2017. Available from: http://hdl.handle.net/10388/8025

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Vanderbilt University

7. Dinkins, Cody Adam. Qualitative Characterization of Single-event Transient and Latchup Trends in 180 nm CMOS Technology.

Degree: MS, Electrical Engineering, 2011, Vanderbilt University

Single-event upsets and errors are of growing concern as technology scales toward smaller transistor sizes. While smaller transistors allow for greater on-chip integration, this comes… (more)

Subjects/Keywords: characterization; transient; latchup; single event; 180 nm

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APA (6th Edition):

Dinkins, C. A. (2011). Qualitative Characterization of Single-event Transient and Latchup Trends in 180 nm CMOS Technology. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-04082011-122316/ ;

Chicago Manual of Style (16th Edition):

Dinkins, Cody Adam. “Qualitative Characterization of Single-event Transient and Latchup Trends in 180 nm CMOS Technology.” 2011. Masters Thesis, Vanderbilt University. Accessed November 22, 2019. http://etd.library.vanderbilt.edu/available/etd-04082011-122316/ ;.

MLA Handbook (7th Edition):

Dinkins, Cody Adam. “Qualitative Characterization of Single-event Transient and Latchup Trends in 180 nm CMOS Technology.” 2011. Web. 22 Nov 2019.

Vancouver:

Dinkins CA. Qualitative Characterization of Single-event Transient and Latchup Trends in 180 nm CMOS Technology. [Internet] [Masters thesis]. Vanderbilt University; 2011. [cited 2019 Nov 22]. Available from: http://etd.library.vanderbilt.edu/available/etd-04082011-122316/ ;.

Council of Science Editors:

Dinkins CA. Qualitative Characterization of Single-event Transient and Latchup Trends in 180 nm CMOS Technology. [Masters Thesis]. Vanderbilt University; 2011. Available from: http://etd.library.vanderbilt.edu/available/etd-04082011-122316/ ;


Vanderbilt University

8. Maharrey, Jeffrey Alan. Dual interlocked logic: a radiation-hardened-by-design technique for single-event logic errors.

Degree: PhD, Electrical Engineering, 2018, Vanderbilt University

 As design choices within a single CMOS technology become ever more complex with each new technology generation, and power consumption constraints push operating voltages lower,… (more)

Subjects/Keywords: single event transient; radiation; rhbd; digital

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APA (6th Edition):

Maharrey, J. A. (2018). Dual interlocked logic: a radiation-hardened-by-design technique for single-event logic errors. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-03042018-174735/ ;

Chicago Manual of Style (16th Edition):

Maharrey, Jeffrey Alan. “Dual interlocked logic: a radiation-hardened-by-design technique for single-event logic errors.” 2018. Doctoral Dissertation, Vanderbilt University. Accessed November 22, 2019. http://etd.library.vanderbilt.edu/available/etd-03042018-174735/ ;.

MLA Handbook (7th Edition):

Maharrey, Jeffrey Alan. “Dual interlocked logic: a radiation-hardened-by-design technique for single-event logic errors.” 2018. Web. 22 Nov 2019.

Vancouver:

Maharrey JA. Dual interlocked logic: a radiation-hardened-by-design technique for single-event logic errors. [Internet] [Doctoral dissertation]. Vanderbilt University; 2018. [cited 2019 Nov 22]. Available from: http://etd.library.vanderbilt.edu/available/etd-03042018-174735/ ;.

Council of Science Editors:

Maharrey JA. Dual interlocked logic: a radiation-hardened-by-design technique for single-event logic errors. [Doctoral Dissertation]. Vanderbilt University; 2018. Available from: http://etd.library.vanderbilt.edu/available/etd-03042018-174735/ ;


Vanderbilt University

9. Kiddie, Bradley Thomas. Single-Event Multiple-Transient Characterization and Mitigation via Standard Cell Placement Methods.

Degree: PhD, Electrical Engineering, 2016, Vanderbilt University

 The effects of radiation on the operation of integrated circuits (IC) continue to take a more important role as technology feature sizes scale down, critical… (more)

Subjects/Keywords: reliability; radiation; eda; single-event transient; single-event multiple-transient; placement; algorithm

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APA (6th Edition):

Kiddie, B. T. (2016). Single-Event Multiple-Transient Characterization and Mitigation via Standard Cell Placement Methods. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-09282016-101105/ ;

Chicago Manual of Style (16th Edition):

Kiddie, Bradley Thomas. “Single-Event Multiple-Transient Characterization and Mitigation via Standard Cell Placement Methods.” 2016. Doctoral Dissertation, Vanderbilt University. Accessed November 22, 2019. http://etd.library.vanderbilt.edu/available/etd-09282016-101105/ ;.

MLA Handbook (7th Edition):

Kiddie, Bradley Thomas. “Single-Event Multiple-Transient Characterization and Mitigation via Standard Cell Placement Methods.” 2016. Web. 22 Nov 2019.

Vancouver:

Kiddie BT. Single-Event Multiple-Transient Characterization and Mitigation via Standard Cell Placement Methods. [Internet] [Doctoral dissertation]. Vanderbilt University; 2016. [cited 2019 Nov 22]. Available from: http://etd.library.vanderbilt.edu/available/etd-09282016-101105/ ;.

Council of Science Editors:

Kiddie BT. Single-Event Multiple-Transient Characterization and Mitigation via Standard Cell Placement Methods. [Doctoral Dissertation]. Vanderbilt University; 2016. Available from: http://etd.library.vanderbilt.edu/available/etd-09282016-101105/ ;


Universidade do Rio Grande do Sul

10. Chielle, Eduardo. Selective software-implemented hardware fault tolerance tecnhiques to detect soft errors in processors with reduced overhead.

Degree: 2016, Universidade do Rio Grande do Sul

Software-based fault tolerance techniques are a low-cost way to protect processors against soft errors. However, they introduce significant overheads to the execution time and code… (more)

Subjects/Keywords: SIHFT techniques; Microeletrônica; Tolerancia : Falhas : Software; Selective hardening; Transient faults; Processadores; Soft errors; Single event effects; SEU; SET; Processor; Reliability; Execution time; Code size; Energy consumption; Lower overheads

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APA (6th Edition):

Chielle, E. (2016). Selective software-implemented hardware fault tolerance tecnhiques to detect soft errors in processors with reduced overhead. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/142568

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chielle, Eduardo. “Selective software-implemented hardware fault tolerance tecnhiques to detect soft errors in processors with reduced overhead.” 2016. Thesis, Universidade do Rio Grande do Sul. Accessed November 22, 2019. http://hdl.handle.net/10183/142568.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chielle, Eduardo. “Selective software-implemented hardware fault tolerance tecnhiques to detect soft errors in processors with reduced overhead.” 2016. Web. 22 Nov 2019.

Vancouver:

Chielle E. Selective software-implemented hardware fault tolerance tecnhiques to detect soft errors in processors with reduced overhead. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2016. [cited 2019 Nov 22]. Available from: http://hdl.handle.net/10183/142568.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chielle E. Selective software-implemented hardware fault tolerance tecnhiques to detect soft errors in processors with reduced overhead. [Thesis]. Universidade do Rio Grande do Sul; 2016. Available from: http://hdl.handle.net/10183/142568

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Vanderbilt University

11. Gong, Huiqi. Single-event transients in Indium Gallium Arsenide MOSFETs for Sub-10 nm CMOS technology.

Degree: PhD, Electrical Engineering, 2018, Vanderbilt University

 MOSFETs are the building blocks of modern electronics. A modern microprocessor contains billions of transistors. The microelectronics revolution can be characterized by the motto âsmaller… (more)

Subjects/Keywords: pulsed-laser; technology computer-aided design (TCAD); InGaAs; FinFET; CMOS; single-event transient (SET); bipolar amplification; heavy ion; technology scaling; charge collection

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APA (6th Edition):

Gong, H. (2018). Single-event transients in Indium Gallium Arsenide MOSFETs for Sub-10 nm CMOS technology. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-09172018-130053/ ;

Chicago Manual of Style (16th Edition):

Gong, Huiqi. “Single-event transients in Indium Gallium Arsenide MOSFETs for Sub-10 nm CMOS technology.” 2018. Doctoral Dissertation, Vanderbilt University. Accessed November 22, 2019. http://etd.library.vanderbilt.edu/available/etd-09172018-130053/ ;.

MLA Handbook (7th Edition):

Gong, Huiqi. “Single-event transients in Indium Gallium Arsenide MOSFETs for Sub-10 nm CMOS technology.” 2018. Web. 22 Nov 2019.

Vancouver:

Gong H. Single-event transients in Indium Gallium Arsenide MOSFETs for Sub-10 nm CMOS technology. [Internet] [Doctoral dissertation]. Vanderbilt University; 2018. [cited 2019 Nov 22]. Available from: http://etd.library.vanderbilt.edu/available/etd-09172018-130053/ ;.

Council of Science Editors:

Gong H. Single-event transients in Indium Gallium Arsenide MOSFETs for Sub-10 nm CMOS technology. [Doctoral Dissertation]. Vanderbilt University; 2018. Available from: http://etd.library.vanderbilt.edu/available/etd-09172018-130053/ ;


University of Southern California

12. Haghi, Mahta. Modeling and mitigation of radiation-induced charge sharing effects in advanced electronics.

Degree: PhD, Electrical Engineering, 2012, University of Southern California

 As semiconductor industry continues to scale down to ever smaller feature sizes, radiation-induced soft errors are becoming a major concern for microelectronics reliability. A rising… (more)

Subjects/Keywords: radiation hardening by design; sub-micron CMOS; single event upset; single event transient; charge sharing

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APA (6th Edition):

Haghi, M. (2012). Modeling and mitigation of radiation-induced charge sharing effects in advanced electronics. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/17193/rec/4116

Chicago Manual of Style (16th Edition):

Haghi, Mahta. “Modeling and mitigation of radiation-induced charge sharing effects in advanced electronics.” 2012. Doctoral Dissertation, University of Southern California. Accessed November 22, 2019. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/17193/rec/4116.

MLA Handbook (7th Edition):

Haghi, Mahta. “Modeling and mitigation of radiation-induced charge sharing effects in advanced electronics.” 2012. Web. 22 Nov 2019.

Vancouver:

Haghi M. Modeling and mitigation of radiation-induced charge sharing effects in advanced electronics. [Internet] [Doctoral dissertation]. University of Southern California; 2012. [cited 2019 Nov 22]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/17193/rec/4116.

Council of Science Editors:

Haghi M. Modeling and mitigation of radiation-induced charge sharing effects in advanced electronics. [Doctoral Dissertation]. University of Southern California; 2012. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/17193/rec/4116


Arizona State University

13. Shambhulingaiah, Sandeep. Methodical Design Approaches to Multiple Node Collection Robustness for Flip-Flop Soft Error MItigation.

Degree: Electrical Engineering, 2015, Arizona State University

Subjects/Keywords: Electrical engineering; Flip-flop; Methodology; Multi node charge collection; Radiation hardening by design; Single Event Transient (SET); Single Event Upset (SEU)

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APA (6th Edition):

Shambhulingaiah, S. (2015). Methodical Design Approaches to Multiple Node Collection Robustness for Flip-Flop Soft Error MItigation. (Doctoral Dissertation). Arizona State University. Retrieved from http://repository.asu.edu/items/29650

Chicago Manual of Style (16th Edition):

Shambhulingaiah, Sandeep. “Methodical Design Approaches to Multiple Node Collection Robustness for Flip-Flop Soft Error MItigation.” 2015. Doctoral Dissertation, Arizona State University. Accessed November 22, 2019. http://repository.asu.edu/items/29650.

MLA Handbook (7th Edition):

Shambhulingaiah, Sandeep. “Methodical Design Approaches to Multiple Node Collection Robustness for Flip-Flop Soft Error MItigation.” 2015. Web. 22 Nov 2019.

Vancouver:

Shambhulingaiah S. Methodical Design Approaches to Multiple Node Collection Robustness for Flip-Flop Soft Error MItigation. [Internet] [Doctoral dissertation]. Arizona State University; 2015. [cited 2019 Nov 22]. Available from: http://repository.asu.edu/items/29650.

Council of Science Editors:

Shambhulingaiah S. Methodical Design Approaches to Multiple Node Collection Robustness for Flip-Flop Soft Error MItigation. [Doctoral Dissertation]. Arizona State University; 2015. Available from: http://repository.asu.edu/items/29650

14. 会見, 真宏. 完全空乏型SOI MOSFETにおけるシングル・イベント・トランジェントパルスの解析 : Analysis of Single Event Transient Pulses of a Fully-Depleted SOI MOSFET.

Degree: 修士(工学), 2017, The University of Tokyo / 東京大学

近年,宇宙放射線や中性子線が引き起こすソフトエラーの一種である,シングル・イベント・トランジェント(Single Event Transient、以下SET) が問題視されている.SET とは,高エネルギー荷電粒子がデバイスに入射することで生じる電流(電圧)パルスである.論理回路中を伝播して誤動作を引き起こすため,その対策が急務となっている.一方,SOI デバイスは,埋め込み酸化膜が存在し、イオン化放射の影響を受ける体積が少ないため、ソフトエラー対策に有効なデバイスとして知られている。しかし、そのSET 特性は未だ明らかにされていない部分が多い.そこで,我々が開発している耐放射線完全空乏型SOI MOSFETにおけるSET パルスの解析をシミュレーションにより行った.

Subjects/Keywords: SOI; Single Event Transient

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APA (6th Edition):

会見, . (2017). 完全空乏型SOI MOSFETにおけるシングル・イベント・トランジェントパルスの解析 : Analysis of Single Event Transient Pulses of a Fully-Depleted SOI MOSFET. (Thesis). The University of Tokyo / 東京大学. Retrieved from http://hdl.handle.net/2261/43701

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

会見, 真宏. “完全空乏型SOI MOSFETにおけるシングル・イベント・トランジェントパルスの解析 : Analysis of Single Event Transient Pulses of a Fully-Depleted SOI MOSFET.” 2017. Thesis, The University of Tokyo / 東京大学. Accessed November 22, 2019. http://hdl.handle.net/2261/43701.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

会見, 真宏. “完全空乏型SOI MOSFETにおけるシングル・イベント・トランジェントパルスの解析 : Analysis of Single Event Transient Pulses of a Fully-Depleted SOI MOSFET.” 2017. Web. 22 Nov 2019.

Vancouver:

会見 . 完全空乏型SOI MOSFETにおけるシングル・イベント・トランジェントパルスの解析 : Analysis of Single Event Transient Pulses of a Fully-Depleted SOI MOSFET. [Internet] [Thesis]. The University of Tokyo / 東京大学; 2017. [cited 2019 Nov 22]. Available from: http://hdl.handle.net/2261/43701.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

会見 . 完全空乏型SOI MOSFETにおけるシングル・イベント・トランジェントパルスの解析 : Analysis of Single Event Transient Pulses of a Fully-Depleted SOI MOSFET. [Thesis]. The University of Tokyo / 東京大学; 2017. Available from: http://hdl.handle.net/2261/43701

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Wright State University

15. Hopkins, Thomas A. An Automated Approach to a 90-nm CMOS DRFM DSSM Circuit Design.

Degree: MSEgr, Electrical Engineering, 2010, Wright State University

  A digital single sideband modulator (DSSM) for a digital radio frequency memory (DRFM) was designed and implemented in a commercial 90-nm radiation-hardened-by-design (RHBD) structured… (more)

Subjects/Keywords: Electrical Engineering; digital single sideband modulator; DSSM; digital radio frequency memory; DRFM; Radiation hardened; rad hard; radiation hardened by design; RHBD; electronic warfare; EW; automated; guard ring; guard band; single event transient; SET

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APA (6th Edition):

Hopkins, T. A. (2010). An Automated Approach to a 90-nm CMOS DRFM DSSM Circuit Design. (Masters Thesis). Wright State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=wright1281645939

Chicago Manual of Style (16th Edition):

Hopkins, Thomas A. “An Automated Approach to a 90-nm CMOS DRFM DSSM Circuit Design.” 2010. Masters Thesis, Wright State University. Accessed November 22, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=wright1281645939.

MLA Handbook (7th Edition):

Hopkins, Thomas A. “An Automated Approach to a 90-nm CMOS DRFM DSSM Circuit Design.” 2010. Web. 22 Nov 2019.

Vancouver:

Hopkins TA. An Automated Approach to a 90-nm CMOS DRFM DSSM Circuit Design. [Internet] [Masters thesis]. Wright State University; 2010. [cited 2019 Nov 22]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1281645939.

Council of Science Editors:

Hopkins TA. An Automated Approach to a 90-nm CMOS DRFM DSSM Circuit Design. [Masters Thesis]. Wright State University; 2010. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1281645939


Vanderbilt University

16. Nsengiyumva, Patrick. Characterization of the CMOS FinFET structure on single-event effects â basic charge collection mechanisms and soft error modes.

Degree: PhD, Electrical Engineering, 2018, Vanderbilt University

 With technology scaling at 22 nm and beyond, the semiconductor industry has successfully transitioned to 3D multi-gate transistors (i.e., FinFETs) due to the excellent FinFET… (more)

Subjects/Keywords: RHBD; Charge Collection Mechanisms; Integrated Circuit; SEE Simulations; Soft Error Modes; Bulk Technologies; CMOS IC; Angular SEE Mechanisms; Rad-hard; Three-Dimensional Transistor; Multi-Gate Transistor; Planar Technologies; Radiation Effects; Single-Event Upset (SEU); Spatial and Temporal SEE Considerations; SET Pulse Width; Single-Event Transient (SET); FinFET Geometric and Orientation Dependence; FinFET Structure; Single-Event Effects (SEE); FinFET; Digital Circuits; Alpha Particle Data; Upset Cross-Section; Flip-flop; Heavy-Ion Data; TCAD; Advanced Technologies

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APA (6th Edition):

Nsengiyumva, P. (2018). Characterization of the CMOS FinFET structure on single-event effects â basic charge collection mechanisms and soft error modes. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-03202018-160105/ ;

Chicago Manual of Style (16th Edition):

Nsengiyumva, Patrick. “Characterization of the CMOS FinFET structure on single-event effects â basic charge collection mechanisms and soft error modes.” 2018. Doctoral Dissertation, Vanderbilt University. Accessed November 22, 2019. http://etd.library.vanderbilt.edu/available/etd-03202018-160105/ ;.

MLA Handbook (7th Edition):

Nsengiyumva, Patrick. “Characterization of the CMOS FinFET structure on single-event effects â basic charge collection mechanisms and soft error modes.” 2018. Web. 22 Nov 2019.

Vancouver:

Nsengiyumva P. Characterization of the CMOS FinFET structure on single-event effects â basic charge collection mechanisms and soft error modes. [Internet] [Doctoral dissertation]. Vanderbilt University; 2018. [cited 2019 Nov 22]. Available from: http://etd.library.vanderbilt.edu/available/etd-03202018-160105/ ;.

Council of Science Editors:

Nsengiyumva P. Characterization of the CMOS FinFET structure on single-event effects â basic charge collection mechanisms and soft error modes. [Doctoral Dissertation]. Vanderbilt University; 2018. Available from: http://etd.library.vanderbilt.edu/available/etd-03202018-160105/ ;


Vanderbilt University

17. Kay, William Hunter. Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology.

Degree: MS, Electrical Engineering, 2015, Vanderbilt University

 The scaling of CMOS technology has brought about the increased susceptibility of circuits to single-event (SE) effects. Electronic systems operating in space often face extreme… (more)

Subjects/Keywords: flip flop; 20 nm; single event; SET; SEE; SEU

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APA (6th Edition):

Kay, W. H. (2015). Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-03302015-133003/ ;

Chicago Manual of Style (16th Edition):

Kay, William Hunter. “Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology.” 2015. Masters Thesis, Vanderbilt University. Accessed November 22, 2019. http://etd.library.vanderbilt.edu/available/etd-03302015-133003/ ;.

MLA Handbook (7th Edition):

Kay, William Hunter. “Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology.” 2015. Web. 22 Nov 2019.

Vancouver:

Kay WH. Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology. [Internet] [Masters thesis]. Vanderbilt University; 2015. [cited 2019 Nov 22]. Available from: http://etd.library.vanderbilt.edu/available/etd-03302015-133003/ ;.

Council of Science Editors:

Kay WH. Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology. [Masters Thesis]. Vanderbilt University; 2015. Available from: http://etd.library.vanderbilt.edu/available/etd-03302015-133003/ ;


Arizona State University

18. Gujja, Aditya. Redundant Skewed Clocking of Pulse-Clocked Latches for Low Power Soft-Error Mitigation.

Degree: Electrical Engineering, 2015, Arizona State University

 An integrated methodology combining redundant clock tree synthesis and pulse clocked latches mitigates both single event upsets (SEU) and single event transients (SET) with reduced… (more)

Subjects/Keywords: Electrical engineering; Flip-Flop; multiple node charge collection; single event transient; single event upset; temporal hardening; triple mode redundancy

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APA (6th Edition):

Gujja, A. (2015). Redundant Skewed Clocking of Pulse-Clocked Latches for Low Power Soft-Error Mitigation. (Masters Thesis). Arizona State University. Retrieved from http://repository.asu.edu/items/36471

Chicago Manual of Style (16th Edition):

Gujja, Aditya. “Redundant Skewed Clocking of Pulse-Clocked Latches for Low Power Soft-Error Mitigation.” 2015. Masters Thesis, Arizona State University. Accessed November 22, 2019. http://repository.asu.edu/items/36471.

MLA Handbook (7th Edition):

Gujja, Aditya. “Redundant Skewed Clocking of Pulse-Clocked Latches for Low Power Soft-Error Mitigation.” 2015. Web. 22 Nov 2019.

Vancouver:

Gujja A. Redundant Skewed Clocking of Pulse-Clocked Latches for Low Power Soft-Error Mitigation. [Internet] [Masters thesis]. Arizona State University; 2015. [cited 2019 Nov 22]. Available from: http://repository.asu.edu/items/36471.

Council of Science Editors:

Gujja A. Redundant Skewed Clocking of Pulse-Clocked Latches for Low Power Soft-Error Mitigation. [Masters Thesis]. Arizona State University; 2015. Available from: http://repository.asu.edu/items/36471


Vanderbilt University

19. Narasimham, Balaji. On Chip Characterization of Single Event Transient Pulse Widths.

Degree: MS, Electrical Engineering, 2005, Vanderbilt University

 It is now well known to the radiation effects community that single event effects caused by energetic particles, particularly single event transients, will be among… (more)

Subjects/Keywords: transient pulse width; SET; SEU; single event; CMOS; RHBD; Radiation hardening; Integrated circuits  – Effect of radiation on  – Computer simulation

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APA (6th Edition):

Narasimham, B. (2005). On Chip Characterization of Single Event Transient Pulse Widths. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-11302005-010732/ ;

Chicago Manual of Style (16th Edition):

Narasimham, Balaji. “On Chip Characterization of Single Event Transient Pulse Widths.” 2005. Masters Thesis, Vanderbilt University. Accessed November 22, 2019. http://etd.library.vanderbilt.edu/available/etd-11302005-010732/ ;.

MLA Handbook (7th Edition):

Narasimham, Balaji. “On Chip Characterization of Single Event Transient Pulse Widths.” 2005. Web. 22 Nov 2019.

Vancouver:

Narasimham B. On Chip Characterization of Single Event Transient Pulse Widths. [Internet] [Masters thesis]. Vanderbilt University; 2005. [cited 2019 Nov 22]. Available from: http://etd.library.vanderbilt.edu/available/etd-11302005-010732/ ;.

Council of Science Editors:

Narasimham B. On Chip Characterization of Single Event Transient Pulse Widths. [Masters Thesis]. Vanderbilt University; 2005. Available from: http://etd.library.vanderbilt.edu/available/etd-11302005-010732/ ;


Universidade do Rio Grande do Sul

20. Bartra, Walter Enrique Calienes. Modelamento do single-Event effiects em circuitos de memória FDSOI.

Degree: 2016, Universidade do Rio Grande do Sul

Este trabalho mostra a comparação dos efeitos das falhas provocadas pelos Single-Event Effects em dispositivos 28nm FDSOI, 28nm FDSOI High-K e 32nm Bulk CMOS e… (more)

Subjects/Keywords: Single-event effects; Microeletrônica; Single-event transient; Modelagem computacional; Single-event upset; Fully depleted silicon on insulator; 2D simulation; 3D simulation; Modeling

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APA (6th Edition):

Bartra, W. E. C. (2016). Modelamento do single-Event effiects em circuitos de memória FDSOI. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/159203

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bartra, Walter Enrique Calienes. “Modelamento do single-Event effiects em circuitos de memória FDSOI.” 2016. Thesis, Universidade do Rio Grande do Sul. Accessed November 22, 2019. http://hdl.handle.net/10183/159203.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bartra, Walter Enrique Calienes. “Modelamento do single-Event effiects em circuitos de memória FDSOI.” 2016. Web. 22 Nov 2019.

Vancouver:

Bartra WEC. Modelamento do single-Event effiects em circuitos de memória FDSOI. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2016. [cited 2019 Nov 22]. Available from: http://hdl.handle.net/10183/159203.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bartra WEC. Modelamento do single-Event effiects em circuitos de memória FDSOI. [Thesis]. Universidade do Rio Grande do Sul; 2016. Available from: http://hdl.handle.net/10183/159203

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of New South Wales

21. Li, Tuo. Cost-Efficient Soft-Error Resiliency for ASIP-based Embedded Systems.

Degree: Computer Science & Engineering, 2013, University of New South Wales

 Recent decades have witnessed the rapid growth of embedded systems. At present, embedded systems are widely applied in a broad range of critical applications including… (more)

Subjects/Keywords: Recovery; Application-specific instruction-set processor; Soft error; Fault tolerance; Embedded system; Checkpoint recovery; Instruction set extension; Single event upset

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APA (6th Edition):

Li, T. (2013). Cost-Efficient Soft-Error Resiliency for ASIP-based Embedded Systems. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/53542 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:12237/SOURCE02?view=true

Chicago Manual of Style (16th Edition):

Li, Tuo. “Cost-Efficient Soft-Error Resiliency for ASIP-based Embedded Systems.” 2013. Doctoral Dissertation, University of New South Wales. Accessed November 22, 2019. http://handle.unsw.edu.au/1959.4/53542 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:12237/SOURCE02?view=true.

MLA Handbook (7th Edition):

Li, Tuo. “Cost-Efficient Soft-Error Resiliency for ASIP-based Embedded Systems.” 2013. Web. 22 Nov 2019.

Vancouver:

Li T. Cost-Efficient Soft-Error Resiliency for ASIP-based Embedded Systems. [Internet] [Doctoral dissertation]. University of New South Wales; 2013. [cited 2019 Nov 22]. Available from: http://handle.unsw.edu.au/1959.4/53542 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:12237/SOURCE02?view=true.

Council of Science Editors:

Li T. Cost-Efficient Soft-Error Resiliency for ASIP-based Embedded Systems. [Doctoral Dissertation]. University of New South Wales; 2013. Available from: http://handle.unsw.edu.au/1959.4/53542 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:12237/SOURCE02?view=true


Universidade do Rio Grande do Sul

22. Furtado, Gabriela Firpo. Metodologia determinística para simulação elétrica do impacto de BTI em circuitos MOS.

Degree: 2017, Universidade do Rio Grande do Sul

Aborda-se, nesse trabalho, o fenômeno de envelhecimento de transistores MOS por bias temperature instability (BTI), relevante fator de degradação da confiabilidade e de redução do… (more)

Subjects/Keywords: Bias temperature instability; Circuitos integrados; Logic gates; Cmos; Simulação elétrica; Propagation delay; Single event transient; Propagation induced pulse broadening

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APA (6th Edition):

Furtado, G. F. (2017). Metodologia determinística para simulação elétrica do impacto de BTI em circuitos MOS. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/165167

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Furtado, Gabriela Firpo. “Metodologia determinística para simulação elétrica do impacto de BTI em circuitos MOS.” 2017. Thesis, Universidade do Rio Grande do Sul. Accessed November 22, 2019. http://hdl.handle.net/10183/165167.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Furtado, Gabriela Firpo. “Metodologia determinística para simulação elétrica do impacto de BTI em circuitos MOS.” 2017. Web. 22 Nov 2019.

Vancouver:

Furtado GF. Metodologia determinística para simulação elétrica do impacto de BTI em circuitos MOS. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2017. [cited 2019 Nov 22]. Available from: http://hdl.handle.net/10183/165167.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Furtado GF. Metodologia determinística para simulação elétrica do impacto de BTI em circuitos MOS. [Thesis]. Universidade do Rio Grande do Sul; 2017. Available from: http://hdl.handle.net/10183/165167

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Arizona State University

23. Masand, Lovish. Radiation Effects Measurement Test Structure using GF 32-nm SOI process.

Degree: Electrical Engineering, 2017, Arizona State University

 This thesis describes the design of a Single Event Transient (SET) duration measurement test-structure on the Global Foundries (previously IBM) 32-nm silicon-on insulator (SOI) process.… (more)

Subjects/Keywords: Engineering; Capture Structure; Global Foundry SOI 32 nm Process; Measurement Structure; Pulse Width Broadening; Radiation Effects; Single Event Transient

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APA (6th Edition):

Masand, L. (2017). Radiation Effects Measurement Test Structure using GF 32-nm SOI process. (Masters Thesis). Arizona State University. Retrieved from http://repository.asu.edu/items/44999

Chicago Manual of Style (16th Edition):

Masand, Lovish. “Radiation Effects Measurement Test Structure using GF 32-nm SOI process.” 2017. Masters Thesis, Arizona State University. Accessed November 22, 2019. http://repository.asu.edu/items/44999.

MLA Handbook (7th Edition):

Masand, Lovish. “Radiation Effects Measurement Test Structure using GF 32-nm SOI process.” 2017. Web. 22 Nov 2019.

Vancouver:

Masand L. Radiation Effects Measurement Test Structure using GF 32-nm SOI process. [Internet] [Masters thesis]. Arizona State University; 2017. [cited 2019 Nov 22]. Available from: http://repository.asu.edu/items/44999.

Council of Science Editors:

Masand L. Radiation Effects Measurement Test Structure using GF 32-nm SOI process. [Masters Thesis]. Arizona State University; 2017. Available from: http://repository.asu.edu/items/44999

24. Ding, Yan. Study of radiation-tolerant integrated circuits for space applications.

Degree: 2010, University of Saskatchewan

 Integrated Circuits in space suffer from reliability problems due to the radiative surroundings. High energy particles can ionize the semiconductor and lead to single event(more)

Subjects/Keywords: single event effect; radiation tolerent; single event transient; single event upset

…data path leading to loss of normal operation) and single event transient (SET… …Gate Rupture SEL Single Event Latch-up SERT Single Event Resistant Topology SET Single… …Event Transient SEU Single Event Upset SHE Single Event Hard Errors SOI Silicon on… …Single Event Transient In conventional semiconductor processes, metal and polysilicon layers… …happens. The new bit information remains even after the transient fades away. 2.4 Single-Event… 

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APA (6th Edition):

Ding, Y. (2010). Study of radiation-tolerant integrated circuits for space applications. (Thesis). University of Saskatchewan. Retrieved from http://hdl.handle.net/10388/etd-05312010-164533

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ding, Yan. “Study of radiation-tolerant integrated circuits for space applications.” 2010. Thesis, University of Saskatchewan. Accessed November 22, 2019. http://hdl.handle.net/10388/etd-05312010-164533.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ding, Yan. “Study of radiation-tolerant integrated circuits for space applications.” 2010. Web. 22 Nov 2019.

Vancouver:

Ding Y. Study of radiation-tolerant integrated circuits for space applications. [Internet] [Thesis]. University of Saskatchewan; 2010. [cited 2019 Nov 22]. Available from: http://hdl.handle.net/10388/etd-05312010-164533.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ding Y. Study of radiation-tolerant integrated circuits for space applications. [Thesis]. University of Saskatchewan; 2010. Available from: http://hdl.handle.net/10388/etd-05312010-164533

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Vanderbilt University

25. Balasubramanian, Anitha. A Built-In Self-Test (BIST) Technique for Single-Event Transient Testing in Digital Circuits.

Degree: MS, Electrical Engineering, 2008, Vanderbilt University

 With shrinking device feature sizes, integrated circuits are becoming more vulnerable to Single-Event Transients (SETs). Characterizing error rates due to SETs is essential for choosing… (more)

Subjects/Keywords: single-event transient; random number generator; current starved inverters; single-event; Integrated circuits  – Effect of radiation on  – Testing; Radiation hardening

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APA (6th Edition):

Balasubramanian, A. (2008). A Built-In Self-Test (BIST) Technique for Single-Event Transient Testing in Digital Circuits. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-07292008-093802/ ;

Chicago Manual of Style (16th Edition):

Balasubramanian, Anitha. “A Built-In Self-Test (BIST) Technique for Single-Event Transient Testing in Digital Circuits.” 2008. Masters Thesis, Vanderbilt University. Accessed November 22, 2019. http://etd.library.vanderbilt.edu/available/etd-07292008-093802/ ;.

MLA Handbook (7th Edition):

Balasubramanian, Anitha. “A Built-In Self-Test (BIST) Technique for Single-Event Transient Testing in Digital Circuits.” 2008. Web. 22 Nov 2019.

Vancouver:

Balasubramanian A. A Built-In Self-Test (BIST) Technique for Single-Event Transient Testing in Digital Circuits. [Internet] [Masters thesis]. Vanderbilt University; 2008. [cited 2019 Nov 22]. Available from: http://etd.library.vanderbilt.edu/available/etd-07292008-093802/ ;.

Council of Science Editors:

Balasubramanian A. A Built-In Self-Test (BIST) Technique for Single-Event Transient Testing in Digital Circuits. [Masters Thesis]. Vanderbilt University; 2008. Available from: http://etd.library.vanderbilt.edu/available/etd-07292008-093802/ ;

26. Black, Dolores Archuleta. Direct ionization-induced transient fault analysis for combinational logic and sequential capture in digital integrated circuits for lightly-ionizing environments.

Degree: PhD, Electrical Engineering, 2011, Vanderbilt University

 Digital integrated circuits (ICs) fabricated in advanced semiconductor processes are susceptible to single event effects from lightly ionizing particles (e.g., alpha particles, protons, and muons).… (more)

Subjects/Keywords: Fault Injection; Ions; Ionization; Single Event Transient; Single Event Effect; Integrated Circuit; Transistor

Single Event Effect SER Soft Error Rate SET Single Event Transient SEU Single… …dissertation describes an integrated technique to model the impact of a single event transient (… …ix DC‐DFF memory circuit from logic state 1 to logic state 0. A single event to… …DFF memory circuit from logic state 1 to logic state 0. A single event to the memory… …diagram of circuits for single event simulation of DC‐D‐Latch. .................. 85 45… 

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APA (6th Edition):

Black, D. A. (2011). Direct ionization-induced transient fault analysis for combinational logic and sequential capture in digital integrated circuits for lightly-ionizing environments. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-11302011-123349/ ;

Chicago Manual of Style (16th Edition):

Black, Dolores Archuleta. “Direct ionization-induced transient fault analysis for combinational logic and sequential capture in digital integrated circuits for lightly-ionizing environments.” 2011. Doctoral Dissertation, Vanderbilt University. Accessed November 22, 2019. http://etd.library.vanderbilt.edu/available/etd-11302011-123349/ ;.

MLA Handbook (7th Edition):

Black, Dolores Archuleta. “Direct ionization-induced transient fault analysis for combinational logic and sequential capture in digital integrated circuits for lightly-ionizing environments.” 2011. Web. 22 Nov 2019.

Vancouver:

Black DA. Direct ionization-induced transient fault analysis for combinational logic and sequential capture in digital integrated circuits for lightly-ionizing environments. [Internet] [Doctoral dissertation]. Vanderbilt University; 2011. [cited 2019 Nov 22]. Available from: http://etd.library.vanderbilt.edu/available/etd-11302011-123349/ ;.

Council of Science Editors:

Black DA. Direct ionization-induced transient fault analysis for combinational logic and sequential capture in digital integrated circuits for lightly-ionizing environments. [Doctoral Dissertation]. Vanderbilt University; 2011. Available from: http://etd.library.vanderbilt.edu/available/etd-11302011-123349/ ;

27. Wang, Tao. Study of Single-Event Transient Effects on Analog Circuits.

Degree: 2011, University of Saskatchewan

 Radiation in space is potentially hazardous to microelectronic circuits and systems such as spacecraft electronics. Transient effects on circuits and systems from high energetic particles… (more)

Subjects/Keywords: Integrated Circuit; Complementary Metal-Oxide-Semiconductor; Radiation-Hardening-by-Design; Single-Event Transient; Single-Event Effects

…same word of memory. C- Single-event transient (SET) [15]: Once a… …80 A Single-Event Transient-Tolerant Monolithic Phase-Locked Loop Design .... 82 6.1… …101 7.2 Voltage Mode Bulk Built-In Current Sensing Circuit for Single-Event Transient… …Oscillator SE Single Event SEL Single-Event Latch-up SER Soft Error Rate SET Single-Event… …Transient SEE Single-Event Effects SEU Single-Event Upset SNR Signal To Noise Ratio SPICE… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, T. (2011). Study of Single-Event Transient Effects on Analog Circuits. (Thesis). University of Saskatchewan. Retrieved from http://hdl.handle.net/10388/ETD-2011-08-45

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Tao. “Study of Single-Event Transient Effects on Analog Circuits.” 2011. Thesis, University of Saskatchewan. Accessed November 22, 2019. http://hdl.handle.net/10388/ETD-2011-08-45.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Tao. “Study of Single-Event Transient Effects on Analog Circuits.” 2011. Web. 22 Nov 2019.

Vancouver:

Wang T. Study of Single-Event Transient Effects on Analog Circuits. [Internet] [Thesis]. University of Saskatchewan; 2011. [cited 2019 Nov 22]. Available from: http://hdl.handle.net/10388/ETD-2011-08-45.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang T. Study of Single-Event Transient Effects on Analog Circuits. [Thesis]. University of Saskatchewan; 2011. Available from: http://hdl.handle.net/10388/ETD-2011-08-45

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Vanderbilt University

28. Vibbert, Daniel Scott. An Enhanced Single-Event Charge Cancellation Technique for Sensitive Circuit Nodes.

Degree: MS, Electrical Engineering, 2018, Vanderbilt University

 An enhancement to an existing radiation hardening by design (RHBD) technique is proposed. The technique, Sensitive Node Active Charge Cancellation (SNACC), protects sensitive A/MS circuit… (more)

Subjects/Keywords: single-event hardening; single-event transients; single-event effects; radiation hardening by design

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vibbert, D. S. (2018). An Enhanced Single-Event Charge Cancellation Technique for Sensitive Circuit Nodes. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-08152018-130817/ ;

Chicago Manual of Style (16th Edition):

Vibbert, Daniel Scott. “An Enhanced Single-Event Charge Cancellation Technique for Sensitive Circuit Nodes.” 2018. Masters Thesis, Vanderbilt University. Accessed November 22, 2019. http://etd.library.vanderbilt.edu/available/etd-08152018-130817/ ;.

MLA Handbook (7th Edition):

Vibbert, Daniel Scott. “An Enhanced Single-Event Charge Cancellation Technique for Sensitive Circuit Nodes.” 2018. Web. 22 Nov 2019.

Vancouver:

Vibbert DS. An Enhanced Single-Event Charge Cancellation Technique for Sensitive Circuit Nodes. [Internet] [Masters thesis]. Vanderbilt University; 2018. [cited 2019 Nov 22]. Available from: http://etd.library.vanderbilt.edu/available/etd-08152018-130817/ ;.

Council of Science Editors:

Vibbert DS. An Enhanced Single-Event Charge Cancellation Technique for Sensitive Circuit Nodes. [Masters Thesis]. Vanderbilt University; 2018. Available from: http://etd.library.vanderbilt.edu/available/etd-08152018-130817/ ;


Vanderbilt University

29. Kauppila, Amy Vaughn. Analysis of parameter variation impact on the single event response in sub-100nm CMOS storage cells.

Degree: PhD, Electrical Engineering, 2012, Vanderbilt University

 Current deep sub-micron technologies are particularly susceptible to single events. The challenge derives from a conglomeration of effects that affect circuitsâ radiation response. For instance,… (more)

Subjects/Keywords: single event upset; parameter variation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kauppila, A. V. (2012). Analysis of parameter variation impact on the single event response in sub-100nm CMOS storage cells. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-04092012-111410/ ;

Chicago Manual of Style (16th Edition):

Kauppila, Amy Vaughn. “Analysis of parameter variation impact on the single event response in sub-100nm CMOS storage cells.” 2012. Doctoral Dissertation, Vanderbilt University. Accessed November 22, 2019. http://etd.library.vanderbilt.edu/available/etd-04092012-111410/ ;.

MLA Handbook (7th Edition):

Kauppila, Amy Vaughn. “Analysis of parameter variation impact on the single event response in sub-100nm CMOS storage cells.” 2012. Web. 22 Nov 2019.

Vancouver:

Kauppila AV. Analysis of parameter variation impact on the single event response in sub-100nm CMOS storage cells. [Internet] [Doctoral dissertation]. Vanderbilt University; 2012. [cited 2019 Nov 22]. Available from: http://etd.library.vanderbilt.edu/available/etd-04092012-111410/ ;.

Council of Science Editors:

Kauppila AV. Analysis of parameter variation impact on the single event response in sub-100nm CMOS storage cells. [Doctoral Dissertation]. Vanderbilt University; 2012. Available from: http://etd.library.vanderbilt.edu/available/etd-04092012-111410/ ;


University of New Mexico

30. Bowen, Douglas. Space-Time Kinetics of the AGN-201M Research Reactor at the University of New Mexico.

Degree: Nuclear Engineering, 2015, University of New Mexico

 A series of experimental measurements were performed on the AGN- 201M reactor (AGN) at the University of New Mexico. Steady-state measurements were made with the… (more)

Subjects/Keywords: AGN-201; Research Reactor; critical; transient; EVENT

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bowen, D. (2015). Space-Time Kinetics of the AGN-201M Research Reactor at the University of New Mexico. (Doctoral Dissertation). University of New Mexico. Retrieved from http://hdl.handle.net/1928/27762

Chicago Manual of Style (16th Edition):

Bowen, Douglas. “Space-Time Kinetics of the AGN-201M Research Reactor at the University of New Mexico.” 2015. Doctoral Dissertation, University of New Mexico. Accessed November 22, 2019. http://hdl.handle.net/1928/27762.

MLA Handbook (7th Edition):

Bowen, Douglas. “Space-Time Kinetics of the AGN-201M Research Reactor at the University of New Mexico.” 2015. Web. 22 Nov 2019.

Vancouver:

Bowen D. Space-Time Kinetics of the AGN-201M Research Reactor at the University of New Mexico. [Internet] [Doctoral dissertation]. University of New Mexico; 2015. [cited 2019 Nov 22]. Available from: http://hdl.handle.net/1928/27762.

Council of Science Editors:

Bowen D. Space-Time Kinetics of the AGN-201M Research Reactor at the University of New Mexico. [Doctoral Dissertation]. University of New Mexico; 2015. Available from: http://hdl.handle.net/1928/27762

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