Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

Sorted by: relevance · author · university · dateNew search

You searched for subject:(silicon on insulator SOI ). Showing records 1 – 30 of 24188 total matches.

[1] [2] [3] [4] [5] … [807]

Search Limiters

Last 2 Years | English Only

Degrees

Levels

Languages

Country

▼ Search Limiters


University of Tennessee – Knoxville

1. Hasan, Md Sakib. MODELING AND SPICE IMPLEMENTATION OF SILICON-ON-INSULATOR (SOI) FOUR GATE (G4FET) TRANSISTOR.

Degree: 2017, University of Tennessee – Knoxville

 As the device dimensions have reduced from micrometer to nanometer range, new bulk silicon devices are now facing many undesirable effects of scaling leading device… (more)

Subjects/Keywords: Silicon-on-insulator (SOI); G4FET; Spline; Lagrange; regression; SPICE; Engineering

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hasan, M. S. (2017). MODELING AND SPICE IMPLEMENTATION OF SILICON-ON-INSULATOR (SOI) FOUR GATE (G4FET) TRANSISTOR. (Doctoral Dissertation). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_graddiss/4626

Chicago Manual of Style (16th Edition):

Hasan, Md Sakib. “MODELING AND SPICE IMPLEMENTATION OF SILICON-ON-INSULATOR (SOI) FOUR GATE (G4FET) TRANSISTOR.” 2017. Doctoral Dissertation, University of Tennessee – Knoxville. Accessed September 26, 2020. https://trace.tennessee.edu/utk_graddiss/4626.

MLA Handbook (7th Edition):

Hasan, Md Sakib. “MODELING AND SPICE IMPLEMENTATION OF SILICON-ON-INSULATOR (SOI) FOUR GATE (G4FET) TRANSISTOR.” 2017. Web. 26 Sep 2020.

Vancouver:

Hasan MS. MODELING AND SPICE IMPLEMENTATION OF SILICON-ON-INSULATOR (SOI) FOUR GATE (G4FET) TRANSISTOR. [Internet] [Doctoral dissertation]. University of Tennessee – Knoxville; 2017. [cited 2020 Sep 26]. Available from: https://trace.tennessee.edu/utk_graddiss/4626.

Council of Science Editors:

Hasan MS. MODELING AND SPICE IMPLEMENTATION OF SILICON-ON-INSULATOR (SOI) FOUR GATE (G4FET) TRANSISTOR. [Doctoral Dissertation]. University of Tennessee – Knoxville; 2017. Available from: https://trace.tennessee.edu/utk_graddiss/4626


Virginia Tech

2. Ndoye, Coumba. Characterization of Dopant Diffusion in Bulk and lower dimensional Silicon Structures.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 The semiconductor industry scaling has mainly been driven by Mooreâ s law, which states that the number of transistors on a single chip should double… (more)

Subjects/Keywords: Silicon; diffusion; Silicon on Insulator (SOI); Metal Oxide Semiconductor Field Effect Transistor; Nanowire

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ndoye, C. (2010). Characterization of Dopant Diffusion in Bulk and lower dimensional Silicon Structures. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/46321

Chicago Manual of Style (16th Edition):

Ndoye, Coumba. “Characterization of Dopant Diffusion in Bulk and lower dimensional Silicon Structures.” 2010. Masters Thesis, Virginia Tech. Accessed September 26, 2020. http://hdl.handle.net/10919/46321.

MLA Handbook (7th Edition):

Ndoye, Coumba. “Characterization of Dopant Diffusion in Bulk and lower dimensional Silicon Structures.” 2010. Web. 26 Sep 2020.

Vancouver:

Ndoye C. Characterization of Dopant Diffusion in Bulk and lower dimensional Silicon Structures. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2020 Sep 26]. Available from: http://hdl.handle.net/10919/46321.

Council of Science Editors:

Ndoye C. Characterization of Dopant Diffusion in Bulk and lower dimensional Silicon Structures. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/46321


Rochester Institute of Technology

3. Veeramachaneni, Bharat. Oxidized porous silicon for localized formation of SOI active regions.

Degree: Microelectronic Engineering, 2010, Rochester Institute of Technology

 The oxidation of electrochemically etched porous silicon (Si) has demonstrated success in the formation of device quality Localized Silicon on Insulator (L-SOI) for Complementary Metal… (more)

Subjects/Keywords: Silicon on insulator

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Veeramachaneni, B. (2010). Oxidized porous silicon for localized formation of SOI active regions. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/5539

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Veeramachaneni, Bharat. “Oxidized porous silicon for localized formation of SOI active regions.” 2010. Thesis, Rochester Institute of Technology. Accessed September 26, 2020. https://scholarworks.rit.edu/theses/5539.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Veeramachaneni, Bharat. “Oxidized porous silicon for localized formation of SOI active regions.” 2010. Web. 26 Sep 2020.

Vancouver:

Veeramachaneni B. Oxidized porous silicon for localized formation of SOI active regions. [Internet] [Thesis]. Rochester Institute of Technology; 2010. [cited 2020 Sep 26]. Available from: https://scholarworks.rit.edu/theses/5539.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Veeramachaneni B. Oxidized porous silicon for localized formation of SOI active regions. [Thesis]. Rochester Institute of Technology; 2010. Available from: https://scholarworks.rit.edu/theses/5539

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

4. Kiihamäki, Jyrki. Fabrication of SOI Micromechanical Devices.

Degree: 2005, VTT Technical Research Centre of Finland

This work reports on studies and the fabrication process development of micromechanical silicon-on-insulator (SOI) devices. SOI is a promising starting material for fabrication of single… (more)

Subjects/Keywords: silicon-on-insulator; SOI; micromechanics; MEMS; microfabrication; HARMST; DRIE; etching; vacuum cavities; resonators; monolithic integration

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kiihamäki, J. (2005). Fabrication of SOI Micromechanical Devices. (Thesis). VTT Technical Research Centre of Finland. Retrieved from http://lib.tkk.fi/Diss/2005/isbn9513864367/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kiihamäki, Jyrki. “Fabrication of SOI Micromechanical Devices.” 2005. Thesis, VTT Technical Research Centre of Finland. Accessed September 26, 2020. http://lib.tkk.fi/Diss/2005/isbn9513864367/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kiihamäki, Jyrki. “Fabrication of SOI Micromechanical Devices.” 2005. Web. 26 Sep 2020.

Vancouver:

Kiihamäki J. Fabrication of SOI Micromechanical Devices. [Internet] [Thesis]. VTT Technical Research Centre of Finland; 2005. [cited 2020 Sep 26]. Available from: http://lib.tkk.fi/Diss/2005/isbn9513864367/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kiihamäki J. Fabrication of SOI Micromechanical Devices. [Thesis]. VTT Technical Research Centre of Finland; 2005. Available from: http://lib.tkk.fi/Diss/2005/isbn9513864367/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

5. Huang, Hsueh-liang. Study of Novel High Integration-Density and Low Power Non-classical CTFET Inverter.

Degree: Master, Electrical Engineering, 2013, NSYSU

 The research discusses a novel CTFET inverter which is composed of a N-typed TFET(NTFET) as a driven transistor and a Gated control I-I-P transistor as… (more)

Subjects/Keywords: Gated control; SOI (Silicon on Insulator); TFET; Low power; High packing density; CTFET

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Huang, H. (2013). Study of Novel High Integration-Density and Low Power Non-classical CTFET Inverter. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0709113-092337

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Hsueh-liang. “Study of Novel High Integration-Density and Low Power Non-classical CTFET Inverter.” 2013. Thesis, NSYSU. Accessed September 26, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0709113-092337.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Hsueh-liang. “Study of Novel High Integration-Density and Low Power Non-classical CTFET Inverter.” 2013. Web. 26 Sep 2020.

Vancouver:

Huang H. Study of Novel High Integration-Density and Low Power Non-classical CTFET Inverter. [Internet] [Thesis]. NSYSU; 2013. [cited 2020 Sep 26]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0709113-092337.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang H. Study of Novel High Integration-Density and Low Power Non-classical CTFET Inverter. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0709113-092337

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

6. Passanante, Thibault. Mécanismes de démouillage à l'état solide : Etude par microscopie à électrons lents des systèmes SOI et GOI : Mechanisms of solid-state dewetting.

Degree: Docteur es, Sciences des Matériaux, Physique, Chimie et Nanosciences, 2014, Aix Marseille Université

Ce travail de thèse est consacré à l’étude expérimentale des mécanismes de démouillage de films solides d’épaisseur nanométrique conduisant à la transformation d’un film mince… (more)

Subjects/Keywords: Démouillage; Films solides; Silicium sur isolant (SOI); Germanium sur isolant (GOI); Leem; Gisaxs; Dewetting; Solid films; Silicon On Insulator (SOI); Germanium On Insulator (GOI); Leem; Gisaxs; 530

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Passanante, T. (2014). Mécanismes de démouillage à l'état solide : Etude par microscopie à électrons lents des systèmes SOI et GOI : Mechanisms of solid-state dewetting. (Doctoral Dissertation). Aix Marseille Université. Retrieved from http://www.theses.fr/2014AIXM4020

Chicago Manual of Style (16th Edition):

Passanante, Thibault. “Mécanismes de démouillage à l'état solide : Etude par microscopie à électrons lents des systèmes SOI et GOI : Mechanisms of solid-state dewetting.” 2014. Doctoral Dissertation, Aix Marseille Université. Accessed September 26, 2020. http://www.theses.fr/2014AIXM4020.

MLA Handbook (7th Edition):

Passanante, Thibault. “Mécanismes de démouillage à l'état solide : Etude par microscopie à électrons lents des systèmes SOI et GOI : Mechanisms of solid-state dewetting.” 2014. Web. 26 Sep 2020.

Vancouver:

Passanante T. Mécanismes de démouillage à l'état solide : Etude par microscopie à électrons lents des systèmes SOI et GOI : Mechanisms of solid-state dewetting. [Internet] [Doctoral dissertation]. Aix Marseille Université 2014. [cited 2020 Sep 26]. Available from: http://www.theses.fr/2014AIXM4020.

Council of Science Editors:

Passanante T. Mécanismes de démouillage à l'état solide : Etude par microscopie à électrons lents des systèmes SOI et GOI : Mechanisms of solid-state dewetting. [Doctoral Dissertation]. Aix Marseille Université 2014. Available from: http://www.theses.fr/2014AIXM4020


Université Catholique de Louvain

7. Soung Yee, Lawrence. Evaluation of monolithic pixel detector readout in silicon-on-insulator technology.

Degree: 2015, Université Catholique de Louvain

Silicon particle detectors are found at the forefront of scientific imaging applications. From medical imaging machines that scan the human body to space telescopes observing… (more)

Subjects/Keywords: Pixel; Monolithic; Silicon on insulator

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Soung Yee, L. (2015). Evaluation of monolithic pixel detector readout in silicon-on-insulator technology. (Thesis). Université Catholique de Louvain. Retrieved from http://hdl.handle.net/2078.1/160969

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Soung Yee, Lawrence. “Evaluation of monolithic pixel detector readout in silicon-on-insulator technology.” 2015. Thesis, Université Catholique de Louvain. Accessed September 26, 2020. http://hdl.handle.net/2078.1/160969.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Soung Yee, Lawrence. “Evaluation of monolithic pixel detector readout in silicon-on-insulator technology.” 2015. Web. 26 Sep 2020.

Vancouver:

Soung Yee L. Evaluation of monolithic pixel detector readout in silicon-on-insulator technology. [Internet] [Thesis]. Université Catholique de Louvain; 2015. [cited 2020 Sep 26]. Available from: http://hdl.handle.net/2078.1/160969.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Soung Yee L. Evaluation of monolithic pixel detector readout in silicon-on-insulator technology. [Thesis]. Université Catholique de Louvain; 2015. Available from: http://hdl.handle.net/2078.1/160969

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

8. Kulawski, Martin. Advanced CMP Processes for Special Substrates and for Device Manufacturing in MEMS Applications.

Degree: 2006, VTT Technical Research Centre of Finland

The present work reports on studies and process developments to utilize the chemical mechanical planarization (CMP) technology in the field of micro electrical mechanical systems… (more)

Subjects/Keywords: CMP; micro electro mechanical systems; polishing; fixed abrasive; MEMS; SOI; silicon-on-insulator; direct wafer bonding; DWB; low temperature bonding; FA

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kulawski, M. (2006). Advanced CMP Processes for Special Substrates and for Device Manufacturing in MEMS Applications. (Thesis). VTT Technical Research Centre of Finland. Retrieved from http://lib.tkk.fi/Diss/2006/isbn9513868567/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kulawski, Martin. “Advanced CMP Processes for Special Substrates and for Device Manufacturing in MEMS Applications.” 2006. Thesis, VTT Technical Research Centre of Finland. Accessed September 26, 2020. http://lib.tkk.fi/Diss/2006/isbn9513868567/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kulawski, Martin. “Advanced CMP Processes for Special Substrates and for Device Manufacturing in MEMS Applications.” 2006. Web. 26 Sep 2020.

Vancouver:

Kulawski M. Advanced CMP Processes for Special Substrates and for Device Manufacturing in MEMS Applications. [Internet] [Thesis]. VTT Technical Research Centre of Finland; 2006. [cited 2020 Sep 26]. Available from: http://lib.tkk.fi/Diss/2006/isbn9513868567/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kulawski M. Advanced CMP Processes for Special Substrates and for Device Manufacturing in MEMS Applications. [Thesis]. VTT Technical Research Centre of Finland; 2006. Available from: http://lib.tkk.fi/Diss/2006/isbn9513868567/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Vanderbilt University

9. Gorchichko, Mariia. Total-Ionizing-Dose Effects and Low-Frequency Noise in 30-nm Gate-Length Bulk and SOI FinFETs with SiO2/HfO2 Gate Dielectrics.

Degree: MS, Electrical Engineering, 2019, Vanderbilt University

 Due to the advances in manufacturing and enhanced gate control of the transistor channel, FinFETs are commonly used in highly-scaled ICs. The geometry of the… (more)

Subjects/Keywords: FinFET; silicon-on-insulator (SOI); total ionizing dose (TID); low-frequency noise; random telegraph noise (RTN)

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gorchichko, M. (2019). Total-Ionizing-Dose Effects and Low-Frequency Noise in 30-nm Gate-Length Bulk and SOI FinFETs with SiO2/HfO2 Gate Dielectrics. (Thesis). Vanderbilt University. Retrieved from http://hdl.handle.net/1803/14529

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gorchichko, Mariia. “Total-Ionizing-Dose Effects and Low-Frequency Noise in 30-nm Gate-Length Bulk and SOI FinFETs with SiO2/HfO2 Gate Dielectrics.” 2019. Thesis, Vanderbilt University. Accessed September 26, 2020. http://hdl.handle.net/1803/14529.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gorchichko, Mariia. “Total-Ionizing-Dose Effects and Low-Frequency Noise in 30-nm Gate-Length Bulk and SOI FinFETs with SiO2/HfO2 Gate Dielectrics.” 2019. Web. 26 Sep 2020.

Vancouver:

Gorchichko M. Total-Ionizing-Dose Effects and Low-Frequency Noise in 30-nm Gate-Length Bulk and SOI FinFETs with SiO2/HfO2 Gate Dielectrics. [Internet] [Thesis]. Vanderbilt University; 2019. [cited 2020 Sep 26]. Available from: http://hdl.handle.net/1803/14529.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gorchichko M. Total-Ionizing-Dose Effects and Low-Frequency Noise in 30-nm Gate-Length Bulk and SOI FinFETs with SiO2/HfO2 Gate Dielectrics. [Thesis]. Vanderbilt University; 2019. Available from: http://hdl.handle.net/1803/14529

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


RMIT University

10. Dalvand, N. Silicon photonic devices utilizing lateral leakage behaviour.

Degree: 2014, RMIT University

 Transverse magnetic (TM)-like modes of thin-ridge Silicon-on-Insulator (SOI) waveguide can leak into radiating transverse electric (TE) slab modes in the lateral direction unless the waveguide… (more)

Subjects/Keywords: Fields of Research; transverse magnetic (TM); transverse electric (TE); Silicon-on-Insulator (SOI); polarization rotator-splitter; wavelength de-multiplexer

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dalvand, N. (2014). Silicon photonic devices utilizing lateral leakage behaviour. (Thesis). RMIT University. Retrieved from http://researchbank.rmit.edu.au/view/rmit:160748

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Dalvand, N. “Silicon photonic devices utilizing lateral leakage behaviour.” 2014. Thesis, RMIT University. Accessed September 26, 2020. http://researchbank.rmit.edu.au/view/rmit:160748.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Dalvand, N. “Silicon photonic devices utilizing lateral leakage behaviour.” 2014. Web. 26 Sep 2020.

Vancouver:

Dalvand N. Silicon photonic devices utilizing lateral leakage behaviour. [Internet] [Thesis]. RMIT University; 2014. [cited 2020 Sep 26]. Available from: http://researchbank.rmit.edu.au/view/rmit:160748.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dalvand N. Silicon photonic devices utilizing lateral leakage behaviour. [Thesis]. RMIT University; 2014. Available from: http://researchbank.rmit.edu.au/view/rmit:160748

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

11. Xiao, Min-Yuan. Silicon-on-Insulator Polarization Beam Splitter Based on a Taper Asymmetrical Directional Coupler.

Degree: Master, Electro-Optical Engineering, 2012, NSYSU

 Polarization dependences of optical devices in highly-integrated optical systems become a major problem. To overcome this issue, one can implement polarization diversity scheme to achieve… (more)

Subjects/Keywords: planar lightwave circuit (PLC); silicon on insulator (SOI); directional coupler; tapered waveguide; polarization beam splitter (PBS); integrated optics

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Xiao, M. (2012). Silicon-on-Insulator Polarization Beam Splitter Based on a Taper Asymmetrical Directional Coupler. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725112-182701

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Xiao, Min-Yuan. “Silicon-on-Insulator Polarization Beam Splitter Based on a Taper Asymmetrical Directional Coupler.” 2012. Thesis, NSYSU. Accessed September 26, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725112-182701.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Xiao, Min-Yuan. “Silicon-on-Insulator Polarization Beam Splitter Based on a Taper Asymmetrical Directional Coupler.” 2012. Web. 26 Sep 2020.

Vancouver:

Xiao M. Silicon-on-Insulator Polarization Beam Splitter Based on a Taper Asymmetrical Directional Coupler. [Internet] [Thesis]. NSYSU; 2012. [cited 2020 Sep 26]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725112-182701.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Xiao M. Silicon-on-Insulator Polarization Beam Splitter Based on a Taper Asymmetrical Directional Coupler. [Thesis]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725112-182701

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

12. Chang, Wei-Lun. Characteristic Analysis of Grating Assisted SOI Racetrack Resonators.

Degree: Master, Electro-Optical Engineering, 2012, NSYSU

Silicon-on-Insulator (SOI) micro-ring resonators (MRRs) are versatile elements in high-density integrated optics telecommunication systems. However, small inaccuracies in the fabrication process intensely deteriorate the response… (more)

Subjects/Keywords: CMT; EIM; micro-ring resonators; Silicon-on-Insulator; grating-assisted SOI racetrack resonators; 2-D FDTD method

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chang, W. (2012). Characteristic Analysis of Grating Assisted SOI Racetrack Resonators. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0723112-231158

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chang, Wei-Lun. “Characteristic Analysis of Grating Assisted SOI Racetrack Resonators.” 2012. Thesis, NSYSU. Accessed September 26, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0723112-231158.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chang, Wei-Lun. “Characteristic Analysis of Grating Assisted SOI Racetrack Resonators.” 2012. Web. 26 Sep 2020.

Vancouver:

Chang W. Characteristic Analysis of Grating Assisted SOI Racetrack Resonators. [Internet] [Thesis]. NSYSU; 2012. [cited 2020 Sep 26]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0723112-231158.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chang W. Characteristic Analysis of Grating Assisted SOI Racetrack Resonators. [Thesis]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0723112-231158

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Lehigh University

13. Yan, Liangyue. Analysis of Photonic Integrated Circuits for Optical Coherence Tomography Application.

Degree: MS, Electrical Engineering, 2016, Lehigh University

 Nowadays, optical coherence tomography (OCT) technology is well known in the in-vivo disease diagnose, attributed to the low-cost operation of the three-dimensional medical imaging. In… (more)

Subjects/Keywords: low loss; Optical Coherence Tomography (OCT); Photonic Integrated Circuits (PICs); Silicon on Insulator (SOI); surface roughness; Electrical and Computer Engineering; Engineering

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yan, L. (2016). Analysis of Photonic Integrated Circuits for Optical Coherence Tomography Application. (Thesis). Lehigh University. Retrieved from https://preserve.lehigh.edu/etd/2893

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yan, Liangyue. “Analysis of Photonic Integrated Circuits for Optical Coherence Tomography Application.” 2016. Thesis, Lehigh University. Accessed September 26, 2020. https://preserve.lehigh.edu/etd/2893.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yan, Liangyue. “Analysis of Photonic Integrated Circuits for Optical Coherence Tomography Application.” 2016. Web. 26 Sep 2020.

Vancouver:

Yan L. Analysis of Photonic Integrated Circuits for Optical Coherence Tomography Application. [Internet] [Thesis]. Lehigh University; 2016. [cited 2020 Sep 26]. Available from: https://preserve.lehigh.edu/etd/2893.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yan L. Analysis of Photonic Integrated Circuits for Optical Coherence Tomography Application. [Thesis]. Lehigh University; 2016. Available from: https://preserve.lehigh.edu/etd/2893

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

14. Mangal, Nivesh. SOI Based Integrated-Optic Microring Resonators for Biomedical Sensing Applications.

Degree: MSc Engg, Faculty of Engineering, 2018, Indian Institute of Science

 Integrated Silicon Photonics has emerged as a powerful platform in the last two decades amongst high-bandwidth technologies, particularly since the adop- tion of CMOS compatible… (more)

Subjects/Keywords: Integrated Silicon Photonics; Silicon-On-Insulator (SOI); Microring Resonators; Biosensors; Integrated -Optic Waveguides; Ring Resonators; Silicon Photonics - Biomedical Sensing; Microring Resonators - Biomedical Sensing; Submicron Integrated-Optic Waveguides; Applied Optics

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mangal, N. (2018). SOI Based Integrated-Optic Microring Resonators for Biomedical Sensing Applications. (Masters Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/3174

Chicago Manual of Style (16th Edition):

Mangal, Nivesh. “SOI Based Integrated-Optic Microring Resonators for Biomedical Sensing Applications.” 2018. Masters Thesis, Indian Institute of Science. Accessed September 26, 2020. http://etd.iisc.ac.in/handle/2005/3174.

MLA Handbook (7th Edition):

Mangal, Nivesh. “SOI Based Integrated-Optic Microring Resonators for Biomedical Sensing Applications.” 2018. Web. 26 Sep 2020.

Vancouver:

Mangal N. SOI Based Integrated-Optic Microring Resonators for Biomedical Sensing Applications. [Internet] [Masters thesis]. Indian Institute of Science; 2018. [cited 2020 Sep 26]. Available from: http://etd.iisc.ac.in/handle/2005/3174.

Council of Science Editors:

Mangal N. SOI Based Integrated-Optic Microring Resonators for Biomedical Sensing Applications. [Masters Thesis]. Indian Institute of Science; 2018. Available from: http://etd.iisc.ac.in/handle/2005/3174

15. Massy, Damien. Etude de la dynamique de fracture dans la technologie Smart Cut™ : Fracture dynamics analysis on Smart Cut™ technology.

Degree: Docteur es, Physique des materiaux, 2015, Université Grenoble Alpes (ComUE)

La technologie Smart Cut™ est un procédé générique de transfert de couches minces utilisé pour la fabrication des substrats silicium sur isolant (SOI) à l’échelle… (more)

Subjects/Keywords: Smart Cut™; Dynamique de fracture; Emission acoustique; Silicium sur Isolant (SOI); Smart Cut™; Fracture dynamics; Acoustic emission; Silicon on Insulator (SOI); 570

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Massy, D. (2015). Etude de la dynamique de fracture dans la technologie Smart Cut™ : Fracture dynamics analysis on Smart Cut™ technology. (Doctoral Dissertation). Université Grenoble Alpes (ComUE). Retrieved from http://www.theses.fr/2015GREAY101

Chicago Manual of Style (16th Edition):

Massy, Damien. “Etude de la dynamique de fracture dans la technologie Smart Cut™ : Fracture dynamics analysis on Smart Cut™ technology.” 2015. Doctoral Dissertation, Université Grenoble Alpes (ComUE). Accessed September 26, 2020. http://www.theses.fr/2015GREAY101.

MLA Handbook (7th Edition):

Massy, Damien. “Etude de la dynamique de fracture dans la technologie Smart Cut™ : Fracture dynamics analysis on Smart Cut™ technology.” 2015. Web. 26 Sep 2020.

Vancouver:

Massy D. Etude de la dynamique de fracture dans la technologie Smart Cut™ : Fracture dynamics analysis on Smart Cut™ technology. [Internet] [Doctoral dissertation]. Université Grenoble Alpes (ComUE); 2015. [cited 2020 Sep 26]. Available from: http://www.theses.fr/2015GREAY101.

Council of Science Editors:

Massy D. Etude de la dynamique de fracture dans la technologie Smart Cut™ : Fracture dynamics analysis on Smart Cut™ technology. [Doctoral Dissertation]. Université Grenoble Alpes (ComUE); 2015. Available from: http://www.theses.fr/2015GREAY101

16. Damianos, Dimitrios. Génération de seconde harmonique (SHG) pour la caractérisation des interfaces entre diélectriques et semiconducteurs : Second harmonic generation (SHG) for contactless characterization of dielectric-semiconductor interfaces.

Degree: Docteur es, Nano electronique et nano technologies, 2018, Université Grenoble Alpes (ComUE)

Cette thèse s’intéresse à une technique de caractérisation particulièrement bien adaptée à l’étude de couches diélectriques ultra-minces sur semiconducteurs. La génération de seconde harmonique (SHG)… (more)

Subjects/Keywords: Génération de seconde harmonique; Caractérisation optique; Silicium sur Isolant (SOI); Al2O3; Optical modeling; Electrical characterization; Second harmonic generation; Optical characterization; Silicon on Insulator (SOI); Al2O3; Optical modeling; Electrical characterization; 620

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Damianos, D. (2018). Génération de seconde harmonique (SHG) pour la caractérisation des interfaces entre diélectriques et semiconducteurs : Second harmonic generation (SHG) for contactless characterization of dielectric-semiconductor interfaces. (Doctoral Dissertation). Université Grenoble Alpes (ComUE). Retrieved from http://www.theses.fr/2018GREAT072

Chicago Manual of Style (16th Edition):

Damianos, Dimitrios. “Génération de seconde harmonique (SHG) pour la caractérisation des interfaces entre diélectriques et semiconducteurs : Second harmonic generation (SHG) for contactless characterization of dielectric-semiconductor interfaces.” 2018. Doctoral Dissertation, Université Grenoble Alpes (ComUE). Accessed September 26, 2020. http://www.theses.fr/2018GREAT072.

MLA Handbook (7th Edition):

Damianos, Dimitrios. “Génération de seconde harmonique (SHG) pour la caractérisation des interfaces entre diélectriques et semiconducteurs : Second harmonic generation (SHG) for contactless characterization of dielectric-semiconductor interfaces.” 2018. Web. 26 Sep 2020.

Vancouver:

Damianos D. Génération de seconde harmonique (SHG) pour la caractérisation des interfaces entre diélectriques et semiconducteurs : Second harmonic generation (SHG) for contactless characterization of dielectric-semiconductor interfaces. [Internet] [Doctoral dissertation]. Université Grenoble Alpes (ComUE); 2018. [cited 2020 Sep 26]. Available from: http://www.theses.fr/2018GREAT072.

Council of Science Editors:

Damianos D. Génération de seconde harmonique (SHG) pour la caractérisation des interfaces entre diélectriques et semiconducteurs : Second harmonic generation (SHG) for contactless characterization of dielectric-semiconductor interfaces. [Doctoral Dissertation]. Université Grenoble Alpes (ComUE); 2018. Available from: http://www.theses.fr/2018GREAT072

17. Suni, Tommi. Direct Wafer Bonding for MEMS and Microelectronics.

Degree: 2006, VTT Technical Research Centre of Finland

Direct wafer bonding is a method for fabricating advanced substrates for microelectromechanical systems (MEMS) and integrated circuits (IC). The most typical example of such an… (more)

Subjects/Keywords: direct water bonding; MEMS; microelectronics; microelectromechanical systems; SOI; silicon-on-insulator; integrated circuits; bond strength measurement; heterogeneous integration; pre-processed SOI fabrication; water-scale packaging; plasma activation; direct wafer bonding; MEMS; microelectronics; microelectromechanical systems; SOI; silicon-on-insulator; integrated circuits; bond strength measurement; heterogeneous integration; pre-processed SOI fabrication; wafer-scale packaging; plasma activation

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Suni, T. (2006). Direct Wafer Bonding for MEMS and Microelectronics. (Thesis). VTT Technical Research Centre of Finland. Retrieved from http://lib.tkk.fi/Diss/2006/isbn9513868524/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Suni, Tommi. “Direct Wafer Bonding for MEMS and Microelectronics.” 2006. Thesis, VTT Technical Research Centre of Finland. Accessed September 26, 2020. http://lib.tkk.fi/Diss/2006/isbn9513868524/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Suni, Tommi. “Direct Wafer Bonding for MEMS and Microelectronics.” 2006. Web. 26 Sep 2020.

Vancouver:

Suni T. Direct Wafer Bonding for MEMS and Microelectronics. [Internet] [Thesis]. VTT Technical Research Centre of Finland; 2006. [cited 2020 Sep 26]. Available from: http://lib.tkk.fi/Diss/2006/isbn9513868524/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Suni T. Direct Wafer Bonding for MEMS and Microelectronics. [Thesis]. VTT Technical Research Centre of Finland; 2006. Available from: http://lib.tkk.fi/Diss/2006/isbn9513868524/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

18. Aalto, Timo. Microphotonic Silicon Waveguide Components.

Degree: 2004, VTT Technical Research Centre of Finland

This thesis describes the design, simulation, fabrication and characterisation of microphotonic silicon waveguide components on silicon-on-insulator (SOI) substrates. The focus is on approximately 10 μm thick… (more)

Subjects/Keywords: silicon microphotonics; integrated optics; silicon-on-insulator waveguides; SOI waveguides; waveguide bends; thermo-optical switching; multi-step patterning; polarisation maintaining fibers; polarisation extinction ratio

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Aalto, T. (2004). Microphotonic Silicon Waveguide Components. (Thesis). VTT Technical Research Centre of Finland. Retrieved from http://lib.tkk.fi/Diss/2004/isbn9513864235/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Aalto, Timo. “Microphotonic Silicon Waveguide Components.” 2004. Thesis, VTT Technical Research Centre of Finland. Accessed September 26, 2020. http://lib.tkk.fi/Diss/2004/isbn9513864235/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Aalto, Timo. “Microphotonic Silicon Waveguide Components.” 2004. Web. 26 Sep 2020.

Vancouver:

Aalto T. Microphotonic Silicon Waveguide Components. [Internet] [Thesis]. VTT Technical Research Centre of Finland; 2004. [cited 2020 Sep 26]. Available from: http://lib.tkk.fi/Diss/2004/isbn9513864235/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Aalto T. Microphotonic Silicon Waveguide Components. [Thesis]. VTT Technical Research Centre of Finland; 2004. Available from: http://lib.tkk.fi/Diss/2004/isbn9513864235/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

19. Gallet, Antonin. Hybrid III-V on silicon lasers for optical communications : Sources lasers hybrides III-V sur silicium pour les communications optiques.

Degree: Docteur es, Electronique et Optoélectronique, Nano- et Microtechnologies, 2019, Université Paris-Saclay (ComUE)

L’intégration photonique permet de réduire la taille et la consommation d’énergie des systèmes de communication par fibre optique par rapport aux systèmes assemblés à partir… (more)

Subjects/Keywords: Photonique sur silicium; Lasers hybrides; Circuit intégré photonique, PIC; III-V sur silicium; Silicium sur isolant, SOI; Silicon photonics; Hybrid lasers; Photonic integrated circuit, PIC; III-V on Silicon; Silicon on insulator, SOI

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gallet, A. (2019). Hybrid III-V on silicon lasers for optical communications : Sources lasers hybrides III-V sur silicium pour les communications optiques. (Doctoral Dissertation). Université Paris-Saclay (ComUE). Retrieved from http://www.theses.fr/2019SACLT019

Chicago Manual of Style (16th Edition):

Gallet, Antonin. “Hybrid III-V on silicon lasers for optical communications : Sources lasers hybrides III-V sur silicium pour les communications optiques.” 2019. Doctoral Dissertation, Université Paris-Saclay (ComUE). Accessed September 26, 2020. http://www.theses.fr/2019SACLT019.

MLA Handbook (7th Edition):

Gallet, Antonin. “Hybrid III-V on silicon lasers for optical communications : Sources lasers hybrides III-V sur silicium pour les communications optiques.” 2019. Web. 26 Sep 2020.

Vancouver:

Gallet A. Hybrid III-V on silicon lasers for optical communications : Sources lasers hybrides III-V sur silicium pour les communications optiques. [Internet] [Doctoral dissertation]. Université Paris-Saclay (ComUE); 2019. [cited 2020 Sep 26]. Available from: http://www.theses.fr/2019SACLT019.

Council of Science Editors:

Gallet A. Hybrid III-V on silicon lasers for optical communications : Sources lasers hybrides III-V sur silicium pour les communications optiques. [Doctoral Dissertation]. Université Paris-Saclay (ComUE); 2019. Available from: http://www.theses.fr/2019SACLT019

20. LUO SIQI. FABRICATION AND CHARACTERIZATION OF SOI MOSFETS.

Degree: 2003, National University of Singapore

Subjects/Keywords: Fabrication; metal-on-semiconductor field-effect transistors; MOSFETs; characterization; silicon-on-insulator; SOI

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

SIQI, L. (2003). FABRICATION AND CHARACTERIZATION OF SOI MOSFETS. (Thesis). National University of Singapore. Retrieved from https://scholarbank.nus.edu.sg/handle/10635/154127

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

SIQI, LUO. “FABRICATION AND CHARACTERIZATION OF SOI MOSFETS.” 2003. Thesis, National University of Singapore. Accessed September 26, 2020. https://scholarbank.nus.edu.sg/handle/10635/154127.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

SIQI, LUO. “FABRICATION AND CHARACTERIZATION OF SOI MOSFETS.” 2003. Web. 26 Sep 2020.

Vancouver:

SIQI L. FABRICATION AND CHARACTERIZATION OF SOI MOSFETS. [Internet] [Thesis]. National University of Singapore; 2003. [cited 2020 Sep 26]. Available from: https://scholarbank.nus.edu.sg/handle/10635/154127.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

SIQI L. FABRICATION AND CHARACTERIZATION OF SOI MOSFETS. [Thesis]. National University of Singapore; 2003. Available from: https://scholarbank.nus.edu.sg/handle/10635/154127

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Bath

21. Hobbs, Gareth. Optical properties of silicon-on-insulator waveguide arrays and cavities.

Degree: PhD, 2014, University of Bath

 This thesis details work undertaken over the past three and a half years looking at the optical properties of silicon-on-insulator waveguide arrays and 1D photonic… (more)

Subjects/Keywords: 621.36; silicon-on-insulator; photonics; waveguides; microcavities

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hobbs, G. (2014). Optical properties of silicon-on-insulator waveguide arrays and cavities. (Doctoral Dissertation). University of Bath. Retrieved from https://researchportal.bath.ac.uk/en/studentthesis/optical-properties-of-silicononinsulator-waveguide-arrays-and-cavities(515ceb52-3d48-4f0c-ade5-02914676b80c).html ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.636523

Chicago Manual of Style (16th Edition):

Hobbs, Gareth. “Optical properties of silicon-on-insulator waveguide arrays and cavities.” 2014. Doctoral Dissertation, University of Bath. Accessed September 26, 2020. https://researchportal.bath.ac.uk/en/studentthesis/optical-properties-of-silicononinsulator-waveguide-arrays-and-cavities(515ceb52-3d48-4f0c-ade5-02914676b80c).html ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.636523.

MLA Handbook (7th Edition):

Hobbs, Gareth. “Optical properties of silicon-on-insulator waveguide arrays and cavities.” 2014. Web. 26 Sep 2020.

Vancouver:

Hobbs G. Optical properties of silicon-on-insulator waveguide arrays and cavities. [Internet] [Doctoral dissertation]. University of Bath; 2014. [cited 2020 Sep 26]. Available from: https://researchportal.bath.ac.uk/en/studentthesis/optical-properties-of-silicononinsulator-waveguide-arrays-and-cavities(515ceb52-3d48-4f0c-ade5-02914676b80c).html ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.636523.

Council of Science Editors:

Hobbs G. Optical properties of silicon-on-insulator waveguide arrays and cavities. [Doctoral Dissertation]. University of Bath; 2014. Available from: https://researchportal.bath.ac.uk/en/studentthesis/optical-properties-of-silicononinsulator-waveguide-arrays-and-cavities(515ceb52-3d48-4f0c-ade5-02914676b80c).html ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.636523


University of New Mexico

22. Aarestad, James. Characterizing within-die and die-to-die delay variations introduced By process variations and SOI history effect.

Degree: Electrical and Computer Engineering, 2011, University of New Mexico

 Variations in delay caused by within-die and die-to-die process variations and SOI history effect increase timing margins and reduce performance. In order to develop mitigation… (more)

Subjects/Keywords: Delay faults (Semiconductors); Silicon-on-insulator technology.

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Aarestad, J. (2011). Characterizing within-die and die-to-die delay variations introduced By process variations and SOI history effect. (Masters Thesis). University of New Mexico. Retrieved from http://hdl.handle.net/1928/12832

Chicago Manual of Style (16th Edition):

Aarestad, James. “Characterizing within-die and die-to-die delay variations introduced By process variations and SOI history effect.” 2011. Masters Thesis, University of New Mexico. Accessed September 26, 2020. http://hdl.handle.net/1928/12832.

MLA Handbook (7th Edition):

Aarestad, James. “Characterizing within-die and die-to-die delay variations introduced By process variations and SOI history effect.” 2011. Web. 26 Sep 2020.

Vancouver:

Aarestad J. Characterizing within-die and die-to-die delay variations introduced By process variations and SOI history effect. [Internet] [Masters thesis]. University of New Mexico; 2011. [cited 2020 Sep 26]. Available from: http://hdl.handle.net/1928/12832.

Council of Science Editors:

Aarestad J. Characterizing within-die and die-to-die delay variations introduced By process variations and SOI history effect. [Masters Thesis]. University of New Mexico; 2011. Available from: http://hdl.handle.net/1928/12832

23. Lauerman Tomáš. Nonlinear propagation in photonic waveguide microresonators .

Degree: 2012, Czech University of Technology

Nonlinear propagation in photonic waveguide microresonators; Nonlinear propagation in photonic waveguide microresonators Advisors/Committee Members: Čtyroký Jiří (advisor).

Subjects/Keywords: ring microresonator; silicon-on-insulator waveguides

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tomáš, L. (2012). Nonlinear propagation in photonic waveguide microresonators . (Thesis). Czech University of Technology. Retrieved from http://hdl.handle.net/10467/9202

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tomáš, Lauerman. “Nonlinear propagation in photonic waveguide microresonators .” 2012. Thesis, Czech University of Technology. Accessed September 26, 2020. http://hdl.handle.net/10467/9202.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tomáš, Lauerman. “Nonlinear propagation in photonic waveguide microresonators .” 2012. Web. 26 Sep 2020.

Vancouver:

Tomáš L. Nonlinear propagation in photonic waveguide microresonators . [Internet] [Thesis]. Czech University of Technology; 2012. [cited 2020 Sep 26]. Available from: http://hdl.handle.net/10467/9202.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tomáš L. Nonlinear propagation in photonic waveguide microresonators . [Thesis]. Czech University of Technology; 2012. Available from: http://hdl.handle.net/10467/9202

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Michigan

24. Rao, Rahul M. Digital circuit design techniques for low -leakage silicon -on -insulator (SOI) CMOS technology.

Degree: PhD, Electrical engineering, 2004, University of Michigan

 With aggressive scaling of device dimensions, threshold voltages and oxide-thicknesses, leakage-power consumption has emerged as a critical metric in the design of integrated circuits and… (more)

Subjects/Keywords: Cmos; Digital Circuit Design; Low-leakage; Silicon-on-insulator; Soi; Techniques; Technology; Vlsi

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Rao, R. M. (2004). Digital circuit design techniques for low -leakage silicon -on -insulator (SOI) CMOS technology. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/124540

Chicago Manual of Style (16th Edition):

Rao, Rahul M. “Digital circuit design techniques for low -leakage silicon -on -insulator (SOI) CMOS technology.” 2004. Doctoral Dissertation, University of Michigan. Accessed September 26, 2020. http://hdl.handle.net/2027.42/124540.

MLA Handbook (7th Edition):

Rao, Rahul M. “Digital circuit design techniques for low -leakage silicon -on -insulator (SOI) CMOS technology.” 2004. Web. 26 Sep 2020.

Vancouver:

Rao RM. Digital circuit design techniques for low -leakage silicon -on -insulator (SOI) CMOS technology. [Internet] [Doctoral dissertation]. University of Michigan; 2004. [cited 2020 Sep 26]. Available from: http://hdl.handle.net/2027.42/124540.

Council of Science Editors:

Rao RM. Digital circuit design techniques for low -leakage silicon -on -insulator (SOI) CMOS technology. [Doctoral Dissertation]. University of Michigan; 2004. Available from: http://hdl.handle.net/2027.42/124540


University of Michigan

25. Das, Koushik K. Robust low -power digital circuit design in silicon -on -insulator (SOI) CMOS technology.

Degree: PhD, Electrical engineering, 2003, University of Michigan

 Low-power will be the primary focus of the semiconductor industry in the next decade. The threshold voltage has been scaled to a few hundred millivolts,… (more)

Subjects/Keywords: Cmos; Design; Digital Circuit; Low-power; Robust; Silicon-on-insulator; Soi; Technology

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Das, K. K. (2003). Robust low -power digital circuit design in silicon -on -insulator (SOI) CMOS technology. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/123817

Chicago Manual of Style (16th Edition):

Das, Koushik K. “Robust low -power digital circuit design in silicon -on -insulator (SOI) CMOS technology.” 2003. Doctoral Dissertation, University of Michigan. Accessed September 26, 2020. http://hdl.handle.net/2027.42/123817.

MLA Handbook (7th Edition):

Das, Koushik K. “Robust low -power digital circuit design in silicon -on -insulator (SOI) CMOS technology.” 2003. Web. 26 Sep 2020.

Vancouver:

Das KK. Robust low -power digital circuit design in silicon -on -insulator (SOI) CMOS technology. [Internet] [Doctoral dissertation]. University of Michigan; 2003. [cited 2020 Sep 26]. Available from: http://hdl.handle.net/2027.42/123817.

Council of Science Editors:

Das KK. Robust low -power digital circuit design in silicon -on -insulator (SOI) CMOS technology. [Doctoral Dissertation]. University of Michigan; 2003. Available from: http://hdl.handle.net/2027.42/123817


University of Waterloo

26. Cui, Bolun. 22-32 GHz Low-Noise Amplifier Design in 22-nm CMOS-SOI Technology.

Degree: 2019, University of Waterloo

 This thesis explores the use of a 22-nm CMOS-SOI technology in the design of a two-stage amplifier which targets wide bandwidth, low noise and modest… (more)

Subjects/Keywords: Low-noise amplifier; RF feedback; mm-wave transformer; CMOS-SOI; Broadband amplifier; Metal oxide semiconductors, Complementary.; Silicon-on-insulator technology; Low noise amplifiers; Broadband amplifiers

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cui, B. (2019). 22-32 GHz Low-Noise Amplifier Design in 22-nm CMOS-SOI Technology. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/14446

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Cui, Bolun. “22-32 GHz Low-Noise Amplifier Design in 22-nm CMOS-SOI Technology.” 2019. Thesis, University of Waterloo. Accessed September 26, 2020. http://hdl.handle.net/10012/14446.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Cui, Bolun. “22-32 GHz Low-Noise Amplifier Design in 22-nm CMOS-SOI Technology.” 2019. Web. 26 Sep 2020.

Vancouver:

Cui B. 22-32 GHz Low-Noise Amplifier Design in 22-nm CMOS-SOI Technology. [Internet] [Thesis]. University of Waterloo; 2019. [cited 2020 Sep 26]. Available from: http://hdl.handle.net/10012/14446.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Cui B. 22-32 GHz Low-Noise Amplifier Design in 22-nm CMOS-SOI Technology. [Thesis]. University of Waterloo; 2019. Available from: http://hdl.handle.net/10012/14446

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Waterloo

27. Khaira, Navjot Kaur. SOI RF-MEMS Based Variable Attenuator for Millimeter-Wave Applications.

Degree: 2019, University of Waterloo

 The most-attractive feature of microelectromechanical systems (MEMS) technology is that it enables the integration of a whole system on a single chip, leading to positive… (more)

Subjects/Keywords: millimeter-wave applications; RF-MEMS; variable attenuator; thermal imaging; impedance tuner; chevron actuator; micro-fabrication; SOI MEMS; silicon-on-insulator; microelectromechanical systems

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Khaira, N. K. (2019). SOI RF-MEMS Based Variable Attenuator for Millimeter-Wave Applications. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/14672

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Khaira, Navjot Kaur. “SOI RF-MEMS Based Variable Attenuator for Millimeter-Wave Applications.” 2019. Thesis, University of Waterloo. Accessed September 26, 2020. http://hdl.handle.net/10012/14672.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Khaira, Navjot Kaur. “SOI RF-MEMS Based Variable Attenuator for Millimeter-Wave Applications.” 2019. Web. 26 Sep 2020.

Vancouver:

Khaira NK. SOI RF-MEMS Based Variable Attenuator for Millimeter-Wave Applications. [Internet] [Thesis]. University of Waterloo; 2019. [cited 2020 Sep 26]. Available from: http://hdl.handle.net/10012/14672.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Khaira NK. SOI RF-MEMS Based Variable Attenuator for Millimeter-Wave Applications. [Thesis]. University of Waterloo; 2019. Available from: http://hdl.handle.net/10012/14672

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


North Carolina State University

28. Damiano, John. Active Body Bias for Low-Power Silicon-On-Insulator Design.

Degree: PhD, Electrical Engineering, 2007, North Carolina State University

SOI device technology offers the circuit designer higher performance and greater flexibility. This work proposes the use of a targeted substrate bias and innovative device… (more)

Subjects/Keywords: SOI; circuit design; silicon-on-insulator; body bias; layout techniques; layout

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Damiano, J. (2007). Active Body Bias for Low-Power Silicon-On-Insulator Design. (Doctoral Dissertation). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/3990

Chicago Manual of Style (16th Edition):

Damiano, John. “Active Body Bias for Low-Power Silicon-On-Insulator Design.” 2007. Doctoral Dissertation, North Carolina State University. Accessed September 26, 2020. http://www.lib.ncsu.edu/resolver/1840.16/3990.

MLA Handbook (7th Edition):

Damiano, John. “Active Body Bias for Low-Power Silicon-On-Insulator Design.” 2007. Web. 26 Sep 2020.

Vancouver:

Damiano J. Active Body Bias for Low-Power Silicon-On-Insulator Design. [Internet] [Doctoral dissertation]. North Carolina State University; 2007. [cited 2020 Sep 26]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/3990.

Council of Science Editors:

Damiano J. Active Body Bias for Low-Power Silicon-On-Insulator Design. [Doctoral Dissertation]. North Carolina State University; 2007. Available from: http://www.lib.ncsu.edu/resolver/1840.16/3990


University of Akron

29. Kollarits, Matthew David. Design and Simulation of a Temperature-Insensitive Rail-to-Rail Comparator for Analog-to-Digital Converter Application.

Degree: MS, Electrical Engineering, 2010, University of Akron

  A comparator with rail-to-rail input voltage range is presented. The rail-to-rail operation is achieved using two folded-cascode differential amplifiers operating in parallel as an… (more)

Subjects/Keywords: Electrical Engineering; Comparator; ADC; Analog-to-Digital Converter; ZTC; Zero-Temperature Coefficient; Rail-to-Rail; Complementary Folded Cascode; Folded Cascode; Transmission Gate; SOI; Silicon-on-Insulator

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kollarits, M. D. (2010). Design and Simulation of a Temperature-Insensitive Rail-to-Rail Comparator for Analog-to-Digital Converter Application. (Masters Thesis). University of Akron. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=akron1279036924

Chicago Manual of Style (16th Edition):

Kollarits, Matthew David. “Design and Simulation of a Temperature-Insensitive Rail-to-Rail Comparator for Analog-to-Digital Converter Application.” 2010. Masters Thesis, University of Akron. Accessed September 26, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=akron1279036924.

MLA Handbook (7th Edition):

Kollarits, Matthew David. “Design and Simulation of a Temperature-Insensitive Rail-to-Rail Comparator for Analog-to-Digital Converter Application.” 2010. Web. 26 Sep 2020.

Vancouver:

Kollarits MD. Design and Simulation of a Temperature-Insensitive Rail-to-Rail Comparator for Analog-to-Digital Converter Application. [Internet] [Masters thesis]. University of Akron; 2010. [cited 2020 Sep 26]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=akron1279036924.

Council of Science Editors:

Kollarits MD. Design and Simulation of a Temperature-Insensitive Rail-to-Rail Comparator for Analog-to-Digital Converter Application. [Masters Thesis]. University of Akron; 2010. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=akron1279036924

30. Falahi, Khalil El. Contribution à la conception de driver en technologie CMOS SOI pour la commande de transistors JFET SiC pour un environnement de haute température : High temperature CMOS SOI driver for JFET SiC transistors.

Degree: Docteur es, Electronique, 2012, INSA Lyon

Dans le domaine aéronautique, les systèmes électriques remplacement progressivement les systèmes de contrôle mécaniques ou hydrauliques. Les bénéfices immédiats sont la réduction de la masse… (more)

Subjects/Keywords: Électronique de puissance; Transistor de puissance à jonction à effet de champ en SiC - JFET-SiC de puissance; Haute température; Silicium sur isolant - SOI; Commande électrique; Driver SOI haute température; Power Electronics; JFET-SiC - Silicon Carbide Power Junction Field Effect Transistor; High temperature; SOI - Silicon On Insulator; Electric Control; High temperature SOI Driver; 621.317 072

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Falahi, K. E. (2012). Contribution à la conception de driver en technologie CMOS SOI pour la commande de transistors JFET SiC pour un environnement de haute température : High temperature CMOS SOI driver for JFET SiC transistors. (Doctoral Dissertation). INSA Lyon. Retrieved from http://www.theses.fr/2012ISAL0056

Chicago Manual of Style (16th Edition):

Falahi, Khalil El. “Contribution à la conception de driver en technologie CMOS SOI pour la commande de transistors JFET SiC pour un environnement de haute température : High temperature CMOS SOI driver for JFET SiC transistors.” 2012. Doctoral Dissertation, INSA Lyon. Accessed September 26, 2020. http://www.theses.fr/2012ISAL0056.

MLA Handbook (7th Edition):

Falahi, Khalil El. “Contribution à la conception de driver en technologie CMOS SOI pour la commande de transistors JFET SiC pour un environnement de haute température : High temperature CMOS SOI driver for JFET SiC transistors.” 2012. Web. 26 Sep 2020.

Vancouver:

Falahi KE. Contribution à la conception de driver en technologie CMOS SOI pour la commande de transistors JFET SiC pour un environnement de haute température : High temperature CMOS SOI driver for JFET SiC transistors. [Internet] [Doctoral dissertation]. INSA Lyon; 2012. [cited 2020 Sep 26]. Available from: http://www.theses.fr/2012ISAL0056.

Council of Science Editors:

Falahi KE. Contribution à la conception de driver en technologie CMOS SOI pour la commande de transistors JFET SiC pour un environnement de haute température : High temperature CMOS SOI driver for JFET SiC transistors. [Doctoral Dissertation]. INSA Lyon; 2012. Available from: http://www.theses.fr/2012ISAL0056

[1] [2] [3] [4] [5] … [807]

.