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You searched for subject:(sequential logic). Showing records 1 – 23 of 23 total matches.

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1. Thulasi Raman, Sudheer Ram. Logic Encryption of Sequential Circuits.

Degree: MS, Engineering and Applied Science: Computer Engineering, 2019, University of Cincinnati

 With the advent of semi conductor design industry becoming fab-less to reduce the cost incurred on maintaining the fabrication units due to the advancements in… (more)

Subjects/Keywords: Computer Engineering; Logic Encryption; Sequential Circuit Logic Encryption; Sequential SAT attack; Deep State Encryption; Hardware Security; SAT Resilient Sequential Circuit Encryption

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APA (6th Edition):

Thulasi Raman, S. R. (2019). Logic Encryption of Sequential Circuits. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1553251689992143

Chicago Manual of Style (16th Edition):

Thulasi Raman, Sudheer Ram. “Logic Encryption of Sequential Circuits.” 2019. Masters Thesis, University of Cincinnati. Accessed August 06, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1553251689992143.

MLA Handbook (7th Edition):

Thulasi Raman, Sudheer Ram. “Logic Encryption of Sequential Circuits.” 2019. Web. 06 Aug 2020.

Vancouver:

Thulasi Raman SR. Logic Encryption of Sequential Circuits. [Internet] [Masters thesis]. University of Cincinnati; 2019. [cited 2020 Aug 06]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1553251689992143.

Council of Science Editors:

Thulasi Raman SR. Logic Encryption of Sequential Circuits. [Masters Thesis]. University of Cincinnati; 2019. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1553251689992143


University of Minnesota

2. Li, Peng. Analysis, design, and logic synthesis of finite-state machine-based Stochastic computing.

Degree: PhD, Electrical Engineering, 2013, University of Minnesota

 Most digital systems operate on a positional representation of data, such as binary encoding. An alternative is to operate on random bit streams where the… (more)

Subjects/Keywords: Fault-tolerance; Logic synthesis; Sequential logic; Stochastic computing

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APA (6th Edition):

Li, P. (2013). Analysis, design, and logic synthesis of finite-state machine-based Stochastic computing. (Doctoral Dissertation). University of Minnesota. Retrieved from http://purl.umn.edu/155955

Chicago Manual of Style (16th Edition):

Li, Peng. “Analysis, design, and logic synthesis of finite-state machine-based Stochastic computing.” 2013. Doctoral Dissertation, University of Minnesota. Accessed August 06, 2020. http://purl.umn.edu/155955.

MLA Handbook (7th Edition):

Li, Peng. “Analysis, design, and logic synthesis of finite-state machine-based Stochastic computing.” 2013. Web. 06 Aug 2020.

Vancouver:

Li P. Analysis, design, and logic synthesis of finite-state machine-based Stochastic computing. [Internet] [Doctoral dissertation]. University of Minnesota; 2013. [cited 2020 Aug 06]. Available from: http://purl.umn.edu/155955.

Council of Science Editors:

Li P. Analysis, design, and logic synthesis of finite-state machine-based Stochastic computing. [Doctoral Dissertation]. University of Minnesota; 2013. Available from: http://purl.umn.edu/155955


University of Rochester

3. Papai, Tivadar (1984 - ). Exploiting constraints, sequential structure, and knowledge in Markov logic networks.

Degree: PhD, 2014, University of Rochester

 In this dissertation we propose extensions to Markov logic networks that can improve inference and learning by exploiting deterministic constraints, expert knowledge or se- quential/temporal… (more)

Subjects/Keywords: Constraint programming; Exponential families; Markov logic; Modal logic; Random fields; Sequential domains

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APA (6th Edition):

Papai, T. (. -. ). (2014). Exploiting constraints, sequential structure, and knowledge in Markov logic networks. (Doctoral Dissertation). University of Rochester. Retrieved from http://hdl.handle.net/1802/28364

Chicago Manual of Style (16th Edition):

Papai, Tivadar (1984 - ). “Exploiting constraints, sequential structure, and knowledge in Markov logic networks.” 2014. Doctoral Dissertation, University of Rochester. Accessed August 06, 2020. http://hdl.handle.net/1802/28364.

MLA Handbook (7th Edition):

Papai, Tivadar (1984 - ). “Exploiting constraints, sequential structure, and knowledge in Markov logic networks.” 2014. Web. 06 Aug 2020.

Vancouver:

Papai T(-). Exploiting constraints, sequential structure, and knowledge in Markov logic networks. [Internet] [Doctoral dissertation]. University of Rochester; 2014. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/1802/28364.

Council of Science Editors:

Papai T(-). Exploiting constraints, sequential structure, and knowledge in Markov logic networks. [Doctoral Dissertation]. University of Rochester; 2014. Available from: http://hdl.handle.net/1802/28364


Virginia Tech

4. Duong, Khanh Viet. On Enhancing Deterministic Sequential ATPG.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

 This thesis presents four different techniques for improving the average-case performance of deterministic sequential circuit Automatic Test Patterns Generators (ATPG). Three techniques make use of… (more)

Subjects/Keywords: Automatic Test Pattern Generation; Logic Testing; Sequential Circuits

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APA (6th Edition):

Duong, K. V. (2011). On Enhancing Deterministic Sequential ATPG. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/31283

Chicago Manual of Style (16th Edition):

Duong, Khanh Viet. “On Enhancing Deterministic Sequential ATPG.” 2011. Masters Thesis, Virginia Tech. Accessed August 06, 2020. http://hdl.handle.net/10919/31283.

MLA Handbook (7th Edition):

Duong, Khanh Viet. “On Enhancing Deterministic Sequential ATPG.” 2011. Web. 06 Aug 2020.

Vancouver:

Duong KV. On Enhancing Deterministic Sequential ATPG. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/10919/31283.

Council of Science Editors:

Duong KV. On Enhancing Deterministic Sequential ATPG. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/31283


Brno University of Technology

5. Sileská, Silvia. Ukázkové úlohy pro výuku automatizace: Sample tasks for automation education.

Degree: 2019, Brno University of Technology

 This bachelor´s thesis deals with the design and demonstration of tasks addressing combinatorial and sequential logic circuits. To resolve the assignment must be familiar with… (more)

Subjects/Keywords: Programovateľný automat; LOGO! Soft Comfort; Kombinačný logický obvod; Sekvenčný logický obvod; Programmable logic computer; LOGO! Soft Comfort; Combinational logic circuit; Sequential logic circuit

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APA (6th Edition):

Sileská, S. (2019). Ukázkové úlohy pro výuku automatizace: Sample tasks for automation education. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/14804

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sileská, Silvia. “Ukázkové úlohy pro výuku automatizace: Sample tasks for automation education.” 2019. Thesis, Brno University of Technology. Accessed August 06, 2020. http://hdl.handle.net/11012/14804.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sileská, Silvia. “Ukázkové úlohy pro výuku automatizace: Sample tasks for automation education.” 2019. Web. 06 Aug 2020.

Vancouver:

Sileská S. Ukázkové úlohy pro výuku automatizace: Sample tasks for automation education. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/11012/14804.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sileská S. Ukázkové úlohy pro výuku automatizace: Sample tasks for automation education. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/14804

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

6. Vijayakumari C K; Dr. Mythili P.; Dr. Rekha K. James. Towards the development of automated techniques for the design of digital circuits using genetic algorithms.

Degree: 2016, Cochin University of Science and Technology

Subjects/Keywords: Combinational logic circuits; Genetic Algorithm; Synchronous Sequential Circuits

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APA (6th Edition):

James, V. C. K. D. M. P. D. R. K. (2016). Towards the development of automated techniques for the design of digital circuits using genetic algorithms. (Thesis). Cochin University of Science and Technology. Retrieved from http://dyuthi.cusat.ac.in/purl/5310

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

James, Vijayakumari C K; Dr. Mythili P.; Dr. Rekha K.. “Towards the development of automated techniques for the design of digital circuits using genetic algorithms.” 2016. Thesis, Cochin University of Science and Technology. Accessed August 06, 2020. http://dyuthi.cusat.ac.in/purl/5310.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

James, Vijayakumari C K; Dr. Mythili P.; Dr. Rekha K.. “Towards the development of automated techniques for the design of digital circuits using genetic algorithms.” 2016. Web. 06 Aug 2020.

Vancouver:

James VCKDMPDRK. Towards the development of automated techniques for the design of digital circuits using genetic algorithms. [Internet] [Thesis]. Cochin University of Science and Technology; 2016. [cited 2020 Aug 06]. Available from: http://dyuthi.cusat.ac.in/purl/5310.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

James VCKDMPDRK. Towards the development of automated techniques for the design of digital circuits using genetic algorithms. [Thesis]. Cochin University of Science and Technology; 2016. Available from: http://dyuthi.cusat.ac.in/purl/5310

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Johannesburg

7. Ras, Charl John. Automatically presentable structures.

Degree: 2012, University of Johannesburg

M.Sc.

In this thesis we study some of the propertie of a clas called automatic structures. Automatic structures are structures that can be encoded (in some defined way) into a set of regular languages. This encoding allows one to prove many interesting properties about automatic structures, including decidabilty results.

Subjects/Keywords: Sequential machine theory; Automata; Formal languages; Equivalence relations (Set theory); Permutation groups; Graph theory; Numbers, Natural; Logic, Symbolic and mathematical

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APA (6th Edition):

Ras, C. J. (2012). Automatically presentable structures. (Thesis). University of Johannesburg. Retrieved from http://hdl.handle.net/10210/6838

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ras, Charl John. “Automatically presentable structures.” 2012. Thesis, University of Johannesburg. Accessed August 06, 2020. http://hdl.handle.net/10210/6838.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ras, Charl John. “Automatically presentable structures.” 2012. Web. 06 Aug 2020.

Vancouver:

Ras CJ. Automatically presentable structures. [Internet] [Thesis]. University of Johannesburg; 2012. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/10210/6838.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ras CJ. Automatically presentable structures. [Thesis]. University of Johannesburg; 2012. Available from: http://hdl.handle.net/10210/6838

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Minnesota

8. Repaka, Ravikanth. Efficiently Storing and Discovering Knowledge in Databases via Inductive Logic Programming Implemented Directly in Databases.

Degree: MS, Computer Science, 2015, University of Minnesota

 Inductive Logic Programming (ILP) uses inductive, statistical techniques to generate hypotheses which incorporate the given background knowledge to induce concepts that cover most of the… (more)

Subjects/Keywords: Databases; Inductive Logic Programming; Knowledge discovery in databases; knowledge store in databases; mutagenesis; chess endgame(KRK); Sequential Covering

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APA (6th Edition):

Repaka, R. (2015). Efficiently Storing and Discovering Knowledge in Databases via Inductive Logic Programming Implemented Directly in Databases. (Masters Thesis). University of Minnesota. Retrieved from http://hdl.handle.net/11299/191232

Chicago Manual of Style (16th Edition):

Repaka, Ravikanth. “Efficiently Storing and Discovering Knowledge in Databases via Inductive Logic Programming Implemented Directly in Databases.” 2015. Masters Thesis, University of Minnesota. Accessed August 06, 2020. http://hdl.handle.net/11299/191232.

MLA Handbook (7th Edition):

Repaka, Ravikanth. “Efficiently Storing and Discovering Knowledge in Databases via Inductive Logic Programming Implemented Directly in Databases.” 2015. Web. 06 Aug 2020.

Vancouver:

Repaka R. Efficiently Storing and Discovering Knowledge in Databases via Inductive Logic Programming Implemented Directly in Databases. [Internet] [Masters thesis]. University of Minnesota; 2015. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/11299/191232.

Council of Science Editors:

Repaka R. Efficiently Storing and Discovering Knowledge in Databases via Inductive Logic Programming Implemented Directly in Databases. [Masters Thesis]. University of Minnesota; 2015. Available from: http://hdl.handle.net/11299/191232


California State University – Northridge

9. Liu, Jack C. An interactive delay simulator for digital networks.

Degree: MS, Department of Engineering, 1978, California State University – Northridge

 The maximum speed of a synchronous sequential digital circuit is directly related to the maximum clock rate which can be applied to the circuit. The… (more)

Subjects/Keywords: Sequential logic circuits; Dissertations, Academic  – CSUN  – Engineering

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APA (6th Edition):

Liu, J. C. (1978). An interactive delay simulator for digital networks. (Masters Thesis). California State University – Northridge. Retrieved from http://hdl.handle.net/10211.3/123757

Chicago Manual of Style (16th Edition):

Liu, Jack C. “An interactive delay simulator for digital networks.” 1978. Masters Thesis, California State University – Northridge. Accessed August 06, 2020. http://hdl.handle.net/10211.3/123757.

MLA Handbook (7th Edition):

Liu, Jack C. “An interactive delay simulator for digital networks.” 1978. Web. 06 Aug 2020.

Vancouver:

Liu JC. An interactive delay simulator for digital networks. [Internet] [Masters thesis]. California State University – Northridge; 1978. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/10211.3/123757.

Council of Science Editors:

Liu JC. An interactive delay simulator for digital networks. [Masters Thesis]. California State University – Northridge; 1978. Available from: http://hdl.handle.net/10211.3/123757


Cal Poly

10. Lee, Chris Y. Full Custom VLSI Design of On-Line Stability Checkers.

Degree: MS, Electrical Engineering, 2011, Cal Poly

  A stability checker is a clocked storage element, much like a flip-flop, which detects unstable and late signals in the pipeline of a digital… (more)

Subjects/Keywords: ASIC; logic design; digital simulation; error analysis; sequential logic circuit fault testing; Computer and Systems Architecture; Digital Circuits; Electronic Devices and Semiconductor Manufacturing; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Lee, C. Y. (2011). Full Custom VLSI Design of On-Line Stability Checkers. (Masters Thesis). Cal Poly. Retrieved from https://digitalcommons.calpoly.edu/theses/607 ; 10.15368/theses.2011.165

Chicago Manual of Style (16th Edition):

Lee, Chris Y. “Full Custom VLSI Design of On-Line Stability Checkers.” 2011. Masters Thesis, Cal Poly. Accessed August 06, 2020. https://digitalcommons.calpoly.edu/theses/607 ; 10.15368/theses.2011.165.

MLA Handbook (7th Edition):

Lee, Chris Y. “Full Custom VLSI Design of On-Line Stability Checkers.” 2011. Web. 06 Aug 2020.

Vancouver:

Lee CY. Full Custom VLSI Design of On-Line Stability Checkers. [Internet] [Masters thesis]. Cal Poly; 2011. [cited 2020 Aug 06]. Available from: https://digitalcommons.calpoly.edu/theses/607 ; 10.15368/theses.2011.165.

Council of Science Editors:

Lee CY. Full Custom VLSI Design of On-Line Stability Checkers. [Masters Thesis]. Cal Poly; 2011. Available from: https://digitalcommons.calpoly.edu/theses/607 ; 10.15368/theses.2011.165


Brno University of Technology

11. Janyš, Martin. Generátor konečných automatů z grafického popisu pro jazyk VHDL: Finite State Machines Generator Based on Graphics Definition for VHDL Language.

Degree: 2020, Brno University of Technology

 The work introduces the reader to the possibilities of design and creation of nite state machines with focus on representation using VHDL. The main topic… (more)

Subjects/Keywords: konečný automat; FSM; VHDL; generátor konečných automatů; sekvenční logika; stavový diagram; graf přechodu; nite state machine; FSM; VHDL; generator of nite machine; sequential logic; state diagram; transition diagram

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Janyš, M. (2020). Generátor konečných automatů z grafického popisu pro jazyk VHDL: Finite State Machines Generator Based on Graphics Definition for VHDL Language. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/189704

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Janyš, Martin. “Generátor konečných automatů z grafického popisu pro jazyk VHDL: Finite State Machines Generator Based on Graphics Definition for VHDL Language.” 2020. Thesis, Brno University of Technology. Accessed August 06, 2020. http://hdl.handle.net/11012/189704.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Janyš, Martin. “Generátor konečných automatů z grafického popisu pro jazyk VHDL: Finite State Machines Generator Based on Graphics Definition for VHDL Language.” 2020. Web. 06 Aug 2020.

Vancouver:

Janyš M. Generátor konečných automatů z grafického popisu pro jazyk VHDL: Finite State Machines Generator Based on Graphics Definition for VHDL Language. [Internet] [Thesis]. Brno University of Technology; 2020. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/11012/189704.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Janyš M. Generátor konečných automatů z grafického popisu pro jazyk VHDL: Finite State Machines Generator Based on Graphics Definition for VHDL Language. [Thesis]. Brno University of Technology; 2020. Available from: http://hdl.handle.net/11012/189704

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

12. Janyš, Martin. Generátor konečných automatů z grafického popisu pro jazyk VHDL: Finite State Machines Generator Based on Graphics Definition for VHDL Language.

Degree: 2019, Brno University of Technology

 The work introduces the reader to the possibilities of design and creation of nite state machines with focus on representation using VHDL. The main topic… (more)

Subjects/Keywords: konečný automat; FSM; VHDL; generátor konečných automatů; sekvenční logika; stavový diagram; graf přechodu; nite state machine; FSM; VHDL; generator of nite machine; sequential logic; state diagram; transition diagram

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Janyš, M. (2019). Generátor konečných automatů z grafického popisu pro jazyk VHDL: Finite State Machines Generator Based on Graphics Definition for VHDL Language. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/54794

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Janyš, Martin. “Generátor konečných automatů z grafického popisu pro jazyk VHDL: Finite State Machines Generator Based on Graphics Definition for VHDL Language.” 2019. Thesis, Brno University of Technology. Accessed August 06, 2020. http://hdl.handle.net/11012/54794.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Janyš, Martin. “Generátor konečných automatů z grafického popisu pro jazyk VHDL: Finite State Machines Generator Based on Graphics Definition for VHDL Language.” 2019. Web. 06 Aug 2020.

Vancouver:

Janyš M. Generátor konečných automatů z grafického popisu pro jazyk VHDL: Finite State Machines Generator Based on Graphics Definition for VHDL Language. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/11012/54794.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Janyš M. Generátor konečných automatů z grafického popisu pro jazyk VHDL: Finite State Machines Generator Based on Graphics Definition for VHDL Language. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/54794

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

13. Janyš, Martin. Generátor konečných automatů z grafického popisu pro jazyk VHDL: Finite State Machines Generator Based on Graphics Definition for VHDL Language.

Degree: 2020, Brno University of Technology

 The work introduces the reader to the possibilities of design and creation of nite state machines with focus on representation using VHDL. The main topic… (more)

Subjects/Keywords: konečný automat; FSM; VHDL; generátor konečných automatů; sekvenční logika; stavový diagram; graf přechodu; nite state machine; FSM; VHDL; generator of nite machine; sequential logic; state diagram; transition diagram

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Janyš, M. (2020). Generátor konečných automatů z grafického popisu pro jazyk VHDL: Finite State Machines Generator Based on Graphics Definition for VHDL Language. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/188312

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Janyš, Martin. “Generátor konečných automatů z grafického popisu pro jazyk VHDL: Finite State Machines Generator Based on Graphics Definition for VHDL Language.” 2020. Thesis, Brno University of Technology. Accessed August 06, 2020. http://hdl.handle.net/11012/188312.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Janyš, Martin. “Generátor konečných automatů z grafického popisu pro jazyk VHDL: Finite State Machines Generator Based on Graphics Definition for VHDL Language.” 2020. Web. 06 Aug 2020.

Vancouver:

Janyš M. Generátor konečných automatů z grafického popisu pro jazyk VHDL: Finite State Machines Generator Based on Graphics Definition for VHDL Language. [Internet] [Thesis]. Brno University of Technology; 2020. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/11012/188312.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Janyš M. Generátor konečných automatů z grafického popisu pro jazyk VHDL: Finite State Machines Generator Based on Graphics Definition for VHDL Language. [Thesis]. Brno University of Technology; 2020. Available from: http://hdl.handle.net/11012/188312

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

14. Pučegl, Pavel. Návrh a realizace učební pomůcky „LOGIK“: Design and realization of teaching instrument.

Degree: 2019, Brno University of Technology

 Gradual wear and growing dissatisfaction with current panels for purposes of teaching the course „Logical control and programmable controllers“ has lead the Institute of Automation… (more)

Subjects/Keywords: LOGIK; učební pomůcka; Atmel; 8051; AT89S52; multiplexer; demultiplexer; logické funkce; kombinační logické obvody; sekvenční logcké obvody; kombinační logické funkce; sekvenční logické funkce; assembler; LOGIC; teaching instrument; Atmel; 8051; AT89S52; multiplexer; demultiplexer; logical functions; combinational logical circuits; sequential logical circuits; combinationals logical functions; sequential logical functions; assembler

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pučegl, P. (2019). Návrh a realizace učební pomůcky „LOGIK“: Design and realization of teaching instrument. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/25190

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pučegl, Pavel. “Návrh a realizace učební pomůcky „LOGIK“: Design and realization of teaching instrument.” 2019. Thesis, Brno University of Technology. Accessed August 06, 2020. http://hdl.handle.net/11012/25190.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pučegl, Pavel. “Návrh a realizace učební pomůcky „LOGIK“: Design and realization of teaching instrument.” 2019. Web. 06 Aug 2020.

Vancouver:

Pučegl P. Návrh a realizace učební pomůcky „LOGIK“: Design and realization of teaching instrument. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/11012/25190.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pučegl P. Návrh a realizace učební pomůcky „LOGIK“: Design and realization of teaching instrument. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/25190

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

15. Suzana Ribas de Almeida. Implementation of supervisory control in PLCs using high-level language.

Degree: 2012, Universidade do Estado de Santa Catarina

 Hoje em dia a competitividade entre as empresas está cada vez maior. Em um sistema de produção, a eficácia, a velocidade e a flexibilidade são… (more)

Subjects/Keywords: Controlador lógico programável (CLP); Abordagem modular local; Teoria de controle supevisório; Sequential Function Charts (SFC); Ladder Diagra; Structured Text; AUTOMACAO ELETRONICA DE PROCESSOS ELETRICOS E INDUSTRIAIS; Discrete events systems; Programmable logic controller (PLC); Local modular; Approach; Supervisory control theory; Sequential function charts (SFC); Ladder diagram; Structured text; Sistemas a eventos discretos

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Almeida, S. R. d. (2012). Implementation of supervisory control in PLCs using high-level language. (Thesis). Universidade do Estado de Santa Catarina. Retrieved from http://www.tede.udesc.br/tde_busca/arquivo.php?codArquivo=2976

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Almeida, Suzana Ribas de. “Implementation of supervisory control in PLCs using high-level language.” 2012. Thesis, Universidade do Estado de Santa Catarina. Accessed August 06, 2020. http://www.tede.udesc.br/tde_busca/arquivo.php?codArquivo=2976.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Almeida, Suzana Ribas de. “Implementation of supervisory control in PLCs using high-level language.” 2012. Web. 06 Aug 2020.

Vancouver:

Almeida SRd. Implementation of supervisory control in PLCs using high-level language. [Internet] [Thesis]. Universidade do Estado de Santa Catarina; 2012. [cited 2020 Aug 06]. Available from: http://www.tede.udesc.br/tde_busca/arquivo.php?codArquivo=2976.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Almeida SRd. Implementation of supervisory control in PLCs using high-level language. [Thesis]. Universidade do Estado de Santa Catarina; 2012. Available from: http://www.tede.udesc.br/tde_busca/arquivo.php?codArquivo=2976

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

16. Waldecir Pereira Junior. Mineração de padrões temporais híbridos especificados na lógica temporal de intervalos.

Degree: 2007, Federal University of Uberlândia

Discovering frequent patterns in databases is an important problem for knowledge discovery and its importance is justified by the diversity of areas where it can… (more)

Subjects/Keywords: CIENCIA DA COMPUTACAO; Banco de dados; Mineração de dados (Computação); Mineração baseada em restrições e padrões seqüenciais; Mineração de dados temporais; Lógica temporal de intervalos; Constraint-based mining and sequential patterns; Temporal data mining; Interval temporal logic

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Junior, W. P. (2007). Mineração de padrões temporais híbridos especificados na lógica temporal de intervalos. (Thesis). Federal University of Uberlândia. Retrieved from http://www.bdtd.ufu.br//tde_busca/arquivo.php?codArquivo=1546

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Junior, Waldecir Pereira. “Mineração de padrões temporais híbridos especificados na lógica temporal de intervalos.” 2007. Thesis, Federal University of Uberlândia. Accessed August 06, 2020. http://www.bdtd.ufu.br//tde_busca/arquivo.php?codArquivo=1546.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Junior, Waldecir Pereira. “Mineração de padrões temporais híbridos especificados na lógica temporal de intervalos.” 2007. Web. 06 Aug 2020.

Vancouver:

Junior WP. Mineração de padrões temporais híbridos especificados na lógica temporal de intervalos. [Internet] [Thesis]. Federal University of Uberlândia; 2007. [cited 2020 Aug 06]. Available from: http://www.bdtd.ufu.br//tde_busca/arquivo.php?codArquivo=1546.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Junior WP. Mineração de padrões temporais híbridos especificados na lógica temporal de intervalos. [Thesis]. Federal University of Uberlândia; 2007. Available from: http://www.bdtd.ufu.br//tde_busca/arquivo.php?codArquivo=1546

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

17. Sid-Amar, Ismahane. Autour de la décision qualitative en théorie des possibilités : On the qualitative decision in a possibility theory framework.

Degree: Docteur es, Informatique, 2015, Artois; Université des sciences et de la technologie Houari Boumediene (Alger)

Dans de nombreuses applications réelles, nous sommes souvent confrontés à des problèmes de décision: de choisir des actions et de renoncer à d'autres. Les problèmes… (more)

Subjects/Keywords: Théorie de la décision; Théorie des possibilités; Logique possibiliste; Réseaux possibilistes; Arbres de jonctions; Diagrammes d'influence; Décisions séquentielles; Decision theory; Possibilisty theory; Possibilistic logic; Possibilistic networks; Junction trees; Influence diagrams; Sequential decisions; 006.3

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sid-Amar, I. (2015). Autour de la décision qualitative en théorie des possibilités : On the qualitative decision in a possibility theory framework. (Doctoral Dissertation). Artois; Université des sciences et de la technologie Houari Boumediene (Alger). Retrieved from http://www.theses.fr/2015ARTO0403

Chicago Manual of Style (16th Edition):

Sid-Amar, Ismahane. “Autour de la décision qualitative en théorie des possibilités : On the qualitative decision in a possibility theory framework.” 2015. Doctoral Dissertation, Artois; Université des sciences et de la technologie Houari Boumediene (Alger). Accessed August 06, 2020. http://www.theses.fr/2015ARTO0403.

MLA Handbook (7th Edition):

Sid-Amar, Ismahane. “Autour de la décision qualitative en théorie des possibilités : On the qualitative decision in a possibility theory framework.” 2015. Web. 06 Aug 2020.

Vancouver:

Sid-Amar I. Autour de la décision qualitative en théorie des possibilités : On the qualitative decision in a possibility theory framework. [Internet] [Doctoral dissertation]. Artois; Université des sciences et de la technologie Houari Boumediene (Alger); 2015. [cited 2020 Aug 06]. Available from: http://www.theses.fr/2015ARTO0403.

Council of Science Editors:

Sid-Amar I. Autour de la décision qualitative en théorie des possibilités : On the qualitative decision in a possibility theory framework. [Doctoral Dissertation]. Artois; Université des sciences et de la technologie Houari Boumediene (Alger); 2015. Available from: http://www.theses.fr/2015ARTO0403

18. Yuan, Zeying. Sequential Equivalence Checking of Circuits with Different State Encodings by Pruning Simulation-based Multi-Node Invariants.

Degree: MS, Electrical and Computer Engineering, 2015, Virginia Tech

 Verification is an important step for Integrated Circuit (IC) design. In fact, literature has reported that up to 70% of the design effort is spent… (more)

Subjects/Keywords: Sequential Equivalence Checking(SEC); Multi-node Inductive Invariants; Constrained Logic Synthesis

…2.1.3 Sequential Equivalence Checking A sequential circuit is a digital logic design whose… …logic with state information, which means that we could treat every sequential circuit as two… …parts, combination logic and memory part. Fig. 2.3 shows a view of a sequential circuit. Fig… …2.3 Sequential Design A sequential logic can be defined as: (S, S0, I, O, δ, λ)… …synthesize combinational logic in varying ways. Sequential Equivalence Checking (SEC) is… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yuan, Z. (2015). Sequential Equivalence Checking of Circuits with Different State Encodings by Pruning Simulation-based Multi-Node Invariants. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/56693

Chicago Manual of Style (16th Edition):

Yuan, Zeying. “Sequential Equivalence Checking of Circuits with Different State Encodings by Pruning Simulation-based Multi-Node Invariants.” 2015. Masters Thesis, Virginia Tech. Accessed August 06, 2020. http://hdl.handle.net/10919/56693.

MLA Handbook (7th Edition):

Yuan, Zeying. “Sequential Equivalence Checking of Circuits with Different State Encodings by Pruning Simulation-based Multi-Node Invariants.” 2015. Web. 06 Aug 2020.

Vancouver:

Yuan Z. Sequential Equivalence Checking of Circuits with Different State Encodings by Pruning Simulation-based Multi-Node Invariants. [Internet] [Masters thesis]. Virginia Tech; 2015. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/10919/56693.

Council of Science Editors:

Yuan Z. Sequential Equivalence Checking of Circuits with Different State Encodings by Pruning Simulation-based Multi-Node Invariants. [Masters Thesis]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/56693


University of Oxford

19. Palikareva, Hristina. Techniques and tools for the verification of concurrent systems.

Degree: PhD, 2012, University of Oxford

 Model checking is an automatic formal verification technique for establishing correctness of systems. It has been widely used in industry for analysing and verifying complex… (more)

Subjects/Keywords: 004.35; Theory and automated verification; Communicating Sequential Processing (CSP); Program development and tools; Mathematical logic and foundations; automated verification; model checking; concurrency; process algebra; symbolic techniques; static analysis; livelock; abstraction; tools

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Palikareva, H. (2012). Techniques and tools for the verification of concurrent systems. (Doctoral Dissertation). University of Oxford. Retrieved from http://ora.ox.ac.uk/objects/uuid:fc2028e1-2a45-459a-afdd-70001893f3d8 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.581031

Chicago Manual of Style (16th Edition):

Palikareva, Hristina. “Techniques and tools for the verification of concurrent systems.” 2012. Doctoral Dissertation, University of Oxford. Accessed August 06, 2020. http://ora.ox.ac.uk/objects/uuid:fc2028e1-2a45-459a-afdd-70001893f3d8 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.581031.

MLA Handbook (7th Edition):

Palikareva, Hristina. “Techniques and tools for the verification of concurrent systems.” 2012. Web. 06 Aug 2020.

Vancouver:

Palikareva H. Techniques and tools for the verification of concurrent systems. [Internet] [Doctoral dissertation]. University of Oxford; 2012. [cited 2020 Aug 06]. Available from: http://ora.ox.ac.uk/objects/uuid:fc2028e1-2a45-459a-afdd-70001893f3d8 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.581031.

Council of Science Editors:

Palikareva H. Techniques and tools for the verification of concurrent systems. [Doctoral Dissertation]. University of Oxford; 2012. Available from: http://ora.ox.ac.uk/objects/uuid:fc2028e1-2a45-459a-afdd-70001893f3d8 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.581031


University of Southern California

20. Kazemzadeh, Abe. Natural language description of emotion.

Degree: PhD, Computer Science, 2013, University of Southern California

 This dissertation studies how people describe emotions with language and how computers can simulate this descriptive behavior. Although many non-human animals can express their current… (more)

Subjects/Keywords: natural language processing; emotions; definite descriptions; dialog systems; intersubjectivity; sequential Bayesian update; Socratic epistemology; crowd-sourcing; dialog agent; EMO20Q; question-asking; fuzzy logic; interval type-2 fuzzy sets; human-computer interaction

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kazemzadeh, A. (2013). Natural language description of emotion. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/298137/rec/4339

Chicago Manual of Style (16th Edition):

Kazemzadeh, Abe. “Natural language description of emotion.” 2013. Doctoral Dissertation, University of Southern California. Accessed August 06, 2020. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/298137/rec/4339.

MLA Handbook (7th Edition):

Kazemzadeh, Abe. “Natural language description of emotion.” 2013. Web. 06 Aug 2020.

Vancouver:

Kazemzadeh A. Natural language description of emotion. [Internet] [Doctoral dissertation]. University of Southern California; 2013. [cited 2020 Aug 06]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/298137/rec/4339.

Council of Science Editors:

Kazemzadeh A. Natural language description of emotion. [Doctoral Dissertation]. University of Southern California; 2013. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/298137/rec/4339


Vrije Universiteit Amsterdam

21. Hansen, H.H. Coalgebraic Modelling : Applications in Automata theory and Modal logic .

Degree: 2009, Vrije Universiteit Amsterdam

Subjects/Keywords: Coalgebraic modelling and synthesis of sequential machines. Coalgebraic modal logic and basic model theory for neighbourhood-like structures; coalgebra; automata; bitstream function; synthesis; subsequential transducer; bisimilarity; neighbourhood semantics; classical modal logic

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hansen, H. H. (2009). Coalgebraic Modelling : Applications in Automata theory and Modal logic . (Doctoral Dissertation). Vrije Universiteit Amsterdam. Retrieved from http://hdl.handle.net/1871/13247

Chicago Manual of Style (16th Edition):

Hansen, H H. “Coalgebraic Modelling : Applications in Automata theory and Modal logic .” 2009. Doctoral Dissertation, Vrije Universiteit Amsterdam. Accessed August 06, 2020. http://hdl.handle.net/1871/13247.

MLA Handbook (7th Edition):

Hansen, H H. “Coalgebraic Modelling : Applications in Automata theory and Modal logic .” 2009. Web. 06 Aug 2020.

Vancouver:

Hansen HH. Coalgebraic Modelling : Applications in Automata theory and Modal logic . [Internet] [Doctoral dissertation]. Vrije Universiteit Amsterdam; 2009. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/1871/13247.

Council of Science Editors:

Hansen HH. Coalgebraic Modelling : Applications in Automata theory and Modal logic . [Doctoral Dissertation]. Vrije Universiteit Amsterdam; 2009. Available from: http://hdl.handle.net/1871/13247


Virginia Commonwealth University

22. Ahmed, Anwar. COST AND ACCURACY COMPARISONS IN MEDICAL TESTING USING SEQUENTIAL TESTING STRATEGIES.

Degree: PhD, Biostatistics, 2010, Virginia Commonwealth University

 The practice of sequential testing is followed by the evaluation of accuracy, but often not by the evaluation of cost. This research described and compared… (more)

Subjects/Keywords: Sequential testing; BN; BP; BE; ROC curve; Pima Indians; cost of testing; logic rules; sensitivity; specificity; optimal operating point; OOP; Biostatistics; Physical Sciences and Mathematics; Statistics and Probability

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ahmed, A. (2010). COST AND ACCURACY COMPARISONS IN MEDICAL TESTING USING SEQUENTIAL TESTING STRATEGIES. (Doctoral Dissertation). Virginia Commonwealth University. Retrieved from https://doi.org/10.25772/KFWE-0H08 ; https://scholarscompass.vcu.edu/etd/103

Chicago Manual of Style (16th Edition):

Ahmed, Anwar. “COST AND ACCURACY COMPARISONS IN MEDICAL TESTING USING SEQUENTIAL TESTING STRATEGIES.” 2010. Doctoral Dissertation, Virginia Commonwealth University. Accessed August 06, 2020. https://doi.org/10.25772/KFWE-0H08 ; https://scholarscompass.vcu.edu/etd/103.

MLA Handbook (7th Edition):

Ahmed, Anwar. “COST AND ACCURACY COMPARISONS IN MEDICAL TESTING USING SEQUENTIAL TESTING STRATEGIES.” 2010. Web. 06 Aug 2020.

Vancouver:

Ahmed A. COST AND ACCURACY COMPARISONS IN MEDICAL TESTING USING SEQUENTIAL TESTING STRATEGIES. [Internet] [Doctoral dissertation]. Virginia Commonwealth University; 2010. [cited 2020 Aug 06]. Available from: https://doi.org/10.25772/KFWE-0H08 ; https://scholarscompass.vcu.edu/etd/103.

Council of Science Editors:

Ahmed A. COST AND ACCURACY COMPARISONS IN MEDICAL TESTING USING SEQUENTIAL TESTING STRATEGIES. [Doctoral Dissertation]. Virginia Commonwealth University; 2010. Available from: https://doi.org/10.25772/KFWE-0H08 ; https://scholarscompass.vcu.edu/etd/103

23. Herman, Geoffrey L. The development of a digital logic concept inventory.

Degree: PhD, 1200, 2011, University of Illinois – Urbana-Champaign

 Instructors in electrical and computer engineering and in computer science have developed innovative methods to teach digital logic circuits. These methods attempt to increase student… (more)

Subjects/Keywords: digital logic; concept inventory; number representations; Boolean algebra; medium-scale integrated circuits; state; sequential circuits; combinational circuits; assessment; misconceptions; Delphi process

…CHAPTER 6 STUDENTS’ MISCONCEPTIONS ABOUT BOOLEAN LOGIC… …research on students’ difficulties with logic . . 6.2 Interview Questions… …MISCONCEPTIONS ABOUT STATE AND SEQUENTIAL CIRCUITS . . . . . . . . . . . . . . . . . 8.1 Background… …166 167 168 168 168 CHAPTER 9 CREATING AND VALIDATING THE DIGITAL LOGIC CONCEPT INVENTORY… …for digital logic . . . . . . . . . . . . . 10.5 New Assessment Tools… 

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APA (6th Edition):

Herman, G. L. (2011). The development of a digital logic concept inventory. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/24134

Chicago Manual of Style (16th Edition):

Herman, Geoffrey L. “The development of a digital logic concept inventory.” 2011. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed August 06, 2020. http://hdl.handle.net/2142/24134.

MLA Handbook (7th Edition):

Herman, Geoffrey L. “The development of a digital logic concept inventory.” 2011. Web. 06 Aug 2020.

Vancouver:

Herman GL. The development of a digital logic concept inventory. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2011. [cited 2020 Aug 06]. Available from: http://hdl.handle.net/2142/24134.

Council of Science Editors:

Herman GL. The development of a digital logic concept inventory. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/24134

.