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You searched for subject:(rollback recovery). Showing records 1 – 11 of 11 total matches.

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1. Schramm, Peter. Fehlertolerante Integration limitierter Geräte in SOA unter Verwendung von Geräte-Proxies.

Degree: 2008, Technische Universität Dortmund

 Typische Ubiquitous-Computing-Umgebungen erfordern den Einsatz von Middleware, die in der Regel einen hohen Ressourcenbedarf an die teilnehmenden Geräte stellt. Jedoch befinden sich gerade in Ubiquitous-Computing-Umgebungen… (more)

Subjects/Keywords: Limitierte Geräte; Middleware; Migration; Proxies; Rollback-Recovery; Sindrion; SOA; Ubiquitous Computing; 600

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Schramm, P. (2008). Fehlertolerante Integration limitierter Geräte in SOA unter Verwendung von Geräte-Proxies. (Thesis). Technische Universität Dortmund. Retrieved from http://hdl.handle.net/2003/25000

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Schramm, Peter. “Fehlertolerante Integration limitierter Geräte in SOA unter Verwendung von Geräte-Proxies.” 2008. Thesis, Technische Universität Dortmund. Accessed April 13, 2021. http://hdl.handle.net/2003/25000.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Schramm, Peter. “Fehlertolerante Integration limitierter Geräte in SOA unter Verwendung von Geräte-Proxies.” 2008. Web. 13 Apr 2021.

Vancouver:

Schramm P. Fehlertolerante Integration limitierter Geräte in SOA unter Verwendung von Geräte-Proxies. [Internet] [Thesis]. Technische Universität Dortmund; 2008. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2003/25000.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Schramm P. Fehlertolerante Integration limitierter Geräte in SOA unter Verwendung von Geräte-Proxies. [Thesis]. Technische Universität Dortmund; 2008. Available from: http://hdl.handle.net/2003/25000

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

2. Sanz-Marco, Vicent. Fault tolerance for stream programs on parallel platforms.

Degree: PhD, 2015, University of Hertfordshire

 A distributed system is defined as a collection of autonomous computers connected by a network, and with the appropriate distributed software for the system to… (more)

Subjects/Keywords: 004.2; fault tolerance; S-Net; Leader Election; Checkpoint restore; log-based rollback recovery; distributed systems; compilers; streaming networks; shared memory systems

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APA (6th Edition):

Sanz-Marco, V. (2015). Fault tolerance for stream programs on parallel platforms. (Doctoral Dissertation). University of Hertfordshire. Retrieved from http://hdl.handle.net/2299/17110

Chicago Manual of Style (16th Edition):

Sanz-Marco, Vicent. “Fault tolerance for stream programs on parallel platforms.” 2015. Doctoral Dissertation, University of Hertfordshire. Accessed April 13, 2021. http://hdl.handle.net/2299/17110.

MLA Handbook (7th Edition):

Sanz-Marco, Vicent. “Fault tolerance for stream programs on parallel platforms.” 2015. Web. 13 Apr 2021.

Vancouver:

Sanz-Marco V. Fault tolerance for stream programs on parallel platforms. [Internet] [Doctoral dissertation]. University of Hertfordshire; 2015. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2299/17110.

Council of Science Editors:

Sanz-Marco V. Fault tolerance for stream programs on parallel platforms. [Doctoral Dissertation]. University of Hertfordshire; 2015. Available from: http://hdl.handle.net/2299/17110


Virginia Tech

3. Jeyakumar, Ashwin Raju. Metamori: A library for Incremental File Checkpointing.

Degree: MS, Computer Science, 2004, Virginia Tech

 The advent of cluster computing has resulted in a thrust towards providing software mechanisms for reliability on clusters. The prevalent model for such mechanisms is… (more)

Subjects/Keywords: Fault-tolerance; File Checkpointing; Checkpointing; Rollback-Recovery

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APA (6th Edition):

Jeyakumar, A. R. (2004). Metamori: A library for Incremental File Checkpointing. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/9969

Chicago Manual of Style (16th Edition):

Jeyakumar, Ashwin Raju. “Metamori: A library for Incremental File Checkpointing.” 2004. Masters Thesis, Virginia Tech. Accessed April 13, 2021. http://hdl.handle.net/10919/9969.

MLA Handbook (7th Edition):

Jeyakumar, Ashwin Raju. “Metamori: A library for Incremental File Checkpointing.” 2004. Web. 13 Apr 2021.

Vancouver:

Jeyakumar AR. Metamori: A library for Incremental File Checkpointing. [Internet] [Masters thesis]. Virginia Tech; 2004. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/10919/9969.

Council of Science Editors:

Jeyakumar AR. Metamori: A library for Incremental File Checkpointing. [Masters Thesis]. Virginia Tech; 2004. Available from: http://hdl.handle.net/10919/9969

4. Schramm, Peter. Fehlertolerante Integration limitierter Geräte in SOA unter Verwendung von Geräte-Proxies.

Degree: 2008, Technische Universität Dortmund

 Typische Ubiquitous-Computing-Umgebungen erfordern den Einsatz von Middleware, die in der Regel einen hohen Ressourcenbedarf an die teilnehmenden Geräte stellt. Jedoch befinden sich gerade in Ubiquitous-Computing-Umgebungen… (more)

Subjects/Keywords: Ubiquitous Computing; Middleware; SOA; Limitierte Geräte; Proxies; Sindrion; Migration; Rollback-Recovery; 600

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Schramm, P. (2008). Fehlertolerante Integration limitierter Geräte in SOA unter Verwendung von Geräte-Proxies. (Doctoral Dissertation). Technische Universität Dortmund. Retrieved from http://dx.doi.org/10.17877/DE290R-8417

Chicago Manual of Style (16th Edition):

Schramm, Peter. “Fehlertolerante Integration limitierter Geräte in SOA unter Verwendung von Geräte-Proxies.” 2008. Doctoral Dissertation, Technische Universität Dortmund. Accessed April 13, 2021. http://dx.doi.org/10.17877/DE290R-8417.

MLA Handbook (7th Edition):

Schramm, Peter. “Fehlertolerante Integration limitierter Geräte in SOA unter Verwendung von Geräte-Proxies.” 2008. Web. 13 Apr 2021.

Vancouver:

Schramm P. Fehlertolerante Integration limitierter Geräte in SOA unter Verwendung von Geräte-Proxies. [Internet] [Doctoral dissertation]. Technische Universität Dortmund; 2008. [cited 2021 Apr 13]. Available from: http://dx.doi.org/10.17877/DE290R-8417.

Council of Science Editors:

Schramm P. Fehlertolerante Integration limitierter Geräte in SOA unter Verwendung von Geräte-Proxies. [Doctoral Dissertation]. Technische Universität Dortmund; 2008. Available from: http://dx.doi.org/10.17877/DE290R-8417

5. Ferreira, Ronaldo Rodrigues. The transactional HW/SW stack for fault tolerant embedded computing.

Degree: 2015, Brazil

O desafio de implementar tolerância a falhas em sistemas embarcados advém das restrições físicas de ocupação de área, dissipação de potência e consumo de energia… (more)

Subjects/Keywords: Microeletrônica; Sistemas embarcados; Tolerancia : Falhas; Compiler design; Coverage; Error detection; Error recovery; Fault injection; Hardening by design; Latency; LLVM; Modular redundancy; Register file; Rollback; Single event effects; Soft error

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APA (6th Edition):

Ferreira, R. R. (2015). The transactional HW/SW stack for fault tolerant embedded computing. (Doctoral Dissertation). Brazil. Retrieved from http://hdl.handle.net/10183/114607

Chicago Manual of Style (16th Edition):

Ferreira, Ronaldo Rodrigues. “The transactional HW/SW stack for fault tolerant embedded computing.” 2015. Doctoral Dissertation, Brazil. Accessed April 13, 2021. http://hdl.handle.net/10183/114607.

MLA Handbook (7th Edition):

Ferreira, Ronaldo Rodrigues. “The transactional HW/SW stack for fault tolerant embedded computing.” 2015. Web. 13 Apr 2021.

Vancouver:

Ferreira RR. The transactional HW/SW stack for fault tolerant embedded computing. [Internet] [Doctoral dissertation]. Brazil; 2015. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/10183/114607.

Council of Science Editors:

Ferreira RR. The transactional HW/SW stack for fault tolerant embedded computing. [Doctoral Dissertation]. Brazil; 2015. Available from: http://hdl.handle.net/10183/114607

6. Väyrynen, Mikael. Fault-Tolerant Average Execution Time Optimization for General-Purpose Multi-Processor System-On-Chips.

Degree: Computer and Information Science, 2009, Linköping UniversityLinköping UniversityLinköping University

  Fault tolerance is due to the semiconductor technology development important, not only for safety-critical systems but also for general-purpose (non-safety critical) systems. However, instead… (more)

Subjects/Keywords: Fault tolerance; Execution time optimization; Rollback recovery with checkpointing; Active replication; MPSoC; Computer Sciences; Datavetenskap (datalogi)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Väyrynen, M. (2009). Fault-Tolerant Average Execution Time Optimization for General-Purpose Multi-Processor System-On-Chips. (Thesis). Linköping UniversityLinköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-17705

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Väyrynen, Mikael. “Fault-Tolerant Average Execution Time Optimization for General-Purpose Multi-Processor System-On-Chips.” 2009. Thesis, Linköping UniversityLinköping UniversityLinköping University. Accessed April 13, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-17705.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Väyrynen, Mikael. “Fault-Tolerant Average Execution Time Optimization for General-Purpose Multi-Processor System-On-Chips.” 2009. Web. 13 Apr 2021.

Vancouver:

Väyrynen M. Fault-Tolerant Average Execution Time Optimization for General-Purpose Multi-Processor System-On-Chips. [Internet] [Thesis]. Linköping UniversityLinköping UniversityLinköping University; 2009. [cited 2021 Apr 13]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-17705.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Väyrynen M. Fault-Tolerant Average Execution Time Optimization for General-Purpose Multi-Processor System-On-Chips. [Thesis]. Linköping UniversityLinköping UniversityLinköping University; 2009. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-17705

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

7. Silva, Hélio Antônio Miranda da. Implementação de um mecanismo de recuperação por retorno para a ferramenta ourgrid.

Degree: 2007, Brazil

A computação em grid (ou computação em grade) emergiu como uma área de pesquisa importante por permitir o compartilhamento de recursos computacionais geograficamente distribuídos entre… (more)

Subjects/Keywords: Computação móvel; Tolerancia : Falhas; Processamento distribuido; Grid computation; Fault tolerance; Rollback-recovery; Checkpointing; OurGrid

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Silva, H. A. M. d. (2007). Implementação de um mecanismo de recuperação por retorno para a ferramenta ourgrid. (Masters Thesis). Brazil. Retrieved from http://hdl.handle.net/10183/11517

Chicago Manual of Style (16th Edition):

Silva, Hélio Antônio Miranda da. “Implementação de um mecanismo de recuperação por retorno para a ferramenta ourgrid.” 2007. Masters Thesis, Brazil. Accessed April 13, 2021. http://hdl.handle.net/10183/11517.

MLA Handbook (7th Edition):

Silva, Hélio Antônio Miranda da. “Implementação de um mecanismo de recuperação por retorno para a ferramenta ourgrid.” 2007. Web. 13 Apr 2021.

Vancouver:

Silva HAMd. Implementação de um mecanismo de recuperação por retorno para a ferramenta ourgrid. [Internet] [Masters thesis]. Brazil; 2007. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/10183/11517.

Council of Science Editors:

Silva HAMd. Implementação de um mecanismo de recuperação por retorno para a ferramenta ourgrid. [Masters Thesis]. Brazil; 2007. Available from: http://hdl.handle.net/10183/11517

8. Sjölinder, Max. Preventing data loss using rollback-recovery : A proof-of-concept study at Bolagsverket.

Degree: Information and Communication systems, 2013, Mid Sweden University

  This thesis investigates two alternative approaches, referred to as automatic- and semi-automatic replay, which can be used to prevent data loss due to a… (more)

Subjects/Keywords: Fault tolerance; Rollback-recovery; Data loss; Database; Bolagsverket; Computer and Information Sciences; Data- och informationsvetenskap; Software Engineering; Programvaruteknik; Computer Engineering; Datorteknik

…Preventing data loss using rollback-recovery - A proof-ofconcept study at Bolagsverket… …using rollback-recovery - A proof-ofconcept study at Bolagsverket Max Sjölinder Terminology… …3R Rewind, Repair and Replay x Preventing data loss using rollback-recovery - A proof… …Preventing data loss using rollback-recovery - A proof-ofconcept study at Bolagsverket Max… …not within the 4 Preventing data loss using rollback-recovery - A proof-ofconcept study at… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sjölinder, M. (2013). Preventing data loss using rollback-recovery : A proof-of-concept study at Bolagsverket. (Thesis). Mid Sweden University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-20901

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sjölinder, Max. “Preventing data loss using rollback-recovery : A proof-of-concept study at Bolagsverket.” 2013. Thesis, Mid Sweden University. Accessed April 13, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-20901.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sjölinder, Max. “Preventing data loss using rollback-recovery : A proof-of-concept study at Bolagsverket.” 2013. Web. 13 Apr 2021.

Vancouver:

Sjölinder M. Preventing data loss using rollback-recovery : A proof-of-concept study at Bolagsverket. [Internet] [Thesis]. Mid Sweden University; 2013. [cited 2021 Apr 13]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-20901.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sjölinder M. Preventing data loss using rollback-recovery : A proof-of-concept study at Bolagsverket. [Thesis]. Mid Sweden University; 2013. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-20901

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

9. Vissa, Pranay. Toward high-level synthesis of reliable circuits through low-cost modulo shadow datapaths.

Degree: MS, Electrical & Computer Engr, 2015, University of Illinois – Urbana-Champaign

 With transistor dimensions shrinking to the atomic scale, a plethora of new reliability problems presents a barrier to continued Moore’s law scaling. Traditional modular redundancy… (more)

Subjects/Keywords: high-level synthesis; automation; error detection; scheduling; binding; optimization; pipelining; modulo arithmetic; logic optimization; state machine; datapath; shadow logic; low cost; high performance; electrical faults; Aliasing; stuck-at faults; soft errors; timing errors; checkpointing; rollback recovery

…synthesis. We also explored a rollback recovery method for soft errors with an additional area… …allocated. 4.6 Recovery To enable error recovery for soft errors, we use a checkpoint and… …recovery register transformation, illustrated in Figure 4.3. For each state and datapath register… …error recovery. Error! Checkpoint Corrupted! Detected Checkpoint Our error recovery… …cycles, on average, that we would rollback on detection of an error. Since the rollback length… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vissa, P. (2015). Toward high-level synthesis of reliable circuits through low-cost modulo shadow datapaths. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/78571

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vissa, Pranay. “Toward high-level synthesis of reliable circuits through low-cost modulo shadow datapaths.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed April 13, 2021. http://hdl.handle.net/2142/78571.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vissa, Pranay. “Toward high-level synthesis of reliable circuits through low-cost modulo shadow datapaths.” 2015. Web. 13 Apr 2021.

Vancouver:

Vissa P. Toward high-level synthesis of reliable circuits through low-cost modulo shadow datapaths. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2142/78571.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vissa P. Toward high-level synthesis of reliable circuits through low-cost modulo shadow datapaths. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/78571

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

10. Campbell, Keith A. Low-cost error detection through high-level synthesis.

Degree: MS, Electrical & Computer Engineering, 2015, University of Illinois – Urbana-Champaign

 System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling and complexity has resulted in a… (more)

Subjects/Keywords: High-level synthesis; Automation; error detection; scheduling; binding; compiler transformation; compiler optimization; pipelining; modulo arithmetic; logic optimization; state machine; datapath, control logic; shadow logic; low cost; high performance; electrical bugs; Aliasing; stuck-at faults; soft errors; timing errors; checkpointing; rollback; recovery; post-silicon validation; Accelerators; system on a chip; signature generation; execution signatures; execution hashing; logic bugs; nondeterministic bugs; masked errors; circuit reliability; hot spots; wear out; silent data corruption; observability; detection latency; mixed datapath; diversity; checkpoint corruption; error injection; error removal; Quick Error Detection (QED); Hybrid Quick Error Detection (H-QED); hybrid hardware/software; execution tracing; address conversion; undefined behavior; High-Level Synthesis (HLS) engine bugs; detection coverage

…focus on quick error recovery) to minimize area/performance costs and intrusiveness… …reducers allocated. 3.1.3 Recovery To enable error recovery for soft errors, we use a checkpoint… …and recovery register transformation, illustrated… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Campbell, K. A. (2015). Low-cost error detection through high-level synthesis. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/89068

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Campbell, Keith A. “Low-cost error detection through high-level synthesis.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed April 13, 2021. http://hdl.handle.net/2142/89068.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Campbell, Keith A. “Low-cost error detection through high-level synthesis.” 2015. Web. 13 Apr 2021.

Vancouver:

Campbell KA. Low-cost error detection through high-level synthesis. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2142/89068.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Campbell KA. Low-cost error detection through high-level synthesis. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/89068

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

11. Campbell, Keith A. Robust and reliable hardware accelerator design through high-level synthesis.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling-driven complexity has resulted in a variety… (more)

Subjects/Keywords: High-level synthesis (HLS); Automation; Error detection; Scheduling; Binding; Compiler transformation; Compiler optimization; Pipelining; Modulo arithmetic; Modulo-3; Logic optimization; State machine; Datapath; Control logic; Shadow datapath; Modulo datapath; Low cost; High performance; Electrical bug; Aliasing; Stuck-at fault; Soft error; Timing error; Checkpointing; Rollback; Recovery; Pre-silicon validation; Post-silicon validation; Pre-silicon debug; Post-silicon debug; Accelerator; System on a chip; Signature generation; Execution signature; Execution hash; Logic bug; Nondeterministic bug; Masked error; Circuit reliability; Hot spot; Wear out; Silent data corruption; Observability; Detection latency; Mixed datapath; Diversity; Checkpoint corruption; Error injection; Error removal; Quick Error Detection (QED); Hybrid Quick Error Detection (H-QED); Instrumentation; Hybrid co-simulation; Hardware/software; Integration testing; Hybrid tracing; Hybrid hashing; Source-code localization; Software debugging tool; Valgrind; Clang sanitizer; Clang static analyzer; Cppcheck; Root cause analysis; Execution tracing; Realtime error detection; Simulation trigger; Nonintrusive; Address conversion; Undefined behavior; High-level synthesis (HLS) bug; Detection coverage; Gate-level architecture; Mersenne modulus; Full adder; Half adder; Quarter adder; Wraparound; Modulo reducer; Modulo adder; Modulo multiplier; Modulo comparator; Cross-layer; Algorithm; Instruction; Architecture; Logic synthesis; Physical design; Algorithm-based fault tolerance (ABFT); Error detection by duplicated instructions (EDDI); Parity; Flip-flop hardening; Layout design through error-aware transistor positioning dual interlocked storage cell (LEAP-DICE); Cost-effective; Place-and-route; Field programmable gate array (FPGA) emulation; Application specific integrated circuit (ASIC); Field programmable gate array (FPGA); Energy; Area; Latency

…after a PSV run is acceptable vs. reliability techniques that focus on quick error recovery… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Campbell, K. A. (2017). Robust and reliable hardware accelerator design through high-level synthesis. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99294

Chicago Manual of Style (16th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 13, 2021. http://hdl.handle.net/2142/99294.

MLA Handbook (7th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Web. 13 Apr 2021.

Vancouver:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Apr 13]. Available from: http://hdl.handle.net/2142/99294.

Council of Science Editors:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99294

.