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You searched for subject:(reconfigurable). Showing records 1 – 30 of 775 total matches.

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1. Basterrechea, I. Reconfigurable Architecture:.

Degree: 2013, Delft University of Technology

 This research graduation project aims to explore the possibilities of reconfigurable architecture as a response to the issue of designing for the uncertainty. A keen… (more)

Subjects/Keywords: reconfigurable

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Basterrechea, I. (2013). Reconfigurable Architecture:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:8220a16c-8c8e-4ba7-91f3-18e39af22524

Chicago Manual of Style (16th Edition):

Basterrechea, I. “Reconfigurable Architecture:.” 2013. Masters Thesis, Delft University of Technology. Accessed April 20, 2019. http://resolver.tudelft.nl/uuid:8220a16c-8c8e-4ba7-91f3-18e39af22524.

MLA Handbook (7th Edition):

Basterrechea, I. “Reconfigurable Architecture:.” 2013. Web. 20 Apr 2019.

Vancouver:

Basterrechea I. Reconfigurable Architecture:. [Internet] [Masters thesis]. Delft University of Technology; 2013. [cited 2019 Apr 20]. Available from: http://resolver.tudelft.nl/uuid:8220a16c-8c8e-4ba7-91f3-18e39af22524.

Council of Science Editors:

Basterrechea I. Reconfigurable Architecture:. [Masters Thesis]. Delft University of Technology; 2013. Available from: http://resolver.tudelft.nl/uuid:8220a16c-8c8e-4ba7-91f3-18e39af22524


University of Cincinnati

2. CULLEY, ROBERT J. FDTD METHODS USING PARALLEL COMPUTATIONS AND HARDWARE OPTIMIZATION.

Degree: MS, Engineering : Computer Engineering, 2007, University of Cincinnati

 To achieve faster computation rates using cluster computers, reconfigurable resources are beginning to be utilized in computations. The Finite-Difference Time-Domain (FDTD) is a powerful method… (more)

Subjects/Keywords: FDTD; Reconfigurable Hardware

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APA (6th Edition):

CULLEY, R. J. (2007). FDTD METHODS USING PARALLEL COMPUTATIONS AND HARDWARE OPTIMIZATION. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1182524209

Chicago Manual of Style (16th Edition):

CULLEY, ROBERT J. “FDTD METHODS USING PARALLEL COMPUTATIONS AND HARDWARE OPTIMIZATION.” 2007. Masters Thesis, University of Cincinnati. Accessed April 20, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1182524209.

MLA Handbook (7th Edition):

CULLEY, ROBERT J. “FDTD METHODS USING PARALLEL COMPUTATIONS AND HARDWARE OPTIMIZATION.” 2007. Web. 20 Apr 2019.

Vancouver:

CULLEY RJ. FDTD METHODS USING PARALLEL COMPUTATIONS AND HARDWARE OPTIMIZATION. [Internet] [Masters thesis]. University of Cincinnati; 2007. [cited 2019 Apr 20]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1182524209.

Council of Science Editors:

CULLEY RJ. FDTD METHODS USING PARALLEL COMPUTATIONS AND HARDWARE OPTIMIZATION. [Masters Thesis]. University of Cincinnati; 2007. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1182524209

3. Jusoh Tajudin, Mohd Taufik. Study and design of reconfigurable antennas using plasma medium : Étude et conception d'antennes reconfigurables basées sur des matériaux plasma.

Degree: Docteur es, Traitement du signal et télécommunications, 2014, Rennes 1

Le milieu plasma correspond au 4ème état de la matière présentant une permittivité diélectrique complexe qui peut être exploitée pour les systèmes de communication. Sa… (more)

Subjects/Keywords: Antenne reconfigurable; Antenne à plasma; Antenne réflecteur; Antenne à plasma reconfigurable; Antenne réflecteur reconfigurable; Reconfigurable antenna; Plasma antenna; Reflector antenna; Reconfigurable plasma antenna; Reconfigurable reflector antenna

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APA (6th Edition):

Jusoh Tajudin, M. T. (2014). Study and design of reconfigurable antennas using plasma medium : Étude et conception d'antennes reconfigurables basées sur des matériaux plasma. (Doctoral Dissertation). Rennes 1. Retrieved from http://www.theses.fr/2014REN1S019

Chicago Manual of Style (16th Edition):

Jusoh Tajudin, Mohd Taufik. “Study and design of reconfigurable antennas using plasma medium : Étude et conception d'antennes reconfigurables basées sur des matériaux plasma.” 2014. Doctoral Dissertation, Rennes 1. Accessed April 20, 2019. http://www.theses.fr/2014REN1S019.

MLA Handbook (7th Edition):

Jusoh Tajudin, Mohd Taufik. “Study and design of reconfigurable antennas using plasma medium : Étude et conception d'antennes reconfigurables basées sur des matériaux plasma.” 2014. Web. 20 Apr 2019.

Vancouver:

Jusoh Tajudin MT. Study and design of reconfigurable antennas using plasma medium : Étude et conception d'antennes reconfigurables basées sur des matériaux plasma. [Internet] [Doctoral dissertation]. Rennes 1; 2014. [cited 2019 Apr 20]. Available from: http://www.theses.fr/2014REN1S019.

Council of Science Editors:

Jusoh Tajudin MT. Study and design of reconfigurable antennas using plasma medium : Étude et conception d'antennes reconfigurables basées sur des matériaux plasma. [Doctoral Dissertation]. Rennes 1; 2014. Available from: http://www.theses.fr/2014REN1S019


NSYSU

4. Yeh, Ta-li. Design of the Software/Hardware Codesign Platform-IRES.

Degree: Master, Electrical Engineering, 2008, NSYSU

 High-performance reconfigurable computing has demonstrated its potential to accelerate demanding computational applications. Thus, the current trend is towards combining the microprocessor with the power of… (more)

Subjects/Keywords: reconfigurable computing; embedded system

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APA (6th Edition):

Yeh, T. (2008). Design of the Software/Hardware Codesign Platform-IRES. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0820108-032534

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yeh, Ta-li. “Design of the Software/Hardware Codesign Platform-IRES.” 2008. Thesis, NSYSU. Accessed April 20, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0820108-032534.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yeh, Ta-li. “Design of the Software/Hardware Codesign Platform-IRES.” 2008. Web. 20 Apr 2019.

Vancouver:

Yeh T. Design of the Software/Hardware Codesign Platform-IRES. [Internet] [Thesis]. NSYSU; 2008. [cited 2019 Apr 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0820108-032534.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yeh T. Design of the Software/Hardware Codesign Platform-IRES. [Thesis]. NSYSU; 2008. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0820108-032534

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

5. Nakai, Nobuo. Reconfigurable 1-bit processor array with reduced wiring area : 配線リソースを考慮した再構成可能1bitプロセッサアレイ; ハイセン リソース オ コウリョ シタ サイコウセイ カノウ 1bit プロセッサ アレイ.

Degree: Nara Institute of Science and Technology / 奈良先端科学技術大学院大学

Subjects/Keywords: Reconfigurable Computing

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APA (6th Edition):

Nakai, N. (n.d.). Reconfigurable 1-bit processor array with reduced wiring area : 配線リソースを考慮した再構成可能1bitプロセッサアレイ; ハイセン リソース オ コウリョ シタ サイコウセイ カノウ 1bit プロセッサ アレイ. (Thesis). Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10061/1730

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nakai, Nobuo. “Reconfigurable 1-bit processor array with reduced wiring area : 配線リソースを考慮した再構成可能1bitプロセッサアレイ; ハイセン リソース オ コウリョ シタ サイコウセイ カノウ 1bit プロセッサ アレイ.” Thesis, Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Accessed April 20, 2019. http://hdl.handle.net/10061/1730.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nakai, Nobuo. “Reconfigurable 1-bit processor array with reduced wiring area : 配線リソースを考慮した再構成可能1bitプロセッサアレイ; ハイセン リソース オ コウリョ シタ サイコウセイ カノウ 1bit プロセッサ アレイ.” Web. 20 Apr 2019.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

Nakai N. Reconfigurable 1-bit processor array with reduced wiring area : 配線リソースを考慮した再構成可能1bitプロセッサアレイ; ハイセン リソース オ コウリョ シタ サイコウセイ カノウ 1bit プロセッサ アレイ. [Internet] [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; [cited 2019 Apr 20]. Available from: http://hdl.handle.net/10061/1730.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

Nakai N. Reconfigurable 1-bit processor array with reduced wiring area : 配線リソースを考慮した再構成可能1bitプロセッサアレイ; ハイセン リソース オ コウリョ シタ サイコウセイ カノウ 1bit プロセッサ アレイ. [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; Available from: http://hdl.handle.net/10061/1730

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.


Queens University

6. Wang, Min. Reconfigurable CMOS Mixers for Radio-Frequency Applications .

Degree: Electrical & Computer Engineering, 2010, Queens University

 This thesis focuses on the design of radio-frequency (RF) mixers, including a broadband downconverter mixer, an upconverter mixer and a downconverter mixer with high linearity.… (more)

Subjects/Keywords: Reconfigurable; Radio-Frequency; CMOS; Mixer

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APA (6th Edition):

Wang, M. (2010). Reconfigurable CMOS Mixers for Radio-Frequency Applications . (Thesis). Queens University. Retrieved from http://hdl.handle.net/1974/5712

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Min. “Reconfigurable CMOS Mixers for Radio-Frequency Applications .” 2010. Thesis, Queens University. Accessed April 20, 2019. http://hdl.handle.net/1974/5712.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Min. “Reconfigurable CMOS Mixers for Radio-Frequency Applications .” 2010. Web. 20 Apr 2019.

Vancouver:

Wang M. Reconfigurable CMOS Mixers for Radio-Frequency Applications . [Internet] [Thesis]. Queens University; 2010. [cited 2019 Apr 20]. Available from: http://hdl.handle.net/1974/5712.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang M. Reconfigurable CMOS Mixers for Radio-Frequency Applications . [Thesis]. Queens University; 2010. Available from: http://hdl.handle.net/1974/5712

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Edinburgh

7. Han, Wei. Multi-core architectures with coarse-grained dynamically reconfigurable processors for broadband wireless access technologies.

Degree: PhD, 2010, University of Edinburgh

 Broadband Wireless Access technologies have significant market potential, especially the WiMAX protocol which can deliver data rates of tens of Mbps. Strong demand for high… (more)

Subjects/Keywords: 621.382; multi-core; WiMAX; reconfigurable

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APA (6th Edition):

Han, W. (2010). Multi-core architectures with coarse-grained dynamically reconfigurable processors for broadband wireless access technologies. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/3812

Chicago Manual of Style (16th Edition):

Han, Wei. “Multi-core architectures with coarse-grained dynamically reconfigurable processors for broadband wireless access technologies.” 2010. Doctoral Dissertation, University of Edinburgh. Accessed April 20, 2019. http://hdl.handle.net/1842/3812.

MLA Handbook (7th Edition):

Han, Wei. “Multi-core architectures with coarse-grained dynamically reconfigurable processors for broadband wireless access technologies.” 2010. Web. 20 Apr 2019.

Vancouver:

Han W. Multi-core architectures with coarse-grained dynamically reconfigurable processors for broadband wireless access technologies. [Internet] [Doctoral dissertation]. University of Edinburgh; 2010. [cited 2019 Apr 20]. Available from: http://hdl.handle.net/1842/3812.

Council of Science Editors:

Han W. Multi-core architectures with coarse-grained dynamically reconfigurable processors for broadband wireless access technologies. [Doctoral Dissertation]. University of Edinburgh; 2010. Available from: http://hdl.handle.net/1842/3812


Baylor University

8. [No author]. Circuit modeling and optimization techniques for next-generation radar.

Degree: 2018, Baylor University

 Spectral emission requirements for radar systems are becoming increasingly strict. Future radar systems will require well-designed, reconfigurable circuitry to coexist with the myriads of wireless… (more)

Subjects/Keywords: Reconfigurable circuitry. Radar. Volterra series.

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APA (6th Edition):

author], [. (2018). Circuit modeling and optimization techniques for next-generation radar. (Thesis). Baylor University. Retrieved from http://hdl.handle.net/2104/10348

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

author], [No. “Circuit modeling and optimization techniques for next-generation radar. ” 2018. Thesis, Baylor University. Accessed April 20, 2019. http://hdl.handle.net/2104/10348.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

author], [No. “Circuit modeling and optimization techniques for next-generation radar. ” 2018. Web. 20 Apr 2019.

Vancouver:

author] [. Circuit modeling and optimization techniques for next-generation radar. [Internet] [Thesis]. Baylor University; 2018. [cited 2019 Apr 20]. Available from: http://hdl.handle.net/2104/10348.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

author] [. Circuit modeling and optimization techniques for next-generation radar. [Thesis]. Baylor University; 2018. Available from: http://hdl.handle.net/2104/10348

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

9. Chandrashekhar, Aarti. A fine-grained dataflow library for reconfigurable streaming accelerators.

Degree: MS, Electrical Engineering, 2011, Penn State University

 In this thesis, a library of basic operators for accelerating complex algorithms on an Field Programmable Gate Array (FPGA) is proposed. The components of this… (more)

Subjects/Keywords: FPGA; framework; dataflow; reconfigurable

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APA (6th Edition):

Chandrashekhar, A. (2011). A fine-grained dataflow library for reconfigurable streaming accelerators. (Masters Thesis). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/12324

Chicago Manual of Style (16th Edition):

Chandrashekhar, Aarti. “A fine-grained dataflow library for reconfigurable streaming accelerators.” 2011. Masters Thesis, Penn State University. Accessed April 20, 2019. https://etda.libraries.psu.edu/catalog/12324.

MLA Handbook (7th Edition):

Chandrashekhar, Aarti. “A fine-grained dataflow library for reconfigurable streaming accelerators.” 2011. Web. 20 Apr 2019.

Vancouver:

Chandrashekhar A. A fine-grained dataflow library for reconfigurable streaming accelerators. [Internet] [Masters thesis]. Penn State University; 2011. [cited 2019 Apr 20]. Available from: https://etda.libraries.psu.edu/catalog/12324.

Council of Science Editors:

Chandrashekhar A. A fine-grained dataflow library for reconfigurable streaming accelerators. [Masters Thesis]. Penn State University; 2011. Available from: https://etda.libraries.psu.edu/catalog/12324


University of Nevada – Las Vegas

10. Chmaj, Grzegorz. A Distributed Processing Platform With Reconfigurable Autonomous Nodes.

Degree: PhD, Electrical and Computer Engineering, 2016, University of Nevada – Las Vegas

  Distributed processing is a fast growing area of interest due to the exploding popularity of Internet of Things (IoT) and Unmanned Aerial Vehicles (UAV)… (more)

Subjects/Keywords: computing; distributed; fpga; reconfigurable; Engineering

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APA (6th Edition):

Chmaj, G. (2016). A Distributed Processing Platform With Reconfigurable Autonomous Nodes. (Doctoral Dissertation). University of Nevada – Las Vegas. Retrieved from https://digitalscholarship.unlv.edu/thesesdissertations/2776

Chicago Manual of Style (16th Edition):

Chmaj, Grzegorz. “A Distributed Processing Platform With Reconfigurable Autonomous Nodes.” 2016. Doctoral Dissertation, University of Nevada – Las Vegas. Accessed April 20, 2019. https://digitalscholarship.unlv.edu/thesesdissertations/2776.

MLA Handbook (7th Edition):

Chmaj, Grzegorz. “A Distributed Processing Platform With Reconfigurable Autonomous Nodes.” 2016. Web. 20 Apr 2019.

Vancouver:

Chmaj G. A Distributed Processing Platform With Reconfigurable Autonomous Nodes. [Internet] [Doctoral dissertation]. University of Nevada – Las Vegas; 2016. [cited 2019 Apr 20]. Available from: https://digitalscholarship.unlv.edu/thesesdissertations/2776.

Council of Science Editors:

Chmaj G. A Distributed Processing Platform With Reconfigurable Autonomous Nodes. [Doctoral Dissertation]. University of Nevada – Las Vegas; 2016. Available from: https://digitalscholarship.unlv.edu/thesesdissertations/2776


University of Waterloo

11. Khan, Asif. Towards Microfluidic Design Automation.

Degree: 2016, University of Waterloo

 Microfluidic chips, lab-on-a-chip devices that have channels transporting liquids instead of wires carrying electrons, have attracted considerable attention recently from the bio-medical industry because of… (more)

Subjects/Keywords: Microfluidics; Reconfigurable Tooling; Design Automation

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APA (6th Edition):

Khan, A. (2016). Towards Microfluidic Design Automation. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/10224

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Khan, Asif. “Towards Microfluidic Design Automation.” 2016. Thesis, University of Waterloo. Accessed April 20, 2019. http://hdl.handle.net/10012/10224.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Khan, Asif. “Towards Microfluidic Design Automation.” 2016. Web. 20 Apr 2019.

Vancouver:

Khan A. Towards Microfluidic Design Automation. [Internet] [Thesis]. University of Waterloo; 2016. [cited 2019 Apr 20]. Available from: http://hdl.handle.net/10012/10224.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Khan A. Towards Microfluidic Design Automation. [Thesis]. University of Waterloo; 2016. Available from: http://hdl.handle.net/10012/10224

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Waterloo

12. Phillips, Sean. Development of a Mobile Modular Robotic System, R2TM3, for Enhanced Mobility in Unstructured Environments.

Degree: 2012, University of Waterloo

 Limited mobility of mobile ground robots in highly unstructured environments is a problem that inhibits the use of such robots in applications with irregular terrain.… (more)

Subjects/Keywords: Robotics; Modular; Mobility; Reconfigurable

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APA (6th Edition):

Phillips, S. (2012). Development of a Mobile Modular Robotic System, R2TM3, for Enhanced Mobility in Unstructured Environments. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/7147

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Phillips, Sean. “Development of a Mobile Modular Robotic System, R2TM3, for Enhanced Mobility in Unstructured Environments.” 2012. Thesis, University of Waterloo. Accessed April 20, 2019. http://hdl.handle.net/10012/7147.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Phillips, Sean. “Development of a Mobile Modular Robotic System, R2TM3, for Enhanced Mobility in Unstructured Environments.” 2012. Web. 20 Apr 2019.

Vancouver:

Phillips S. Development of a Mobile Modular Robotic System, R2TM3, for Enhanced Mobility in Unstructured Environments. [Internet] [Thesis]. University of Waterloo; 2012. [cited 2019 Apr 20]. Available from: http://hdl.handle.net/10012/7147.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Phillips S. Development of a Mobile Modular Robotic System, R2TM3, for Enhanced Mobility in Unstructured Environments. [Thesis]. University of Waterloo; 2012. Available from: http://hdl.handle.net/10012/7147

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Luleå University of Technology

13. Uthaicharoenpong, Tawon. Stability enhancement of reconfigurable robots.

Degree: 2008, Luleå University of Technology

Future planetary exploration missions will require mobile robots to excess challenging terrain such as rocky areas, steep slopes or loose soil types which make… (more)

Subjects/Keywords: Technology; Robots; Stability; Reconfigurable; Teknik

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APA (6th Edition):

Uthaicharoenpong, T. (2008). Stability enhancement of reconfigurable robots. (Thesis). Luleå University of Technology. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-49958

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Uthaicharoenpong, Tawon. “Stability enhancement of reconfigurable robots.” 2008. Thesis, Luleå University of Technology. Accessed April 20, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-49958.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Uthaicharoenpong, Tawon. “Stability enhancement of reconfigurable robots.” 2008. Web. 20 Apr 2019.

Vancouver:

Uthaicharoenpong T. Stability enhancement of reconfigurable robots. [Internet] [Thesis]. Luleå University of Technology; 2008. [cited 2019 Apr 20]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-49958.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Uthaicharoenpong T. Stability enhancement of reconfigurable robots. [Thesis]. Luleå University of Technology; 2008. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-49958

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

14. Kobayashi, K. A power-aware fault-tolerant hardware system for a custom reconfigurable platform:.

Degree: 2010, Delft University of Technology

 Electronics systems in deep-submicron era face many new challenges. Increased intricacy of the manufacturing process will likely to increase the manufacturing defect while testing of… (more)

Subjects/Keywords: bio-inspired; reconfigurable hardware

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APA (6th Edition):

Kobayashi, K. (2010). A power-aware fault-tolerant hardware system for a custom reconfigurable platform:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:9beb172a-6e38-43ee-8d08-9180411e26f9

Chicago Manual of Style (16th Edition):

Kobayashi, K. “A power-aware fault-tolerant hardware system for a custom reconfigurable platform:.” 2010. Masters Thesis, Delft University of Technology. Accessed April 20, 2019. http://resolver.tudelft.nl/uuid:9beb172a-6e38-43ee-8d08-9180411e26f9.

MLA Handbook (7th Edition):

Kobayashi, K. “A power-aware fault-tolerant hardware system for a custom reconfigurable platform:.” 2010. Web. 20 Apr 2019.

Vancouver:

Kobayashi K. A power-aware fault-tolerant hardware system for a custom reconfigurable platform:. [Internet] [Masters thesis]. Delft University of Technology; 2010. [cited 2019 Apr 20]. Available from: http://resolver.tudelft.nl/uuid:9beb172a-6e38-43ee-8d08-9180411e26f9.

Council of Science Editors:

Kobayashi K. A power-aware fault-tolerant hardware system for a custom reconfigurable platform:. [Masters Thesis]. Delft University of Technology; 2010. Available from: http://resolver.tudelft.nl/uuid:9beb172a-6e38-43ee-8d08-9180411e26f9


Delft University of Technology

15. Kong, Q. Interrupt support on the ρ-VEX processor:.

Degree: 2011, Delft University of Technology

 In this thesis, we present a design of interrupt system upon an extensible and reconfigurable VLIW softcore processor: r-VEX. This interrupt system is designed and… (more)

Subjects/Keywords: VILW; Reconfigurable; Interrupt; FPGA; VEX

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kong, Q. (2011). Interrupt support on the ρ-VEX processor:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:2f56ca9d-673c-41d6-9141-42bfe84c5c56

Chicago Manual of Style (16th Edition):

Kong, Q. “Interrupt support on the ρ-VEX processor:.” 2011. Masters Thesis, Delft University of Technology. Accessed April 20, 2019. http://resolver.tudelft.nl/uuid:2f56ca9d-673c-41d6-9141-42bfe84c5c56.

MLA Handbook (7th Edition):

Kong, Q. “Interrupt support on the ρ-VEX processor:.” 2011. Web. 20 Apr 2019.

Vancouver:

Kong Q. Interrupt support on the ρ-VEX processor:. [Internet] [Masters thesis]. Delft University of Technology; 2011. [cited 2019 Apr 20]. Available from: http://resolver.tudelft.nl/uuid:2f56ca9d-673c-41d6-9141-42bfe84c5c56.

Council of Science Editors:

Kong Q. Interrupt support on the ρ-VEX processor:. [Masters Thesis]. Delft University of Technology; 2011. Available from: http://resolver.tudelft.nl/uuid:2f56ca9d-673c-41d6-9141-42bfe84c5c56


University of New South Wales

16. Munshi, Shadi Mohammad. Analysis, investigation and design of flexible universal pneumatic industrial manipulators involving Cartesian and joint control in the basis of economic feasibility and appropriate technology.

Degree: Mechanical & Manufacturing Engineering, 2012, University of New South Wales

 Pneumatic cylinders and systems have dominated the majority of industrial plants as two-position actuators due to that they are light-weight, clean, non-flammable; available in a… (more)

Subjects/Keywords: Modular; Manipulator; Pneumatic; RMMS; Reconfigurable

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APA (6th Edition):

Munshi, S. M. (2012). Analysis, investigation and design of flexible universal pneumatic industrial manipulators involving Cartesian and joint control in the basis of economic feasibility and appropriate technology. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/52137 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:10807/SOURCE01?view=true

Chicago Manual of Style (16th Edition):

Munshi, Shadi Mohammad. “Analysis, investigation and design of flexible universal pneumatic industrial manipulators involving Cartesian and joint control in the basis of economic feasibility and appropriate technology.” 2012. Doctoral Dissertation, University of New South Wales. Accessed April 20, 2019. http://handle.unsw.edu.au/1959.4/52137 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:10807/SOURCE01?view=true.

MLA Handbook (7th Edition):

Munshi, Shadi Mohammad. “Analysis, investigation and design of flexible universal pneumatic industrial manipulators involving Cartesian and joint control in the basis of economic feasibility and appropriate technology.” 2012. Web. 20 Apr 2019.

Vancouver:

Munshi SM. Analysis, investigation and design of flexible universal pneumatic industrial manipulators involving Cartesian and joint control in the basis of economic feasibility and appropriate technology. [Internet] [Doctoral dissertation]. University of New South Wales; 2012. [cited 2019 Apr 20]. Available from: http://handle.unsw.edu.au/1959.4/52137 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:10807/SOURCE01?view=true.

Council of Science Editors:

Munshi SM. Analysis, investigation and design of flexible universal pneumatic industrial manipulators involving Cartesian and joint control in the basis of economic feasibility and appropriate technology. [Doctoral Dissertation]. University of New South Wales; 2012. Available from: http://handle.unsw.edu.au/1959.4/52137 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:10807/SOURCE01?view=true


Virginia Tech

17. Chandrasekharan, Athira. Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 FPGA implementation tool turnaround time has unfortunately not kept pace with FPGA density advances. It is difficult to parallelize place-and-route algorithms without sacrificing determinism or… (more)

Subjects/Keywords: Reconfigurable Computing; Incremental Floorplanning; FPGAs

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APA (6th Edition):

Chandrasekharan, A. (2010). Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34499

Chicago Manual of Style (16th Edition):

Chandrasekharan, Athira. “Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity.” 2010. Masters Thesis, Virginia Tech. Accessed April 20, 2019. http://hdl.handle.net/10919/34499.

MLA Handbook (7th Edition):

Chandrasekharan, Athira. “Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity.” 2010. Web. 20 Apr 2019.

Vancouver:

Chandrasekharan A. Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2019 Apr 20]. Available from: http://hdl.handle.net/10919/34499.

Council of Science Editors:

Chandrasekharan A. Accelerating Incremental Floorplanning of Partially Reconfigurable Designs to Improve FPGA Productivity. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/34499


Virginia Tech

18. Raja Gopalan, Sureshwar. Timing-Aware Automatic Floorplanning of Partially Reconfigurable Designs for Accelerating FPGA Productivity.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 FPGA implementation tool speed has not kept pace with the increase in design size and FPGA density. It is difficult to parallelize place-and-route algorithms without… (more)

Subjects/Keywords: FPGAs; Reconfigurable Computing; Automatic Floorplanning

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APA (6th Edition):

Raja Gopalan, S. (2010). Timing-Aware Automatic Floorplanning of Partially Reconfigurable Designs for Accelerating FPGA Productivity. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34993

Chicago Manual of Style (16th Edition):

Raja Gopalan, Sureshwar. “Timing-Aware Automatic Floorplanning of Partially Reconfigurable Designs for Accelerating FPGA Productivity.” 2010. Masters Thesis, Virginia Tech. Accessed April 20, 2019. http://hdl.handle.net/10919/34993.

MLA Handbook (7th Edition):

Raja Gopalan, Sureshwar. “Timing-Aware Automatic Floorplanning of Partially Reconfigurable Designs for Accelerating FPGA Productivity.” 2010. Web. 20 Apr 2019.

Vancouver:

Raja Gopalan S. Timing-Aware Automatic Floorplanning of Partially Reconfigurable Designs for Accelerating FPGA Productivity. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2019 Apr 20]. Available from: http://hdl.handle.net/10919/34993.

Council of Science Editors:

Raja Gopalan S. Timing-Aware Automatic Floorplanning of Partially Reconfigurable Designs for Accelerating FPGA Productivity. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/34993


University of Southern California

19. Chen, Chi-An. Dynamic power sharing for self-reconfigurable modular robots.

Degree: MS, Electrical Engineering, 2012, University of Southern California

 Self-Reconfigurable Modular Robots is one important field in the robotics research. It can be used to deal with the unforeseen situations, fixing the distributed problems,… (more)

Subjects/Keywords: power; power sharing; robot; modular robot; reconfigurable; self-reconfigurable; dynamic

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APA (6th Edition):

Chen, C. (2012). Dynamic power sharing for self-reconfigurable modular robots. (Masters Thesis). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/31886/rec/2126

Chicago Manual of Style (16th Edition):

Chen, Chi-An. “Dynamic power sharing for self-reconfigurable modular robots.” 2012. Masters Thesis, University of Southern California. Accessed April 20, 2019. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/31886/rec/2126.

MLA Handbook (7th Edition):

Chen, Chi-An. “Dynamic power sharing for self-reconfigurable modular robots.” 2012. Web. 20 Apr 2019.

Vancouver:

Chen C. Dynamic power sharing for self-reconfigurable modular robots. [Internet] [Masters thesis]. University of Southern California; 2012. [cited 2019 Apr 20]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/31886/rec/2126.

Council of Science Editors:

Chen C. Dynamic power sharing for self-reconfigurable modular robots. [Masters Thesis]. University of Southern California; 2012. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/31886/rec/2126

20. Khiar, Amel. Virtualisation des communications et déploiement d'acteurs matériels : flot de données pour une plateforme hétérogène et reconfigurable dynamiquement : Virtualization of communications in a heterogeneous and dynamically reconfigurable platform.

Degree: Docteur es, STIC (sciences et technologies de l'information et de la communication) - Cergy, 2014, Cergy-Pontoise

Les applications embarquées ont besoin de plus en plus de puissance de calcul et doivent être déployées sur des architectures spécifiques pour assurer les contraintes… (more)

Subjects/Keywords: Middleware; Système embarqué; Reconfigurable; Fpga; Middleware; Embeded system; Reconfigurable; Fpga

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APA (6th Edition):

Khiar, A. (2014). Virtualisation des communications et déploiement d'acteurs matériels : flot de données pour une plateforme hétérogène et reconfigurable dynamiquement : Virtualization of communications in a heterogeneous and dynamically reconfigurable platform. (Doctoral Dissertation). Cergy-Pontoise. Retrieved from http://www.theses.fr/2014CERG0716

Chicago Manual of Style (16th Edition):

Khiar, Amel. “Virtualisation des communications et déploiement d'acteurs matériels : flot de données pour une plateforme hétérogène et reconfigurable dynamiquement : Virtualization of communications in a heterogeneous and dynamically reconfigurable platform.” 2014. Doctoral Dissertation, Cergy-Pontoise. Accessed April 20, 2019. http://www.theses.fr/2014CERG0716.

MLA Handbook (7th Edition):

Khiar, Amel. “Virtualisation des communications et déploiement d'acteurs matériels : flot de données pour une plateforme hétérogène et reconfigurable dynamiquement : Virtualization of communications in a heterogeneous and dynamically reconfigurable platform.” 2014. Web. 20 Apr 2019.

Vancouver:

Khiar A. Virtualisation des communications et déploiement d'acteurs matériels : flot de données pour une plateforme hétérogène et reconfigurable dynamiquement : Virtualization of communications in a heterogeneous and dynamically reconfigurable platform. [Internet] [Doctoral dissertation]. Cergy-Pontoise; 2014. [cited 2019 Apr 20]. Available from: http://www.theses.fr/2014CERG0716.

Council of Science Editors:

Khiar A. Virtualisation des communications et déploiement d'acteurs matériels : flot de données pour une plateforme hétérogène et reconfigurable dynamiquement : Virtualization of communications in a heterogeneous and dynamically reconfigurable platform. [Doctoral Dissertation]. Cergy-Pontoise; 2014. Available from: http://www.theses.fr/2014CERG0716


INP Toulouse

21. Massiot, Jérôme. Intégration de MEMS pour la réalisation d’ une antenne spirale à hautes performances reconfigurable : MEMS integration for the design of high performance reconfigurable spiral antenna.

Degree: Docteur es, Électromagnétisme et Systèmes Haute Fréquence, 2013, INP Toulouse

L'émergence de nouveaux systèmes de radar et de télécommunication nécessite des antennes adaptables en temps réel. Les antennes reconfigurables permettent de répondre à ce besoin… (more)

Subjects/Keywords: Antenne; Reconfigurable; Multi Fonction; MEMS; Antenna; Reconfigurable; Multi Fonction; MEMS

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APA (6th Edition):

Massiot, J. (2013). Intégration de MEMS pour la réalisation d’ une antenne spirale à hautes performances reconfigurable : MEMS integration for the design of high performance reconfigurable spiral antenna. (Doctoral Dissertation). INP Toulouse. Retrieved from http://www.theses.fr/2013INPT0100

Chicago Manual of Style (16th Edition):

Massiot, Jérôme. “Intégration de MEMS pour la réalisation d’ une antenne spirale à hautes performances reconfigurable : MEMS integration for the design of high performance reconfigurable spiral antenna.” 2013. Doctoral Dissertation, INP Toulouse. Accessed April 20, 2019. http://www.theses.fr/2013INPT0100.

MLA Handbook (7th Edition):

Massiot, Jérôme. “Intégration de MEMS pour la réalisation d’ une antenne spirale à hautes performances reconfigurable : MEMS integration for the design of high performance reconfigurable spiral antenna.” 2013. Web. 20 Apr 2019.

Vancouver:

Massiot J. Intégration de MEMS pour la réalisation d’ une antenne spirale à hautes performances reconfigurable : MEMS integration for the design of high performance reconfigurable spiral antenna. [Internet] [Doctoral dissertation]. INP Toulouse; 2013. [cited 2019 Apr 20]. Available from: http://www.theses.fr/2013INPT0100.

Council of Science Editors:

Massiot J. Intégration de MEMS pour la réalisation d’ une antenne spirale à hautes performances reconfigurable : MEMS integration for the design of high performance reconfigurable spiral antenna. [Doctoral Dissertation]. INP Toulouse; 2013. Available from: http://www.theses.fr/2013INPT0100


Indian Institute of Science

22. Alle, Mythri. Compiling For Coarse-Grained Reconfigurable Architectures Based On Dataflow Execution Paradigm.

Degree: 2012, Indian Institute of Science

 Coarse-Grained Reconfigurable Architectures(CGRAs) can be employed for accelerating computational workloads that demand both flexibility and performance. CGRAs comprise a set of computation elements interconnected using… (more)

Subjects/Keywords: Coarse-Grained Reconfigurable Architecture (CGRA); Reconfigurable Fabric; Dataflow Execution; Compilers (Computer Programs); Computer Architecture; Reconfigurable Architectures; Coarse-Grained Reconfigurable Architectures (CGRAs); Run Time Reconfigurable Platform; Runtime Reconfigurable Platform; Runtime Reconfigurable Hardware; Coarse Grained Computation; Computer Science

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APA (6th Edition):

Alle, M. (2012). Compiling For Coarse-Grained Reconfigurable Architectures Based On Dataflow Execution Paradigm. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/2453

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Alle, Mythri. “Compiling For Coarse-Grained Reconfigurable Architectures Based On Dataflow Execution Paradigm.” 2012. Thesis, Indian Institute of Science. Accessed April 20, 2019. http://hdl.handle.net/2005/2453.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Alle, Mythri. “Compiling For Coarse-Grained Reconfigurable Architectures Based On Dataflow Execution Paradigm.” 2012. Web. 20 Apr 2019.

Vancouver:

Alle M. Compiling For Coarse-Grained Reconfigurable Architectures Based On Dataflow Execution Paradigm. [Internet] [Thesis]. Indian Institute of Science; 2012. [cited 2019 Apr 20]. Available from: http://hdl.handle.net/2005/2453.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Alle M. Compiling For Coarse-Grained Reconfigurable Architectures Based On Dataflow Execution Paradigm. [Thesis]. Indian Institute of Science; 2012. Available from: http://hdl.handle.net/2005/2453

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

23. Alle, Mythri. Compiling For Coarse-Grained Reconfigurable Architectures Based On Dataflow Execution Paradigm.

Degree: 2012, Indian Institute of Science

 Coarse-Grained Reconfigurable Architectures(CGRAs) can be employed for accelerating computational workloads that demand both flexibility and performance. CGRAs comprise a set of computation elements interconnected using… (more)

Subjects/Keywords: Coarse-Grained Reconfigurable Architecture (CGRA); Reconfigurable Fabric; Dataflow Execution; Compilers (Computer Programs); Computer Architecture; Reconfigurable Architectures; Coarse-Grained Reconfigurable Architectures (CGRAs); Run Time Reconfigurable Platform; Runtime Reconfigurable Platform; Runtime Reconfigurable Hardware; Coarse Grained Computation; Computer Science

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APA (6th Edition):

Alle, M. (2012). Compiling For Coarse-Grained Reconfigurable Architectures Based On Dataflow Execution Paradigm. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/2453 ; http://etd.ncsi.iisc.ernet.in/abstracts/3167/G25487-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Alle, Mythri. “Compiling For Coarse-Grained Reconfigurable Architectures Based On Dataflow Execution Paradigm.” 2012. Thesis, Indian Institute of Science. Accessed April 20, 2019. http://etd.iisc.ernet.in/handle/2005/2453 ; http://etd.ncsi.iisc.ernet.in/abstracts/3167/G25487-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Alle, Mythri. “Compiling For Coarse-Grained Reconfigurable Architectures Based On Dataflow Execution Paradigm.” 2012. Web. 20 Apr 2019.

Vancouver:

Alle M. Compiling For Coarse-Grained Reconfigurable Architectures Based On Dataflow Execution Paradigm. [Internet] [Thesis]. Indian Institute of Science; 2012. [cited 2019 Apr 20]. Available from: http://etd.iisc.ernet.in/handle/2005/2453 ; http://etd.ncsi.iisc.ernet.in/abstracts/3167/G25487-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Alle M. Compiling For Coarse-Grained Reconfigurable Architectures Based On Dataflow Execution Paradigm. [Thesis]. Indian Institute of Science; 2012. Available from: http://etd.iisc.ernet.in/handle/2005/2453 ; http://etd.ncsi.iisc.ernet.in/abstracts/3167/G25487-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

24. Valiante Filho, Filippo. Ferramentas e metodologias de desenvolvimento para sistemas parcialmente reconfiguráveis.

Degree: Mestrado, Microeletrônica, 2008, University of São Paulo

Alguns tipos de FPGA (Field Programmable Gate Array) possuem a capacidade de serem reconfigurados parcialmente em tempo de execução formando um Sistema Parcialmente Reconfigurável (SPR),… (more)

Subjects/Keywords: Arquitetura reconfigurável; CAD; CAD for FPGAs; Circuitos FPGA; Circuitos integrados; Computação reconfigurável; FPGA; Microeletrônica; Partial reconfigurable system; Reconfigurable architecture; Reconfigurable logic

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APA (6th Edition):

Valiante Filho, F. (2008). Ferramentas e metodologias de desenvolvimento para sistemas parcialmente reconfiguráveis. (Masters Thesis). University of São Paulo. Retrieved from http://www.teses.usp.br/teses/disponiveis/3/3140/tde-18082008-154538/ ;

Chicago Manual of Style (16th Edition):

Valiante Filho, Filippo. “Ferramentas e metodologias de desenvolvimento para sistemas parcialmente reconfiguráveis.” 2008. Masters Thesis, University of São Paulo. Accessed April 20, 2019. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-18082008-154538/ ;.

MLA Handbook (7th Edition):

Valiante Filho, Filippo. “Ferramentas e metodologias de desenvolvimento para sistemas parcialmente reconfiguráveis.” 2008. Web. 20 Apr 2019.

Vancouver:

Valiante Filho F. Ferramentas e metodologias de desenvolvimento para sistemas parcialmente reconfiguráveis. [Internet] [Masters thesis]. University of São Paulo; 2008. [cited 2019 Apr 20]. Available from: http://www.teses.usp.br/teses/disponiveis/3/3140/tde-18082008-154538/ ;.

Council of Science Editors:

Valiante Filho F. Ferramentas e metodologias de desenvolvimento para sistemas parcialmente reconfiguráveis. [Masters Thesis]. University of São Paulo; 2008. Available from: http://www.teses.usp.br/teses/disponiveis/3/3140/tde-18082008-154538/ ;


Brunel University

25. Afandi, Ahmad. Efficient reconfigurable architectures for 3D medical image compression.

Degree: PhD, 2010, Brunel University

 Recently, the more widespread use of three-dimensional (3-D) imaging modalities, such as magnetic resonance imaging (MRI), computed tomography (CT), positron emission tomography (PET), and ultrasound… (more)

Subjects/Keywords: 621.39; Field programmable gate array; Reconfigurable computing

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APA (6th Edition):

Afandi, A. (2010). Efficient reconfigurable architectures for 3D medical image compression. (Doctoral Dissertation). Brunel University. Retrieved from http://bura.brunel.ac.uk/handle/2438/7677 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.582880

Chicago Manual of Style (16th Edition):

Afandi, Ahmad. “Efficient reconfigurable architectures for 3D medical image compression.” 2010. Doctoral Dissertation, Brunel University. Accessed April 20, 2019. http://bura.brunel.ac.uk/handle/2438/7677 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.582880.

MLA Handbook (7th Edition):

Afandi, Ahmad. “Efficient reconfigurable architectures for 3D medical image compression.” 2010. Web. 20 Apr 2019.

Vancouver:

Afandi A. Efficient reconfigurable architectures for 3D medical image compression. [Internet] [Doctoral dissertation]. Brunel University; 2010. [cited 2019 Apr 20]. Available from: http://bura.brunel.ac.uk/handle/2438/7677 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.582880.

Council of Science Editors:

Afandi A. Efficient reconfigurable architectures for 3D medical image compression. [Doctoral Dissertation]. Brunel University; 2010. Available from: http://bura.brunel.ac.uk/handle/2438/7677 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.582880


University of Toronto

26. Rozhko, Daniel. Memory and Network Interface Virtualization for Multi-Tenant Reconfigurable Compute Devices.

Degree: 2018, University of Toronto

Field Programmable Gate Arrays (FPGAs) have increasingly been deployed in datacenters. These devices have proven effective at performing certain compute tasks better (faster, lower latency,… (more)

Subjects/Keywords: Cloud; FPGA; Memory; Networking; Reconfigurable; Virtualization; 0464

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APA (6th Edition):

Rozhko, D. (2018). Memory and Network Interface Virtualization for Multi-Tenant Reconfigurable Compute Devices. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/91740

Chicago Manual of Style (16th Edition):

Rozhko, Daniel. “Memory and Network Interface Virtualization for Multi-Tenant Reconfigurable Compute Devices.” 2018. Masters Thesis, University of Toronto. Accessed April 20, 2019. http://hdl.handle.net/1807/91740.

MLA Handbook (7th Edition):

Rozhko, Daniel. “Memory and Network Interface Virtualization for Multi-Tenant Reconfigurable Compute Devices.” 2018. Web. 20 Apr 2019.

Vancouver:

Rozhko D. Memory and Network Interface Virtualization for Multi-Tenant Reconfigurable Compute Devices. [Internet] [Masters thesis]. University of Toronto; 2018. [cited 2019 Apr 20]. Available from: http://hdl.handle.net/1807/91740.

Council of Science Editors:

Rozhko D. Memory and Network Interface Virtualization for Multi-Tenant Reconfigurable Compute Devices. [Masters Thesis]. University of Toronto; 2018. Available from: http://hdl.handle.net/1807/91740


Indian Institute of Science

27. Varadarajan, Keshavan. A Coarse Grained Reconfigurable Architecture Framework Supporting Macro-Dataflow Execution.

Degree: 2012, Indian Institute of Science

 A Coarse-Grained Reconfigurable Architecture (CGRA) is a processing platform which constitutes an interconnection of coarse-grained computation units (viz. Function Units (FUs), Arithmetic Logic Units (ALUs)).… (more)

Subjects/Keywords: Coarse Grained Computation; Reconfigurable Architectures; Macro Dataflow Execution; Coarse Grained Reconfigurable Architecture; Macro-Dataflow Orchestration; Microarchitectural Optimizations; Reconfigurable Fabric; Coarse-Grained Reconfigurable Architecture (CGRA); Macro Dataflow Execution; Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Varadarajan, K. (2012). A Coarse Grained Reconfigurable Architecture Framework Supporting Macro-Dataflow Execution. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/2302

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Varadarajan, Keshavan. “A Coarse Grained Reconfigurable Architecture Framework Supporting Macro-Dataflow Execution.” 2012. Thesis, Indian Institute of Science. Accessed April 20, 2019. http://hdl.handle.net/2005/2302.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Varadarajan, Keshavan. “A Coarse Grained Reconfigurable Architecture Framework Supporting Macro-Dataflow Execution.” 2012. Web. 20 Apr 2019.

Vancouver:

Varadarajan K. A Coarse Grained Reconfigurable Architecture Framework Supporting Macro-Dataflow Execution. [Internet] [Thesis]. Indian Institute of Science; 2012. [cited 2019 Apr 20]. Available from: http://hdl.handle.net/2005/2302.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Varadarajan K. A Coarse Grained Reconfigurable Architecture Framework Supporting Macro-Dataflow Execution. [Thesis]. Indian Institute of Science; 2012. Available from: http://hdl.handle.net/2005/2302

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

28. Wang, Ling-yu. Integration design environment for configurable on-chip bus monitor.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

 Nowadays, because the advance of the technology, a single chip can contain more and more Intellectual Property(IP). As the design increase with the IPs from… (more)

Subjects/Keywords: Automatically; Reconfigurable; Protocol Monitor; Performance Monitor

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, L. (2017). Integration design environment for configurable on-chip bus monitor. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725117-161146

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Ling-yu. “Integration design environment for configurable on-chip bus monitor.” 2017. Thesis, NSYSU. Accessed April 20, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725117-161146.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Ling-yu. “Integration design environment for configurable on-chip bus monitor.” 2017. Web. 20 Apr 2019.

Vancouver:

Wang L. Integration design environment for configurable on-chip bus monitor. [Internet] [Thesis]. NSYSU; 2017. [cited 2019 Apr 20]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725117-161146.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang L. Integration design environment for configurable on-chip bus monitor. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725117-161146

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

29. Varadarajan, Keshavan. A Coarse Grained Reconfigurable Architecture Framework Supporting Macro-Dataflow Execution.

Degree: 2012, Indian Institute of Science

 A Coarse-Grained Reconfigurable Architecture (CGRA) is a processing platform which constitutes an interconnection of coarse-grained computation units (viz. Function Units (FUs), Arithmetic Logic Units (ALUs)).… (more)

Subjects/Keywords: Coarse Grained Computation; Reconfigurable Architectures; Macro Dataflow Execution; Coarse Grained Reconfigurable Architecture; Macro-Dataflow Orchestration; Microarchitectural Optimizations; Reconfigurable Fabric; Coarse-Grained Reconfigurable Architecture (CGRA); Macro Dataflow Execution; Computer Science

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Varadarajan, K. (2012). A Coarse Grained Reconfigurable Architecture Framework Supporting Macro-Dataflow Execution. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/2302 ; http://etd.ncsi.iisc.ernet.in/abstracts/2962/G25467-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Varadarajan, Keshavan. “A Coarse Grained Reconfigurable Architecture Framework Supporting Macro-Dataflow Execution.” 2012. Thesis, Indian Institute of Science. Accessed April 20, 2019. http://etd.iisc.ernet.in/handle/2005/2302 ; http://etd.ncsi.iisc.ernet.in/abstracts/2962/G25467-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Varadarajan, Keshavan. “A Coarse Grained Reconfigurable Architecture Framework Supporting Macro-Dataflow Execution.” 2012. Web. 20 Apr 2019.

Vancouver:

Varadarajan K. A Coarse Grained Reconfigurable Architecture Framework Supporting Macro-Dataflow Execution. [Internet] [Thesis]. Indian Institute of Science; 2012. [cited 2019 Apr 20]. Available from: http://etd.iisc.ernet.in/handle/2005/2302 ; http://etd.ncsi.iisc.ernet.in/abstracts/2962/G25467-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Varadarajan K. A Coarse Grained Reconfigurable Architecture Framework Supporting Macro-Dataflow Execution. [Thesis]. Indian Institute of Science; 2012. Available from: http://etd.iisc.ernet.in/handle/2005/2302 ; http://etd.ncsi.iisc.ernet.in/abstracts/2962/G25467-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Cincinnati

30. Liao, Linxia. An Adaptive Modeling for Robust Prognostics on a Reconfigurable Platform.

Degree: PhD, Engineering : Industrial Engineering, 2010, University of Cincinnati

 Prognostics focus on failure prediction in order to prevent unexpected machine downtime; which can have major impact on costs in industry. Despite progress made in… (more)

Subjects/Keywords: Industrial Engineering; Prognostics; Adaptive Modeling; Reconfigurable Platform

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liao, L. (2010). An Adaptive Modeling for Robust Prognostics on a Reconfigurable Platform. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1276535854

Chicago Manual of Style (16th Edition):

Liao, Linxia. “An Adaptive Modeling for Robust Prognostics on a Reconfigurable Platform.” 2010. Doctoral Dissertation, University of Cincinnati. Accessed April 20, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1276535854.

MLA Handbook (7th Edition):

Liao, Linxia. “An Adaptive Modeling for Robust Prognostics on a Reconfigurable Platform.” 2010. Web. 20 Apr 2019.

Vancouver:

Liao L. An Adaptive Modeling for Robust Prognostics on a Reconfigurable Platform. [Internet] [Doctoral dissertation]. University of Cincinnati; 2010. [cited 2019 Apr 20]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1276535854.

Council of Science Editors:

Liao L. An Adaptive Modeling for Robust Prognostics on a Reconfigurable Platform. [Doctoral Dissertation]. University of Cincinnati; 2010. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1276535854

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