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You searched for subject:(rapid thermal anneal). Showing records 1 – 2 of 2 total matches.

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University of Cincinnati

1. Schultz, Thomas. ReRAM based platform for monitoring IC integrity and aging.

Degree: PhD, Engineering and Applied Science: Electrical Engineering, 2019, University of Cincinnati

This dissertation reports the work done on MgO based Resistive Random-Access Memory (ReRAM) devices to be used in conjunction with CMOS circuitry to develop a platform capable of monitoring the age and integrity of IC components. The dissertation starts by providing insights into the basic operation of ReRAM devices, hardware security, and other research work performed in this field. A short background introduction of ReRAM devices is provided along with a review of widely accepted switching mechanisms and theory behind them. Thereafter, a short introduction into the increased need for hardware security, some of the current solutions and their pitfalls are discussed. The dissertation then discusses reasons behind why MgO is an excellent candidate for a switching oxide in ReRAM devices. A fabrication process for MgO materials consisting of a systematic optimization of RF magnetron sputtering and Rapid Thermal Annealing (RTA) is presented and supported with experimental results. The process integration of MgO in ReRAM devices involved development of new masks along with the optimization of etch process for thin films of SiN, MgO, Ru, Ti, and W which is discussed in detail. Scanning Electron Microscopy (SEM) images are presented for fabricated devices which demonstrated the success in fabricating the intended ReRAM devices. The compositional analysis of the stack was performed using Energy Dispersive X-Ray Spectroscopy (EDX) and crystallographic structure of MgO with various annealing and deposition conditions was studied using X-Ray Diffraction (XRD). The Process Voltage Temperature (PVT) characteristics, aging, and temperature sensitivity of MgO-ReRAM devices were experimentally studied and modeled to capture resistance distributions and temperature-based modalities. These studies demonstrated excellent temperature sensing and aging modalities with simultaneous storage of sensed temperature and age as a change in the resistive state. A novel read strategy was developed by integrating an Axon-Hillock circuit (AHC) to convert the change in resistive state of the ReRAM device into a measurable spiking frequency using 180 nm CMOS technology. 180nm feature sizes were chosen so these circuits can be fabricated in-house within the US in a trusted foundry. Temporal changes in temperature of underlying CMOS circuit were captured by instantaneous change in resistive state of ReRAM with local temperature fluctuations which translated to a change in the read circuit output. Due to the additive integration of the ReRAM devices and associated circuitry, this approach for aging and integrity monitoring (AIM) ensures large spatial coverage and accurate temporal monitoring of the underlying CMOS die with minimal loss of the functional chip area for these added security features. These circuits were extensively studied through simulations first and were then fabricated through MOSIS/TSMC 180nm CMOS process and tested. Results from the circuit testing and ReRAM integration are presented in detail discussing every component and its… Advisors/Committee Members: Jha, Rashmi (Committee Chair).

Subjects/Keywords: Electrical Engineering; Resistive Random Access Memory; Rapid Thermal Anneal; Integrity; Monitoring; Trojan; Resistance States

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Schultz, T. (2019). ReRAM based platform for monitoring IC integrity and aging. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1573576246158436

Chicago Manual of Style (16th Edition):

Schultz, Thomas. “ReRAM based platform for monitoring IC integrity and aging.” 2019. Doctoral Dissertation, University of Cincinnati. Accessed August 13, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1573576246158436.

MLA Handbook (7th Edition):

Schultz, Thomas. “ReRAM based platform for monitoring IC integrity and aging.” 2019. Web. 13 Aug 2020.

Vancouver:

Schultz T. ReRAM based platform for monitoring IC integrity and aging. [Internet] [Doctoral dissertation]. University of Cincinnati; 2019. [cited 2020 Aug 13]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1573576246158436.

Council of Science Editors:

Schultz T. ReRAM based platform for monitoring IC integrity and aging. [Doctoral Dissertation]. University of Cincinnati; 2019. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1573576246158436


North Carolina State University

2. Jur, Jesse Stephen. Lanthanide-based Oxides and Silicates for High-K Gate Dielectric Applications.

Degree: PhD, Materials Science and Engineering, 2007, North Carolina State University

The ability to improve performance of the high-end metal oxide semiconductor field effect transistor (MOSFET) is highly reliant on the dimensional scaling of such a device. In scaling, a decrease in dielectric thickness results in high leakage current between the electrode and the substrate by way of direct tunneling through the gate dielectric. Observation of a high leakage current when the standard gate dielectric, SiO2, is decreased below a thickness of 1.5 nm requires engineering of a replacement dielectric that is much more scalable. This high- dielectric allows for a physically thicker oxide, reducing leakage current. Integration of select lanthanide-based oxides and silicates, in particular lanthanum oxide and silicate, into MOS gate stack devices is examined. The quality of the high-K dielectrics is monitored electrically to determine properties such as equivalent oxide thickness, leakage current density and defect densities. In addition, analytical characterization of the dielectric and the gate stack is provided to examine the materialistic significance to the change of the electrical properties of the devices. It is shown that optimization of low-temperature processing can result in MOS devices with an equivalent oxide thickness (EOT) as low 5 Å and a leakage current density of 5.0 A⁄cm2. High-temperature processing, consistent with a MOSFET source-drain activation anneal, yields MOS devices with an EOT as low as 1.1 nm after optimization of the TaN/W electrode properties. The decrease in the device effective work function (phi_M,eff) observed in these samples is examined in detail. First, as a La2O3 capping layer on HfSiO(N), the shift yields ideal-phi_M,eff values for nMOSFET deices (4.0 eV) that were previously inaccessible. Other lanthanide oxides (Dy, Ho and Yb) used as capping layers show similar effects. It is also shown that tuning of phi_M,eff can be realized by controlling the extent of lanthanide-silicate formation. This research, conducted in conjunction with SEMATECH and the SRC, represents a significant technological advancement in realizing 45 and sub-45 nm MOSFET device nodes. Advisors/Committee Members: Angus Kingon, Committee Chair (advisor), Gregory Parsons, Committee Member (advisor), Jon-Paul Maria, Committee Member (advisor), Mark Johnson, Committee Member (advisor).

Subjects/Keywords: dc magnetron sputtering; physical vapor deposition; tungsten oxide; tungsten; W; tantalum nitride; TaN; lanthanum; lanthanum oxide; La; La2O3; La2SiO5; lanthanum silicate; La2Si2O7; Ho; holmium; holmium oxide; cation diffusion; back-side SIMS; secondary ion mass spectroscopy; SIMS; XRD; x-ray diffraction; molecular beam deposition; PMA; XPS; x-ray photoemission spectroscopy; post metallization anneal; RCA; chemical oxide; metal oxide semiconductor field effect transistor; MBE; silica; SiO2; interfacial layer; gate dielectric; dielectric; silicate; oxide; high-kappa; EOT; equivalent oxide thickness; high-k; band diagram; valance band offset; conduction band offset; band gap energy; effective work function; work function; voltage shift; threshold voltage; flat band voltage; leakage current; capacitance; mobility; electronic materials; scaling; Moore?s Law; MIS; MOS; MOSFET; high resolution transmission electron microscopy; HRTEM; RTA; rapid thermal anneal; PVD; tantalum; Ta; gate electrode; metal electrode; hafnium silicate; hafnium oxide; hafnium; ytterbium; ytterbium oxide; Yb; dysprosium oxide; dysprosium; Dy; E-beam evaporation; thermal evaporation; forming gas anneal; ozone; ammonia anneal; FGA

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jur, J. S. (2007). Lanthanide-based Oxides and Silicates for High-K Gate Dielectric Applications. (Doctoral Dissertation). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/5447

Chicago Manual of Style (16th Edition):

Jur, Jesse Stephen. “Lanthanide-based Oxides and Silicates for High-K Gate Dielectric Applications.” 2007. Doctoral Dissertation, North Carolina State University. Accessed August 13, 2020. http://www.lib.ncsu.edu/resolver/1840.16/5447.

MLA Handbook (7th Edition):

Jur, Jesse Stephen. “Lanthanide-based Oxides and Silicates for High-K Gate Dielectric Applications.” 2007. Web. 13 Aug 2020.

Vancouver:

Jur JS. Lanthanide-based Oxides and Silicates for High-K Gate Dielectric Applications. [Internet] [Doctoral dissertation]. North Carolina State University; 2007. [cited 2020 Aug 13]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/5447.

Council of Science Editors:

Jur JS. Lanthanide-based Oxides and Silicates for High-K Gate Dielectric Applications. [Doctoral Dissertation]. North Carolina State University; 2007. Available from: http://www.lib.ncsu.edu/resolver/1840.16/5447

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