Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

Sorted by: relevance · author · university · dateNew search

You searched for subject:(process variations). Showing records 1 – 30 of 46 total matches.

[1] [2]

Search Limiters

Last 2 Years | English Only

Degrees

▼ Search Limiters


Cornell University

1. Xu, Qianying. Process Variations In Cmos Memory Devices: Analysis, Mitigation And Application .

Degree: 2014, Cornell University

 Driven by the improvements on performance and cost, new generations of complementary metal oxide semiconductor (CMOS) memory devices such as SRAM, DRAM, and Flash have… (more)

Subjects/Keywords: CMOS; Memory Devices; Process Variations

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Xu, Q. (2014). Process Variations In Cmos Memory Devices: Analysis, Mitigation And Application . (Thesis). Cornell University. Retrieved from http://hdl.handle.net/1813/37116

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Xu, Qianying. “Process Variations In Cmos Memory Devices: Analysis, Mitigation And Application .” 2014. Thesis, Cornell University. Accessed November 17, 2019. http://hdl.handle.net/1813/37116.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Xu, Qianying. “Process Variations In Cmos Memory Devices: Analysis, Mitigation And Application .” 2014. Web. 17 Nov 2019.

Vancouver:

Xu Q. Process Variations In Cmos Memory Devices: Analysis, Mitigation And Application . [Internet] [Thesis]. Cornell University; 2014. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/1813/37116.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Xu Q. Process Variations In Cmos Memory Devices: Analysis, Mitigation And Application . [Thesis]. Cornell University; 2014. Available from: http://hdl.handle.net/1813/37116

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

2. Wang, Feng. DEEP SUBMICRON (DSM) DESIGN AUTOMATION TECHNIQUES TO MITIGATE PROCESS VARIATIONS.

Degree: PhD, Computer Science and Engineering, 2008, Penn State University

 Technology scaling provides an integration capacity of billions of transistors and continuously enhances system performance. However, fabricating transistors at feature sizes in the deep sub-micron… (more)

Subjects/Keywords: high level synthesis; design automation; process variations

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, F. (2008). DEEP SUBMICRON (DSM) DESIGN AUTOMATION TECHNIQUES TO MITIGATE PROCESS VARIATIONS. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/8173

Chicago Manual of Style (16th Edition):

Wang, Feng. “DEEP SUBMICRON (DSM) DESIGN AUTOMATION TECHNIQUES TO MITIGATE PROCESS VARIATIONS.” 2008. Doctoral Dissertation, Penn State University. Accessed November 17, 2019. https://etda.libraries.psu.edu/catalog/8173.

MLA Handbook (7th Edition):

Wang, Feng. “DEEP SUBMICRON (DSM) DESIGN AUTOMATION TECHNIQUES TO MITIGATE PROCESS VARIATIONS.” 2008. Web. 17 Nov 2019.

Vancouver:

Wang F. DEEP SUBMICRON (DSM) DESIGN AUTOMATION TECHNIQUES TO MITIGATE PROCESS VARIATIONS. [Internet] [Doctoral dissertation]. Penn State University; 2008. [cited 2019 Nov 17]. Available from: https://etda.libraries.psu.edu/catalog/8173.

Council of Science Editors:

Wang F. DEEP SUBMICRON (DSM) DESIGN AUTOMATION TECHNIQUES TO MITIGATE PROCESS VARIATIONS. [Doctoral Dissertation]. Penn State University; 2008. Available from: https://etda.libraries.psu.edu/catalog/8173


Georgia Tech

3. Lu, Hao. Impact of fabrication process variations on the electrical performance of impedance controlled 2 micron multilayer redistribution layers (RDL) on glass interposers.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 The objective of this PhD dissertation is to study the impact of redistribution layer (RDL) processes and their variations on the electrical performance of 50-ohm… (more)

Subjects/Keywords: Multilayer RDL; Process variations; Impedance control; Glass interposer; Semi-additive process

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lu, H. (2017). Impact of fabrication process variations on the electrical performance of impedance controlled 2 micron multilayer redistribution layers (RDL) on glass interposers. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59238

Chicago Manual of Style (16th Edition):

Lu, Hao. “Impact of fabrication process variations on the electrical performance of impedance controlled 2 micron multilayer redistribution layers (RDL) on glass interposers.” 2017. Doctoral Dissertation, Georgia Tech. Accessed November 17, 2019. http://hdl.handle.net/1853/59238.

MLA Handbook (7th Edition):

Lu, Hao. “Impact of fabrication process variations on the electrical performance of impedance controlled 2 micron multilayer redistribution layers (RDL) on glass interposers.” 2017. Web. 17 Nov 2019.

Vancouver:

Lu H. Impact of fabrication process variations on the electrical performance of impedance controlled 2 micron multilayer redistribution layers (RDL) on glass interposers. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/1853/59238.

Council of Science Editors:

Lu H. Impact of fabrication process variations on the electrical performance of impedance controlled 2 micron multilayer redistribution layers (RDL) on glass interposers. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/59238


Addis Ababa University

4. Goytom, Desta. MULTI-STAGE AND MULTI-RESPONSE PROCESS OPTIMIZATION BASED ON APPLICATION OF DESIGN OF EXPERIMENTS FOR REDUCING PRODUCT PERFORMANCE VARIATIONS A Study on Harar Brewery S. Co.

Degree: 2013, Addis Ababa University

 Everything is the result or outcome of some process. All process also exhibit some sort of variation. These variations cause deviation of product’s performance characteristics… (more)

Subjects/Keywords: MULTI-STAGE AND MULTI-RESPONSE PROCESS OPTIMIZATION; PRODUCT PERFORMANCE VARIATIONS

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Goytom, D. (2013). MULTI-STAGE AND MULTI-RESPONSE PROCESS OPTIMIZATION BASED ON APPLICATION OF DESIGN OF EXPERIMENTS FOR REDUCING PRODUCT PERFORMANCE VARIATIONS A Study on Harar Brewery S. Co. (Thesis). Addis Ababa University. Retrieved from http://etd.aau.edu.et/dspace/handle/123456789/5062

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Goytom, Desta. “MULTI-STAGE AND MULTI-RESPONSE PROCESS OPTIMIZATION BASED ON APPLICATION OF DESIGN OF EXPERIMENTS FOR REDUCING PRODUCT PERFORMANCE VARIATIONS A Study on Harar Brewery S. Co. ” 2013. Thesis, Addis Ababa University. Accessed November 17, 2019. http://etd.aau.edu.et/dspace/handle/123456789/5062.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Goytom, Desta. “MULTI-STAGE AND MULTI-RESPONSE PROCESS OPTIMIZATION BASED ON APPLICATION OF DESIGN OF EXPERIMENTS FOR REDUCING PRODUCT PERFORMANCE VARIATIONS A Study on Harar Brewery S. Co. ” 2013. Web. 17 Nov 2019.

Vancouver:

Goytom D. MULTI-STAGE AND MULTI-RESPONSE PROCESS OPTIMIZATION BASED ON APPLICATION OF DESIGN OF EXPERIMENTS FOR REDUCING PRODUCT PERFORMANCE VARIATIONS A Study on Harar Brewery S. Co. [Internet] [Thesis]. Addis Ababa University; 2013. [cited 2019 Nov 17]. Available from: http://etd.aau.edu.et/dspace/handle/123456789/5062.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Goytom D. MULTI-STAGE AND MULTI-RESPONSE PROCESS OPTIMIZATION BASED ON APPLICATION OF DESIGN OF EXPERIMENTS FOR REDUCING PRODUCT PERFORMANCE VARIATIONS A Study on Harar Brewery S. Co. [Thesis]. Addis Ababa University; 2013. Available from: http://etd.aau.edu.et/dspace/handle/123456789/5062

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

5. Soundararajan, Niranjan Kumar. Addressing Reliability Issues in Performance-Critical Processor Structures.

Degree: PhD, Computer Science and Engineering, 2010, Penn State University

 Diminishing transistor sizes combined with power and performance constraints have decreased the inherent robustness in devices. With each new generation, designers find it difficult to… (more)

Subjects/Keywords: Microprocessor; Reliability; Soft Errors; Process Variations; Wearout; Fault Tolerance

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Soundararajan, N. K. (2010). Addressing Reliability Issues in Performance-Critical Processor Structures. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/10960

Chicago Manual of Style (16th Edition):

Soundararajan, Niranjan Kumar. “Addressing Reliability Issues in Performance-Critical Processor Structures.” 2010. Doctoral Dissertation, Penn State University. Accessed November 17, 2019. https://etda.libraries.psu.edu/catalog/10960.

MLA Handbook (7th Edition):

Soundararajan, Niranjan Kumar. “Addressing Reliability Issues in Performance-Critical Processor Structures.” 2010. Web. 17 Nov 2019.

Vancouver:

Soundararajan NK. Addressing Reliability Issues in Performance-Critical Processor Structures. [Internet] [Doctoral dissertation]. Penn State University; 2010. [cited 2019 Nov 17]. Available from: https://etda.libraries.psu.edu/catalog/10960.

Council of Science Editors:

Soundararajan NK. Addressing Reliability Issues in Performance-Critical Processor Structures. [Doctoral Dissertation]. Penn State University; 2010. Available from: https://etda.libraries.psu.edu/catalog/10960

6. O'Sullivan, Conor. Test Chip Design for Process Variation Characterization in 3D Integrated Circuits.

Degree: 2013, University of Waterloo

 A test chip design is presented for the characterization of process variations and Through Silicon Via (TSV) induced mechanical stress in 3D integrated circuits. The… (more)

Subjects/Keywords: 3D; TSV; process variations

…left), and the impact of TSV stress and process variations on DUT current (right… …little published work examining experimentally measured data for process variations. A… …the performance of short-channel devices. Process variations have always been present in… …photolithographic step of the manufacturing process might cause variations in the channel width (W… …x5B;18]. Some of the most important sources of process variations include variations in… 

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

O'Sullivan, C. (2013). Test Chip Design for Process Variation Characterization in 3D Integrated Circuits. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/7888

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

O'Sullivan, Conor. “Test Chip Design for Process Variation Characterization in 3D Integrated Circuits.” 2013. Thesis, University of Waterloo. Accessed November 17, 2019. http://hdl.handle.net/10012/7888.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

O'Sullivan, Conor. “Test Chip Design for Process Variation Characterization in 3D Integrated Circuits.” 2013. Web. 17 Nov 2019.

Vancouver:

O'Sullivan C. Test Chip Design for Process Variation Characterization in 3D Integrated Circuits. [Internet] [Thesis]. University of Waterloo; 2013. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/10012/7888.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

O'Sullivan C. Test Chip Design for Process Variation Characterization in 3D Integrated Circuits. [Thesis]. University of Waterloo; 2013. Available from: http://hdl.handle.net/10012/7888

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

7. Corey, Ryan. Statistical inference with unreliable binary observations.

Degree: MS, 1200, 2015, University of Illinois – Urbana-Champaign

 We describe a novel statistical inference approach to data conversion for mixed-signal interfaces. We propose a data conversion architecture in which a signal is observed… (more)

Subjects/Keywords: Analog-to-digital conversion; detection and estimation; process variations; stochastic systems

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Corey, R. (2015). Statistical inference with unreliable binary observations. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/72838

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Corey, Ryan. “Statistical inference with unreliable binary observations.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed November 17, 2019. http://hdl.handle.net/2142/72838.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Corey, Ryan. “Statistical inference with unreliable binary observations.” 2015. Web. 17 Nov 2019.

Vancouver:

Corey R. Statistical inference with unreliable binary observations. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/2142/72838.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Corey R. Statistical inference with unreliable binary observations. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/72838

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

8. Abellán Nebot, José Vicente. Prediction and improvement of part quality in multi-station machining systems applying the Stream of Variation model.

Degree: Departament d'Enginyeria de Sistemes Industrials i Disseny, 2011, Universitat Jaume I

 Recent research efforts have been aimed toward deriving mathematical models to relate manufacturing sources of variation with part quality variations in multi-station machining systems in… (more)

Subjects/Keywords: Stream of Variation; error propagation; machining systems; sensor-based fixtures; process oriented tolerancing; process planning; fixture-induced variations; machining-induced variations; Ingeniería de los Procesos de Fabricación; 62; 621

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Abellán Nebot, J. V. (2011). Prediction and improvement of part quality in multi-station machining systems applying the Stream of Variation model. (Thesis). Universitat Jaume I. Retrieved from http://hdl.handle.net/10803/134355

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Abellán Nebot, José Vicente. “Prediction and improvement of part quality in multi-station machining systems applying the Stream of Variation model.” 2011. Thesis, Universitat Jaume I. Accessed November 17, 2019. http://hdl.handle.net/10803/134355.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Abellán Nebot, José Vicente. “Prediction and improvement of part quality in multi-station machining systems applying the Stream of Variation model.” 2011. Web. 17 Nov 2019.

Vancouver:

Abellán Nebot JV. Prediction and improvement of part quality in multi-station machining systems applying the Stream of Variation model. [Internet] [Thesis]. Universitat Jaume I; 2011. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/10803/134355.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Abellán Nebot JV. Prediction and improvement of part quality in multi-station machining systems applying the Stream of Variation model. [Thesis]. Universitat Jaume I; 2011. Available from: http://hdl.handle.net/10803/134355

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

9. Veluswami, Senthilkumar. Statistical static timing analysis considering process variations and crosstalk.

Degree: 2005, Texas A&M University

 Increasing relative semiconductor process variations are making the prediction of realistic worst-case integrated circuit delay or sign-off yield more difficult. As process geometries shrink, intra-die… (more)

Subjects/Keywords: Timing analysis; Process variations; Crosstalk

…Circuits and Systems. 2 B. Process Variations As the feature size decreases, the influence of… …process variations on circuit design and performance is increasing manifold. Process variations… …can be classified into inter-die process variations and intra-die variations. Process… …parameters that change from die to die are called inter-die variations while process parameters… …has been found that the intra-die process variations of a gate are spatially correlated with… 

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Veluswami, S. (2005). Statistical static timing analysis considering process variations and crosstalk. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/2545

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Veluswami, Senthilkumar. “Statistical static timing analysis considering process variations and crosstalk.” 2005. Thesis, Texas A&M University. Accessed November 17, 2019. http://hdl.handle.net/1969.1/2545.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Veluswami, Senthilkumar. “Statistical static timing analysis considering process variations and crosstalk.” 2005. Web. 17 Nov 2019.

Vancouver:

Veluswami S. Statistical static timing analysis considering process variations and crosstalk. [Internet] [Thesis]. Texas A&M University; 2005. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/1969.1/2545.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Veluswami S. Statistical static timing analysis considering process variations and crosstalk. [Thesis]. Texas A&M University; 2005. Available from: http://hdl.handle.net/1969.1/2545

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

10. Mushtaq, Muhammad Umar. Reliability and Power Analysis of FinFET-based FPGAs.

Degree: MS, Computer Science and Engineering, 2008, Penn State University

 This thesis presents the results of exploring hitherto unchartered territory for the emerging FinFET device: FPGAs. As the inexorable descent to lower technology nodes continues… (more)

Subjects/Keywords: FPGA; FinFET; Soft-Error; Process Variations; Sub-Threshold Leakage; Independent Gate Control

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mushtaq, M. U. (2008). Reliability and Power Analysis of FinFET-based FPGAs. (Masters Thesis). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/8699

Chicago Manual of Style (16th Edition):

Mushtaq, Muhammad Umar. “Reliability and Power Analysis of FinFET-based FPGAs.” 2008. Masters Thesis, Penn State University. Accessed November 17, 2019. https://etda.libraries.psu.edu/catalog/8699.

MLA Handbook (7th Edition):

Mushtaq, Muhammad Umar. “Reliability and Power Analysis of FinFET-based FPGAs.” 2008. Web. 17 Nov 2019.

Vancouver:

Mushtaq MU. Reliability and Power Analysis of FinFET-based FPGAs. [Internet] [Masters thesis]. Penn State University; 2008. [cited 2019 Nov 17]. Available from: https://etda.libraries.psu.edu/catalog/8699.

Council of Science Editors:

Mushtaq MU. Reliability and Power Analysis of FinFET-based FPGAs. [Masters Thesis]. Penn State University; 2008. Available from: https://etda.libraries.psu.edu/catalog/8699


University of Southern California

11. Das, Prasanjeet. A variation aware resilient framework for post-silicon delay validation of high performance circuits.

Degree: PhD, Electrical Engineering, 2013, University of Southern California

 Despite advances in design and verification, it is becoming increasingly common for high-performance designs to misbehave on silicon. This is due to performance issues, such… (more)

Subjects/Keywords: post-silicon; delay validation; marginality; process variations; delay model; multiple input switching

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Das, P. (2013). A variation aware resilient framework for post-silicon delay validation of high performance circuits. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/219698/rec/446

Chicago Manual of Style (16th Edition):

Das, Prasanjeet. “A variation aware resilient framework for post-silicon delay validation of high performance circuits.” 2013. Doctoral Dissertation, University of Southern California. Accessed November 17, 2019. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/219698/rec/446.

MLA Handbook (7th Edition):

Das, Prasanjeet. “A variation aware resilient framework for post-silicon delay validation of high performance circuits.” 2013. Web. 17 Nov 2019.

Vancouver:

Das P. A variation aware resilient framework for post-silicon delay validation of high performance circuits. [Internet] [Doctoral dissertation]. University of Southern California; 2013. [cited 2019 Nov 17]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/219698/rec/446.

Council of Science Editors:

Das P. A variation aware resilient framework for post-silicon delay validation of high performance circuits. [Doctoral Dissertation]. University of Southern California; 2013. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/219698/rec/446


Vanderbilt University

12. Kou, Lingbo. Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region.

Degree: MS, Electrical Engineering, 2014, Vanderbilt University

 Power consumption has become a major concern of integrated circuit (IC) design. Reducing the supply voltage to the near-threshold region is one method to reduce… (more)

Subjects/Keywords: flip-flop; radiation-induced soft errors; sram; near-threshold voltage; critical charge; process variations; reliability

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kou, L. (2014). Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region. (Masters Thesis). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-04082014-141041/ ;

Chicago Manual of Style (16th Edition):

Kou, Lingbo. “Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region.” 2014. Masters Thesis, Vanderbilt University. Accessed November 17, 2019. http://etd.library.vanderbilt.edu/available/etd-04082014-141041/ ;.

MLA Handbook (7th Edition):

Kou, Lingbo. “Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region.” 2014. Web. 17 Nov 2019.

Vancouver:

Kou L. Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region. [Internet] [Masters thesis]. Vanderbilt University; 2014. [cited 2019 Nov 17]. Available from: http://etd.library.vanderbilt.edu/available/etd-04082014-141041/ ;.

Council of Science Editors:

Kou L. Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region. [Masters Thesis]. Vanderbilt University; 2014. Available from: http://etd.library.vanderbilt.edu/available/etd-04082014-141041/ ;

13. LEE CHEE SING. A framework to explore low-power architecture and variability-aware timing estimation of FPGAs.

Degree: 2007, National University of Singapore

Subjects/Keywords: FPGA; VPR; Affine; process variations; reconfigurable

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

SING, L. C. (2007). A framework to explore low-power architecture and variability-aware timing estimation of FPGAs. (Thesis). National University of Singapore. Retrieved from http://scholarbank.nus.edu.sg/handle/10635/23150

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

SING, LEE CHEE. “A framework to explore low-power architecture and variability-aware timing estimation of FPGAs.” 2007. Thesis, National University of Singapore. Accessed November 17, 2019. http://scholarbank.nus.edu.sg/handle/10635/23150.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

SING, LEE CHEE. “A framework to explore low-power architecture and variability-aware timing estimation of FPGAs.” 2007. Web. 17 Nov 2019.

Vancouver:

SING LC. A framework to explore low-power architecture and variability-aware timing estimation of FPGAs. [Internet] [Thesis]. National University of Singapore; 2007. [cited 2019 Nov 17]. Available from: http://scholarbank.nus.edu.sg/handle/10635/23150.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

SING LC. A framework to explore low-power architecture and variability-aware timing estimation of FPGAs. [Thesis]. National University of Singapore; 2007. Available from: http://scholarbank.nus.edu.sg/handle/10635/23150

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Colorado State University

14. Chittamuru, Sai Vineel Reddy. Reliable, energy-efficient, and secure silicon photonic network-on-chip design for manycore architectures.

Degree: PhD, Electrical and Computer Engineering, 2018, Colorado State University

 Advances in technology scaling over the past s+H91everal decades have enabled the integration of billions of transistors on a single die. Such a massive number… (more)

Subjects/Keywords: Hardware Security; Photonic Network on Chip; Reliability; MR Aging; Crosstalk Noise; Process and Thermal Variations

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chittamuru, S. V. R. (2018). Reliable, energy-efficient, and secure silicon photonic network-on-chip design for manycore architectures. (Doctoral Dissertation). Colorado State University. Retrieved from http://hdl.handle.net/10217/189288

Chicago Manual of Style (16th Edition):

Chittamuru, Sai Vineel Reddy. “Reliable, energy-efficient, and secure silicon photonic network-on-chip design for manycore architectures.” 2018. Doctoral Dissertation, Colorado State University. Accessed November 17, 2019. http://hdl.handle.net/10217/189288.

MLA Handbook (7th Edition):

Chittamuru, Sai Vineel Reddy. “Reliable, energy-efficient, and secure silicon photonic network-on-chip design for manycore architectures.” 2018. Web. 17 Nov 2019.

Vancouver:

Chittamuru SVR. Reliable, energy-efficient, and secure silicon photonic network-on-chip design for manycore architectures. [Internet] [Doctoral dissertation]. Colorado State University; 2018. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/10217/189288.

Council of Science Editors:

Chittamuru SVR. Reliable, energy-efficient, and secure silicon photonic network-on-chip design for manycore architectures. [Doctoral Dissertation]. Colorado State University; 2018. Available from: http://hdl.handle.net/10217/189288


Texas A&M University

15. Garg, Rajesh. Analysis and Design of Resilient VLSI Circuits.

Degree: 2010, Texas A&M University

 The reliable operation of Integrated Circuits (ICs) has become increasingly difficult to achieve in the deep sub-micron (DSM) era. With continuously decreasing device feature sizes,… (more)

Subjects/Keywords: Radiation Particle Strikes; Single Event Upsets (SEUs); Soft Errors; Single Event Transients; Design; Analysis; Modeling; DVS; Process Variations

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Garg, R. (2010). Analysis and Design of Resilient VLSI Circuits. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2009-05-410

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Garg, Rajesh. “Analysis and Design of Resilient VLSI Circuits.” 2010. Thesis, Texas A&M University. Accessed November 17, 2019. http://hdl.handle.net/1969.1/ETD-TAMU-2009-05-410.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Garg, Rajesh. “Analysis and Design of Resilient VLSI Circuits.” 2010. Web. 17 Nov 2019.

Vancouver:

Garg R. Analysis and Design of Resilient VLSI Circuits. [Internet] [Thesis]. Texas A&M University; 2010. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2009-05-410.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Garg R. Analysis and Design of Resilient VLSI Circuits. [Thesis]. Texas A&M University; 2010. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2009-05-410

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

16. Srinivasan, Suresh. Toward Low Power and Reliable FPGA Design.

Degree: PhD, Computer Science and Engineering, 2007, Penn State University

 Field Programmable Gate Arrays (FPGAs) are seen to be the emerging future architectures due to their extremely low NRE costs and tremendous design flexibility. This… (more)

Subjects/Keywords: Soft Errors; Leakage Power; Permanent Failures; FPGAs; Process Variations

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Srinivasan, S. (2007). Toward Low Power and Reliable FPGA Design. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/7915

Chicago Manual of Style (16th Edition):

Srinivasan, Suresh. “Toward Low Power and Reliable FPGA Design.” 2007. Doctoral Dissertation, Penn State University. Accessed November 17, 2019. https://etda.libraries.psu.edu/catalog/7915.

MLA Handbook (7th Edition):

Srinivasan, Suresh. “Toward Low Power and Reliable FPGA Design.” 2007. Web. 17 Nov 2019.

Vancouver:

Srinivasan S. Toward Low Power and Reliable FPGA Design. [Internet] [Doctoral dissertation]. Penn State University; 2007. [cited 2019 Nov 17]. Available from: https://etda.libraries.psu.edu/catalog/7915.

Council of Science Editors:

Srinivasan S. Toward Low Power and Reliable FPGA Design. [Doctoral Dissertation]. Penn State University; 2007. Available from: https://etda.libraries.psu.edu/catalog/7915


University of Waterloo

17. Jaramillo Ramirez, Rodrigo. Variability-Aware Design of Subthreshold Devices.

Degree: 2007, University of Waterloo

 Over the last 10 years, digital subthreshold logic circuits have been developed for applications in the ultra-low power design domain, where performance is not the… (more)

Subjects/Keywords: subthreshold operation; device yield; process variations; leakage current

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jaramillo Ramirez, R. (2007). Variability-Aware Design of Subthreshold Devices. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/3156

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jaramillo Ramirez, Rodrigo. “Variability-Aware Design of Subthreshold Devices.” 2007. Thesis, University of Waterloo. Accessed November 17, 2019. http://hdl.handle.net/10012/3156.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jaramillo Ramirez, Rodrigo. “Variability-Aware Design of Subthreshold Devices.” 2007. Web. 17 Nov 2019.

Vancouver:

Jaramillo Ramirez R. Variability-Aware Design of Subthreshold Devices. [Internet] [Thesis]. University of Waterloo; 2007. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/10012/3156.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jaramillo Ramirez R. Variability-Aware Design of Subthreshold Devices. [Thesis]. University of Waterloo; 2007. Available from: http://hdl.handle.net/10012/3156

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Waterloo

18. Rennie, David J. Analysis and Design of Robust Multi-Gb/s Clock and Data Recovery Circuits.

Degree: 2007, University of Waterloo

 The bandwidth demands of modern computing systems have been continually increasing and the recent focus on parallel processing will only increase the demands placed on… (more)

Subjects/Keywords: clock and data recovery; CMOS; process variations; calibration

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Rennie, D. J. (2007). Analysis and Design of Robust Multi-Gb/s Clock and Data Recovery Circuits. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/3312

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Rennie, David J. “Analysis and Design of Robust Multi-Gb/s Clock and Data Recovery Circuits.” 2007. Thesis, University of Waterloo. Accessed November 17, 2019. http://hdl.handle.net/10012/3312.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Rennie, David J. “Analysis and Design of Robust Multi-Gb/s Clock and Data Recovery Circuits.” 2007. Web. 17 Nov 2019.

Vancouver:

Rennie DJ. Analysis and Design of Robust Multi-Gb/s Clock and Data Recovery Circuits. [Internet] [Thesis]. University of Waterloo; 2007. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/10012/3312.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Rennie DJ. Analysis and Design of Robust Multi-Gb/s Clock and Data Recovery Circuits. [Thesis]. University of Waterloo; 2007. Available from: http://hdl.handle.net/10012/3312

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

19. Dolatshahi, Sepideh. Information Theoretic Identification and Compensation of Nonlinear Devices.

Degree: MS, Electrical & Computer Engineering, 2009, University of Massachusetts

 Breaking the anonymity of different wireless users with the purpose of decreasing internet crime rates is addressed in this thesis by considering radiometric identification techniques.… (more)

Subjects/Keywords: Radiometric identification; Volterra series; GLRT; Breaking anonymity; process variations; information theoretic; Signal Processing; Systems and Communications

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dolatshahi, S. (2009). Information Theoretic Identification and Compensation of Nonlinear Devices. (Masters Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/theses/325

Chicago Manual of Style (16th Edition):

Dolatshahi, Sepideh. “Information Theoretic Identification and Compensation of Nonlinear Devices.” 2009. Masters Thesis, University of Massachusetts. Accessed November 17, 2019. https://scholarworks.umass.edu/theses/325.

MLA Handbook (7th Edition):

Dolatshahi, Sepideh. “Information Theoretic Identification and Compensation of Nonlinear Devices.” 2009. Web. 17 Nov 2019.

Vancouver:

Dolatshahi S. Information Theoretic Identification and Compensation of Nonlinear Devices. [Internet] [Masters thesis]. University of Massachusetts; 2009. [cited 2019 Nov 17]. Available from: https://scholarworks.umass.edu/theses/325.

Council of Science Editors:

Dolatshahi S. Information Theoretic Identification and Compensation of Nonlinear Devices. [Masters Thesis]. University of Massachusetts; 2009. Available from: https://scholarworks.umass.edu/theses/325

20. Datta, Basab. On-chip Thermal Sensing In Deep Sub-micron Cmos.

Degree: MS, Electrical & Computer Engineering, 2007, University of Massachusetts

 ON-CHIP THERMAL SENSING IN DEEP SUB-MICRON CMOS August 2007 BASAB DATTA B.S., G.G.S. INDRAPRASTHA UNIVERSITY, NEW DELHI M.S.E.C.E, UNIVERSITY OF MASSACHUSETTS AMHERST Directed by: Professor… (more)

Subjects/Keywords: Thermal Sensor; Process variations; Supply noise; Power; Interconnect; Oscillator

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Datta, B. (2007). On-chip Thermal Sensing In Deep Sub-micron Cmos. (Masters Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/theses/52

Chicago Manual of Style (16th Edition):

Datta, Basab. “On-chip Thermal Sensing In Deep Sub-micron Cmos.” 2007. Masters Thesis, University of Massachusetts. Accessed November 17, 2019. https://scholarworks.umass.edu/theses/52.

MLA Handbook (7th Edition):

Datta, Basab. “On-chip Thermal Sensing In Deep Sub-micron Cmos.” 2007. Web. 17 Nov 2019.

Vancouver:

Datta B. On-chip Thermal Sensing In Deep Sub-micron Cmos. [Internet] [Masters thesis]. University of Massachusetts; 2007. [cited 2019 Nov 17]. Available from: https://scholarworks.umass.edu/theses/52.

Council of Science Editors:

Datta B. On-chip Thermal Sensing In Deep Sub-micron Cmos. [Masters Thesis]. University of Massachusetts; 2007. Available from: https://scholarworks.umass.edu/theses/52


University of Illinois – Urbana-Champaign

21. Karpuzcu, Rahmet. Novel many-core architectures for energy-efficiency.

Degree: PhD, 1200, 2012, University of Illinois – Urbana-Champaign

 Ideal CMOS device scaling relies on scaling voltages down with lithographic dimensions at every technology generation. This gives rise to faster circuits due to higher… (more)

Subjects/Keywords: Power constraints; Dark silicon; Near-threshold voltage; Many-core architectures; Process variations; Static random-access memory (SRAM) fault models; Wear-Out

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Karpuzcu, R. (2012). Novel many-core architectures for energy-efficiency. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/34560

Chicago Manual of Style (16th Edition):

Karpuzcu, Rahmet. “Novel many-core architectures for energy-efficiency.” 2012. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed November 17, 2019. http://hdl.handle.net/2142/34560.

MLA Handbook (7th Edition):

Karpuzcu, Rahmet. “Novel many-core architectures for energy-efficiency.” 2012. Web. 17 Nov 2019.

Vancouver:

Karpuzcu R. Novel many-core architectures for energy-efficiency. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2012. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/2142/34560.

Council of Science Editors:

Karpuzcu R. Novel many-core architectures for energy-efficiency. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2012. Available from: http://hdl.handle.net/2142/34560


University of South Florida

22. Challa, Rohith Prasad. SR Flip-Flop Based Physically Unclonable Function (PUF) for Hardware Security.

Degree: 2018, University of South Florida

 Physically Unclonable Functions (PUFs) are now widely being used to uniquely identify Integrated Circuits (ICs). In this work, we propose a novel Set-Reset (SR) Flip-flop… (more)

Subjects/Keywords: Challenge Response Pairs; Inter Chip Variation; Intra Chip Variation; Process Variations; Race Condition; Weak PUF; Strong PUF; Computer Engineering

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Challa, R. P. (2018). SR Flip-Flop Based Physically Unclonable Function (PUF) for Hardware Security. (Thesis). University of South Florida. Retrieved from https://scholarcommons.usf.edu/etd/7669

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Challa, Rohith Prasad. “SR Flip-Flop Based Physically Unclonable Function (PUF) for Hardware Security.” 2018. Thesis, University of South Florida. Accessed November 17, 2019. https://scholarcommons.usf.edu/etd/7669.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Challa, Rohith Prasad. “SR Flip-Flop Based Physically Unclonable Function (PUF) for Hardware Security.” 2018. Web. 17 Nov 2019.

Vancouver:

Challa RP. SR Flip-Flop Based Physically Unclonable Function (PUF) for Hardware Security. [Internet] [Thesis]. University of South Florida; 2018. [cited 2019 Nov 17]. Available from: https://scholarcommons.usf.edu/etd/7669.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Challa RP. SR Flip-Flop Based Physically Unclonable Function (PUF) for Hardware Security. [Thesis]. University of South Florida; 2018. Available from: https://scholarcommons.usf.edu/etd/7669

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

23. Phan, Ngoc Anh. Simulation of time-dependent crack propagation in a quasi-brittle material under relative humidity variations based on cohesive zone approach : application to wood : Simulation de la propagation de fissures dans un matériau quasifragile soumis à des variations d’humidité relative selon une approche de zone cohésive : application au bois.

Degree: Docteur es, Mécanique, 2016, Bordeaux

Cette thèse est consacrée à la simulation du comportement à la rupture de bois sous des chargements à long terme et sous des conditions d'Humidité… (more)

Subjects/Keywords: Quasi-fragile; Variations d’humidité relative; Bois; Zone cohésive; Fracture process zone; Propagation de fissure; Mécanosorption; Couplage; Quasi-brittle; Relative humidity variations; Wood; Cohesive zone; Fracture process zone; Time-dependent crack growth; Mechano-sorption; Coupling

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Phan, N. A. (2016). Simulation of time-dependent crack propagation in a quasi-brittle material under relative humidity variations based on cohesive zone approach : application to wood : Simulation de la propagation de fissures dans un matériau quasifragile soumis à des variations d’humidité relative selon une approche de zone cohésive : application au bois. (Doctoral Dissertation). Bordeaux. Retrieved from http://www.theses.fr/2016BORD0008

Chicago Manual of Style (16th Edition):

Phan, Ngoc Anh. “Simulation of time-dependent crack propagation in a quasi-brittle material under relative humidity variations based on cohesive zone approach : application to wood : Simulation de la propagation de fissures dans un matériau quasifragile soumis à des variations d’humidité relative selon une approche de zone cohésive : application au bois.” 2016. Doctoral Dissertation, Bordeaux. Accessed November 17, 2019. http://www.theses.fr/2016BORD0008.

MLA Handbook (7th Edition):

Phan, Ngoc Anh. “Simulation of time-dependent crack propagation in a quasi-brittle material under relative humidity variations based on cohesive zone approach : application to wood : Simulation de la propagation de fissures dans un matériau quasifragile soumis à des variations d’humidité relative selon une approche de zone cohésive : application au bois.” 2016. Web. 17 Nov 2019.

Vancouver:

Phan NA. Simulation of time-dependent crack propagation in a quasi-brittle material under relative humidity variations based on cohesive zone approach : application to wood : Simulation de la propagation de fissures dans un matériau quasifragile soumis à des variations d’humidité relative selon une approche de zone cohésive : application au bois. [Internet] [Doctoral dissertation]. Bordeaux; 2016. [cited 2019 Nov 17]. Available from: http://www.theses.fr/2016BORD0008.

Council of Science Editors:

Phan NA. Simulation of time-dependent crack propagation in a quasi-brittle material under relative humidity variations based on cohesive zone approach : application to wood : Simulation de la propagation de fissures dans un matériau quasifragile soumis à des variations d’humidité relative selon une approche de zone cohésive : application au bois. [Doctoral Dissertation]. Bordeaux; 2016. Available from: http://www.theses.fr/2016BORD0008

24. Exurville, Ingrid. Détection non destructive de modification malveillante de circuits intégrés : NON-DESTRUCTIVE DETECTION OF HARDWARE TROJANS IN INTEGRATED CIRCUITS.

Degree: Docteur es, Microélectronique, 2015, Saint-Etienne, EMSE

L'exportation et la mutualisation des industries de fabrication des circuits intégrés impliquent de nombreuses interrogations concernant l'intégrité des circuits fabriqués. On se retrouve alors confronté… (more)

Subjects/Keywords: Chevaux de Troie Matériel; Circuits Intégrés; Temps de Calcul; Glitchs d’Horloge; Contraintes Temporelles; Variations de Procédés; FPGA; Attaques en Faute; Hardware Trojans; Integrated circuits; Fault attack; Clock glitches; Timing constraints; FPGA; Process variations; Data Path Delays

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Exurville, I. (2015). Détection non destructive de modification malveillante de circuits intégrés : NON-DESTRUCTIVE DETECTION OF HARDWARE TROJANS IN INTEGRATED CIRCUITS. (Doctoral Dissertation). Saint-Etienne, EMSE. Retrieved from http://www.theses.fr/2015EMSE0800

Chicago Manual of Style (16th Edition):

Exurville, Ingrid. “Détection non destructive de modification malveillante de circuits intégrés : NON-DESTRUCTIVE DETECTION OF HARDWARE TROJANS IN INTEGRATED CIRCUITS.” 2015. Doctoral Dissertation, Saint-Etienne, EMSE. Accessed November 17, 2019. http://www.theses.fr/2015EMSE0800.

MLA Handbook (7th Edition):

Exurville, Ingrid. “Détection non destructive de modification malveillante de circuits intégrés : NON-DESTRUCTIVE DETECTION OF HARDWARE TROJANS IN INTEGRATED CIRCUITS.” 2015. Web. 17 Nov 2019.

Vancouver:

Exurville I. Détection non destructive de modification malveillante de circuits intégrés : NON-DESTRUCTIVE DETECTION OF HARDWARE TROJANS IN INTEGRATED CIRCUITS. [Internet] [Doctoral dissertation]. Saint-Etienne, EMSE; 2015. [cited 2019 Nov 17]. Available from: http://www.theses.fr/2015EMSE0800.

Council of Science Editors:

Exurville I. Détection non destructive de modification malveillante de circuits intégrés : NON-DESTRUCTIVE DETECTION OF HARDWARE TROJANS IN INTEGRATED CIRCUITS. [Doctoral Dissertation]. Saint-Etienne, EMSE; 2015. Available from: http://www.theses.fr/2015EMSE0800

25. Mhira, Souhir. Méthodes innovantes de gestion statique et dynamique de la fiabilité électrique des circuits CMOS M40 et 28FD sous conditions réelles d'utilisation (HTOL) : Innovative approaches to static and dynamic compensation schemes for Process and Aging variations in 40nm and 28nm FDSOI.

Degree: Docteur es, Sciences pour l'ingénieur. Micro et nanoélectronique, 2018, Aix Marseille Université

Cette thèse porte sur la conception et le test des premiers circuits CMOS auto-adaptatifs nanométriques dédiés aux applications automobiles, avioniques et aérospatiales, dans des environnements… (more)

Subjects/Keywords: Compensation; Vieillissement; Fdsoi; Automobile; Tension de bulk; Processeurs; Variations de procede; Boucle d'asservisement; Apprentisage automatique; Chaine de markov; Compensation; Aging; Process variations; Fdsoi; Body Bias; Automotive; Processors; Control loop; Machine learning; Markov chain

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mhira, S. (2018). Méthodes innovantes de gestion statique et dynamique de la fiabilité électrique des circuits CMOS M40 et 28FD sous conditions réelles d'utilisation (HTOL) : Innovative approaches to static and dynamic compensation schemes for Process and Aging variations in 40nm and 28nm FDSOI. (Doctoral Dissertation). Aix Marseille Université. Retrieved from http://www.theses.fr/2018AIXM0129

Chicago Manual of Style (16th Edition):

Mhira, Souhir. “Méthodes innovantes de gestion statique et dynamique de la fiabilité électrique des circuits CMOS M40 et 28FD sous conditions réelles d'utilisation (HTOL) : Innovative approaches to static and dynamic compensation schemes for Process and Aging variations in 40nm and 28nm FDSOI.” 2018. Doctoral Dissertation, Aix Marseille Université. Accessed November 17, 2019. http://www.theses.fr/2018AIXM0129.

MLA Handbook (7th Edition):

Mhira, Souhir. “Méthodes innovantes de gestion statique et dynamique de la fiabilité électrique des circuits CMOS M40 et 28FD sous conditions réelles d'utilisation (HTOL) : Innovative approaches to static and dynamic compensation schemes for Process and Aging variations in 40nm and 28nm FDSOI.” 2018. Web. 17 Nov 2019.

Vancouver:

Mhira S. Méthodes innovantes de gestion statique et dynamique de la fiabilité électrique des circuits CMOS M40 et 28FD sous conditions réelles d'utilisation (HTOL) : Innovative approaches to static and dynamic compensation schemes for Process and Aging variations in 40nm and 28nm FDSOI. [Internet] [Doctoral dissertation]. Aix Marseille Université 2018. [cited 2019 Nov 17]. Available from: http://www.theses.fr/2018AIXM0129.

Council of Science Editors:

Mhira S. Méthodes innovantes de gestion statique et dynamique de la fiabilité électrique des circuits CMOS M40 et 28FD sous conditions réelles d'utilisation (HTOL) : Innovative approaches to static and dynamic compensation schemes for Process and Aging variations in 40nm and 28nm FDSOI. [Doctoral Dissertation]. Aix Marseille Université 2018. Available from: http://www.theses.fr/2018AIXM0129

26. Vitale, Claudio Horacio. Dez peças para quinteto de sopros de György Ligeti: a gradação como uma ferramenta para a construção do discurso musical.

Degree: Mestrado, Processos de Criação Musical, 2008, University of São Paulo

O objetivo desta dissertação é descrever os processos graduais utilizados por György Ligeti na composição de sua obra Dez peças para quinteto de sopros (1968).… (more)

Subjects/Keywords: Dez Peças Para Quinteto de Sopros; Gradação; Gradual Process; György Ligeti; György Ligeti; Minimal Variations; Progressive Transformations; Ten Pieces For Wind Quintet; Transformações Progressivas; Variações Mínimas

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vitale, C. H. (2008). Dez peças para quinteto de sopros de György Ligeti: a gradação como uma ferramenta para a construção do discurso musical. (Masters Thesis). University of São Paulo. Retrieved from http://www.teses.usp.br/teses/disponiveis/27/27158/tde-28042009-101615/ ;

Chicago Manual of Style (16th Edition):

Vitale, Claudio Horacio. “Dez peças para quinteto de sopros de György Ligeti: a gradação como uma ferramenta para a construção do discurso musical.” 2008. Masters Thesis, University of São Paulo. Accessed November 17, 2019. http://www.teses.usp.br/teses/disponiveis/27/27158/tde-28042009-101615/ ;.

MLA Handbook (7th Edition):

Vitale, Claudio Horacio. “Dez peças para quinteto de sopros de György Ligeti: a gradação como uma ferramenta para a construção do discurso musical.” 2008. Web. 17 Nov 2019.

Vancouver:

Vitale CH. Dez peças para quinteto de sopros de György Ligeti: a gradação como uma ferramenta para a construção do discurso musical. [Internet] [Masters thesis]. University of São Paulo; 2008. [cited 2019 Nov 17]. Available from: http://www.teses.usp.br/teses/disponiveis/27/27158/tde-28042009-101615/ ;.

Council of Science Editors:

Vitale CH. Dez peças para quinteto de sopros de György Ligeti: a gradação como uma ferramenta para a construção do discurso musical. [Masters Thesis]. University of São Paulo; 2008. Available from: http://www.teses.usp.br/teses/disponiveis/27/27158/tde-28042009-101615/ ;


University of New South Wales

27. Yang, Yuanyuan. Power efficient current recycling linear regulators for biomedical implants.

Degree: Electrical Engineering & Telecommunications, 2012, University of New South Wales

 The current state-of-the-art power saving designs progressively evolve, boosted by the notable advancements in microelectronics technologies. However, due to scaling in size of the electrodes… (more)

Subjects/Keywords: Biomedical Implants; Current recycling; Linear regulator; Linear power supply; Neuro-stimulator; High-Voltage; CMOS; DMOS; Power saving; Current saving; Current efficiency; Process variations and mismatch

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yang, Y. (2012). Power efficient current recycling linear regulators for biomedical implants. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/51838 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:10505/SOURCE02?view=true

Chicago Manual of Style (16th Edition):

Yang, Yuanyuan. “Power efficient current recycling linear regulators for biomedical implants.” 2012. Doctoral Dissertation, University of New South Wales. Accessed November 17, 2019. http://handle.unsw.edu.au/1959.4/51838 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:10505/SOURCE02?view=true.

MLA Handbook (7th Edition):

Yang, Yuanyuan. “Power efficient current recycling linear regulators for biomedical implants.” 2012. Web. 17 Nov 2019.

Vancouver:

Yang Y. Power efficient current recycling linear regulators for biomedical implants. [Internet] [Doctoral dissertation]. University of New South Wales; 2012. [cited 2019 Nov 17]. Available from: http://handle.unsw.edu.au/1959.4/51838 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:10505/SOURCE02?view=true.

Council of Science Editors:

Yang Y. Power efficient current recycling linear regulators for biomedical implants. [Doctoral Dissertation]. University of New South Wales; 2012. Available from: http://handle.unsw.edu.au/1959.4/51838 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:10505/SOURCE02?view=true

28. Choudhary, Aarti. A Process Variation Tolerant Self-Compensation Sense Amplifier Design.

Degree: MS, Electrical & Computer Engineering, 2008, University of Massachusetts

  As we move under the aegis of the Moore's law, we have to deal with its darker side with problems like leakage and short… (more)

Subjects/Keywords: Sense Amplifier; Process Variations; FinFET; Electrical and Computer Engineering; Engineering

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Choudhary, A. (2008). A Process Variation Tolerant Self-Compensation Sense Amplifier Design. (Masters Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/theses/166

Chicago Manual of Style (16th Edition):

Choudhary, Aarti. “A Process Variation Tolerant Self-Compensation Sense Amplifier Design.” 2008. Masters Thesis, University of Massachusetts. Accessed November 17, 2019. https://scholarworks.umass.edu/theses/166.

MLA Handbook (7th Edition):

Choudhary, Aarti. “A Process Variation Tolerant Self-Compensation Sense Amplifier Design.” 2008. Web. 17 Nov 2019.

Vancouver:

Choudhary A. A Process Variation Tolerant Self-Compensation Sense Amplifier Design. [Internet] [Masters thesis]. University of Massachusetts; 2008. [cited 2019 Nov 17]. Available from: https://scholarworks.umass.edu/theses/166.

Council of Science Editors:

Choudhary A. A Process Variation Tolerant Self-Compensation Sense Amplifier Design. [Masters Thesis]. University of Massachusetts; 2008. Available from: https://scholarworks.umass.edu/theses/166


Northeastern University

29. Ni, Yuchi. Low-power CMOS relaxation oscillator design with an on-chip circuit for combined temperature-compensated reference voltage and current generation.

Degree: MS, Department of Electrical and Computer Engineering, 2013, Northeastern University

 Low-power oscillators are essential components of battery-powered medical devices for which the battery life must be maximized, such as pacemakers, blood glucose meters and heart… (more)

Subjects/Keywords: CMOS process variations; Low-power analog design; Reference current generation; Reference voltage generation; Relaxation oscillator; Temperature compensation; Electrical and Computer Engineering; Engineering

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ni, Y. (2013). Low-power CMOS relaxation oscillator design with an on-chip circuit for combined temperature-compensated reference voltage and current generation. (Masters Thesis). Northeastern University. Retrieved from http://hdl.handle.net/2047/d20004909

Chicago Manual of Style (16th Edition):

Ni, Yuchi. “Low-power CMOS relaxation oscillator design with an on-chip circuit for combined temperature-compensated reference voltage and current generation.” 2013. Masters Thesis, Northeastern University. Accessed November 17, 2019. http://hdl.handle.net/2047/d20004909.

MLA Handbook (7th Edition):

Ni, Yuchi. “Low-power CMOS relaxation oscillator design with an on-chip circuit for combined temperature-compensated reference voltage and current generation.” 2013. Web. 17 Nov 2019.

Vancouver:

Ni Y. Low-power CMOS relaxation oscillator design with an on-chip circuit for combined temperature-compensated reference voltage and current generation. [Internet] [Masters thesis]. Northeastern University; 2013. [cited 2019 Nov 17]. Available from: http://hdl.handle.net/2047/d20004909.

Council of Science Editors:

Ni Y. Low-power CMOS relaxation oscillator design with an on-chip circuit for combined temperature-compensated reference voltage and current generation. [Masters Thesis]. Northeastern University; 2013. Available from: http://hdl.handle.net/2047/d20004909

30. Griffin, William Paul. Variation-Derived Chip Security And Accelerated Simulation Of Variations.

Degree: PhD, Electrical and Computer Engineering, 2013, Purdue University

  In modern ICs, variations can be quite troublesome. Ensuring quality and yield requires careful and resource-intensive simulation under the effects of parameter variations. Threshold… (more)

Subjects/Keywords: hardware security; mosfet simulation; process variations; Electrical and Computer Engineering

…common approximation method for simplifying process variations’ role is to represent process… …as it offers both a convenient means to simulate process variations, and it conveys a vast… …Process variations arise from acceptable imperfections during manufacture; these imperfections… …stability, random logic timing, and their associated power usage. Handling process variations… …express process variations in lieu of simulation using variations in the original L, W , tox… 

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Griffin, W. P. (2013). Variation-Derived Chip Security And Accelerated Simulation Of Variations. (Doctoral Dissertation). Purdue University. Retrieved from https://docs.lib.purdue.edu/open_access_dissertations/158

Chicago Manual of Style (16th Edition):

Griffin, William Paul. “Variation-Derived Chip Security And Accelerated Simulation Of Variations.” 2013. Doctoral Dissertation, Purdue University. Accessed November 17, 2019. https://docs.lib.purdue.edu/open_access_dissertations/158.

MLA Handbook (7th Edition):

Griffin, William Paul. “Variation-Derived Chip Security And Accelerated Simulation Of Variations.” 2013. Web. 17 Nov 2019.

Vancouver:

Griffin WP. Variation-Derived Chip Security And Accelerated Simulation Of Variations. [Internet] [Doctoral dissertation]. Purdue University; 2013. [cited 2019 Nov 17]. Available from: https://docs.lib.purdue.edu/open_access_dissertations/158.

Council of Science Editors:

Griffin WP. Variation-Derived Chip Security And Accelerated Simulation Of Variations. [Doctoral Dissertation]. Purdue University; 2013. Available from: https://docs.lib.purdue.edu/open_access_dissertations/158

[1] [2]

.