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You searched for subject:(phase locked loop ). Showing records 1 – 30 of 14728 total matches.

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California State University – Sacramento

1. Sawant, Sanjeet. Time-to-digital converter for an all-digital phase-locked loop.

Degree: MS, Electrical and Electronic Engineering, 2017, California State University – Sacramento

 A phase-locked loop (PLL) is a widely-used mixed-signal circuit that is used to create the precise clocks required on almost every integrated circuit. A PLL… (more)

Subjects/Keywords: Phase-locked loop; PLL

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sawant, S. (2017). Time-to-digital converter for an all-digital phase-locked loop. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.3/190765

Chicago Manual of Style (16th Edition):

Sawant, Sanjeet. “Time-to-digital converter for an all-digital phase-locked loop.” 2017. Masters Thesis, California State University – Sacramento. Accessed September 19, 2020. http://hdl.handle.net/10211.3/190765.

MLA Handbook (7th Edition):

Sawant, Sanjeet. “Time-to-digital converter for an all-digital phase-locked loop.” 2017. Web. 19 Sep 2020.

Vancouver:

Sawant S. Time-to-digital converter for an all-digital phase-locked loop. [Internet] [Masters thesis]. California State University – Sacramento; 2017. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/10211.3/190765.

Council of Science Editors:

Sawant S. Time-to-digital converter for an all-digital phase-locked loop. [Masters Thesis]. California State University – Sacramento; 2017. Available from: http://hdl.handle.net/10211.3/190765


Anna University

2. Dhurga devi J. Investigations on performance Improvements of self biased Adaptive bandwidth PLLS;.

Degree: Investigations on performance Improvements of self biased Adaptive bandwidth PLLS, 2015, Anna University

The present research work attempts a number of modifications of newlinethe well established self biased adaptive bandwidth Phase Locked Loop newline PLLs These modifications are… (more)

Subjects/Keywords: Delay Locked Loop; Microprocessor clock generation; Phase Locked Loop

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APA (6th Edition):

J, D. d. (2015). Investigations on performance Improvements of self biased Adaptive bandwidth PLLS;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/49446

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

J, Dhurga devi. “Investigations on performance Improvements of self biased Adaptive bandwidth PLLS;.” 2015. Thesis, Anna University. Accessed September 19, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/49446.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

J, Dhurga devi. “Investigations on performance Improvements of self biased Adaptive bandwidth PLLS;.” 2015. Web. 19 Sep 2020.

Vancouver:

J Dd. Investigations on performance Improvements of self biased Adaptive bandwidth PLLS;. [Internet] [Thesis]. Anna University; 2015. [cited 2020 Sep 19]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/49446.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

J Dd. Investigations on performance Improvements of self biased Adaptive bandwidth PLLS;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/49446

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

3. Chang, Chun-Yuan. The Digital Delay-Controlled SAR Delay Locked-Loop with Low Power in Sleep Mode.

Degree: Master, Computer Science and Engineering, 2011, NSYSU

 A successive approximation register (SAR) circuit is adopted to control the digital delay line in the delay-locked loop (DLL) to achieve very fast locking effect… (more)

Subjects/Keywords: Sleep Mode; Low Power; CMOS; Phase-Locked Loop; Delay-Locked Loop

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APA (6th Edition):

Chang, C. (2011). The Digital Delay-Controlled SAR Delay Locked-Loop with Low Power in Sleep Mode. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0812111-115518

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chang, Chun-Yuan. “The Digital Delay-Controlled SAR Delay Locked-Loop with Low Power in Sleep Mode.” 2011. Thesis, NSYSU. Accessed September 19, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0812111-115518.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chang, Chun-Yuan. “The Digital Delay-Controlled SAR Delay Locked-Loop with Low Power in Sleep Mode.” 2011. Web. 19 Sep 2020.

Vancouver:

Chang C. The Digital Delay-Controlled SAR Delay Locked-Loop with Low Power in Sleep Mode. [Internet] [Thesis]. NSYSU; 2011. [cited 2020 Sep 19]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0812111-115518.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chang C. The Digital Delay-Controlled SAR Delay Locked-Loop with Low Power in Sleep Mode. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0812111-115518

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

4. Wei, Da. Clock synthesizer design with analog and digital phase locked loop.

Degree: MS, 1200, 2014, University of Illinois – Urbana-Champaign

 As process technology has aggressively scaled, the demand for fast, robust computing has grown tremendously. With the rise of large scale data centers to handhold… (more)

Subjects/Keywords: All Digital Phase-Locked Loop (PLL); Charge Pump Phase-Locked Loop (PLL); Clock Synthesizer; Phase Locked Loop

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APA (6th Edition):

Wei, D. (2014). Clock synthesizer design with analog and digital phase locked loop. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/50472

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wei, Da. “Clock synthesizer design with analog and digital phase locked loop.” 2014. Thesis, University of Illinois – Urbana-Champaign. Accessed September 19, 2020. http://hdl.handle.net/2142/50472.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wei, Da. “Clock synthesizer design with analog and digital phase locked loop.” 2014. Web. 19 Sep 2020.

Vancouver:

Wei D. Clock synthesizer design with analog and digital phase locked loop. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2014. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/2142/50472.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wei D. Clock synthesizer design with analog and digital phase locked loop. [Thesis]. University of Illinois – Urbana-Champaign; 2014. Available from: http://hdl.handle.net/2142/50472

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

5. Lai, Pei-Ying. FPGA-Based Phase-Locked-Loop Frequency-Locking Algorithm for Ultrasonic Spray Coating System.

Degree: Master, Electrical Engineering, 2016, NSYSU

 A phase-locked-loop frequency-locking algorithm implemented on an FPGA is presented for an ultrasonic spray coating system. The algorithm generates a sine wave for driving the… (more)

Subjects/Keywords: FPGA; ultrasonic transducer; phase-locked-loop

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lai, P. (2016). FPGA-Based Phase-Locked-Loop Frequency-Locking Algorithm for Ultrasonic Spray Coating System. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0026116-174014

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lai, Pei-Ying. “FPGA-Based Phase-Locked-Loop Frequency-Locking Algorithm for Ultrasonic Spray Coating System.” 2016. Thesis, NSYSU. Accessed September 19, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0026116-174014.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lai, Pei-Ying. “FPGA-Based Phase-Locked-Loop Frequency-Locking Algorithm for Ultrasonic Spray Coating System.” 2016. Web. 19 Sep 2020.

Vancouver:

Lai P. FPGA-Based Phase-Locked-Loop Frequency-Locking Algorithm for Ultrasonic Spray Coating System. [Internet] [Thesis]. NSYSU; 2016. [cited 2020 Sep 19]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0026116-174014.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lai P. FPGA-Based Phase-Locked-Loop Frequency-Locking Algorithm for Ultrasonic Spray Coating System. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0026116-174014

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

6. Liu, Yubo. Design of all digital phase-locked loop in serial link communication.

Degree: MS, Electrical & Computer Engr, 2015, University of Illinois – Urbana-Champaign

 The speed of wireline and wireless communication systems has been increasing aggressively over the past decade. Multi-GHz clocks are in demand more than ever. In… (more)

Subjects/Keywords: phase-locked loop (PLL); serial link; all digital phase-locked loop (ADPLL); jitter

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APA (6th Edition):

Liu, Y. (2015). Design of all digital phase-locked loop in serial link communication. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/78736

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Yubo. “Design of all digital phase-locked loop in serial link communication.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed September 19, 2020. http://hdl.handle.net/2142/78736.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Yubo. “Design of all digital phase-locked loop in serial link communication.” 2015. Web. 19 Sep 2020.

Vancouver:

Liu Y. Design of all digital phase-locked loop in serial link communication. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/2142/78736.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu Y. Design of all digital phase-locked loop in serial link communication. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/78736

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Wright State University

7. Keregudadhahalli, Rajesh Kumar. Costas PLL Loop System for BPSK Detection.

Degree: MSEgr, Electrical Engineering, 2008, Wright State University

  A 2GHz carrier recovery Costas Loop based BPSK detector is designed using CMOS 0.18µm technology. The designed BPSK detector consists of single to differential… (more)

Subjects/Keywords: Electrical Engineering; Costas Phase Locked Loop; PLL Loop System; BPSK Detection

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APA (6th Edition):

Keregudadhahalli, R. K. (2008). Costas PLL Loop System for BPSK Detection. (Masters Thesis). Wright State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=wright1220921515

Chicago Manual of Style (16th Edition):

Keregudadhahalli, Rajesh Kumar. “Costas PLL Loop System for BPSK Detection.” 2008. Masters Thesis, Wright State University. Accessed September 19, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=wright1220921515.

MLA Handbook (7th Edition):

Keregudadhahalli, Rajesh Kumar. “Costas PLL Loop System for BPSK Detection.” 2008. Web. 19 Sep 2020.

Vancouver:

Keregudadhahalli RK. Costas PLL Loop System for BPSK Detection. [Internet] [Masters thesis]. Wright State University; 2008. [cited 2020 Sep 19]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1220921515.

Council of Science Editors:

Keregudadhahalli RK. Costas PLL Loop System for BPSK Detection. [Masters Thesis]. Wright State University; 2008. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1220921515


Oregon State University

8. Brownlee, Merrick. Low noise clocking for high speed serial links.

Degree: PhD, Electrical and Computer Engineering, 2006, Oregon State University

 As the functionality of digital chips continues to increase dramatically, chip- to-chip communication bandwidths must scale accordingly to avoid constraining the overall system performance. Therefore,… (more)

Subjects/Keywords: Phase Locked Loop; Phase-locked loops

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APA (6th Edition):

Brownlee, M. (2006). Low noise clocking for high speed serial links. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/3506

Chicago Manual of Style (16th Edition):

Brownlee, Merrick. “Low noise clocking for high speed serial links.” 2006. Doctoral Dissertation, Oregon State University. Accessed September 19, 2020. http://hdl.handle.net/1957/3506.

MLA Handbook (7th Edition):

Brownlee, Merrick. “Low noise clocking for high speed serial links.” 2006. Web. 19 Sep 2020.

Vancouver:

Brownlee M. Low noise clocking for high speed serial links. [Internet] [Doctoral dissertation]. Oregon State University; 2006. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1957/3506.

Council of Science Editors:

Brownlee M. Low noise clocking for high speed serial links. [Doctoral Dissertation]. Oregon State University; 2006. Available from: http://hdl.handle.net/1957/3506


Oregon State University

9. Wu, Ting. Design techniques for PVT tolerant phase-locked loops.

Degree: PhD, Electrical and Computer Engineering, 2007, Oregon State University

 The continued scaling of deep-submicron CMOS technology enables low-voltage high-frequency phase-locked loops (PLLs) to be fully integrated in complex mixed-signal systems. However, fluctuations due to… (more)

Subjects/Keywords: phase-locked loop; Phase-locked loops

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APA (6th Edition):

Wu, T. (2007). Design techniques for PVT tolerant phase-locked loops. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/3866

Chicago Manual of Style (16th Edition):

Wu, Ting. “Design techniques for PVT tolerant phase-locked loops.” 2007. Doctoral Dissertation, Oregon State University. Accessed September 19, 2020. http://hdl.handle.net/1957/3866.

MLA Handbook (7th Edition):

Wu, Ting. “Design techniques for PVT tolerant phase-locked loops.” 2007. Web. 19 Sep 2020.

Vancouver:

Wu T. Design techniques for PVT tolerant phase-locked loops. [Internet] [Doctoral dissertation]. Oregon State University; 2007. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1957/3866.

Council of Science Editors:

Wu T. Design techniques for PVT tolerant phase-locked loops. [Doctoral Dissertation]. Oregon State University; 2007. Available from: http://hdl.handle.net/1957/3866


Indian Institute of Science

10. Raghavendra, R G. Summer-Less Dual Charge Pump Based PLL With Wide Lock Range Using Analog Frequency Detector.

Degree: MSc Engg, Faculty of Engineering, 2011, Indian Institute of Science

Phase Locked Loop (PLL) is an integral component of clock generation circuits. A third order Charge Pump PLL (CPPLL) is most widely employed PLL architecture… (more)

Subjects/Keywords: Special Devices (Computer Engineering); Analog Frequency Detector; Charge Pump Phase Locked Loop; Phase Locked Loop (PLL); Phase Locked Loop Filters; Phase Locked Loop Filter Design; Summer-Less Dual Charge Pump Based Loop Filters; Loop Filter Design; Computer Engineering

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APA (6th Edition):

Raghavendra, R. G. (2011). Summer-Less Dual Charge Pump Based PLL With Wide Lock Range Using Analog Frequency Detector. (Masters Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/1006

Chicago Manual of Style (16th Edition):

Raghavendra, R G. “Summer-Less Dual Charge Pump Based PLL With Wide Lock Range Using Analog Frequency Detector.” 2011. Masters Thesis, Indian Institute of Science. Accessed September 19, 2020. http://etd.iisc.ac.in/handle/2005/1006.

MLA Handbook (7th Edition):

Raghavendra, R G. “Summer-Less Dual Charge Pump Based PLL With Wide Lock Range Using Analog Frequency Detector.” 2011. Web. 19 Sep 2020.

Vancouver:

Raghavendra RG. Summer-Less Dual Charge Pump Based PLL With Wide Lock Range Using Analog Frequency Detector. [Internet] [Masters thesis]. Indian Institute of Science; 2011. [cited 2020 Sep 19]. Available from: http://etd.iisc.ac.in/handle/2005/1006.

Council of Science Editors:

Raghavendra RG. Summer-Less Dual Charge Pump Based PLL With Wide Lock Range Using Analog Frequency Detector. [Masters Thesis]. Indian Institute of Science; 2011. Available from: http://etd.iisc.ac.in/handle/2005/1006


University of California – Berkeley

11. Marcu, Cristian. LO Generation and Distribution for 60GHz Phased Array Transceivers.

Degree: Electrical Engineering & Computer Sciences, 2011, University of California – Berkeley

 Increased memory capacity and processing power in mobile devices has created a need for radios that can transmit data at multi-Gb/s rates over a short… (more)

Subjects/Keywords: Electrical engineering; 60GHz; CMOS; mm-wave; oscillator; phase-locked loop

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APA (6th Edition):

Marcu, C. (2011). LO Generation and Distribution for 60GHz Phased Array Transceivers. (Thesis). University of California – Berkeley. Retrieved from http://www.escholarship.org/uc/item/767642t2

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Marcu, Cristian. “LO Generation and Distribution for 60GHz Phased Array Transceivers.” 2011. Thesis, University of California – Berkeley. Accessed September 19, 2020. http://www.escholarship.org/uc/item/767642t2.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Marcu, Cristian. “LO Generation and Distribution for 60GHz Phased Array Transceivers.” 2011. Web. 19 Sep 2020.

Vancouver:

Marcu C. LO Generation and Distribution for 60GHz Phased Array Transceivers. [Internet] [Thesis]. University of California – Berkeley; 2011. [cited 2020 Sep 19]. Available from: http://www.escholarship.org/uc/item/767642t2.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Marcu C. LO Generation and Distribution for 60GHz Phased Array Transceivers. [Thesis]. University of California – Berkeley; 2011. Available from: http://www.escholarship.org/uc/item/767642t2

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

12. Kuo, Ting-wei. Phase Estimation for Phase-Locked-Loop Ultrasonic Drive.

Degree: Master, Electrical Engineering, 2018, NSYSU

 An ultrasonic drive requires frequency locking at its resonance for high vibration efficiency. Phase locked loop is a common approach to achieving this purpose. To… (more)

Subjects/Keywords: phase-locked loop; Newton's method; interpolation; ultrasonic driving; FPGA

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APA (6th Edition):

Kuo, T. (2018). Phase Estimation for Phase-Locked-Loop Ultrasonic Drive. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0507118-193218

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kuo, Ting-wei. “Phase Estimation for Phase-Locked-Loop Ultrasonic Drive.” 2018. Thesis, NSYSU. Accessed September 19, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0507118-193218.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kuo, Ting-wei. “Phase Estimation for Phase-Locked-Loop Ultrasonic Drive.” 2018. Web. 19 Sep 2020.

Vancouver:

Kuo T. Phase Estimation for Phase-Locked-Loop Ultrasonic Drive. [Internet] [Thesis]. NSYSU; 2018. [cited 2020 Sep 19]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0507118-193218.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kuo T. Phase Estimation for Phase-Locked-Loop Ultrasonic Drive. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0507118-193218

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

13. Narasimhan, Srinath S. Circuit Optimization Using Efficient Parallel Pattern Search.

Degree: MS, Electrical Engineering, 2011, Texas A&M University

 Circuit optimization is extremely important in order to design today's high performance integrated circuits. As systems become more and more complex, traditional optimization techniques are… (more)

Subjects/Keywords: APPS; Circuit Optimization; Clock Mesh; Phase Locked Loop; Skew; Lock Time

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APA (6th Edition):

Narasimhan, S. S. (2011). Circuit Optimization Using Efficient Parallel Pattern Search. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2010-05-7704

Chicago Manual of Style (16th Edition):

Narasimhan, Srinath S. “Circuit Optimization Using Efficient Parallel Pattern Search.” 2011. Masters Thesis, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2010-05-7704.

MLA Handbook (7th Edition):

Narasimhan, Srinath S. “Circuit Optimization Using Efficient Parallel Pattern Search.” 2011. Web. 19 Sep 2020.

Vancouver:

Narasimhan SS. Circuit Optimization Using Efficient Parallel Pattern Search. [Internet] [Masters thesis]. Texas A&M University; 2011. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-05-7704.

Council of Science Editors:

Narasimhan SS. Circuit Optimization Using Efficient Parallel Pattern Search. [Masters Thesis]. Texas A&M University; 2011. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-05-7704


Texas A&M University

14. Kwarteng, Ntiamoah. A Fast Transient Response ESR-Controlled Fixed Frequency Hysteretic Buck Converter.

Degree: MS, Electrical Engineering, 2016, Texas A&M University

 Modern application processors (microprocessors and Digital Signal Processors) are power hungry and demand power management solutions that can withstand their frequent and high slew-rate load… (more)

Subjects/Keywords: hysteretic; Buck Converter; phase-locked loop; equivalent sesries resistance; fixed frequency

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APA (6th Edition):

Kwarteng, N. (2016). A Fast Transient Response ESR-Controlled Fixed Frequency Hysteretic Buck Converter. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/157066

Chicago Manual of Style (16th Edition):

Kwarteng, Ntiamoah. “A Fast Transient Response ESR-Controlled Fixed Frequency Hysteretic Buck Converter.” 2016. Masters Thesis, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/157066.

MLA Handbook (7th Edition):

Kwarteng, Ntiamoah. “A Fast Transient Response ESR-Controlled Fixed Frequency Hysteretic Buck Converter.” 2016. Web. 19 Sep 2020.

Vancouver:

Kwarteng N. A Fast Transient Response ESR-Controlled Fixed Frequency Hysteretic Buck Converter. [Internet] [Masters thesis]. Texas A&M University; 2016. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/157066.

Council of Science Editors:

Kwarteng N. A Fast Transient Response ESR-Controlled Fixed Frequency Hysteretic Buck Converter. [Masters Thesis]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/157066


Texas A&M University

15. Park, Sang Wook. Oscillator Architectures and Enhanced Frequency Synthesizer.

Degree: PhD, Electrical Engineering, 2009, Texas A&M University

 A voltage controlled oscillator (VCO), that generates a periodic signal whose frequency is tuned by a voltage, is a key building block in any integrated… (more)

Subjects/Keywords: Oscillator; Phase locked loop

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APA (6th Edition):

Park, S. W. (2009). Oscillator Architectures and Enhanced Frequency Synthesizer. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/148445

Chicago Manual of Style (16th Edition):

Park, Sang Wook. “Oscillator Architectures and Enhanced Frequency Synthesizer.” 2009. Doctoral Dissertation, Texas A&M University. Accessed September 19, 2020. http://hdl.handle.net/1969.1/148445.

MLA Handbook (7th Edition):

Park, Sang Wook. “Oscillator Architectures and Enhanced Frequency Synthesizer.” 2009. Web. 19 Sep 2020.

Vancouver:

Park SW. Oscillator Architectures and Enhanced Frequency Synthesizer. [Internet] [Doctoral dissertation]. Texas A&M University; 2009. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1969.1/148445.

Council of Science Editors:

Park SW. Oscillator Architectures and Enhanced Frequency Synthesizer. [Doctoral Dissertation]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/148445


NSYSU

16. Chien, Yu-Tsun. A Load-Optimized 500 MHz VCO Design for Phase-Locked Loop and Half-Swing PLA and The Applications for High-Speed Circuit Design.

Degree: Master, Electrical Engineering, 2000, NSYSU

 The first topic of this thesis is a practical load-optimized VCO design for low-jitter 5V 500 MHz digital phase-locked loop. Besides the low jitter advantage,… (more)

Subjects/Keywords: Half-Swing; Phase-Locked Loop

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APA (6th Edition):

Chien, Y. (2000). A Load-Optimized 500 MHz VCO Design for Phase-Locked Loop and Half-Swing PLA and The Applications for High-Speed Circuit Design. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627100-162514

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chien, Yu-Tsun. “A Load-Optimized 500 MHz VCO Design for Phase-Locked Loop and Half-Swing PLA and The Applications for High-Speed Circuit Design.” 2000. Thesis, NSYSU. Accessed September 19, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627100-162514.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chien, Yu-Tsun. “A Load-Optimized 500 MHz VCO Design for Phase-Locked Loop and Half-Swing PLA and The Applications for High-Speed Circuit Design.” 2000. Web. 19 Sep 2020.

Vancouver:

Chien Y. A Load-Optimized 500 MHz VCO Design for Phase-Locked Loop and Half-Swing PLA and The Applications for High-Speed Circuit Design. [Internet] [Thesis]. NSYSU; 2000. [cited 2020 Sep 19]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627100-162514.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chien Y. A Load-Optimized 500 MHz VCO Design for Phase-Locked Loop and Half-Swing PLA and The Applications for High-Speed Circuit Design. [Thesis]. NSYSU; 2000. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627100-162514

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

17. Li, Chun-wei. Phase-Locked Double-Loop Speed Regulation of a Temperature controlled Fan.

Degree: Master, Electrical Engineering, 2009, NSYSU

 Cooling fans, widely used in desktop and laptop computers, have been designed toward the tendency of low noise and low consumption power. This thesis purposes… (more)

Subjects/Keywords: Sliding Mode; Relay Control; BLDC; Phase-Locked Loop

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APA (6th Edition):

Li, C. (2009). Phase-Locked Double-Loop Speed Regulation of a Temperature controlled Fan. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0824109-035945

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Li, Chun-wei. “Phase-Locked Double-Loop Speed Regulation of a Temperature controlled Fan.” 2009. Thesis, NSYSU. Accessed September 19, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0824109-035945.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Li, Chun-wei. “Phase-Locked Double-Loop Speed Regulation of a Temperature controlled Fan.” 2009. Web. 19 Sep 2020.

Vancouver:

Li C. Phase-Locked Double-Loop Speed Regulation of a Temperature controlled Fan. [Internet] [Thesis]. NSYSU; 2009. [cited 2020 Sep 19]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0824109-035945.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li C. Phase-Locked Double-Loop Speed Regulation of a Temperature controlled Fan. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0824109-035945

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

18. Pereira de Arruda, Josué. Métodos de sincronização de conversores em sistemas de geração distribuída .

Degree: 2008, Universidade Federal de Pernambuco

 O uso de conversores de freqüência CC/CA para integrar a energia renovável como uma fonte de geração distribuída tem se tornado cada vez mais comum.… (more)

Subjects/Keywords: Geração distribuída; Métodos de sincronização; Phase locked loop; Eletrônica de potência

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APA (6th Edition):

Pereira de Arruda, J. (2008). Métodos de sincronização de conversores em sistemas de geração distribuída . (Thesis). Universidade Federal de Pernambuco. Retrieved from http://repositorio.ufpe.br/handle/123456789/5274

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pereira de Arruda, Josué. “Métodos de sincronização de conversores em sistemas de geração distribuída .” 2008. Thesis, Universidade Federal de Pernambuco. Accessed September 19, 2020. http://repositorio.ufpe.br/handle/123456789/5274.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pereira de Arruda, Josué. “Métodos de sincronização de conversores em sistemas de geração distribuída .” 2008. Web. 19 Sep 2020.

Vancouver:

Pereira de Arruda J. Métodos de sincronização de conversores em sistemas de geração distribuída . [Internet] [Thesis]. Universidade Federal de Pernambuco; 2008. [cited 2020 Sep 19]. Available from: http://repositorio.ufpe.br/handle/123456789/5274.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pereira de Arruda J. Métodos de sincronização de conversores em sistemas de geração distribuída . [Thesis]. Universidade Federal de Pernambuco; 2008. Available from: http://repositorio.ufpe.br/handle/123456789/5274

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

19. Coombs, Daniel R. Ring oscillator based injection locked clock multiplier.

Degree: MS, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 This thesis describes a ring-based injection locked clock multiplier (ILCM) designed with the goal of generating a high-frequency and low-jitter clock. Building on prior research… (more)

Subjects/Keywords: Phase-locked loop; Injection locking; Ring oscillator; High-performance clocking

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APA (6th Edition):

Coombs, D. R. (2017). Ring oscillator based injection locked clock multiplier. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/97744

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Coombs, Daniel R. “Ring oscillator based injection locked clock multiplier.” 2017. Thesis, University of Illinois – Urbana-Champaign. Accessed September 19, 2020. http://hdl.handle.net/2142/97744.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Coombs, Daniel R. “Ring oscillator based injection locked clock multiplier.” 2017. Web. 19 Sep 2020.

Vancouver:

Coombs DR. Ring oscillator based injection locked clock multiplier. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2017. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/2142/97744.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Coombs DR. Ring oscillator based injection locked clock multiplier. [Thesis]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/97744

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Queens University

20. Eren, Suzan. Modifying the Three-Phase Synchronous Reference Frame Phase-Locked Loop to Remove Unbalance and Harmonic Errors .

Degree: Electrical and Computer Engineering, 2008, Queens University

 As an increasing number of distributed power generation systems (DPGS) are being connected to the utility grid, there is a growing requirement for the DPGS… (more)

Subjects/Keywords: grid synchronization ; phase-locked loop

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APA (6th Edition):

Eren, S. (2008). Modifying the Three-Phase Synchronous Reference Frame Phase-Locked Loop to Remove Unbalance and Harmonic Errors . (Thesis). Queens University. Retrieved from http://hdl.handle.net/1974/1635

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Eren, Suzan. “Modifying the Three-Phase Synchronous Reference Frame Phase-Locked Loop to Remove Unbalance and Harmonic Errors .” 2008. Thesis, Queens University. Accessed September 19, 2020. http://hdl.handle.net/1974/1635.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Eren, Suzan. “Modifying the Three-Phase Synchronous Reference Frame Phase-Locked Loop to Remove Unbalance and Harmonic Errors .” 2008. Web. 19 Sep 2020.

Vancouver:

Eren S. Modifying the Three-Phase Synchronous Reference Frame Phase-Locked Loop to Remove Unbalance and Harmonic Errors . [Internet] [Thesis]. Queens University; 2008. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1974/1635.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Eren S. Modifying the Three-Phase Synchronous Reference Frame Phase-Locked Loop to Remove Unbalance and Harmonic Errors . [Thesis]. Queens University; 2008. Available from: http://hdl.handle.net/1974/1635

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


McGill University

21. Martin, Louis V. Phase-Locked Loop Simulation in Transient Stabilities Studies.

Degree: M. Eng., Department of Electrical Engineering, 1989, McGill University

L'objectif de cette thèse est de développer et de vérifier un modèle pour les boucles d'accrocha.ge de phase, utilisable dans les études de stabilité transitoire… (more)

Subjects/Keywords: Phase-locked loop (PLL)

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APA (6th Edition):

Martin, L. V. (1989). Phase-Locked Loop Simulation in Transient Stabilities Studies. (Masters Thesis). McGill University. Retrieved from https://escholarship.mcgill.ca/downloads/dj52w6974.pdf ; https://escholarship.mcgill.ca/concern/theses/5138jg99z

Chicago Manual of Style (16th Edition):

Martin, Louis V. “Phase-Locked Loop Simulation in Transient Stabilities Studies.” 1989. Masters Thesis, McGill University. Accessed September 19, 2020. https://escholarship.mcgill.ca/downloads/dj52w6974.pdf ; https://escholarship.mcgill.ca/concern/theses/5138jg99z.

MLA Handbook (7th Edition):

Martin, Louis V. “Phase-Locked Loop Simulation in Transient Stabilities Studies.” 1989. Web. 19 Sep 2020.

Vancouver:

Martin LV. Phase-Locked Loop Simulation in Transient Stabilities Studies. [Internet] [Masters thesis]. McGill University; 1989. [cited 2020 Sep 19]. Available from: https://escholarship.mcgill.ca/downloads/dj52w6974.pdf ; https://escholarship.mcgill.ca/concern/theses/5138jg99z.

Council of Science Editors:

Martin LV. Phase-Locked Loop Simulation in Transient Stabilities Studies. [Masters Thesis]. McGill University; 1989. Available from: https://escholarship.mcgill.ca/downloads/dj52w6974.pdf ; https://escholarship.mcgill.ca/concern/theses/5138jg99z


University of Windsor

22. Richard, Donatus Silva. Phase Locking Authentication for Scan Architecture.

Degree: Electrical and Computer Engineering, 2017, University of Windsor

 Scan design is a widely used Design for Testability (DfT) approach for digital circuits. It provides a high level of controllability and observability resulting in… (more)

Subjects/Keywords: Clock and Data Recovery; Delay Locked Loop; Design for Testability; Hardware Security; Phase Locked Loop; Scan Architecture; Engineering

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APA (6th Edition):

Richard, D. S. (2017). Phase Locking Authentication for Scan Architecture. (Thesis). University of Windsor. Retrieved from https://scholar.uwindsor.ca/etd/7338

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Richard, Donatus Silva. “Phase Locking Authentication for Scan Architecture.” 2017. Thesis, University of Windsor. Accessed September 19, 2020. https://scholar.uwindsor.ca/etd/7338.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Richard, Donatus Silva. “Phase Locking Authentication for Scan Architecture.” 2017. Web. 19 Sep 2020.

Vancouver:

Richard DS. Phase Locking Authentication for Scan Architecture. [Internet] [Thesis]. University of Windsor; 2017. [cited 2020 Sep 19]. Available from: https://scholar.uwindsor.ca/etd/7338.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Richard DS. Phase Locking Authentication for Scan Architecture. [Thesis]. University of Windsor; 2017. Available from: https://scholar.uwindsor.ca/etd/7338

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

23. Kratyuk, Volodymyr. Digital phase-locked loops for multi-GHz clock generation.

Degree: PhD, Electrical and Computer Engineering, 2007, Oregon State University

 A digital implementation of a PLL has several advantages compared to its analog counterpart. These include easy scalability with process shrink, elimination of the noise… (more)

Subjects/Keywords: digital phase-locked loop; Phase-locked loops

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APA (6th Edition):

Kratyuk, V. (2007). Digital phase-locked loops for multi-GHz clock generation. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/3804

Chicago Manual of Style (16th Edition):

Kratyuk, Volodymyr. “Digital phase-locked loops for multi-GHz clock generation.” 2007. Doctoral Dissertation, Oregon State University. Accessed September 19, 2020. http://hdl.handle.net/1957/3804.

MLA Handbook (7th Edition):

Kratyuk, Volodymyr. “Digital phase-locked loops for multi-GHz clock generation.” 2007. Web. 19 Sep 2020.

Vancouver:

Kratyuk V. Digital phase-locked loops for multi-GHz clock generation. [Internet] [Doctoral dissertation]. Oregon State University; 2007. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1957/3804.

Council of Science Editors:

Kratyuk V. Digital phase-locked loops for multi-GHz clock generation. [Doctoral Dissertation]. Oregon State University; 2007. Available from: http://hdl.handle.net/1957/3804


NSYSU

24. Zhou, Sheng-Jun. Synchronization Phase Locked Loop Controller Design for Unbalanced Three-Phase Power Networks.

Degree: Master, Electrical Engineering, 2016, NSYSU

 This thesis focuses on the phase locked loop controller design for power networks under the scenario that the three-phase power output of the network is… (more)

Subjects/Keywords: phase locked loop; phase angle tracking; unbalanced; wind turbine power generation system; networks failure

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APA (6th Edition):

Zhou, S. (2016). Synchronization Phase Locked Loop Controller Design for Unbalanced Three-Phase Power Networks. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0626116-175332

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhou, Sheng-Jun. “Synchronization Phase Locked Loop Controller Design for Unbalanced Three-Phase Power Networks.” 2016. Thesis, NSYSU. Accessed September 19, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0626116-175332.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhou, Sheng-Jun. “Synchronization Phase Locked Loop Controller Design for Unbalanced Three-Phase Power Networks.” 2016. Web. 19 Sep 2020.

Vancouver:

Zhou S. Synchronization Phase Locked Loop Controller Design for Unbalanced Three-Phase Power Networks. [Internet] [Thesis]. NSYSU; 2016. [cited 2020 Sep 19]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0626116-175332.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhou S. Synchronization Phase Locked Loop Controller Design for Unbalanced Three-Phase Power Networks. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0626116-175332

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Toronto

25. Samarah, Amer. Improved Phase Detection for Digital Phase-locked Loops.

Degree: PhD, 2016, University of Toronto

Digital PLLs (DPLLs) have emerged as reliable alternatives to analog PLLs since they are more robust in the presence of process variations and mismatch and… (more)

Subjects/Keywords: bang bang phase locked loop; dead zone of phase detector; Digital phase locked loop; frequency synthesizer; modulator dithering; time to digital converter; 0544

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Samarah, A. (2016). Improved Phase Detection for Digital Phase-locked Loops. (Doctoral Dissertation). University of Toronto. Retrieved from http://hdl.handle.net/1807/78796

Chicago Manual of Style (16th Edition):

Samarah, Amer. “Improved Phase Detection for Digital Phase-locked Loops.” 2016. Doctoral Dissertation, University of Toronto. Accessed September 19, 2020. http://hdl.handle.net/1807/78796.

MLA Handbook (7th Edition):

Samarah, Amer. “Improved Phase Detection for Digital Phase-locked Loops.” 2016. Web. 19 Sep 2020.

Vancouver:

Samarah A. Improved Phase Detection for Digital Phase-locked Loops. [Internet] [Doctoral dissertation]. University of Toronto; 2016. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/1807/78796.

Council of Science Editors:

Samarah A. Improved Phase Detection for Digital Phase-locked Loops. [Doctoral Dissertation]. University of Toronto; 2016. Available from: http://hdl.handle.net/1807/78796


University of Illinois – Urbana-Champaign

26. Anand, Tejasvi. Toward realizing power scalable and energy proportional high-speed wireline links.

Degree: PhD, Electrical & Computer Engineering, 2015, University of Illinois – Urbana-Champaign

 Growing computational demand and proliferation of cloud computing has placed high-speed serial links at the center stage. Due to saturating energy efficiency improvements over the… (more)

Subjects/Keywords: energy proportional; rapid-on/off; Phase locked loops (PLLs); multiplying delay locked loop (MDLL); delay locked loop; transceiver; Input/Output (I/O); serial link; temperature sensor; LC oscillator; LC oscillator

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APA (6th Edition):

Anand, T. (2015). Toward realizing power scalable and energy proportional high-speed wireline links. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/89205

Chicago Manual of Style (16th Edition):

Anand, Tejasvi. “Toward realizing power scalable and energy proportional high-speed wireline links.” 2015. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed September 19, 2020. http://hdl.handle.net/2142/89205.

MLA Handbook (7th Edition):

Anand, Tejasvi. “Toward realizing power scalable and energy proportional high-speed wireline links.” 2015. Web. 19 Sep 2020.

Vancouver:

Anand T. Toward realizing power scalable and energy proportional high-speed wireline links. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2015. [cited 2020 Sep 19]. Available from: http://hdl.handle.net/2142/89205.

Council of Science Editors:

Anand T. Toward realizing power scalable and energy proportional high-speed wireline links. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/89205

27. Bueno, Átila Madureira. Estudo do jitter de fase em redes de distribuição de sinais de tempo.

Degree: PhD, Engenharia de Sistemas, 2009, University of São Paulo

As redes de distribuição de sinais de tempo - ou redes de sincronismo - têm a tarefa de distribuir os sinais de fase e freqüência… (more)

Subjects/Keywords: Double frequency jitter; Nonlinear systems; Phase locked loop; Sistemas dinâmicos; Sistemas não lineares; Stability; Synchronization

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bueno, . M. (2009). Estudo do jitter de fase em redes de distribuição de sinais de tempo. (Doctoral Dissertation). University of São Paulo. Retrieved from http://www.teses.usp.br/teses/disponiveis/3/3139/tde-21072009-143554/ ;

Chicago Manual of Style (16th Edition):

Bueno, Átila Madureira. “Estudo do jitter de fase em redes de distribuição de sinais de tempo.” 2009. Doctoral Dissertation, University of São Paulo. Accessed September 19, 2020. http://www.teses.usp.br/teses/disponiveis/3/3139/tde-21072009-143554/ ;.

MLA Handbook (7th Edition):

Bueno, Átila Madureira. “Estudo do jitter de fase em redes de distribuição de sinais de tempo.” 2009. Web. 19 Sep 2020.

Vancouver:

Bueno M. Estudo do jitter de fase em redes de distribuição de sinais de tempo. [Internet] [Doctoral dissertation]. University of São Paulo; 2009. [cited 2020 Sep 19]. Available from: http://www.teses.usp.br/teses/disponiveis/3/3139/tde-21072009-143554/ ;.

Council of Science Editors:

Bueno M. Estudo do jitter de fase em redes de distribuição de sinais de tempo. [Doctoral Dissertation]. University of São Paulo; 2009. Available from: http://www.teses.usp.br/teses/disponiveis/3/3139/tde-21072009-143554/ ;


University of Alberta

28. Radwan, Amr A A. Modeling, Analysis and Advanced Control of Voltage- and Current-Source Converters in Renewable Energy-Based Active Distribution Systems.

Degree: PhD, Department of Electrical and Computer Engineering, 2015, University of Alberta

 This thesis addresses the integration of renewable energy resources into the grid-connected and isolated distribution systems using voltage- and current-source converters. Motivated by its promising… (more)

Subjects/Keywords: Current-Source-Converters; Voltage-Source-Converters; Weak-Grid; Microgrid; Phase-Locked-Loop; AC/DC; Stability

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APA (6th Edition):

Radwan, A. A. A. (2015). Modeling, Analysis and Advanced Control of Voltage- and Current-Source Converters in Renewable Energy-Based Active Distribution Systems. (Doctoral Dissertation). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/c3197xm08j

Chicago Manual of Style (16th Edition):

Radwan, Amr A A. “Modeling, Analysis and Advanced Control of Voltage- and Current-Source Converters in Renewable Energy-Based Active Distribution Systems.” 2015. Doctoral Dissertation, University of Alberta. Accessed September 19, 2020. https://era.library.ualberta.ca/files/c3197xm08j.

MLA Handbook (7th Edition):

Radwan, Amr A A. “Modeling, Analysis and Advanced Control of Voltage- and Current-Source Converters in Renewable Energy-Based Active Distribution Systems.” 2015. Web. 19 Sep 2020.

Vancouver:

Radwan AAA. Modeling, Analysis and Advanced Control of Voltage- and Current-Source Converters in Renewable Energy-Based Active Distribution Systems. [Internet] [Doctoral dissertation]. University of Alberta; 2015. [cited 2020 Sep 19]. Available from: https://era.library.ualberta.ca/files/c3197xm08j.

Council of Science Editors:

Radwan AAA. Modeling, Analysis and Advanced Control of Voltage- and Current-Source Converters in Renewable Energy-Based Active Distribution Systems. [Doctoral Dissertation]. University of Alberta; 2015. Available from: https://era.library.ualberta.ca/files/c3197xm08j


NSYSU

29. Kung, Hui-Hsuan. APSK Transmission Experiment with Homodyne Receiver Using Carrier Phase Recovery.

Degree: Master, Electro-Optical Engineering, 2011, NSYSU

 In the current transmission systems, the transmission capacity is still not enough. The information bandwidth of the optical fiber communication system is limited by the… (more)

Subjects/Keywords: APSK; Modulation format; Optical phase-locked loop; Coherent detection; Digital coherent receiver; Digital signal processing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kung, H. (2011). APSK Transmission Experiment with Homodyne Receiver Using Carrier Phase Recovery. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0628111-184600

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kung, Hui-Hsuan. “APSK Transmission Experiment with Homodyne Receiver Using Carrier Phase Recovery.” 2011. Thesis, NSYSU. Accessed September 19, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0628111-184600.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kung, Hui-Hsuan. “APSK Transmission Experiment with Homodyne Receiver Using Carrier Phase Recovery.” 2011. Web. 19 Sep 2020.

Vancouver:

Kung H. APSK Transmission Experiment with Homodyne Receiver Using Carrier Phase Recovery. [Internet] [Thesis]. NSYSU; 2011. [cited 2020 Sep 19]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0628111-184600.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kung H. APSK Transmission Experiment with Homodyne Receiver Using Carrier Phase Recovery. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0628111-184600

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

30. Kuo, Chun-Yi. Design of A Droop-Controlled Inverter with Seamlessly Grid-Connected Transition.

Degree: Master, Electrical Engineering, 2011, NSYSU

 The grid voltage is normally required to avoid transient current of the inverter due to asynchronously grid-paralleling connection. This paper presents a seamless transition method… (more)

Subjects/Keywords: seamless transition; phase-locked loop; virtual inductance; droop-controlled; zero-current control

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kuo, C. (2011). Design of A Droop-Controlled Inverter with Seamlessly Grid-Connected Transition. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0825111-012553

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kuo, Chun-Yi. “Design of A Droop-Controlled Inverter with Seamlessly Grid-Connected Transition.” 2011. Thesis, NSYSU. Accessed September 19, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0825111-012553.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kuo, Chun-Yi. “Design of A Droop-Controlled Inverter with Seamlessly Grid-Connected Transition.” 2011. Web. 19 Sep 2020.

Vancouver:

Kuo C. Design of A Droop-Controlled Inverter with Seamlessly Grid-Connected Transition. [Internet] [Thesis]. NSYSU; 2011. [cited 2020 Sep 19]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0825111-012553.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kuo C. Design of A Droop-Controlled Inverter with Seamlessly Grid-Connected Transition. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0825111-012553

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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