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You searched for subject:(offset voltage). Showing records 1 – 6 of 6 total matches.

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University of Akron

1. Naini, Srikar Reddy. PING-PONG AUTO-ZERO AMPLIFIER WITH RAIL-TO-RAIL OUTPUT BUFFER.

Degree: MS, Electrical Engineering, 2018, University of Akron

 This work presents a ping-pong auto-zero amplifier for precision sensor applications. The transistor level circuit design of the amplifier building blocks including the transconductance stage… (more)

Subjects/Keywords: Electrical Engineering; Auto-zero, Ping-Pong Auto-zero amplifier, DC Offset voltage, Noise

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Naini, S. R. (2018). PING-PONG AUTO-ZERO AMPLIFIER WITH RAIL-TO-RAIL OUTPUT BUFFER. (Masters Thesis). University of Akron. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=akron1537224512595497

Chicago Manual of Style (16th Edition):

Naini, Srikar Reddy. “PING-PONG AUTO-ZERO AMPLIFIER WITH RAIL-TO-RAIL OUTPUT BUFFER.” 2018. Masters Thesis, University of Akron. Accessed August 05, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=akron1537224512595497.

MLA Handbook (7th Edition):

Naini, Srikar Reddy. “PING-PONG AUTO-ZERO AMPLIFIER WITH RAIL-TO-RAIL OUTPUT BUFFER.” 2018. Web. 05 Aug 2020.

Vancouver:

Naini SR. PING-PONG AUTO-ZERO AMPLIFIER WITH RAIL-TO-RAIL OUTPUT BUFFER. [Internet] [Masters thesis]. University of Akron; 2018. [cited 2020 Aug 05]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=akron1537224512595497.

Council of Science Editors:

Naini SR. PING-PONG AUTO-ZERO AMPLIFIER WITH RAIL-TO-RAIL OUTPUT BUFFER. [Masters Thesis]. University of Akron; 2018. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=akron1537224512595497


University of Illinois – Urbana-Champaign

2. Kim, Katherine A. Voltage-Offset Resistive Control for Photovoltaics.

Degree: MS, 1200, 2012, University of Illinois – Urbana-Champaign

 This thesis introduces voltage-offset resistive control (VRC) for photovoltaic (PV) applications that exhibits low sensitivity to solar irradiance changes. Although there are numerous control schemes… (more)

Subjects/Keywords: voltage-offset resistive control; photovoltaics; power electronics; dc-dc converter control; maximum power point tracking; irradiance sensitivity; direct current (dc)

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APA (6th Edition):

Kim, K. A. (2012). Voltage-Offset Resistive Control for Photovoltaics. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/29691

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kim, Katherine A. “Voltage-Offset Resistive Control for Photovoltaics.” 2012. Thesis, University of Illinois – Urbana-Champaign. Accessed August 05, 2020. http://hdl.handle.net/2142/29691.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kim, Katherine A. “Voltage-Offset Resistive Control for Photovoltaics.” 2012. Web. 05 Aug 2020.

Vancouver:

Kim KA. Voltage-Offset Resistive Control for Photovoltaics. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2012. [cited 2020 Aug 05]. Available from: http://hdl.handle.net/2142/29691.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kim KA. Voltage-Offset Resistive Control for Photovoltaics. [Thesis]. University of Illinois – Urbana-Champaign; 2012. Available from: http://hdl.handle.net/2142/29691

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

3. LI TI. Design and implementation of a high speed and low power flash ADC with fully dynamic comparators.

Degree: 2010, National University of Singapore

Subjects/Keywords: low power; flash ADC; fully dynamic comparators; background calibration; high speed; offset voltage

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APA (6th Edition):

TI, L. (2010). Design and implementation of a high speed and low power flash ADC with fully dynamic comparators. (Thesis). National University of Singapore. Retrieved from http://scholarbank.nus.edu.sg/handle/10635/23792

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

TI, LI. “Design and implementation of a high speed and low power flash ADC with fully dynamic comparators.” 2010. Thesis, National University of Singapore. Accessed August 05, 2020. http://scholarbank.nus.edu.sg/handle/10635/23792.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

TI, LI. “Design and implementation of a high speed and low power flash ADC with fully dynamic comparators.” 2010. Web. 05 Aug 2020.

Vancouver:

TI L. Design and implementation of a high speed and low power flash ADC with fully dynamic comparators. [Internet] [Thesis]. National University of Singapore; 2010. [cited 2020 Aug 05]. Available from: http://scholarbank.nus.edu.sg/handle/10635/23792.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

TI L. Design and implementation of a high speed and low power flash ADC with fully dynamic comparators. [Thesis]. National University of Singapore; 2010. Available from: http://scholarbank.nus.edu.sg/handle/10635/23792

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

4. Bommireddipalli, Aditya Vighnesh Ramakanth. Design of a Precision Low Voltage Resistor Multiplying Digital-to-Analog Converter.

Degree: MS, Electrical Engineering, 2017, Texas A&M University

 This work aims to model the effect of the input offset voltage of an operational amplifier on the performance of a high-precision, voltage-mode, resistor-based multiplying… (more)

Subjects/Keywords: DAC; input offset voltage; high-precision; current buffer

offset voltage reduced to offset error . . . . . . . . . . . . . . . . . 34 4.6 Step… …currents (≤1pA). The input offset voltage is defined in [14] as the voltage… …transistors and components during fabrication. In CMOS amplifiers the input offset voltage is… …Effect of offset on IOU T Linearity can be preserved only if the offset voltage is less than 1… …Unfortunately, the offset voltage of an untrimmed CMOS amplifier can be in the range of ±5mV to ±50mV… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bommireddipalli, A. V. R. (2017). Design of a Precision Low Voltage Resistor Multiplying Digital-to-Analog Converter. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/165708

Chicago Manual of Style (16th Edition):

Bommireddipalli, Aditya Vighnesh Ramakanth. “Design of a Precision Low Voltage Resistor Multiplying Digital-to-Analog Converter.” 2017. Masters Thesis, Texas A&M University. Accessed August 05, 2020. http://hdl.handle.net/1969.1/165708.

MLA Handbook (7th Edition):

Bommireddipalli, Aditya Vighnesh Ramakanth. “Design of a Precision Low Voltage Resistor Multiplying Digital-to-Analog Converter.” 2017. Web. 05 Aug 2020.

Vancouver:

Bommireddipalli AVR. Design of a Precision Low Voltage Resistor Multiplying Digital-to-Analog Converter. [Internet] [Masters thesis]. Texas A&M University; 2017. [cited 2020 Aug 05]. Available from: http://hdl.handle.net/1969.1/165708.

Council of Science Editors:

Bommireddipalli AVR. Design of a Precision Low Voltage Resistor Multiplying Digital-to-Analog Converter. [Masters Thesis]. Texas A&M University; 2017. Available from: http://hdl.handle.net/1969.1/165708


Georgia Tech

5. Srinivasan, Venkatesh. Programmable Analog Techniques For Precision Analog Circuits, Low-Power Signal Processing and On-Chip Learning.

Degree: PhD, Electrical and Computer Engineering, 2006, Georgia Tech

 In this work, programmable analog techniques using floating-gate transistors have been developed to design precision analog circuits, low-power signal processing primitives and adaptive systems that… (more)

Subjects/Keywords: Programmable multipliers; Adaptive filters; Voltage references; Offset cancellation; Floating-gate transistors; Synapse; Neural networks (Computer science); Signal processing; Adaptive signal processing; Electronic analog computers Circuits; Gate array circuits

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Srinivasan, V. (2006). Programmable Analog Techniques For Precision Analog Circuits, Low-Power Signal Processing and On-Chip Learning. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/11588

Chicago Manual of Style (16th Edition):

Srinivasan, Venkatesh. “Programmable Analog Techniques For Precision Analog Circuits, Low-Power Signal Processing and On-Chip Learning.” 2006. Doctoral Dissertation, Georgia Tech. Accessed August 05, 2020. http://hdl.handle.net/1853/11588.

MLA Handbook (7th Edition):

Srinivasan, Venkatesh. “Programmable Analog Techniques For Precision Analog Circuits, Low-Power Signal Processing and On-Chip Learning.” 2006. Web. 05 Aug 2020.

Vancouver:

Srinivasan V. Programmable Analog Techniques For Precision Analog Circuits, Low-Power Signal Processing and On-Chip Learning. [Internet] [Doctoral dissertation]. Georgia Tech; 2006. [cited 2020 Aug 05]. Available from: http://hdl.handle.net/1853/11588.

Council of Science Editors:

Srinivasan V. Programmable Analog Techniques For Precision Analog Circuits, Low-Power Signal Processing and On-Chip Learning. [Doctoral Dissertation]. Georgia Tech; 2006. Available from: http://hdl.handle.net/1853/11588


Queens University

6. Carr, John. A 26 GHz Phase-Locked Loop Frequency Multiplier in 0.18-um CMOS .

Degree: Electrical and Computer Engineering, 2009, Queens University

 This thesis presents the analysis, design and characterization of an integrated high-frequency phase-locked loop (PLL) frequency multiplier. The frequency multiplier is novel in its use… (more)

Subjects/Keywords: phase-locked loop ; frequency multiplier ; CMOS ; integrated circuit ; voltage controlled oscillator ; injection locked frequency divider ; phase detector ; phase noise ; Accumulation MOS varactor ; monolithic integration ; static phase offset ; common mode rejection ; 26 GHz ; master-slave flip-flop divider ; direct injection ; differential ; phase plane

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Carr, J. (2009). A 26 GHz Phase-Locked Loop Frequency Multiplier in 0.18-um CMOS . (Thesis). Queens University. Retrieved from http://hdl.handle.net/1974/1796

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Carr, John. “A 26 GHz Phase-Locked Loop Frequency Multiplier in 0.18-um CMOS .” 2009. Thesis, Queens University. Accessed August 05, 2020. http://hdl.handle.net/1974/1796.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Carr, John. “A 26 GHz Phase-Locked Loop Frequency Multiplier in 0.18-um CMOS .” 2009. Web. 05 Aug 2020.

Vancouver:

Carr J. A 26 GHz Phase-Locked Loop Frequency Multiplier in 0.18-um CMOS . [Internet] [Thesis]. Queens University; 2009. [cited 2020 Aug 05]. Available from: http://hdl.handle.net/1974/1796.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Carr J. A 26 GHz Phase-Locked Loop Frequency Multiplier in 0.18-um CMOS . [Thesis]. Queens University; 2009. Available from: http://hdl.handle.net/1974/1796

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

.