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You searched for subject:(multiprocessor). Showing records 1 – 30 of 192 total matches.

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NSYSU

1. Chang, Heng-Hao. Performance Evaluation of A Multiprocessor Support for Concurrent Execution of Critical Sections.

Degree: Master, Electrical Engineering, 2001, NSYSU

 In this research, in order to improve the concurrency of critical sections on distributed shared memory multiprocessors, we designed various concurrency control support for critical… (more)

Subjects/Keywords: multiprocessor

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chang, H. (2001). Performance Evaluation of A Multiprocessor Support for Concurrent Execution of Critical Sections. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1001101-030730

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chang, Heng-Hao. “Performance Evaluation of A Multiprocessor Support for Concurrent Execution of Critical Sections.” 2001. Thesis, NSYSU. Accessed October 19, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1001101-030730.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chang, Heng-Hao. “Performance Evaluation of A Multiprocessor Support for Concurrent Execution of Critical Sections.” 2001. Web. 19 Oct 2019.

Vancouver:

Chang H. Performance Evaluation of A Multiprocessor Support for Concurrent Execution of Critical Sections. [Internet] [Thesis]. NSYSU; 2001. [cited 2019 Oct 19]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1001101-030730.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chang H. Performance Evaluation of A Multiprocessor Support for Concurrent Execution of Critical Sections. [Thesis]. NSYSU; 2001. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-1001101-030730

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Debrecen

2. Morsiani, Renato. Processzorütemezés Többprocesszoros Rendszerekben .

Degree: DE – TEK – Informatikai Kar, 2009, University of Debrecen

A dolgozat a többprocesszoros rendszerekben való ütemezés elméleti területeiről, valamint ezen belül a valós idejű rendszerek ütemezhetőségéről szól. Advisors/Committee Members: Fazekas, Gábor (advisor).

Subjects/Keywords: multiprocessor; real-time

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APA (6th Edition):

Morsiani, R. (2009). Processzorütemezés Többprocesszoros Rendszerekben . (Thesis). University of Debrecen. Retrieved from http://hdl.handle.net/2437/90335

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Morsiani, Renato. “Processzorütemezés Többprocesszoros Rendszerekben .” 2009. Thesis, University of Debrecen. Accessed October 19, 2019. http://hdl.handle.net/2437/90335.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Morsiani, Renato. “Processzorütemezés Többprocesszoros Rendszerekben .” 2009. Web. 19 Oct 2019.

Vancouver:

Morsiani R. Processzorütemezés Többprocesszoros Rendszerekben . [Internet] [Thesis]. University of Debrecen; 2009. [cited 2019 Oct 19]. Available from: http://hdl.handle.net/2437/90335.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Morsiani R. Processzorütemezés Többprocesszoros Rendszerekben . [Thesis]. University of Debrecen; 2009. Available from: http://hdl.handle.net/2437/90335

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Manchester

3. Rosas Ham, Demian. Dynamic Scheduling in Multicore Processors.

Degree: 2012, University of Manchester

 The advent of multi-core processors, particularly with projections that numbersof cores will continue to increase, has focused attention on parallelprogramming. It is widely recognized that… (more)

Subjects/Keywords: Dynamic Load Balancing; Chip Multiprocessor

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APA (6th Edition):

Rosas Ham, D. (2012). Dynamic Scheduling in Multicore Processors. (Doctoral Dissertation). University of Manchester. Retrieved from http://www.manchester.ac.uk/escholar/uk-ac-man-scw:157788

Chicago Manual of Style (16th Edition):

Rosas Ham, Demian. “Dynamic Scheduling in Multicore Processors.” 2012. Doctoral Dissertation, University of Manchester. Accessed October 19, 2019. http://www.manchester.ac.uk/escholar/uk-ac-man-scw:157788.

MLA Handbook (7th Edition):

Rosas Ham, Demian. “Dynamic Scheduling in Multicore Processors.” 2012. Web. 19 Oct 2019.

Vancouver:

Rosas Ham D. Dynamic Scheduling in Multicore Processors. [Internet] [Doctoral dissertation]. University of Manchester; 2012. [cited 2019 Oct 19]. Available from: http://www.manchester.ac.uk/escholar/uk-ac-man-scw:157788.

Council of Science Editors:

Rosas Ham D. Dynamic Scheduling in Multicore Processors. [Doctoral Dissertation]. University of Manchester; 2012. Available from: http://www.manchester.ac.uk/escholar/uk-ac-man-scw:157788

4. Verriet, J.H. Scheduling with communication for multiprocessor computation.

Degree: 1998, University Utrecht

Multiprocessor scheduling houdt zich bezig met de planning van de uitvoering van computer-programma s op een parallelle computer. Een computerprogramma kan worden gezien als een… (more)

Subjects/Keywords: multiprocessor computation

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APA (6th Edition):

Verriet, J. H. (1998). Scheduling with communication for multiprocessor computation. (Doctoral Dissertation). University Utrecht. Retrieved from http://dspace.library.uu.nl/handle/1874/835 ; URN:NBN:NL:UI:10-1874-835 ; URN:NBN:NL:UI:10-1874-835 ; http://dspace.library.uu.nl/handle/1874/835

Chicago Manual of Style (16th Edition):

Verriet, J H. “Scheduling with communication for multiprocessor computation.” 1998. Doctoral Dissertation, University Utrecht. Accessed October 19, 2019. http://dspace.library.uu.nl/handle/1874/835 ; URN:NBN:NL:UI:10-1874-835 ; URN:NBN:NL:UI:10-1874-835 ; http://dspace.library.uu.nl/handle/1874/835.

MLA Handbook (7th Edition):

Verriet, J H. “Scheduling with communication for multiprocessor computation.” 1998. Web. 19 Oct 2019.

Vancouver:

Verriet JH. Scheduling with communication for multiprocessor computation. [Internet] [Doctoral dissertation]. University Utrecht; 1998. [cited 2019 Oct 19]. Available from: http://dspace.library.uu.nl/handle/1874/835 ; URN:NBN:NL:UI:10-1874-835 ; URN:NBN:NL:UI:10-1874-835 ; http://dspace.library.uu.nl/handle/1874/835.

Council of Science Editors:

Verriet JH. Scheduling with communication for multiprocessor computation. [Doctoral Dissertation]. University Utrecht; 1998. Available from: http://dspace.library.uu.nl/handle/1874/835 ; URN:NBN:NL:UI:10-1874-835 ; URN:NBN:NL:UI:10-1874-835 ; http://dspace.library.uu.nl/handle/1874/835


University of Illinois – Urbana-Champaign

5. Greskamp, Brian. Improving Per-Thread Performance on CMPs through Timing Speculation.

Degree: PhD, Computer Science, 2009, University of Illinois – Urbana-Champaign

 The future of performance scaling lies in massively parallel workloads, but less-parallel applications will remain important. Unfortunately, future process technologies and core microarchitectures no longer… (more)

Subjects/Keywords: chip multiprocessor; microarchitecture; timing speculation

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APA (6th Edition):

Greskamp, B. (2009). Improving Per-Thread Performance on CMPs through Timing Speculation. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/13148

Chicago Manual of Style (16th Edition):

Greskamp, Brian. “Improving Per-Thread Performance on CMPs through Timing Speculation.” 2009. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed October 19, 2019. http://hdl.handle.net/2142/13148.

MLA Handbook (7th Edition):

Greskamp, Brian. “Improving Per-Thread Performance on CMPs through Timing Speculation.” 2009. Web. 19 Oct 2019.

Vancouver:

Greskamp B. Improving Per-Thread Performance on CMPs through Timing Speculation. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2009. [cited 2019 Oct 19]. Available from: http://hdl.handle.net/2142/13148.

Council of Science Editors:

Greskamp B. Improving Per-Thread Performance on CMPs through Timing Speculation. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2009. Available from: http://hdl.handle.net/2142/13148


Texas A&M University

6. An, Baik Song. Architectural Support for High-Performance, Power-Efficient and Secure Multiprocessor Systems.

Degree: 2012, Texas A&M University

 High performance systems have been widely adopted in many fields and the demand for better performance is constantly increasing. And the need of powerful yet… (more)

Subjects/Keywords: computer architecture; chip multiprocessor; network-on-chip

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APA (6th Edition):

An, B. S. (2012). Architectural Support for High-Performance, Power-Efficient and Secure Multiprocessor Systems. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11665

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

An, Baik Song. “Architectural Support for High-Performance, Power-Efficient and Secure Multiprocessor Systems.” 2012. Thesis, Texas A&M University. Accessed October 19, 2019. http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11665.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

An, Baik Song. “Architectural Support for High-Performance, Power-Efficient and Secure Multiprocessor Systems.” 2012. Web. 19 Oct 2019.

Vancouver:

An BS. Architectural Support for High-Performance, Power-Efficient and Secure Multiprocessor Systems. [Internet] [Thesis]. Texas A&M University; 2012. [cited 2019 Oct 19]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11665.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

An BS. Architectural Support for High-Performance, Power-Efficient and Secure Multiprocessor Systems. [Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11665

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

7. Mittal, Shaily. Memory customization in multiprocessor Systems-On-Chip.

Degree: Computer Science Engineering, 2014, Jaypee University of Information Technology, Solan

With the change in time, there is increase in the demand of embedded system applications with advanced technologies. Multiprocessor Systems-on-Chip (MPSoC s) become usual in… (more)

Subjects/Keywords: Embedded Systems; Multiprocessor; Systems-On-Chip

Page 1

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APA (6th Edition):

Mittal, S. (2014). Memory customization in multiprocessor Systems-On-Chip. (Thesis). Jaypee University of Information Technology, Solan. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/18806

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mittal, Shaily. “Memory customization in multiprocessor Systems-On-Chip.” 2014. Thesis, Jaypee University of Information Technology, Solan. Accessed October 19, 2019. http://shodhganga.inflibnet.ac.in/handle/10603/18806.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mittal, Shaily. “Memory customization in multiprocessor Systems-On-Chip.” 2014. Web. 19 Oct 2019.

Vancouver:

Mittal S. Memory customization in multiprocessor Systems-On-Chip. [Internet] [Thesis]. Jaypee University of Information Technology, Solan; 2014. [cited 2019 Oct 19]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/18806.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mittal S. Memory customization in multiprocessor Systems-On-Chip. [Thesis]. Jaypee University of Information Technology, Solan; 2014. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/18806

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Cincinnati

8. Ramakrishnan, Divya. Design and Analysis of Location Cache in a Network-on-Chip Based Multiprocessor System.

Degree: MS, Engineering : Computer Engineering, 2009, University of Cincinnati

  In recent years, the direction of research to improve the performance of computing systems is focused toward chip multiprocessor (CMP) designs with multiple cores… (more)

Subjects/Keywords: Engineering; location cache; network on chip; multiprocessor

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APA (6th Edition):

Ramakrishnan, D. (2009). Design and Analysis of Location Cache in a Network-on-Chip Based Multiprocessor System. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1228441816

Chicago Manual of Style (16th Edition):

Ramakrishnan, Divya. “Design and Analysis of Location Cache in a Network-on-Chip Based Multiprocessor System.” 2009. Masters Thesis, University of Cincinnati. Accessed October 19, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1228441816.

MLA Handbook (7th Edition):

Ramakrishnan, Divya. “Design and Analysis of Location Cache in a Network-on-Chip Based Multiprocessor System.” 2009. Web. 19 Oct 2019.

Vancouver:

Ramakrishnan D. Design and Analysis of Location Cache in a Network-on-Chip Based Multiprocessor System. [Internet] [Masters thesis]. University of Cincinnati; 2009. [cited 2019 Oct 19]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1228441816.

Council of Science Editors:

Ramakrishnan D. Design and Analysis of Location Cache in a Network-on-Chip Based Multiprocessor System. [Masters Thesis]. University of Cincinnati; 2009. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1228441816


University of Manchester

9. Rosas Ham, Demian. Dynamic scheduling in multicore processors.

Degree: PhD, 2012, University of Manchester

 The advent of multi-core processors, particularly with projections that numbers of cores will continue to increase, has focused attention on parallel programming. It is widely… (more)

Subjects/Keywords: 004.1; Dynamic Load Balancing; Chip Multiprocessor

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APA (6th Edition):

Rosas Ham, D. (2012). Dynamic scheduling in multicore processors. (Doctoral Dissertation). University of Manchester. Retrieved from https://www.research.manchester.ac.uk/portal/en/theses/dynamic-scheduling-in-multicore-processors(c96d6641-ba16-44d2-9da5-34c41fd15956).html ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.553491

Chicago Manual of Style (16th Edition):

Rosas Ham, Demian. “Dynamic scheduling in multicore processors.” 2012. Doctoral Dissertation, University of Manchester. Accessed October 19, 2019. https://www.research.manchester.ac.uk/portal/en/theses/dynamic-scheduling-in-multicore-processors(c96d6641-ba16-44d2-9da5-34c41fd15956).html ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.553491.

MLA Handbook (7th Edition):

Rosas Ham, Demian. “Dynamic scheduling in multicore processors.” 2012. Web. 19 Oct 2019.

Vancouver:

Rosas Ham D. Dynamic scheduling in multicore processors. [Internet] [Doctoral dissertation]. University of Manchester; 2012. [cited 2019 Oct 19]. Available from: https://www.research.manchester.ac.uk/portal/en/theses/dynamic-scheduling-in-multicore-processors(c96d6641-ba16-44d2-9da5-34c41fd15956).html ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.553491.

Council of Science Editors:

Rosas Ham D. Dynamic scheduling in multicore processors. [Doctoral Dissertation]. University of Manchester; 2012. Available from: https://www.research.manchester.ac.uk/portal/en/theses/dynamic-scheduling-in-multicore-processors(c96d6641-ba16-44d2-9da5-34c41fd15956).html ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.553491


Delft University of Technology

10. Vasilikos, V. Heuristic Search for Defect Tolerant Multiprocessor Arrays:.

Degree: 2011, Delft University of Technology

 In this paper, new heuristic-search methods and algorithms are presented for enabling highly efficient and adaptive, defect-tolerant multiprocessor arrays. We consider systems where a homogeneous… (more)

Subjects/Keywords: heuristic search; fault tolerance; multiprocessor array

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APA (6th Edition):

Vasilikos, V. (2011). Heuristic Search for Defect Tolerant Multiprocessor Arrays:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:6bd8fee2-806b-4a95-ac66-056348f8c36c

Chicago Manual of Style (16th Edition):

Vasilikos, V. “Heuristic Search for Defect Tolerant Multiprocessor Arrays:.” 2011. Masters Thesis, Delft University of Technology. Accessed October 19, 2019. http://resolver.tudelft.nl/uuid:6bd8fee2-806b-4a95-ac66-056348f8c36c.

MLA Handbook (7th Edition):

Vasilikos, V. “Heuristic Search for Defect Tolerant Multiprocessor Arrays:.” 2011. Web. 19 Oct 2019.

Vancouver:

Vasilikos V. Heuristic Search for Defect Tolerant Multiprocessor Arrays:. [Internet] [Masters thesis]. Delft University of Technology; 2011. [cited 2019 Oct 19]. Available from: http://resolver.tudelft.nl/uuid:6bd8fee2-806b-4a95-ac66-056348f8c36c.

Council of Science Editors:

Vasilikos V. Heuristic Search for Defect Tolerant Multiprocessor Arrays:. [Masters Thesis]. Delft University of Technology; 2011. Available from: http://resolver.tudelft.nl/uuid:6bd8fee2-806b-4a95-ac66-056348f8c36c


University of New South Wales

11. von Tessin, Michael. The clustered multikernel: an approach to formal verification of multiprocessor operating-system kernels.

Degree: Computer Science & Engineering, 2013, University of New South Wales

 The key software component of a computer system is the operating-system kernel. Italways needs to be trusted because it runs in the CPU’s privileged mode… (more)

Subjects/Keywords: Microkernel; Formal verification; Multiprocessor; seL4; Isabelle/HOL

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APA (6th Edition):

von Tessin, M. (2013). The clustered multikernel: an approach to formal verification of multiprocessor operating-system kernels. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/53099 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:11785/SOURCE01?view=true

Chicago Manual of Style (16th Edition):

von Tessin, Michael. “The clustered multikernel: an approach to formal verification of multiprocessor operating-system kernels.” 2013. Doctoral Dissertation, University of New South Wales. Accessed October 19, 2019. http://handle.unsw.edu.au/1959.4/53099 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:11785/SOURCE01?view=true.

MLA Handbook (7th Edition):

von Tessin, Michael. “The clustered multikernel: an approach to formal verification of multiprocessor operating-system kernels.” 2013. Web. 19 Oct 2019.

Vancouver:

von Tessin M. The clustered multikernel: an approach to formal verification of multiprocessor operating-system kernels. [Internet] [Doctoral dissertation]. University of New South Wales; 2013. [cited 2019 Oct 19]. Available from: http://handle.unsw.edu.au/1959.4/53099 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:11785/SOURCE01?view=true.

Council of Science Editors:

von Tessin M. The clustered multikernel: an approach to formal verification of multiprocessor operating-system kernels. [Doctoral Dissertation]. University of New South Wales; 2013. Available from: http://handle.unsw.edu.au/1959.4/53099 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:11785/SOURCE01?view=true


North Carolina State University

12. Christner, Robert K. Static Determination of Synchronization Method for Slipstream Multiprocessors.

Degree: MS, Computer Engineering, 2004, North Carolina State University

 The scalability of a distributed shared memory systems is limited largely by communication overhead, most of which can be attributed to memory latency and synchronization.… (more)

Subjects/Keywords: CMP; multiprocessor; slipstream

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APA (6th Edition):

Christner, R. K. (2004). Static Determination of Synchronization Method for Slipstream Multiprocessors. (Thesis). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/2963

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Christner, Robert K. “Static Determination of Synchronization Method for Slipstream Multiprocessors.” 2004. Thesis, North Carolina State University. Accessed October 19, 2019. http://www.lib.ncsu.edu/resolver/1840.16/2963.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Christner, Robert K. “Static Determination of Synchronization Method for Slipstream Multiprocessors.” 2004. Web. 19 Oct 2019.

Vancouver:

Christner RK. Static Determination of Synchronization Method for Slipstream Multiprocessors. [Internet] [Thesis]. North Carolina State University; 2004. [cited 2019 Oct 19]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/2963.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Christner RK. Static Determination of Synchronization Method for Slipstream Multiprocessors. [Thesis]. North Carolina State University; 2004. Available from: http://www.lib.ncsu.edu/resolver/1840.16/2963

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


North Carolina State University

13. Kuebel, Robert. The Performance of Token Coherence on Scientific Workloads.

Degree: MS, Computer Engineering, 2005, North Carolina State University

 Broadcast snooping and directory protocols are, by far, the most common coherence protocols in research and commercial systems. These protocols represent two extremes of cache… (more)

Subjects/Keywords: multiprocessor; token coherence

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APA (6th Edition):

Kuebel, R. (2005). The Performance of Token Coherence on Scientific Workloads. (Thesis). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/36

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kuebel, Robert. “The Performance of Token Coherence on Scientific Workloads.” 2005. Thesis, North Carolina State University. Accessed October 19, 2019. http://www.lib.ncsu.edu/resolver/1840.16/36.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kuebel, Robert. “The Performance of Token Coherence on Scientific Workloads.” 2005. Web. 19 Oct 2019.

Vancouver:

Kuebel R. The Performance of Token Coherence on Scientific Workloads. [Internet] [Thesis]. North Carolina State University; 2005. [cited 2019 Oct 19]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/36.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kuebel R. The Performance of Token Coherence on Scientific Workloads. [Thesis]. North Carolina State University; 2005. Available from: http://www.lib.ncsu.edu/resolver/1840.16/36

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Southern California

14. Chen, Jianwei. Parallel simulation of chip-multiprocessor.

Degree: PhD, Computer Engineering, 2009, University of Southern California

 Simulation is an indispensable tool for computer architecture research. However, as target systems become increasingly complex, designers of computer architecture simulators are facing several challenges… (more)

Subjects/Keywords: chip-multiprocessor; computer architecture; parallel simulation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, J. (2009). Parallel simulation of chip-multiprocessor. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/252311/rec/4909

Chicago Manual of Style (16th Edition):

Chen, Jianwei. “Parallel simulation of chip-multiprocessor.” 2009. Doctoral Dissertation, University of Southern California. Accessed October 19, 2019. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/252311/rec/4909.

MLA Handbook (7th Edition):

Chen, Jianwei. “Parallel simulation of chip-multiprocessor.” 2009. Web. 19 Oct 2019.

Vancouver:

Chen J. Parallel simulation of chip-multiprocessor. [Internet] [Doctoral dissertation]. University of Southern California; 2009. [cited 2019 Oct 19]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/252311/rec/4909.

Council of Science Editors:

Chen J. Parallel simulation of chip-multiprocessor. [Doctoral Dissertation]. University of Southern California; 2009. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/252311/rec/4909


University of Bath

15. Bakti, Zulkifli Abdul Kadir. A demand driven multiprocessor.

Degree: PhD, 1985, University of Bath

 It is thought that fast low cost computers can be built by employing large numbers of cheap microprocessors working together in a system. However increasing… (more)

Subjects/Keywords: 621.39; Multiprocessor systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bakti, Z. A. K. (1985). A demand driven multiprocessor. (Doctoral Dissertation). University of Bath. Retrieved from https://researchportal.bath.ac.uk/en/studentthesis/a-demand-driven-multiprocessor(3d33014f-3a6f-4c48-b05e-848e800c09c3).html ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.352834

Chicago Manual of Style (16th Edition):

Bakti, Zulkifli Abdul Kadir. “A demand driven multiprocessor.” 1985. Doctoral Dissertation, University of Bath. Accessed October 19, 2019. https://researchportal.bath.ac.uk/en/studentthesis/a-demand-driven-multiprocessor(3d33014f-3a6f-4c48-b05e-848e800c09c3).html ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.352834.

MLA Handbook (7th Edition):

Bakti, Zulkifli Abdul Kadir. “A demand driven multiprocessor.” 1985. Web. 19 Oct 2019.

Vancouver:

Bakti ZAK. A demand driven multiprocessor. [Internet] [Doctoral dissertation]. University of Bath; 1985. [cited 2019 Oct 19]. Available from: https://researchportal.bath.ac.uk/en/studentthesis/a-demand-driven-multiprocessor(3d33014f-3a6f-4c48-b05e-848e800c09c3).html ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.352834.

Council of Science Editors:

Bakti ZAK. A demand driven multiprocessor. [Doctoral Dissertation]. University of Bath; 1985. Available from: https://researchportal.bath.ac.uk/en/studentthesis/a-demand-driven-multiprocessor(3d33014f-3a6f-4c48-b05e-848e800c09c3).html ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.352834


Indian Institute of Science

16. Darera, Vivek N. Bounds For Scheduling In Non-Identical Uniform Multiprocessor Systems.

Degree: 2006, Indian Institute of Science

 With multiprocessors and multicore processors becoming ubiquitous, focus has shifted from research on uniprocessors to that on multiprocessors. Results derived for the uniprocessor case unfortunately… (more)

Subjects/Keywords: Multiprocessing; Multiprocessor Systems - Scheduling Algorithms; Dynamic-Priority Scheduling; Fixed-Priority Scheduling; Uniform Multiprocessor Model; Multiprocessor Scheduling; Allocation Decreasing Algorithm; Earliest Deadline First (EDF); Rate Monotonic (RM); Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Darera, V. N. (2006). Bounds For Scheduling In Non-Identical Uniform Multiprocessor Systems. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/342

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Darera, Vivek N. “Bounds For Scheduling In Non-Identical Uniform Multiprocessor Systems.” 2006. Thesis, Indian Institute of Science. Accessed October 19, 2019. http://hdl.handle.net/2005/342.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Darera, Vivek N. “Bounds For Scheduling In Non-Identical Uniform Multiprocessor Systems.” 2006. Web. 19 Oct 2019.

Vancouver:

Darera VN. Bounds For Scheduling In Non-Identical Uniform Multiprocessor Systems. [Internet] [Thesis]. Indian Institute of Science; 2006. [cited 2019 Oct 19]. Available from: http://hdl.handle.net/2005/342.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Darera VN. Bounds For Scheduling In Non-Identical Uniform Multiprocessor Systems. [Thesis]. Indian Institute of Science; 2006. Available from: http://hdl.handle.net/2005/342

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Anna University

17. Saravanakumar U. An investigation on macro and micro Architectures for network on chip;.

Degree: An investigation on macro and micro Architectures for network on chip, 2015, Anna University

As the technology scales down more processors or Processing newlineElements PEs are integrated in the same die and such technology is called as newlineMultiprocessor System… (more)

Subjects/Keywords: Microarchitectural aims; Multiprocessor System on Chip; Network on Chip

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APA (6th Edition):

U, S. (2015). An investigation on macro and micro Architectures for network on chip;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/40748

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

U, Saravanakumar. “An investigation on macro and micro Architectures for network on chip;.” 2015. Thesis, Anna University. Accessed October 19, 2019. http://shodhganga.inflibnet.ac.in/handle/10603/40748.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

U, Saravanakumar. “An investigation on macro and micro Architectures for network on chip;.” 2015. Web. 19 Oct 2019.

Vancouver:

U S. An investigation on macro and micro Architectures for network on chip;. [Internet] [Thesis]. Anna University; 2015. [cited 2019 Oct 19]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/40748.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

U S. An investigation on macro and micro Architectures for network on chip;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/40748

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Anna University

18. Deeba K. Certain investigations on particle swarm optimization techniques for multiprocessor scheduling;.

Degree: Particle swarm optimization techniques for Multiprocessor scheduling, 2014, Anna University

The present research focuses on Particle Swarm Optimization and its variant approaches for multiprocessor static and dynamic task scheduling problem Scheduling in a multiprocessor architecture… (more)

Subjects/Keywords: Information and communication engineering; Multiprocessor; Particle Swarm Optimization

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APA (6th Edition):

K, D. (2014). Certain investigations on particle swarm optimization techniques for multiprocessor scheduling;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/22652

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

K, Deeba. “Certain investigations on particle swarm optimization techniques for multiprocessor scheduling;.” 2014. Thesis, Anna University. Accessed October 19, 2019. http://shodhganga.inflibnet.ac.in/handle/10603/22652.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

K, Deeba. “Certain investigations on particle swarm optimization techniques for multiprocessor scheduling;.” 2014. Web. 19 Oct 2019.

Vancouver:

K D. Certain investigations on particle swarm optimization techniques for multiprocessor scheduling;. [Internet] [Thesis]. Anna University; 2014. [cited 2019 Oct 19]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/22652.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

K D. Certain investigations on particle swarm optimization techniques for multiprocessor scheduling;. [Thesis]. Anna University; 2014. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/22652

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

19. Visalakshi P. Certain investigations on particle Swarm optimization techniques for Multiprocessor scheduling problems;.

Degree: Certain investigations on particle Swarm optimization techniques for Multiprocessor scheduling problems, 2014, Anna University

The importance of scheduling has increased in recent years due to newlinethe growing consumer demand for variety of reduced product life cycles newline changing markets… (more)

Subjects/Keywords: Dynamic task scheduling; Genetic Algorithms; Multiprocessor scheduling problems; Particle Swarm Optimization

Page 1

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

P, V. (2014). Certain investigations on particle Swarm optimization techniques for Multiprocessor scheduling problems;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/29042

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

P, Visalakshi. “Certain investigations on particle Swarm optimization techniques for Multiprocessor scheduling problems;.” 2014. Thesis, Anna University. Accessed October 19, 2019. http://shodhganga.inflibnet.ac.in/handle/10603/29042.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

P, Visalakshi. “Certain investigations on particle Swarm optimization techniques for Multiprocessor scheduling problems;.” 2014. Web. 19 Oct 2019.

Vancouver:

P V. Certain investigations on particle Swarm optimization techniques for Multiprocessor scheduling problems;. [Internet] [Thesis]. Anna University; 2014. [cited 2019 Oct 19]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/29042.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

P V. Certain investigations on particle Swarm optimization techniques for Multiprocessor scheduling problems;. [Thesis]. Anna University; 2014. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/29042

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

20. Yang, Ming-Shiun. Performance Analysis for Multiprocessor Target Platform in QEMU-SystemC.

Degree: Master, Computer Science and Engineering, 2017, NSYSU

 With the development of embedded systems, there are more and more functions in the system and the chip speed increasingly faster and faster. Multiprocessor architecture… (more)

Subjects/Keywords: SystemC; QEMU; SW/HW Co-Verification; Performance Analysis; Multiprocessor

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APA (6th Edition):

Yang, M. (2017). Performance Analysis for Multiprocessor Target Platform in QEMU-SystemC. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-123237

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yang, Ming-Shiun. “Performance Analysis for Multiprocessor Target Platform in QEMU-SystemC.” 2017. Thesis, NSYSU. Accessed October 19, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-123237.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yang, Ming-Shiun. “Performance Analysis for Multiprocessor Target Platform in QEMU-SystemC.” 2017. Web. 19 Oct 2019.

Vancouver:

Yang M. Performance Analysis for Multiprocessor Target Platform in QEMU-SystemC. [Internet] [Thesis]. NSYSU; 2017. [cited 2019 Oct 19]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-123237.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang M. Performance Analysis for Multiprocessor Target Platform in QEMU-SystemC. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-123237

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

21. Boberg, Jessika. A comparison of sequencing formulations in a constraint generation procedure for avionics scheduling.

Degree: Faculty of Science & Engineering, 2017, Linköping UniversityLinköping University

  This thesis compares different mixed integer programming (MIP) formulations for sequencing of tasks in the context of avionics scheduling. Sequencing is a key concern… (more)

Subjects/Keywords: Scheduling; avionics scheduling; multiprocessor scheduling; mixed integer programming; Mathematics; Matematik

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APA (6th Edition):

Boberg, J. (2017). A comparison of sequencing formulations in a constraint generation procedure for avionics scheduling. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-143274

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Boberg, Jessika. “A comparison of sequencing formulations in a constraint generation procedure for avionics scheduling.” 2017. Thesis, Linköping UniversityLinköping University. Accessed October 19, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-143274.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Boberg, Jessika. “A comparison of sequencing formulations in a constraint generation procedure for avionics scheduling.” 2017. Web. 19 Oct 2019.

Vancouver:

Boberg J. A comparison of sequencing formulations in a constraint generation procedure for avionics scheduling. [Internet] [Thesis]. Linköping UniversityLinköping University; 2017. [cited 2019 Oct 19]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-143274.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Boberg J. A comparison of sequencing formulations in a constraint generation procedure for avionics scheduling. [Thesis]. Linköping UniversityLinköping University; 2017. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-143274

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

22. Liang, Yuchen. OpenMPBench : An Open-Source Benchmark for Multiprocessor Based Embedded Systems.

Degree: 2010, , School of Computing

It is a new and open-source benchmark for multiprocessor based embedded system. It comprises a set of parallel implementations for seven classical algorithms that… (more)

Subjects/Keywords: Benchmark; Multiprocessor; Linux Multithread; Parallel Algorithm; Computer Sciences; Datavetenskap (datalogi)

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APA (6th Edition):

Liang, Y. (2010). OpenMPBench : An Open-Source Benchmark for Multiprocessor Based Embedded Systems. (Thesis). , School of Computing. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:bth-4556

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liang, Yuchen. “OpenMPBench : An Open-Source Benchmark for Multiprocessor Based Embedded Systems.” 2010. Thesis, , School of Computing. Accessed October 19, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-4556.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liang, Yuchen. “OpenMPBench : An Open-Source Benchmark for Multiprocessor Based Embedded Systems.” 2010. Web. 19 Oct 2019.

Vancouver:

Liang Y. OpenMPBench : An Open-Source Benchmark for Multiprocessor Based Embedded Systems. [Internet] [Thesis]. , School of Computing; 2010. [cited 2019 Oct 19]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:bth-4556.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liang Y. OpenMPBench : An Open-Source Benchmark for Multiprocessor Based Embedded Systems. [Thesis]. , School of Computing; 2010. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:bth-4556

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Cincinnati

23. Panda, Amayika. A Novel Configurable Benchmarking System for Multi-core Architectures.

Degree: MS, Engineering and Applied Science: Computer Engineering, 2011, University of Cincinnati

  Multi-core architectures have been an important area of research in recent years. This has been driven by the constant need to improve the performance… (more)

Subjects/Keywords: Computer Engineering; benchmark; multi-core; architecture; configurable; benchmarking; multiprocessor

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APA (6th Edition):

Panda, A. (2011). A Novel Configurable Benchmarking System for Multi-core Architectures. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1300479983

Chicago Manual of Style (16th Edition):

Panda, Amayika. “A Novel Configurable Benchmarking System for Multi-core Architectures.” 2011. Masters Thesis, University of Cincinnati. Accessed October 19, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1300479983.

MLA Handbook (7th Edition):

Panda, Amayika. “A Novel Configurable Benchmarking System for Multi-core Architectures.” 2011. Web. 19 Oct 2019.

Vancouver:

Panda A. A Novel Configurable Benchmarking System for Multi-core Architectures. [Internet] [Masters thesis]. University of Cincinnati; 2011. [cited 2019 Oct 19]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1300479983.

Council of Science Editors:

Panda A. A Novel Configurable Benchmarking System for Multi-core Architectures. [Masters Thesis]. University of Cincinnati; 2011. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1300479983


Universiteit Utrecht

24. Verriet, J.H. Scheduling with communication for multiprocessor computation.

Degree: 1998, Universiteit Utrecht

Multiprocessor scheduling houdt zich bezig met de planning van de uitvoering van computer-programma s op een parallelle computer. Een computerprogramma kan worden gezien als een… (more)

Subjects/Keywords: Wiskunde en Informatica; multiprocessor computation

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APA (6th Edition):

Verriet, J. H. (1998). Scheduling with communication for multiprocessor computation. (Doctoral Dissertation). Universiteit Utrecht. Retrieved from http://dspace.library.uu.nl:8080/handle/1874/835

Chicago Manual of Style (16th Edition):

Verriet, J H. “Scheduling with communication for multiprocessor computation.” 1998. Doctoral Dissertation, Universiteit Utrecht. Accessed October 19, 2019. http://dspace.library.uu.nl:8080/handle/1874/835.

MLA Handbook (7th Edition):

Verriet, J H. “Scheduling with communication for multiprocessor computation.” 1998. Web. 19 Oct 2019.

Vancouver:

Verriet JH. Scheduling with communication for multiprocessor computation. [Internet] [Doctoral dissertation]. Universiteit Utrecht; 1998. [cited 2019 Oct 19]. Available from: http://dspace.library.uu.nl:8080/handle/1874/835.

Council of Science Editors:

Verriet JH. Scheduling with communication for multiprocessor computation. [Doctoral Dissertation]. Universiteit Utrecht; 1998. Available from: http://dspace.library.uu.nl:8080/handle/1874/835

25. Coêlho de Araújo, Cristiano. Communication mapping in multiprocessor platforms .

Degree: 2005, Universidade Federal de Pernambuco

 Os avanços na tecnologia de fabricação de circuitos integrados tem permitido a implementação de sistemas inteiros em um único chip, combinando alto poder de processamento… (more)

Subjects/Keywords: Multiprocessor platform; Digital systems

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APA (6th Edition):

Coêlho de Araújo, C. (2005). Communication mapping in multiprocessor platforms . (Thesis). Universidade Federal de Pernambuco. Retrieved from http://repositorio.ufpe.br/handle/123456789/2098

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Coêlho de Araújo, Cristiano. “Communication mapping in multiprocessor platforms .” 2005. Thesis, Universidade Federal de Pernambuco. Accessed October 19, 2019. http://repositorio.ufpe.br/handle/123456789/2098.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Coêlho de Araújo, Cristiano. “Communication mapping in multiprocessor platforms .” 2005. Web. 19 Oct 2019.

Vancouver:

Coêlho de Araújo C. Communication mapping in multiprocessor platforms . [Internet] [Thesis]. Universidade Federal de Pernambuco; 2005. [cited 2019 Oct 19]. Available from: http://repositorio.ufpe.br/handle/123456789/2098.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Coêlho de Araújo C. Communication mapping in multiprocessor platforms . [Thesis]. Universidade Federal de Pernambuco; 2005. Available from: http://repositorio.ufpe.br/handle/123456789/2098

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Case Western Reserve University

26. Kim, Hyun Soo. Bat Intelligent Hunting Optimization with Application to Multiprocessor Scheduling.

Degree: PhD, EECS - System and Control Engineering, 2010, Case Western Reserve University

 In this dissertation, we introduce a novel heuristic, Bat Intelligent Hunting, for the first time. Similar to many existing heuristics, the Bat Intelligent Hunting provides… (more)

Subjects/Keywords: Computer Science; Systems Design; heuristic; multiprocessor scheduling, multiple objective optimization

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APA (6th Edition):

Kim, H. S. (2010). Bat Intelligent Hunting Optimization with Application to Multiprocessor Scheduling. (Doctoral Dissertation). Case Western Reserve University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=case1274471808

Chicago Manual of Style (16th Edition):

Kim, Hyun Soo. “Bat Intelligent Hunting Optimization with Application to Multiprocessor Scheduling.” 2010. Doctoral Dissertation, Case Western Reserve University. Accessed October 19, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=case1274471808.

MLA Handbook (7th Edition):

Kim, Hyun Soo. “Bat Intelligent Hunting Optimization with Application to Multiprocessor Scheduling.” 2010. Web. 19 Oct 2019.

Vancouver:

Kim HS. Bat Intelligent Hunting Optimization with Application to Multiprocessor Scheduling. [Internet] [Doctoral dissertation]. Case Western Reserve University; 2010. [cited 2019 Oct 19]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=case1274471808.

Council of Science Editors:

Kim HS. Bat Intelligent Hunting Optimization with Application to Multiprocessor Scheduling. [Doctoral Dissertation]. Case Western Reserve University; 2010. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=case1274471808


Ohio University

27. Bien-aise, Hemsley. Adaptive Shared Cache Migration Policy.

Degree: MS, Electrical Engineering (Engineering and Technology), 2010, Ohio University

 The expensive off-chip memory accesses combined with growing on-chip communication delays have called for a reconfigurable last level cache (LLC) to avoid caches from becoming… (more)

Subjects/Keywords: Electrical Engineering; L2 cache; CMP; chip multiprocessor; shared; migration; tiled; NUCA

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bien-aise, H. (2010). Adaptive Shared Cache Migration Policy. (Masters Thesis). Ohio University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1275506661

Chicago Manual of Style (16th Edition):

Bien-aise, Hemsley. “Adaptive Shared Cache Migration Policy.” 2010. Masters Thesis, Ohio University. Accessed October 19, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1275506661.

MLA Handbook (7th Edition):

Bien-aise, Hemsley. “Adaptive Shared Cache Migration Policy.” 2010. Web. 19 Oct 2019.

Vancouver:

Bien-aise H. Adaptive Shared Cache Migration Policy. [Internet] [Masters thesis]. Ohio University; 2010. [cited 2019 Oct 19]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1275506661.

Council of Science Editors:

Bien-aise H. Adaptive Shared Cache Migration Policy. [Masters Thesis]. Ohio University; 2010. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1275506661


Penn State University

28. Johnson, Jacob. Power Efficiency and Scaling of the Cell Broadband Engine.

Degree: MS, Computer Science and Engineering, 2009, Penn State University

  Since the 1980s, frequency scaling, brought on by Moore's Law, has given us increased uniprocessor performance at a steady rate and with no cost… (more)

Subjects/Keywords: memory bottleneck; power efficiency; Littles Law; Cell processor; chip multiprocessor

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Johnson, J. (2009). Power Efficiency and Scaling of the Cell Broadband Engine. (Masters Thesis). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/9587

Chicago Manual of Style (16th Edition):

Johnson, Jacob. “Power Efficiency and Scaling of the Cell Broadband Engine.” 2009. Masters Thesis, Penn State University. Accessed October 19, 2019. https://etda.libraries.psu.edu/catalog/9587.

MLA Handbook (7th Edition):

Johnson, Jacob. “Power Efficiency and Scaling of the Cell Broadband Engine.” 2009. Web. 19 Oct 2019.

Vancouver:

Johnson J. Power Efficiency and Scaling of the Cell Broadband Engine. [Internet] [Masters thesis]. Penn State University; 2009. [cited 2019 Oct 19]. Available from: https://etda.libraries.psu.edu/catalog/9587.

Council of Science Editors:

Johnson J. Power Efficiency and Scaling of the Cell Broadband Engine. [Masters Thesis]. Penn State University; 2009. Available from: https://etda.libraries.psu.edu/catalog/9587


Halmstad University

29. Gong, Shaojie. Benchmarks for Embedded Multi-processors.

Degree: Computer and Electrical Engineering (IDE), 2007, Halmstad University

  During the recent years, computer performance has increased dramatically. To measure the performance of computers, benchmarks are ideal tools. Benchmarks exist in many areas… (more)

Subjects/Keywords: benchmarks; embedded multiprocessor systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gong, S. (2007). Benchmarks for Embedded Multi-processors. (Thesis). Halmstad University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-660

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gong, Shaojie. “Benchmarks for Embedded Multi-processors.” 2007. Thesis, Halmstad University. Accessed October 19, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-660.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gong, Shaojie. “Benchmarks for Embedded Multi-processors.” 2007. Web. 19 Oct 2019.

Vancouver:

Gong S. Benchmarks for Embedded Multi-processors. [Internet] [Thesis]. Halmstad University; 2007. [cited 2019 Oct 19]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-660.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gong S. Benchmarks for Embedded Multi-processors. [Thesis]. Halmstad University; 2007. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-660

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Pontifical Catholic University of Rio de Janeiro

30. LUIZ ANDRE BARROSO. [en] A METHODOLOGY TO ANALYZE THE PERFORMANCE OF SCIENTIFIC APPLICATIONS IN MULTIPROCESSOR SYSTEM.

Degree: 2009, Pontifical Catholic University of Rio de Janeiro

[pt] Neste trabalho é abordado o problema da análise de desempenho de aplicações paralelas, especificamente de programas científicos. Apresentamos uma metodologia para a construção de… (more)

Subjects/Keywords: [pt] MULTIPROCESSADOR; [en] MULTIPROCESSOR; [pt] MEMORIA COMPARTILHADA; [en] SHARED MEMORY

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

BARROSO, L. A. (2009). [en] A METHODOLOGY TO ANALYZE THE PERFORMANCE OF SCIENTIFIC APPLICATIONS IN MULTIPROCESSOR SYSTEM. (Thesis). Pontifical Catholic University of Rio de Janeiro. Retrieved from http://www.maxwell.vrac.puc-rio.br/Busca_etds.php?strSecao=resultado&nrSeq=14121

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

BARROSO, LUIZ ANDRE. “[en] A METHODOLOGY TO ANALYZE THE PERFORMANCE OF SCIENTIFIC APPLICATIONS IN MULTIPROCESSOR SYSTEM.” 2009. Thesis, Pontifical Catholic University of Rio de Janeiro. Accessed October 19, 2019. http://www.maxwell.vrac.puc-rio.br/Busca_etds.php?strSecao=resultado&nrSeq=14121.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

BARROSO, LUIZ ANDRE. “[en] A METHODOLOGY TO ANALYZE THE PERFORMANCE OF SCIENTIFIC APPLICATIONS IN MULTIPROCESSOR SYSTEM.” 2009. Web. 19 Oct 2019.

Vancouver:

BARROSO LA. [en] A METHODOLOGY TO ANALYZE THE PERFORMANCE OF SCIENTIFIC APPLICATIONS IN MULTIPROCESSOR SYSTEM. [Internet] [Thesis]. Pontifical Catholic University of Rio de Janeiro; 2009. [cited 2019 Oct 19]. Available from: http://www.maxwell.vrac.puc-rio.br/Busca_etds.php?strSecao=resultado&nrSeq=14121.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

BARROSO LA. [en] A METHODOLOGY TO ANALYZE THE PERFORMANCE OF SCIENTIFIC APPLICATIONS IN MULTIPROCESSOR SYSTEM. [Thesis]. Pontifical Catholic University of Rio de Janeiro; 2009. Available from: http://www.maxwell.vrac.puc-rio.br/Busca_etds.php?strSecao=resultado&nrSeq=14121

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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