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You searched for subject:(multiprocessing). Showing records 1 – 30 of 45 total matches.

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University of Oulu

1. Boutellier, J. (Jani). Quasi-static scheduling for fine-grained embedded multiprocessing.

Degree: 2009, University of Oulu

 Abstract Designing energy-efficient multiprocessing hardware for applications such as video decoding or MIMO-OFDM baseband processing is challenging because these applications require high throughput, as well… (more)

Subjects/Keywords: multiprocessing; scheduling; signal processing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Boutellier, J. (. (2009). Quasi-static scheduling for fine-grained embedded multiprocessing. (Doctoral Dissertation). University of Oulu. Retrieved from http://urn.fi/urn:isbn:9789514292729

Chicago Manual of Style (16th Edition):

Boutellier, J (Jani). “Quasi-static scheduling for fine-grained embedded multiprocessing.” 2009. Doctoral Dissertation, University of Oulu. Accessed March 29, 2020. http://urn.fi/urn:isbn:9789514292729.

MLA Handbook (7th Edition):

Boutellier, J (Jani). “Quasi-static scheduling for fine-grained embedded multiprocessing.” 2009. Web. 29 Mar 2020.

Vancouver:

Boutellier J(. Quasi-static scheduling for fine-grained embedded multiprocessing. [Internet] [Doctoral dissertation]. University of Oulu; 2009. [cited 2020 Mar 29]. Available from: http://urn.fi/urn:isbn:9789514292729.

Council of Science Editors:

Boutellier J(. Quasi-static scheduling for fine-grained embedded multiprocessing. [Doctoral Dissertation]. University of Oulu; 2009. Available from: http://urn.fi/urn:isbn:9789514292729


Virginia Tech

2. Chao, Lance Rolin. Symmetric MultiProcessing for the Pintos Instructional Operating System.

Degree: MS, Computer Science, 2017, Virginia Tech

 For the last decade, practical limitations have prevented processor speeds from increasing significantly. To increase throughput, the computing industry has turned to multiprocessing; that is,… (more)

Subjects/Keywords: Pintos; Symmetric Multiprocessing; Education; OS

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APA (6th Edition):

Chao, L. R. (2017). Symmetric MultiProcessing for the Pintos Instructional Operating System. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/78293

Chicago Manual of Style (16th Edition):

Chao, Lance Rolin. “Symmetric MultiProcessing for the Pintos Instructional Operating System.” 2017. Masters Thesis, Virginia Tech. Accessed March 29, 2020. http://hdl.handle.net/10919/78293.

MLA Handbook (7th Edition):

Chao, Lance Rolin. “Symmetric MultiProcessing for the Pintos Instructional Operating System.” 2017. Web. 29 Mar 2020.

Vancouver:

Chao LR. Symmetric MultiProcessing for the Pintos Instructional Operating System. [Internet] [Masters thesis]. Virginia Tech; 2017. [cited 2020 Mar 29]. Available from: http://hdl.handle.net/10919/78293.

Council of Science Editors:

Chao LR. Symmetric MultiProcessing for the Pintos Instructional Operating System. [Masters Thesis]. Virginia Tech; 2017. Available from: http://hdl.handle.net/10919/78293

3. Schnarz, Pierre. Security patterns for AMP-based embedded systems.

Degree: 2019, Technische Universität Dortmund

The consolidation of diverse functionalities onto a single platform is an ongoing, and still emerging, trend in the development of automotive electronic control units. More… (more)

Subjects/Keywords: ddc:004; Security  – Asynchronous  – Multiprocessing

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APA (6th Edition):

Schnarz, P. (2019). Security patterns for AMP-based embedded systems. (Thesis). Technische Universität Dortmund. Retrieved from https://doi.org/10.21268/20190606-0 ; https://nbn-resolving.org/urn:nbn:de:gbv:104-20190606-00000-8 ; https://dokumente.ub.tu-clausthal.de/receive/clausthal_mods_00000907 ; https://dokumente.ub.tu-clausthal.de/servlets/MCRFileNodeServlet/clausthal_derivate_00000662/Db114064.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Schnarz, Pierre. “Security patterns for AMP-based embedded systems.” 2019. Thesis, Technische Universität Dortmund. Accessed March 29, 2020. https://doi.org/10.21268/20190606-0 ; https://nbn-resolving.org/urn:nbn:de:gbv:104-20190606-00000-8 ; https://dokumente.ub.tu-clausthal.de/receive/clausthal_mods_00000907 ; https://dokumente.ub.tu-clausthal.de/servlets/MCRFileNodeServlet/clausthal_derivate_00000662/Db114064.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Schnarz, Pierre. “Security patterns for AMP-based embedded systems.” 2019. Web. 29 Mar 2020.

Vancouver:

Schnarz P. Security patterns for AMP-based embedded systems. [Internet] [Thesis]. Technische Universität Dortmund; 2019. [cited 2020 Mar 29]. Available from: https://doi.org/10.21268/20190606-0 ; https://nbn-resolving.org/urn:nbn:de:gbv:104-20190606-00000-8 ; https://dokumente.ub.tu-clausthal.de/receive/clausthal_mods_00000907 ; https://dokumente.ub.tu-clausthal.de/servlets/MCRFileNodeServlet/clausthal_derivate_00000662/Db114064.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Schnarz P. Security patterns for AMP-based embedded systems. [Thesis]. Technische Universität Dortmund; 2019. Available from: https://doi.org/10.21268/20190606-0 ; https://nbn-resolving.org/urn:nbn:de:gbv:104-20190606-00000-8 ; https://dokumente.ub.tu-clausthal.de/receive/clausthal_mods_00000907 ; https://dokumente.ub.tu-clausthal.de/servlets/MCRFileNodeServlet/clausthal_derivate_00000662/Db114064.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Manitoba

4. Cook, Darcy Philip. A multiprocessng system-on-chip framework targeting stream-oriented applications.

Degree: Electrical and Computer Engineering, 2011, University of Manitoba

 Over the past decade, the processing speed requirement of embedded systems has steadily increased. Since faster clocking of a single processor can no longer be… (more)

Subjects/Keywords: system-on-chip; multiprocessing

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APA (6th Edition):

Cook, D. P. (2011). A multiprocessng system-on-chip framework targeting stream-oriented applications. (Masters Thesis). University of Manitoba. Retrieved from http://hdl.handle.net/1993/4383

Chicago Manual of Style (16th Edition):

Cook, Darcy Philip. “A multiprocessng system-on-chip framework targeting stream-oriented applications.” 2011. Masters Thesis, University of Manitoba. Accessed March 29, 2020. http://hdl.handle.net/1993/4383.

MLA Handbook (7th Edition):

Cook, Darcy Philip. “A multiprocessng system-on-chip framework targeting stream-oriented applications.” 2011. Web. 29 Mar 2020.

Vancouver:

Cook DP. A multiprocessng system-on-chip framework targeting stream-oriented applications. [Internet] [Masters thesis]. University of Manitoba; 2011. [cited 2020 Mar 29]. Available from: http://hdl.handle.net/1993/4383.

Council of Science Editors:

Cook DP. A multiprocessng system-on-chip framework targeting stream-oriented applications. [Masters Thesis]. University of Manitoba; 2011. Available from: http://hdl.handle.net/1993/4383


Georgia State University

5. Sindhu, Viney. Exploring Parallel Efficiency and Synergy for Max-P Region Problem Using Python.

Degree: MS, Computer Science, 2018, Georgia State University

  Given a set of n areas spatially covering a geographical zone such as a province, forming contiguous regions from homogeneous neighboring areas satisfying a… (more)

Subjects/Keywords: Clustering; Geospatial; Homogeneous Regions; Multiprocessing; Optimization

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APA (6th Edition):

Sindhu, V. (2018). Exploring Parallel Efficiency and Synergy for Max-P Region Problem Using Python. (Thesis). Georgia State University. Retrieved from https://scholarworks.gsu.edu/cs_theses/88

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sindhu, Viney. “Exploring Parallel Efficiency and Synergy for Max-P Region Problem Using Python.” 2018. Thesis, Georgia State University. Accessed March 29, 2020. https://scholarworks.gsu.edu/cs_theses/88.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sindhu, Viney. “Exploring Parallel Efficiency and Synergy for Max-P Region Problem Using Python.” 2018. Web. 29 Mar 2020.

Vancouver:

Sindhu V. Exploring Parallel Efficiency and Synergy for Max-P Region Problem Using Python. [Internet] [Thesis]. Georgia State University; 2018. [cited 2020 Mar 29]. Available from: https://scholarworks.gsu.edu/cs_theses/88.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sindhu V. Exploring Parallel Efficiency and Synergy for Max-P Region Problem Using Python. [Thesis]. Georgia State University; 2018. Available from: https://scholarworks.gsu.edu/cs_theses/88

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

6. Dubovský, Tomáš. Framework pro automatizované testování MCUXpresso Config Tools .

Degree: 2019, Brno University of Technology

 Cílem této práce bylo analyzovat stávající řešení frameworku pro testování MCUXpresso Config Tools, dále navrhnout a implementovat různé možnosti optimalizace, které povedou ke zvýšení efektivity… (more)

Subjects/Keywords: MCUXpresso Config Tools; testování; optimalizace; multiprocessing; multithreading; asyncio; python; OOP; MCUXpresso Config Tools; testing; optimization; multiprocessing; multithreading; asyncio; python; OOP

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Dubovský, T. (2019). Framework pro automatizované testování MCUXpresso Config Tools . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/180282

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Dubovský, Tomáš. “Framework pro automatizované testování MCUXpresso Config Tools .” 2019. Thesis, Brno University of Technology. Accessed March 29, 2020. http://hdl.handle.net/11012/180282.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Dubovský, Tomáš. “Framework pro automatizované testování MCUXpresso Config Tools .” 2019. Web. 29 Mar 2020.

Vancouver:

Dubovský T. Framework pro automatizované testování MCUXpresso Config Tools . [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2020 Mar 29]. Available from: http://hdl.handle.net/11012/180282.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Dubovský T. Framework pro automatizované testování MCUXpresso Config Tools . [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/180282

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Queens University

7. Pau, Ronny. A Configurable Router for Embedded Network-on-Chip Support in Field-Programmable Gate Arrays .

Degree: Electrical and Computer Engineering, 2008, Queens University

 The scaling of VLSI technology has allowed extensive integration of processing resources on a single chip. Consequently, programmable chips is able to have a high… (more)

Subjects/Keywords: FPGA; multiprocessing; network-on-chip

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APA (6th Edition):

Pau, R. (2008). A Configurable Router for Embedded Network-on-Chip Support in Field-Programmable Gate Arrays . (Thesis). Queens University. Retrieved from http://hdl.handle.net/1974/1516

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pau, Ronny. “A Configurable Router for Embedded Network-on-Chip Support in Field-Programmable Gate Arrays .” 2008. Thesis, Queens University. Accessed March 29, 2020. http://hdl.handle.net/1974/1516.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pau, Ronny. “A Configurable Router for Embedded Network-on-Chip Support in Field-Programmable Gate Arrays .” 2008. Web. 29 Mar 2020.

Vancouver:

Pau R. A Configurable Router for Embedded Network-on-Chip Support in Field-Programmable Gate Arrays . [Internet] [Thesis]. Queens University; 2008. [cited 2020 Mar 29]. Available from: http://hdl.handle.net/1974/1516.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pau R. A Configurable Router for Embedded Network-on-Chip Support in Field-Programmable Gate Arrays . [Thesis]. Queens University; 2008. Available from: http://hdl.handle.net/1974/1516

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

8. Bueno, Maikon Adiles Fernandez. Co-projeto de hardware e software de um escalonador de processos para arquiteturas multicore heterogêneas baseadas em computação reconfigurável.

Degree: PhD, Ciências de Computação e Matemática Computacional, 2013, University of São Paulo

As arquiteturas multiprocessadas heterogêneas têm como objetivo principal a extração de maior desempenho da execução dos processos, por meio da utilização de núcleos apropriados às… (more)

Subjects/Keywords: Computação reconfigurável; Escalonador; Heterogeneous multiprocessing; Multi-core; Multicore; Multiprocessamento heterogêneo; Reconfigurable computing; Scheduler

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bueno, M. A. F. (2013). Co-projeto de hardware e software de um escalonador de processos para arquiteturas multicore heterogêneas baseadas em computação reconfigurável. (Doctoral Dissertation). University of São Paulo. Retrieved from http://www.teses.usp.br/teses/disponiveis/55/55134/tde-29012014-105417/ ;

Chicago Manual of Style (16th Edition):

Bueno, Maikon Adiles Fernandez. “Co-projeto de hardware e software de um escalonador de processos para arquiteturas multicore heterogêneas baseadas em computação reconfigurável.” 2013. Doctoral Dissertation, University of São Paulo. Accessed March 29, 2020. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-29012014-105417/ ;.

MLA Handbook (7th Edition):

Bueno, Maikon Adiles Fernandez. “Co-projeto de hardware e software de um escalonador de processos para arquiteturas multicore heterogêneas baseadas em computação reconfigurável.” 2013. Web. 29 Mar 2020.

Vancouver:

Bueno MAF. Co-projeto de hardware e software de um escalonador de processos para arquiteturas multicore heterogêneas baseadas em computação reconfigurável. [Internet] [Doctoral dissertation]. University of São Paulo; 2013. [cited 2020 Mar 29]. Available from: http://www.teses.usp.br/teses/disponiveis/55/55134/tde-29012014-105417/ ;.

Council of Science Editors:

Bueno MAF. Co-projeto de hardware e software de um escalonador de processos para arquiteturas multicore heterogêneas baseadas em computação reconfigurável. [Doctoral Dissertation]. University of São Paulo; 2013. Available from: http://www.teses.usp.br/teses/disponiveis/55/55134/tde-29012014-105417/ ;


Universidad Nacional de La Plata

9. Gaudiani, Adriana. Análisis del rendimiento de algoritmos paralelos de propósito general en GPGPU : Aplicación a un problema de mallado de elementos finitos.

Degree: 2012, Universidad Nacional de La Plata

El objetivo de este trabajo es analizar el desarrollo, optimización y evaluación de algoritmos paralelos de propósito general cuya ejecución se implementa sobre la arquitectura… (more)

Subjects/Keywords: Ciencias Informáticas; GPGPU; algoritmo de mallado; CUDA; multiprocesador; Multiprocessing/multiprogramming/multitasking; Parallel algorithms; Algorithms

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APA (6th Edition):

Gaudiani, A. (2012). Análisis del rendimiento de algoritmos paralelos de propósito general en GPGPU : Aplicación a un problema de mallado de elementos finitos. (Thesis). Universidad Nacional de La Plata. Retrieved from http://hdl.handle.net/10915/22691

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gaudiani, Adriana. “Análisis del rendimiento de algoritmos paralelos de propósito general en GPGPU : Aplicación a un problema de mallado de elementos finitos.” 2012. Thesis, Universidad Nacional de La Plata. Accessed March 29, 2020. http://hdl.handle.net/10915/22691.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gaudiani, Adriana. “Análisis del rendimiento de algoritmos paralelos de propósito general en GPGPU : Aplicación a un problema de mallado de elementos finitos.” 2012. Web. 29 Mar 2020.

Vancouver:

Gaudiani A. Análisis del rendimiento de algoritmos paralelos de propósito general en GPGPU : Aplicación a un problema de mallado de elementos finitos. [Internet] [Thesis]. Universidad Nacional de La Plata; 2012. [cited 2020 Mar 29]. Available from: http://hdl.handle.net/10915/22691.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gaudiani A. Análisis del rendimiento de algoritmos paralelos de propósito general en GPGPU : Aplicación a un problema de mallado de elementos finitos. [Thesis]. Universidad Nacional de La Plata; 2012. Available from: http://hdl.handle.net/10915/22691

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Aristotle University Of Thessaloniki (AUTH); Αριστοτέλειο Πανεπιστήμιο Θεσσαλονίκης (ΑΠΘ)

10. Sotiropoulou, Calliope - Louisa. Multiprocessing systems development for implementation of applications.

Degree: 2014, Aristotle University Of Thessaloniki (AUTH); Αριστοτέλειο Πανεπιστήμιο Θεσσαλονίκης (ΑΠΘ)

This dissertation presents the author’s research in the field of multiprocessing systems for implementation of applications. The main objective is the identification of the optimum… (more)

Subjects/Keywords: Ενσωματωμένα συστήματα; Πολυεπεξεργαστικά συστήματα; Επαναδιαμορφώσιμοι επεξεργαστές; Βελτιστοποίηση; Embedded systems; Multiprocessing systems; Reconfigurable processors; Optimization

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APA (6th Edition):

Sotiropoulou, C. -. L. (2014). Multiprocessing systems development for implementation of applications. (Thesis). Aristotle University Of Thessaloniki (AUTH); Αριστοτέλειο Πανεπιστήμιο Θεσσαλονίκης (ΑΠΘ). Retrieved from http://hdl.handle.net/10442/hedi/35170

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sotiropoulou, Calliope - Louisa. “Multiprocessing systems development for implementation of applications.” 2014. Thesis, Aristotle University Of Thessaloniki (AUTH); Αριστοτέλειο Πανεπιστήμιο Θεσσαλονίκης (ΑΠΘ). Accessed March 29, 2020. http://hdl.handle.net/10442/hedi/35170.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sotiropoulou, Calliope - Louisa. “Multiprocessing systems development for implementation of applications.” 2014. Web. 29 Mar 2020.

Vancouver:

Sotiropoulou C-L. Multiprocessing systems development for implementation of applications. [Internet] [Thesis]. Aristotle University Of Thessaloniki (AUTH); Αριστοτέλειο Πανεπιστήμιο Θεσσαλονίκης (ΑΠΘ); 2014. [cited 2020 Mar 29]. Available from: http://hdl.handle.net/10442/hedi/35170.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sotiropoulou C-L. Multiprocessing systems development for implementation of applications. [Thesis]. Aristotle University Of Thessaloniki (AUTH); Αριστοτέλειο Πανεπιστήμιο Θεσσαλονίκης (ΑΠΘ); 2014. Available from: http://hdl.handle.net/10442/hedi/35170

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

11. Κελεφούρας, Βασίλειος. Μεθοδολογία ανάπτυξης μεταγλωττιστών με εκμετάλλευση της δομής του λογισμικού και του μοντέλου του υλικού του.

Degree: 2013, University of Patras

 Οι υπάρχοντες μεταγλωττιστές, έχουν τρία βασικά μειονεκτήματα i) όλα τα υπό-προβλήματα της μεταγλώττισης (π.χ. μετασχηματισμοί, εύρεση χρονοπρογραμματισμού, ανάθεση καταχωρητών) βελτιστοποιούνται ξεχωριστά (εκτός από μεμονωμένες περιπτώσεις… (more)

Subjects/Keywords: Επαναχρησιμοποίηση δεδομένων; Κρυφή μνήμη δεδομένων; Συσχετιστικότητα; Πολυεπεξεργασία; 005.453; Data reuse; Cache memory; Correlativity; Multiprocessing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Κελεφούρας, . (2013). Μεθοδολογία ανάπτυξης μεταγλωττιστών με εκμετάλλευση της δομής του λογισμικού και του μοντέλου του υλικού του. (Doctoral Dissertation). University of Patras. Retrieved from http://hdl.handle.net/10889/7505

Chicago Manual of Style (16th Edition):

Κελεφούρας, Βασίλειος. “Μεθοδολογία ανάπτυξης μεταγλωττιστών με εκμετάλλευση της δομής του λογισμικού και του μοντέλου του υλικού του.” 2013. Doctoral Dissertation, University of Patras. Accessed March 29, 2020. http://hdl.handle.net/10889/7505.

MLA Handbook (7th Edition):

Κελεφούρας, Βασίλειος. “Μεθοδολογία ανάπτυξης μεταγλωττιστών με εκμετάλλευση της δομής του λογισμικού και του μοντέλου του υλικού του.” 2013. Web. 29 Mar 2020.

Vancouver:

Κελεφούρας . Μεθοδολογία ανάπτυξης μεταγλωττιστών με εκμετάλλευση της δομής του λογισμικού και του μοντέλου του υλικού του. [Internet] [Doctoral dissertation]. University of Patras; 2013. [cited 2020 Mar 29]. Available from: http://hdl.handle.net/10889/7505.

Council of Science Editors:

Κελεφούρας . Μεθοδολογία ανάπτυξης μεταγλωττιστών με εκμετάλλευση της δομής του λογισμικού και του μοντέλου του υλικού του. [Doctoral Dissertation]. University of Patras; 2013. Available from: http://hdl.handle.net/10889/7505


McMaster University

12. Brett, Michael Edward. An Interprocessor Communication Link for Data Minicomputers.

Degree: ME, 1977, McMaster University

The ACTR (Asynchronous Communications Transmitter Receiver) is a serial data transfer link for the Data General ECLIPSE and NOVA minicomputer lines. The ACTR allows… (more)

Subjects/Keywords: ECLIPSE; NOVA; ACTR; multiprocessing; minicomputer lines

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APA (6th Edition):

Brett, M. E. (1977). An Interprocessor Communication Link for Data Minicomputers. (Masters Thesis). McMaster University. Retrieved from http://hdl.handle.net/11375/16685

Chicago Manual of Style (16th Edition):

Brett, Michael Edward. “An Interprocessor Communication Link for Data Minicomputers.” 1977. Masters Thesis, McMaster University. Accessed March 29, 2020. http://hdl.handle.net/11375/16685.

MLA Handbook (7th Edition):

Brett, Michael Edward. “An Interprocessor Communication Link for Data Minicomputers.” 1977. Web. 29 Mar 2020.

Vancouver:

Brett ME. An Interprocessor Communication Link for Data Minicomputers. [Internet] [Masters thesis]. McMaster University; 1977. [cited 2020 Mar 29]. Available from: http://hdl.handle.net/11375/16685.

Council of Science Editors:

Brett ME. An Interprocessor Communication Link for Data Minicomputers. [Masters Thesis]. McMaster University; 1977. Available from: http://hdl.handle.net/11375/16685

13. Lobo, Tiago Mendonça. Co-projeto hardware/software para cálculo de fluxo ótico.

Degree: Mestrado, Ciências de Computação e Matemática Computacional, 2013, University of São Paulo

O cálculo dos vetores de movimento é utilizado em vários processos na área de visão computacional. Problemas como estabelecer rotas de colisão e movimentação da… (more)

Subjects/Keywords: Co-desing; Co-projeto; Fluxo ótico; FPGA; FPGA; multiprocessamento; multiprocessing; Nios II; Nios II; Optical flow

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lobo, T. M. (2013). Co-projeto hardware/software para cálculo de fluxo ótico. (Masters Thesis). University of São Paulo. Retrieved from http://www.teses.usp.br/teses/disponiveis/55/55134/tde-28082013-094816/ ;

Chicago Manual of Style (16th Edition):

Lobo, Tiago Mendonça. “Co-projeto hardware/software para cálculo de fluxo ótico.” 2013. Masters Thesis, University of São Paulo. Accessed March 29, 2020. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-28082013-094816/ ;.

MLA Handbook (7th Edition):

Lobo, Tiago Mendonça. “Co-projeto hardware/software para cálculo de fluxo ótico.” 2013. Web. 29 Mar 2020.

Vancouver:

Lobo TM. Co-projeto hardware/software para cálculo de fluxo ótico. [Internet] [Masters thesis]. University of São Paulo; 2013. [cited 2020 Mar 29]. Available from: http://www.teses.usp.br/teses/disponiveis/55/55134/tde-28082013-094816/ ;.

Council of Science Editors:

Lobo TM. Co-projeto hardware/software para cálculo de fluxo ótico. [Masters Thesis]. University of São Paulo; 2013. Available from: http://www.teses.usp.br/teses/disponiveis/55/55134/tde-28082013-094816/ ;

14. Bueno, Maikon Adiles Fernandez. Análise e implementação de suporte a SMP (multiprocessamento simétrico) para o sistema operacional eCos com aplicação em robótica móvel.

Degree: Mestrado, Ciências de Computação e Matemática Computacional, 2007, University of São Paulo

Technological development has significantly reduced the distance between the performance of systems designed using reconfigurable computing and dedicated hardware. The main sources of performance are… (more)

Subjects/Keywords: eCos and Nios II; eCos e Nios II; Multiprocessamento simétrico; Operating systems; Sistemas operacionais; Symmetric multiprocessing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bueno, M. A. F. (2007). Análise e implementação de suporte a SMP (multiprocessamento simétrico) para o sistema operacional eCos com aplicação em robótica móvel. (Masters Thesis). University of São Paulo. Retrieved from http://www.teses.usp.br/teses/disponiveis/55/55134/tde-21062007-150831/ ;

Chicago Manual of Style (16th Edition):

Bueno, Maikon Adiles Fernandez. “Análise e implementação de suporte a SMP (multiprocessamento simétrico) para o sistema operacional eCos com aplicação em robótica móvel.” 2007. Masters Thesis, University of São Paulo. Accessed March 29, 2020. http://www.teses.usp.br/teses/disponiveis/55/55134/tde-21062007-150831/ ;.

MLA Handbook (7th Edition):

Bueno, Maikon Adiles Fernandez. “Análise e implementação de suporte a SMP (multiprocessamento simétrico) para o sistema operacional eCos com aplicação em robótica móvel.” 2007. Web. 29 Mar 2020.

Vancouver:

Bueno MAF. Análise e implementação de suporte a SMP (multiprocessamento simétrico) para o sistema operacional eCos com aplicação em robótica móvel. [Internet] [Masters thesis]. University of São Paulo; 2007. [cited 2020 Mar 29]. Available from: http://www.teses.usp.br/teses/disponiveis/55/55134/tde-21062007-150831/ ;.

Council of Science Editors:

Bueno MAF. Análise e implementação de suporte a SMP (multiprocessamento simétrico) para o sistema operacional eCos com aplicação em robótica móvel. [Masters Thesis]. University of São Paulo; 2007. Available from: http://www.teses.usp.br/teses/disponiveis/55/55134/tde-21062007-150831/ ;


Vilnius Gediminas Technical University

15. Andrijauskaitė, Aistė. Z serijos kompiuterių aplikacijų valdymas.

Degree: Master, Informatics Engineering, 2011, Vilnius Gediminas Technical University

Baigiamajame magistro darbe nagrinėjami IBM z serijos kompiuteriai, susipaţįstama su jų architektūra ir operacine sistema. Bendrais bruoţais z serijos kompiuteriai palyginami su kitų platformų sistemomis,… (more)

Subjects/Keywords: Z serijos kompiuteriai; Komerciniai serveriai; Daugiaprogramis apdorojimas; IBM Tivoli; IBM mainframes; Commercial servers; Multiprocessing and multitasking systems; IBM Tivoli software

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APA (6th Edition):

Andrijauskaitė, A. (2011). Z serijos kompiuterių aplikacijų valdymas. (Masters Thesis). Vilnius Gediminas Technical University. Retrieved from http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2011~D_20110620_141630-63695 ;

Chicago Manual of Style (16th Edition):

Andrijauskaitė, Aistė. “Z serijos kompiuterių aplikacijų valdymas.” 2011. Masters Thesis, Vilnius Gediminas Technical University. Accessed March 29, 2020. http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2011~D_20110620_141630-63695 ;.

MLA Handbook (7th Edition):

Andrijauskaitė, Aistė. “Z serijos kompiuterių aplikacijų valdymas.” 2011. Web. 29 Mar 2020.

Vancouver:

Andrijauskaitė A. Z serijos kompiuterių aplikacijų valdymas. [Internet] [Masters thesis]. Vilnius Gediminas Technical University; 2011. [cited 2020 Mar 29]. Available from: http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2011~D_20110620_141630-63695 ;.

Council of Science Editors:

Andrijauskaitė A. Z serijos kompiuterių aplikacijų valdymas. [Masters Thesis]. Vilnius Gediminas Technical University; 2011. Available from: http://vddb.laba.lt/obj/LT-eLABa-0001:E.02~2011~D_20110620_141630-63695 ;


UCLA

16. Singh, Digvijay. Improving the Energy Efficiency of Modern Computing Platforms using High-Resolution Real-Time Energy Measurements.

Degree: Electrical Engineering, 2014, UCLA

 High-performance computing platforms have become critical in meeting the demands of modern computing applications. Rising performance requirements in a broad range of platforms from mobile… (more)

Subjects/Keywords: Engineering; Computer science; Computer engineering; Data Compression; Energy Efficient Computing; Energy Measurement; Multiprocessing; Operating System Task Scheduling; Secondary Storage

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APA (6th Edition):

Singh, D. (2014). Improving the Energy Efficiency of Modern Computing Platforms using High-Resolution Real-Time Energy Measurements. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/7j3569nh

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Singh, Digvijay. “Improving the Energy Efficiency of Modern Computing Platforms using High-Resolution Real-Time Energy Measurements.” 2014. Thesis, UCLA. Accessed March 29, 2020. http://www.escholarship.org/uc/item/7j3569nh.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Singh, Digvijay. “Improving the Energy Efficiency of Modern Computing Platforms using High-Resolution Real-Time Energy Measurements.” 2014. Web. 29 Mar 2020.

Vancouver:

Singh D. Improving the Energy Efficiency of Modern Computing Platforms using High-Resolution Real-Time Energy Measurements. [Internet] [Thesis]. UCLA; 2014. [cited 2020 Mar 29]. Available from: http://www.escholarship.org/uc/item/7j3569nh.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Singh D. Improving the Energy Efficiency of Modern Computing Platforms using High-Resolution Real-Time Energy Measurements. [Thesis]. UCLA; 2014. Available from: http://www.escholarship.org/uc/item/7j3569nh

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Western Michigan University

17. Alsafasfeh, Moath Hashim. Multiprocessing Real Time Vision Based System for Condition Monitoring in Solar Panels.

Degree: PhD, Electrical and Computer Engineering, 2017, Western Michigan University

  Enabling an algorithm to be executed in parallel on a multicore or a multiprocessor system has become a necessity for many real time applications.… (more)

Subjects/Keywords: Multiprocessing; real time; solar panels; defect detections; vision based system; condition monitoring; Electrical and Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Alsafasfeh, M. H. (2017). Multiprocessing Real Time Vision Based System for Condition Monitoring in Solar Panels. (Doctoral Dissertation). Western Michigan University. Retrieved from https://scholarworks.wmich.edu/dissertations/3119

Chicago Manual of Style (16th Edition):

Alsafasfeh, Moath Hashim. “Multiprocessing Real Time Vision Based System for Condition Monitoring in Solar Panels.” 2017. Doctoral Dissertation, Western Michigan University. Accessed March 29, 2020. https://scholarworks.wmich.edu/dissertations/3119.

MLA Handbook (7th Edition):

Alsafasfeh, Moath Hashim. “Multiprocessing Real Time Vision Based System for Condition Monitoring in Solar Panels.” 2017. Web. 29 Mar 2020.

Vancouver:

Alsafasfeh MH. Multiprocessing Real Time Vision Based System for Condition Monitoring in Solar Panels. [Internet] [Doctoral dissertation]. Western Michigan University; 2017. [cited 2020 Mar 29]. Available from: https://scholarworks.wmich.edu/dissertations/3119.

Council of Science Editors:

Alsafasfeh MH. Multiprocessing Real Time Vision Based System for Condition Monitoring in Solar Panels. [Doctoral Dissertation]. Western Michigan University; 2017. Available from: https://scholarworks.wmich.edu/dissertations/3119

18. Hoffman, Kevin John. Ribbons: A Partially Shared Memory Programming Model.

Degree: PhD, Computer Science, 2013, Purdue University

  The need for programs to execute subcomponents in isolation from each other or with lower privileges is prevalent among today's systems. While modern operating… (more)

Subjects/Keywords: heap isolation; multiprocessing; shared memory; Computer Sciences

…memory than multiprocessing yet is more restrictive than multithreading. The ribbons model… …ribbonized multiprocessing module, and performance is analyzed via the Apache HTTP benchmarking… …memory than multiprocessing yet is more restrictive than multithreading. The ribbons model… …Apache httpd with a ribbonized multiprocessing module and studies performance di↵erences… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hoffman, K. J. (2013). Ribbons: A Partially Shared Memory Programming Model. (Doctoral Dissertation). Purdue University. Retrieved from https://docs.lib.purdue.edu/open_access_dissertations/159

Chicago Manual of Style (16th Edition):

Hoffman, Kevin John. “Ribbons: A Partially Shared Memory Programming Model.” 2013. Doctoral Dissertation, Purdue University. Accessed March 29, 2020. https://docs.lib.purdue.edu/open_access_dissertations/159.

MLA Handbook (7th Edition):

Hoffman, Kevin John. “Ribbons: A Partially Shared Memory Programming Model.” 2013. Web. 29 Mar 2020.

Vancouver:

Hoffman KJ. Ribbons: A Partially Shared Memory Programming Model. [Internet] [Doctoral dissertation]. Purdue University; 2013. [cited 2020 Mar 29]. Available from: https://docs.lib.purdue.edu/open_access_dissertations/159.

Council of Science Editors:

Hoffman KJ. Ribbons: A Partially Shared Memory Programming Model. [Doctoral Dissertation]. Purdue University; 2013. Available from: https://docs.lib.purdue.edu/open_access_dissertations/159


Linköping University

19. Durairaj, Selva Ganesh. Parallelize Automated Tests in a Build and Test Environment.

Degree: Software and Systems, 2016, Linköping University

  This thesis investigates the possibilities of finding solutions, in order to reduce the total time spent for testing and waiting times for running multiple… (more)

Subjects/Keywords: function tests; test automation; resource allocation; multiprocessing; parallel testing; scheduling algorithms; evaluation; simulation; prototyping; Computer Sciences; Datavetenskap (datalogi)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Durairaj, S. G. (2016). Parallelize Automated Tests in a Build and Test Environment. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-131807

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Durairaj, Selva Ganesh. “Parallelize Automated Tests in a Build and Test Environment.” 2016. Thesis, Linköping University. Accessed March 29, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-131807.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Durairaj, Selva Ganesh. “Parallelize Automated Tests in a Build and Test Environment.” 2016. Web. 29 Mar 2020.

Vancouver:

Durairaj SG. Parallelize Automated Tests in a Build and Test Environment. [Internet] [Thesis]. Linköping University; 2016. [cited 2020 Mar 29]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-131807.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Durairaj SG. Parallelize Automated Tests in a Build and Test Environment. [Thesis]. Linköping University; 2016. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-131807

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

20. Darera, Vivek N. Bounds For Scheduling In Non-Identical Uniform Multiprocessor Systems.

Degree: 2006, Indian Institute of Science

 With multiprocessors and multicore processors becoming ubiquitous, focus has shifted from research on uniprocessors to that on multiprocessors. Results derived for the uniprocessor case unfortunately… (more)

Subjects/Keywords: Multiprocessing; Multiprocessor Systems - Scheduling Algorithms; Dynamic-Priority Scheduling; Fixed-Priority Scheduling; Uniform Multiprocessor Model; Multiprocessor Scheduling; Allocation Decreasing Algorithm; Earliest Deadline First (EDF); Rate Monotonic (RM); Computer Science

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APA (6th Edition):

Darera, V. N. (2006). Bounds For Scheduling In Non-Identical Uniform Multiprocessor Systems. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/342

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Darera, Vivek N. “Bounds For Scheduling In Non-Identical Uniform Multiprocessor Systems.” 2006. Thesis, Indian Institute of Science. Accessed March 29, 2020. http://hdl.handle.net/2005/342.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Darera, Vivek N. “Bounds For Scheduling In Non-Identical Uniform Multiprocessor Systems.” 2006. Web. 29 Mar 2020.

Vancouver:

Darera VN. Bounds For Scheduling In Non-Identical Uniform Multiprocessor Systems. [Internet] [Thesis]. Indian Institute of Science; 2006. [cited 2020 Mar 29]. Available from: http://hdl.handle.net/2005/342.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Darera VN. Bounds For Scheduling In Non-Identical Uniform Multiprocessor Systems. [Thesis]. Indian Institute of Science; 2006. Available from: http://hdl.handle.net/2005/342

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

21. Vivekanand, V. Characterizing The Vulnerability Of Parallelism To Resource Constraints.

Degree: 1996, Indian Institute of Science

Subjects/Keywords: Parallel Processing (Electronic Computers); Multiprocessing; Parallelism; Scheduling Algorithms; Vulnerability; Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vivekanand, V. (1996). Characterizing The Vulnerability Of Parallelism To Resource Constraints. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/1689

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vivekanand, V. “Characterizing The Vulnerability Of Parallelism To Resource Constraints.” 1996. Thesis, Indian Institute of Science. Accessed March 29, 2020. http://hdl.handle.net/2005/1689.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vivekanand, V. “Characterizing The Vulnerability Of Parallelism To Resource Constraints.” 1996. Web. 29 Mar 2020.

Vancouver:

Vivekanand V. Characterizing The Vulnerability Of Parallelism To Resource Constraints. [Internet] [Thesis]. Indian Institute of Science; 1996. [cited 2020 Mar 29]. Available from: http://hdl.handle.net/2005/1689.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vivekanand V. Characterizing The Vulnerability Of Parallelism To Resource Constraints. [Thesis]. Indian Institute of Science; 1996. Available from: http://hdl.handle.net/2005/1689

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brunel University

22. Mohamad, Sabah Mohamad Amin. Construction of a support tool for the design of the activity structures based computer system architectures.

Degree: PhD, 1986, Brunel University

 This thesis is a reapproachment of diverse design concepts, brought to bear upon the computer system engineering problem of identification and control of highly constrained… (more)

Subjects/Keywords: 621.39; Computer system design : Highly constrained multiprocessing : Activity structures methodology : Support software tool

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mohamad, S. M. A. (1986). Construction of a support tool for the design of the activity structures based computer system architectures. (Doctoral Dissertation). Brunel University. Retrieved from http://bura.brunel.ac.uk/handle/2438/7882 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.372516

Chicago Manual of Style (16th Edition):

Mohamad, Sabah Mohamad Amin. “Construction of a support tool for the design of the activity structures based computer system architectures.” 1986. Doctoral Dissertation, Brunel University. Accessed March 29, 2020. http://bura.brunel.ac.uk/handle/2438/7882 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.372516.

MLA Handbook (7th Edition):

Mohamad, Sabah Mohamad Amin. “Construction of a support tool for the design of the activity structures based computer system architectures.” 1986. Web. 29 Mar 2020.

Vancouver:

Mohamad SMA. Construction of a support tool for the design of the activity structures based computer system architectures. [Internet] [Doctoral dissertation]. Brunel University; 1986. [cited 2020 Mar 29]. Available from: http://bura.brunel.ac.uk/handle/2438/7882 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.372516.

Council of Science Editors:

Mohamad SMA. Construction of a support tool for the design of the activity structures based computer system architectures. [Doctoral Dissertation]. Brunel University; 1986. Available from: http://bura.brunel.ac.uk/handle/2438/7882 ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.372516


Indian Institute of Science

23. Vivekanand, V. Characterizing The Vulnerability Of Parallelism To Resource Constraints.

Degree: 1996, Indian Institute of Science

Subjects/Keywords: Parallel Processing (Electronic Computers); Multiprocessing; Parallelism; Scheduling Algorithms; Vulnerability; Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vivekanand, V. (1996). Characterizing The Vulnerability Of Parallelism To Resource Constraints. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/1689 ; http://etd.ncsi.iisc.ernet.in/abstracts/2182/G14450-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vivekanand, V. “Characterizing The Vulnerability Of Parallelism To Resource Constraints.” 1996. Thesis, Indian Institute of Science. Accessed March 29, 2020. http://etd.iisc.ernet.in/handle/2005/1689 ; http://etd.ncsi.iisc.ernet.in/abstracts/2182/G14450-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vivekanand, V. “Characterizing The Vulnerability Of Parallelism To Resource Constraints.” 1996. Web. 29 Mar 2020.

Vancouver:

Vivekanand V. Characterizing The Vulnerability Of Parallelism To Resource Constraints. [Internet] [Thesis]. Indian Institute of Science; 1996. [cited 2020 Mar 29]. Available from: http://etd.iisc.ernet.in/handle/2005/1689 ; http://etd.ncsi.iisc.ernet.in/abstracts/2182/G14450-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vivekanand V. Characterizing The Vulnerability Of Parallelism To Resource Constraints. [Thesis]. Indian Institute of Science; 1996. Available from: http://etd.iisc.ernet.in/handle/2005/1689 ; http://etd.ncsi.iisc.ernet.in/abstracts/2182/G14450-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Ohio University

24. Morel, Michael. Development and evaluation of a multiprocessing structural vibration algorithm.

Degree: MS, Civil Engineering (Engineering), 1988, Ohio University

  A new parallel algorithm utilizing the finite element method for free vibration analysis of large linear elastic models is developed, tested and evaluated herein.… (more)

Subjects/Keywords: Engineering, Civil; Large Linear Elastic Models; Multiprocessing Structural Vibration Classical Frontal Technique

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Morel, M. (1988). Development and evaluation of a multiprocessing structural vibration algorithm. (Masters Thesis). Ohio University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1182868176

Chicago Manual of Style (16th Edition):

Morel, Michael. “Development and evaluation of a multiprocessing structural vibration algorithm.” 1988. Masters Thesis, Ohio University. Accessed March 29, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1182868176.

MLA Handbook (7th Edition):

Morel, Michael. “Development and evaluation of a multiprocessing structural vibration algorithm.” 1988. Web. 29 Mar 2020.

Vancouver:

Morel M. Development and evaluation of a multiprocessing structural vibration algorithm. [Internet] [Masters thesis]. Ohio University; 1988. [cited 2020 Mar 29]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1182868176.

Council of Science Editors:

Morel M. Development and evaluation of a multiprocessing structural vibration algorithm. [Masters Thesis]. Ohio University; 1988. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1182868176


University of South Florida

25. Roy, Soumyaroop. Architecture and Compiler Support for Leakage Reduction Using Power Gating in Microprocessors.

Degree: 2010, University of South Florida

 Power gating is a technique commonly used for runtime leakage reduction in digital CMOS circuits. In microprocessors, power gating can be implemented by using sleep… (more)

Subjects/Keywords: Compiler Directed Power Gating; Microarchitectural Techniques; Embedded Microprocessors; Multithreading; Multiprocessing; Multicore; Niagara; CGMT; FGMT; SMT; GCC; SUIF; MachineSUIF; M5; American Studies; Arts and Humanities; Computer Engineering; Computer Sciences

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APA (6th Edition):

Roy, S. (2010). Architecture and Compiler Support for Leakage Reduction Using Power Gating in Microprocessors. (Thesis). University of South Florida. Retrieved from https://scholarcommons.usf.edu/etd/3479

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Roy, Soumyaroop. “Architecture and Compiler Support for Leakage Reduction Using Power Gating in Microprocessors.” 2010. Thesis, University of South Florida. Accessed March 29, 2020. https://scholarcommons.usf.edu/etd/3479.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Roy, Soumyaroop. “Architecture and Compiler Support for Leakage Reduction Using Power Gating in Microprocessors.” 2010. Web. 29 Mar 2020.

Vancouver:

Roy S. Architecture and Compiler Support for Leakage Reduction Using Power Gating in Microprocessors. [Internet] [Thesis]. University of South Florida; 2010. [cited 2020 Mar 29]. Available from: https://scholarcommons.usf.edu/etd/3479.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Roy S. Architecture and Compiler Support for Leakage Reduction Using Power Gating in Microprocessors. [Thesis]. University of South Florida; 2010. Available from: https://scholarcommons.usf.edu/etd/3479

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

26. Arnesson, Andreas. Comparison and Prediction of Temporal Hotspot Maps.

Degree: 2018, , Department of Software Engineering

  Context. To aid law enforcement agencies when coordinating and planningtheir efforts to prevent crime, there is a need to investigate methods usedin such areas.… (more)

Subjects/Keywords: hotspot; prediction; software packaging; similarity; multiprocessing; Computer Sciences; Datavetenskap (datalogi)

…Aoristic method, multiprocessing with shared memory . . Data setup for similarity measures… …Aoristic method, multiprocessing with shared memory . . Aoristic method, multiprocessing without… …can multiprocessing be utilized to increase performance of the methods Getis-Ord* and… …implemented both utilizing multiprocessing and not utilizing it. Performance testing will be done on… …Introduction 8 behind RQ1 to discover if multiprocessing is appropriate to increase performance of… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Arnesson, A. (2018). Comparison and Prediction of Temporal Hotspot Maps. (Thesis). , Department of Software Engineering. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:bth-16306

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Arnesson, Andreas. “Comparison and Prediction of Temporal Hotspot Maps.” 2018. Thesis, , Department of Software Engineering. Accessed March 29, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-16306.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Arnesson, Andreas. “Comparison and Prediction of Temporal Hotspot Maps.” 2018. Web. 29 Mar 2020.

Vancouver:

Arnesson A. Comparison and Prediction of Temporal Hotspot Maps. [Internet] [Thesis]. , Department of Software Engineering; 2018. [cited 2020 Mar 29]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:bth-16306.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Arnesson A. Comparison and Prediction of Temporal Hotspot Maps. [Thesis]. , Department of Software Engineering; 2018. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:bth-16306

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

27. Bulusu, Girish Rao. Asymmetric Multiprocessing Real Time Operating System on Multicore Platforms.

Degree: Computer Science, 2014, Arizona State University

Subjects/Keywords: Computer science; Asymmetric Multiprocessing; Real-time Operating Systems

Multiprocessing (AMP) mode of operation on a multi-core system. The hardware used in this… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bulusu, G. R. (2014). Asymmetric Multiprocessing Real Time Operating System on Multicore Platforms. (Masters Thesis). Arizona State University. Retrieved from http://repository.asu.edu/items/25932

Chicago Manual of Style (16th Edition):

Bulusu, Girish Rao. “Asymmetric Multiprocessing Real Time Operating System on Multicore Platforms.” 2014. Masters Thesis, Arizona State University. Accessed March 29, 2020. http://repository.asu.edu/items/25932.

MLA Handbook (7th Edition):

Bulusu, Girish Rao. “Asymmetric Multiprocessing Real Time Operating System on Multicore Platforms.” 2014. Web. 29 Mar 2020.

Vancouver:

Bulusu GR. Asymmetric Multiprocessing Real Time Operating System on Multicore Platforms. [Internet] [Masters thesis]. Arizona State University; 2014. [cited 2020 Mar 29]. Available from: http://repository.asu.edu/items/25932.

Council of Science Editors:

Bulusu GR. Asymmetric Multiprocessing Real Time Operating System on Multicore Platforms. [Masters Thesis]. Arizona State University; 2014. Available from: http://repository.asu.edu/items/25932


Indian Institute of Science

28. Prakash, Hastagiri. A Mechanism Design Approach To Resource Procurement In Computational Grids With Rational Resource Providers.

Degree: 2006, Indian Institute of Science

 A computational grid is a hardware and software infrastructure that provides dependable, consistent, pervasive, and inexpensive access to high-end computational capabilities. In the presence of… (more)

Subjects/Keywords: Computational Grids; Multiprocessing (Electronic Digital Computers); Grid Computing; Grid Resource Management; Mechanism Design; G-DISC (Grid-Dominant Strategy Incentive Compatible) Mechanism; G-BIC (Grid-Bayesian Nash Incentive Compatible) Mechanism; G-OPT (Grid-Optimal) Mechanism; Incentive Compatibility (IC); Rational Resource Providers; Grid Resource Procurement; Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Prakash, H. (2006). A Mechanism Design Approach To Resource Procurement In Computational Grids With Rational Resource Providers. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/553

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Prakash, Hastagiri. “A Mechanism Design Approach To Resource Procurement In Computational Grids With Rational Resource Providers.” 2006. Thesis, Indian Institute of Science. Accessed March 29, 2020. http://hdl.handle.net/2005/553.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Prakash, Hastagiri. “A Mechanism Design Approach To Resource Procurement In Computational Grids With Rational Resource Providers.” 2006. Web. 29 Mar 2020.

Vancouver:

Prakash H. A Mechanism Design Approach To Resource Procurement In Computational Grids With Rational Resource Providers. [Internet] [Thesis]. Indian Institute of Science; 2006. [cited 2020 Mar 29]. Available from: http://hdl.handle.net/2005/553.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Prakash H. A Mechanism Design Approach To Resource Procurement In Computational Grids With Rational Resource Providers. [Thesis]. Indian Institute of Science; 2006. Available from: http://hdl.handle.net/2005/553

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

29. Mauro Mesquita Spinola. Máquinas de arquitetura distribuída-considerações sobre testes de "software".

Degree: 1986, Instituto Nacional de Pesquisas Espaciais (INPE)

Sistemas distribuídos tem sido utilizados em escalas crescentes em diversas aplicações. As diferenças existentes entre esses sistemas e os sistemas concentrados trazem impactos nas metodologias… (more)

Subjects/Keywords: testes de "software"; sistemas distribuídos; sistemas operacionais; multiprogramação; multiprocessamento; test "software"; distributed systems; operating systems; multiprogramming; multiprocessing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Spinola, M. M. (1986). Máquinas de arquitetura distribuída-considerações sobre testes de "software". (Thesis). Instituto Nacional de Pesquisas Espaciais (INPE). Retrieved from http://urlib.net/sid.inpe.br/[email protected]/2009/03.27.15.06

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Spinola, Mauro Mesquita. “Máquinas de arquitetura distribuída-considerações sobre testes de "software".” 1986. Thesis, Instituto Nacional de Pesquisas Espaciais (INPE). Accessed March 29, 2020. http://urlib.net/sid.inpe.br/[email protected]/2009/03.27.15.06.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Spinola, Mauro Mesquita. “Máquinas de arquitetura distribuída-considerações sobre testes de "software".” 1986. Web. 29 Mar 2020.

Vancouver:

Spinola MM. Máquinas de arquitetura distribuída-considerações sobre testes de "software". [Internet] [Thesis]. Instituto Nacional de Pesquisas Espaciais (INPE); 1986. [cited 2020 Mar 29]. Available from: http://urlib.net/sid.inpe.br/[email protected]/2009/03.27.15.06.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Spinola MM. Máquinas de arquitetura distribuída-considerações sobre testes de "software". [Thesis]. Instituto Nacional de Pesquisas Espaciais (INPE); 1986. Available from: http://urlib.net/sid.inpe.br/[email protected]/2009/03.27.15.06

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

30. Reddy, Vikrama. The Multiprocessor Scheduling Of Periodic And Sporadic Hard Realtime Systems.

Degree: 2010, Indian Institute of Science

 Real time systems have been a major area of study for many years. Advancements in electronics, computers, information technology and digital networks are fueling major… (more)

Subjects/Keywords: Electronic Data Processing : Multiprocessing; Real Time Processing; Multiprocessors; Real Time Systems; Spordiac Task Systems; Periodic Task Systems; Real Time Systems - Scheduling; Microprocessor Scheduling; Scheduling Algorithms; Real Time Task Systems; Periodic Task Model; Sporadic Task Model; Computer Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Reddy, V. (2010). The Multiprocessor Scheduling Of Periodic And Sporadic Hard Realtime Systems. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/2260

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Reddy, Vikrama. “The Multiprocessor Scheduling Of Periodic And Sporadic Hard Realtime Systems.” 2010. Thesis, Indian Institute of Science. Accessed March 29, 2020. http://hdl.handle.net/2005/2260.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Reddy, Vikrama. “The Multiprocessor Scheduling Of Periodic And Sporadic Hard Realtime Systems.” 2010. Web. 29 Mar 2020.

Vancouver:

Reddy V. The Multiprocessor Scheduling Of Periodic And Sporadic Hard Realtime Systems. [Internet] [Thesis]. Indian Institute of Science; 2010. [cited 2020 Mar 29]. Available from: http://hdl.handle.net/2005/2260.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Reddy V. The Multiprocessor Scheduling Of Periodic And Sporadic Hard Realtime Systems. [Thesis]. Indian Institute of Science; 2010. Available from: http://hdl.handle.net/2005/2260

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

[1] [2]

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