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You searched for subject:(multicore processor). Showing records 1 – 25 of 25 total matches.

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University of Notre Dame

1. Sheng Li. An Integrated Power, Area, and Timing Modeling Framework for the Design of Multithreaded and Multi/Manycore Architectures</h1>.

Degree: PhD, Electrical Engineering, 2010, University of Notre Dame

  Multithreaded and multi/manycore processors have already become an important new research direction. These processors have demonstrated great performance and efficiency advantages. This dissertation presents… (more)

Subjects/Keywords: modeling; power; multicore processor; area; timing

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APA (6th Edition):

Li, S. (2010). An Integrated Power, Area, and Timing Modeling Framework for the Design of Multithreaded and Multi/Manycore Architectures</h1>. (Doctoral Dissertation). University of Notre Dame. Retrieved from https://curate.nd.edu/show/02870v8510q

Chicago Manual of Style (16th Edition):

Li, Sheng. “An Integrated Power, Area, and Timing Modeling Framework for the Design of Multithreaded and Multi/Manycore Architectures</h1>.” 2010. Doctoral Dissertation, University of Notre Dame. Accessed November 22, 2019. https://curate.nd.edu/show/02870v8510q.

MLA Handbook (7th Edition):

Li, Sheng. “An Integrated Power, Area, and Timing Modeling Framework for the Design of Multithreaded and Multi/Manycore Architectures</h1>.” 2010. Web. 22 Nov 2019.

Vancouver:

Li S. An Integrated Power, Area, and Timing Modeling Framework for the Design of Multithreaded and Multi/Manycore Architectures</h1>. [Internet] [Doctoral dissertation]. University of Notre Dame; 2010. [cited 2019 Nov 22]. Available from: https://curate.nd.edu/show/02870v8510q.

Council of Science Editors:

Li S. An Integrated Power, Area, and Timing Modeling Framework for the Design of Multithreaded and Multi/Manycore Architectures</h1>. [Doctoral Dissertation]. University of Notre Dame; 2010. Available from: https://curate.nd.edu/show/02870v8510q


University of Edinburgh

2. Krikellas, Konstantinos. Case for holistic query evaluation.

Degree: PhD, 2010, University of Edinburgh

 In this thesis we present the holistic query evaluation model. We propose a novel query engine design that exploits the characteristics of modern processors when… (more)

Subjects/Keywords: 004.01; holistic; query evaluation; database; multicore processor

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APA (6th Edition):

Krikellas, K. (2010). Case for holistic query evaluation. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/3940

Chicago Manual of Style (16th Edition):

Krikellas, Konstantinos. “Case for holistic query evaluation.” 2010. Doctoral Dissertation, University of Edinburgh. Accessed November 22, 2019. http://hdl.handle.net/1842/3940.

MLA Handbook (7th Edition):

Krikellas, Konstantinos. “Case for holistic query evaluation.” 2010. Web. 22 Nov 2019.

Vancouver:

Krikellas K. Case for holistic query evaluation. [Internet] [Doctoral dissertation]. University of Edinburgh; 2010. [cited 2019 Nov 22]. Available from: http://hdl.handle.net/1842/3940.

Council of Science Editors:

Krikellas K. Case for holistic query evaluation. [Doctoral Dissertation]. University of Edinburgh; 2010. Available from: http://hdl.handle.net/1842/3940


New Jersey Institute of Technology

3. Lu, Yaojie. Instruction fusion and vector processor virtualization for higher throughput simultaneous multithreaded processors.

Degree: PhD, Electrical and Computer Engineering, 2016, New Jersey Institute of Technology

  The utilization wall, caused by the breakdown of threshold voltage scaling, hinders performance gains for new generation microprocessors. To alleviate its impact, an instruction… (more)

Subjects/Keywords: Virtualization; Vector processor; Instruction fusion; Multicore processor; Coprocessor sharing; Electrical and Electronics

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APA (6th Edition):

Lu, Y. (2016). Instruction fusion and vector processor virtualization for higher throughput simultaneous multithreaded processors. (Doctoral Dissertation). New Jersey Institute of Technology. Retrieved from https://digitalcommons.njit.edu/dissertations/73

Chicago Manual of Style (16th Edition):

Lu, Yaojie. “Instruction fusion and vector processor virtualization for higher throughput simultaneous multithreaded processors.” 2016. Doctoral Dissertation, New Jersey Institute of Technology. Accessed November 22, 2019. https://digitalcommons.njit.edu/dissertations/73.

MLA Handbook (7th Edition):

Lu, Yaojie. “Instruction fusion and vector processor virtualization for higher throughput simultaneous multithreaded processors.” 2016. Web. 22 Nov 2019.

Vancouver:

Lu Y. Instruction fusion and vector processor virtualization for higher throughput simultaneous multithreaded processors. [Internet] [Doctoral dissertation]. New Jersey Institute of Technology; 2016. [cited 2019 Nov 22]. Available from: https://digitalcommons.njit.edu/dissertations/73.

Council of Science Editors:

Lu Y. Instruction fusion and vector processor virtualization for higher throughput simultaneous multithreaded processors. [Doctoral Dissertation]. New Jersey Institute of Technology; 2016. Available from: https://digitalcommons.njit.edu/dissertations/73


Anna University

4. Gummadi, Sudhakar. A study of multicore processor performance for network applications; -.

Degree: Information and Communication Engineering, 2014, Anna University

Multicore processors have become the new approach for increase newlinein the performance of the processor based systems General purpose multicore newlineprocessors that are also multithreaded… (more)

Subjects/Keywords: Information and Communication engineering; multicore processor; pipelined processes

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APA (6th Edition):

Gummadi, S. (2014). A study of multicore processor performance for network applications; -. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/24727

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gummadi, Sudhakar. “A study of multicore processor performance for network applications; -.” 2014. Thesis, Anna University. Accessed November 22, 2019. http://shodhganga.inflibnet.ac.in/handle/10603/24727.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gummadi, Sudhakar. “A study of multicore processor performance for network applications; -.” 2014. Web. 22 Nov 2019.

Vancouver:

Gummadi S. A study of multicore processor performance for network applications; -. [Internet] [Thesis]. Anna University; 2014. [cited 2019 Nov 22]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/24727.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gummadi S. A study of multicore processor performance for network applications; -. [Thesis]. Anna University; 2014. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/24727

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Minnesota

5. Mekkat, Vineeth. Performance-correctness challenges in emerging heterogeneous multicore processors.

Degree: PhD, Computer science, 2013, University of Minnesota

 We are witnessing a tremendous amount of change in the design of the modern microprocessor. With dozens of CPU cores on-chip recent multicore processors, the… (more)

Subjects/Keywords: Cache Management; Computer Architecture; Data race dtection; Heterogeneous multicore processor

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APA (6th Edition):

Mekkat, V. (2013). Performance-correctness challenges in emerging heterogeneous multicore processors. (Doctoral Dissertation). University of Minnesota. Retrieved from http://hdl.handle.net/11299/162503

Chicago Manual of Style (16th Edition):

Mekkat, Vineeth. “Performance-correctness challenges in emerging heterogeneous multicore processors.” 2013. Doctoral Dissertation, University of Minnesota. Accessed November 22, 2019. http://hdl.handle.net/11299/162503.

MLA Handbook (7th Edition):

Mekkat, Vineeth. “Performance-correctness challenges in emerging heterogeneous multicore processors.” 2013. Web. 22 Nov 2019.

Vancouver:

Mekkat V. Performance-correctness challenges in emerging heterogeneous multicore processors. [Internet] [Doctoral dissertation]. University of Minnesota; 2013. [cited 2019 Nov 22]. Available from: http://hdl.handle.net/11299/162503.

Council of Science Editors:

Mekkat V. Performance-correctness challenges in emerging heterogeneous multicore processors. [Doctoral Dissertation]. University of Minnesota; 2013. Available from: http://hdl.handle.net/11299/162503


Washington University in St. Louis

6. Fu, Yong. Dynamic Thermal and Power Management: From Computers to Buildings.

Degree: PhD, Computer Science & Engineering, 2013, Washington University in St. Louis

  Thermal and power management have become increasingly important for both computing and physical systems. Computing systems from real-time embedded systems to data centers require… (more)

Subjects/Keywords: buildings; cloud computing; feedback control; multicore processor; power management; thermal management; Engineering

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APA (6th Edition):

Fu, Y. (2013). Dynamic Thermal and Power Management: From Computers to Buildings. (Doctoral Dissertation). Washington University in St. Louis. Retrieved from https://openscholarship.wustl.edu/eng_etds/24

Chicago Manual of Style (16th Edition):

Fu, Yong. “Dynamic Thermal and Power Management: From Computers to Buildings.” 2013. Doctoral Dissertation, Washington University in St. Louis. Accessed November 22, 2019. https://openscholarship.wustl.edu/eng_etds/24.

MLA Handbook (7th Edition):

Fu, Yong. “Dynamic Thermal and Power Management: From Computers to Buildings.” 2013. Web. 22 Nov 2019.

Vancouver:

Fu Y. Dynamic Thermal and Power Management: From Computers to Buildings. [Internet] [Doctoral dissertation]. Washington University in St. Louis; 2013. [cited 2019 Nov 22]. Available from: https://openscholarship.wustl.edu/eng_etds/24.

Council of Science Editors:

Fu Y. Dynamic Thermal and Power Management: From Computers to Buildings. [Doctoral Dissertation]. Washington University in St. Louis; 2013. Available from: https://openscholarship.wustl.edu/eng_etds/24


University of Minnesota

7. Zhou, Pingqiang. Interconnect design techniques for multicore and 3D Integrated circuits.

Degree: PhD, Electrical Engineering, 2012, University of Minnesota

 Over the past 40 years, the semiconductor industry has witnessed the exponential growth trend in system complexity as predicted by Moore’s law, facilitated by continuously… (more)

Subjects/Keywords: 3D integrated circuit; DC-DC converter; Multicore processor; Network-on-chip; Optimization; Power delivery

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APA (6th Edition):

Zhou, P. (2012). Interconnect design techniques for multicore and 3D Integrated circuits. (Doctoral Dissertation). University of Minnesota. Retrieved from http://purl.umn.edu/139877

Chicago Manual of Style (16th Edition):

Zhou, Pingqiang. “Interconnect design techniques for multicore and 3D Integrated circuits.” 2012. Doctoral Dissertation, University of Minnesota. Accessed November 22, 2019. http://purl.umn.edu/139877.

MLA Handbook (7th Edition):

Zhou, Pingqiang. “Interconnect design techniques for multicore and 3D Integrated circuits.” 2012. Web. 22 Nov 2019.

Vancouver:

Zhou P. Interconnect design techniques for multicore and 3D Integrated circuits. [Internet] [Doctoral dissertation]. University of Minnesota; 2012. [cited 2019 Nov 22]. Available from: http://purl.umn.edu/139877.

Council of Science Editors:

Zhou P. Interconnect design techniques for multicore and 3D Integrated circuits. [Doctoral Dissertation]. University of Minnesota; 2012. Available from: http://purl.umn.edu/139877


University of Illinois – Urbana-Champaign

8. Johnson, Matthew. Flexible memory protection for multicore processors.

Degree: MS, 1200, 2013, University of Illinois – Urbana-Champaign

 A system’s memory access control mechanisms profoundly impact the performance, reliability, security, and composability of the software it runs. Desirable features of an access control… (more)

Subjects/Keywords: Memory; Multicore; Processor Architecture; Memory Systems; Memory Protection; Data Structures; Concurrency; Virtual Memory

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APA (6th Edition):

Johnson, M. (2013). Flexible memory protection for multicore processors. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/44416

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Johnson, Matthew. “Flexible memory protection for multicore processors.” 2013. Thesis, University of Illinois – Urbana-Champaign. Accessed November 22, 2019. http://hdl.handle.net/2142/44416.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Johnson, Matthew. “Flexible memory protection for multicore processors.” 2013. Web. 22 Nov 2019.

Vancouver:

Johnson M. Flexible memory protection for multicore processors. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2013. [cited 2019 Nov 22]. Available from: http://hdl.handle.net/2142/44416.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Johnson M. Flexible memory protection for multicore processors. [Thesis]. University of Illinois – Urbana-Champaign; 2013. Available from: http://hdl.handle.net/2142/44416

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Southern California

9. Xia, Yinglong. Exploration of parallelism for probabilistic graphical models.

Degree: PhD, Computer Science, 2010, University of Southern California

 Probabilistic graphical models such as Bayesian networks and junction trees are widely used to compactly represent joint probability distributions. They have found applications in a… (more)

Subjects/Keywords: parallel computing; parallel algorithm; probabilistic graphical model; exact inference; multicore processor; scheduler

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APA (6th Edition):

Xia, Y. (2010). Exploration of parallelism for probabilistic graphical models. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/420474/rec/2645

Chicago Manual of Style (16th Edition):

Xia, Yinglong. “Exploration of parallelism for probabilistic graphical models.” 2010. Doctoral Dissertation, University of Southern California. Accessed November 22, 2019. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/420474/rec/2645.

MLA Handbook (7th Edition):

Xia, Yinglong. “Exploration of parallelism for probabilistic graphical models.” 2010. Web. 22 Nov 2019.

Vancouver:

Xia Y. Exploration of parallelism for probabilistic graphical models. [Internet] [Doctoral dissertation]. University of Southern California; 2010. [cited 2019 Nov 22]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/420474/rec/2645.

Council of Science Editors:

Xia Y. Exploration of parallelism for probabilistic graphical models. [Doctoral Dissertation]. University of Southern California; 2010. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/420474/rec/2645


Universitat Politècnica de València

10. Ubal Tena, Rafael. Out-of-Order Retirement of Instructions in Superscalar, Multithreaded, and Multicore Processors .

Degree: 2010, Universitat Politècnica de València

 Los procesadores superescalares actuales utilizan un reorder buffer (ROB) para contabilizar las instrucciones en vuelo. El ROB se implementa como una cola FIFO first in… (more)

Subjects/Keywords: Out-of-order retirement; Reorder buffer; Processor architecture; Multithreading; Multicore; Superscalar; Sequential consistency

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APA (6th Edition):

Ubal Tena, R. (2010). Out-of-Order Retirement of Instructions in Superscalar, Multithreaded, and Multicore Processors . (Doctoral Dissertation). Universitat Politècnica de València. Retrieved from http://hdl.handle.net/10251/8535

Chicago Manual of Style (16th Edition):

Ubal Tena, Rafael. “Out-of-Order Retirement of Instructions in Superscalar, Multithreaded, and Multicore Processors .” 2010. Doctoral Dissertation, Universitat Politècnica de València. Accessed November 22, 2019. http://hdl.handle.net/10251/8535.

MLA Handbook (7th Edition):

Ubal Tena, Rafael. “Out-of-Order Retirement of Instructions in Superscalar, Multithreaded, and Multicore Processors .” 2010. Web. 22 Nov 2019.

Vancouver:

Ubal Tena R. Out-of-Order Retirement of Instructions in Superscalar, Multithreaded, and Multicore Processors . [Internet] [Doctoral dissertation]. Universitat Politècnica de València; 2010. [cited 2019 Nov 22]. Available from: http://hdl.handle.net/10251/8535.

Council of Science Editors:

Ubal Tena R. Out-of-Order Retirement of Instructions in Superscalar, Multithreaded, and Multicore Processors . [Doctoral Dissertation]. Universitat Politècnica de València; 2010. Available from: http://hdl.handle.net/10251/8535

11. Selva, Manuel. Performance monitoring of throughput constrained dataflow programs executed on shared-memory multi-core architectures : Evaluation de performance d'applications flot de données executées sur des architectures multi-coeur.

Degree: Docteur es, Informatique, 2015, INSA Lyon

Les progrès continus de la microélectronique couplés au problème de gestion de la puissance dissipée ont conduit les fabricants de processeurs à se tourner vers… (more)

Subjects/Keywords: Informatique; Processeur multicoeur; Analyse de la performance; Mémoire; IT - Information Technology; Multicore processor; Profiling; Memory; Throughput; 004.220 72

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APA (6th Edition):

Selva, M. (2015). Performance monitoring of throughput constrained dataflow programs executed on shared-memory multi-core architectures : Evaluation de performance d'applications flot de données executées sur des architectures multi-coeur. (Doctoral Dissertation). INSA Lyon. Retrieved from http://www.theses.fr/2015ISAL0055

Chicago Manual of Style (16th Edition):

Selva, Manuel. “Performance monitoring of throughput constrained dataflow programs executed on shared-memory multi-core architectures : Evaluation de performance d'applications flot de données executées sur des architectures multi-coeur.” 2015. Doctoral Dissertation, INSA Lyon. Accessed November 22, 2019. http://www.theses.fr/2015ISAL0055.

MLA Handbook (7th Edition):

Selva, Manuel. “Performance monitoring of throughput constrained dataflow programs executed on shared-memory multi-core architectures : Evaluation de performance d'applications flot de données executées sur des architectures multi-coeur.” 2015. Web. 22 Nov 2019.

Vancouver:

Selva M. Performance monitoring of throughput constrained dataflow programs executed on shared-memory multi-core architectures : Evaluation de performance d'applications flot de données executées sur des architectures multi-coeur. [Internet] [Doctoral dissertation]. INSA Lyon; 2015. [cited 2019 Nov 22]. Available from: http://www.theses.fr/2015ISAL0055.

Council of Science Editors:

Selva M. Performance monitoring of throughput constrained dataflow programs executed on shared-memory multi-core architectures : Evaluation de performance d'applications flot de données executées sur des architectures multi-coeur. [Doctoral Dissertation]. INSA Lyon; 2015. Available from: http://www.theses.fr/2015ISAL0055


Université de Bordeaux I

12. Dupros, Fabrice. Contribution à la modélisation numérique de la propagation des ondes sismiques sur architectures multicœurs et hiérarchiques : Role of protein HuR and its target genes in hepatocellular carcinoma.

Degree: Docteur es, Informatique, 2010, Université de Bordeaux I

En termes de prévention du risque associé aux séismes, la prédiction quantitative des phénomènes de propagation et d'amplification des ondes sismiques dans des structures géologiques… (more)

Subjects/Keywords: Calcul haute performance; Modélisation sismique; Architectures NUMA; Processeurs multicœurs; High performance computing; Seismic modeling; NUMA architecture; Multicore processor

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APA (6th Edition):

Dupros, F. (2010). Contribution à la modélisation numérique de la propagation des ondes sismiques sur architectures multicœurs et hiérarchiques : Role of protein HuR and its target genes in hepatocellular carcinoma. (Doctoral Dissertation). Université de Bordeaux I. Retrieved from http://www.theses.fr/2010BOR14147

Chicago Manual of Style (16th Edition):

Dupros, Fabrice. “Contribution à la modélisation numérique de la propagation des ondes sismiques sur architectures multicœurs et hiérarchiques : Role of protein HuR and its target genes in hepatocellular carcinoma.” 2010. Doctoral Dissertation, Université de Bordeaux I. Accessed November 22, 2019. http://www.theses.fr/2010BOR14147.

MLA Handbook (7th Edition):

Dupros, Fabrice. “Contribution à la modélisation numérique de la propagation des ondes sismiques sur architectures multicœurs et hiérarchiques : Role of protein HuR and its target genes in hepatocellular carcinoma.” 2010. Web. 22 Nov 2019.

Vancouver:

Dupros F. Contribution à la modélisation numérique de la propagation des ondes sismiques sur architectures multicœurs et hiérarchiques : Role of protein HuR and its target genes in hepatocellular carcinoma. [Internet] [Doctoral dissertation]. Université de Bordeaux I; 2010. [cited 2019 Nov 22]. Available from: http://www.theses.fr/2010BOR14147.

Council of Science Editors:

Dupros F. Contribution à la modélisation numérique de la propagation des ondes sismiques sur architectures multicœurs et hiérarchiques : Role of protein HuR and its target genes in hepatocellular carcinoma. [Doctoral Dissertation]. Université de Bordeaux I; 2010. Available from: http://www.theses.fr/2010BOR14147


University of Florida

13. Wang, Zhe. Thermal-aware Task Scheduling on Multicore Processors.

Degree: PhD, Computer Engineering - Computer and Information Science and Engineering, 2012, University of Florida

 Power and heat density of multicore processor are increasing exponentially with Moore's Law. High temperature negatively affects reliability and the cost of cooling and packaging.… (more)

Subjects/Keywords: Accident prone locations; Algorithms; Ambient temperature; Deadlines; Electric potential; Energy consumption; Heuristics; Matrices; Scheduling; Workloads; dvfs  – management  – multicore  – partitioning  – processor  – scheduling  – task  – thermal

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APA (6th Edition):

Wang, Z. (2012). Thermal-aware Task Scheduling on Multicore Processors. (Doctoral Dissertation). University of Florida. Retrieved from http://ufdc.ufl.edu/UFE0044648

Chicago Manual of Style (16th Edition):

Wang, Zhe. “Thermal-aware Task Scheduling on Multicore Processors.” 2012. Doctoral Dissertation, University of Florida. Accessed November 22, 2019. http://ufdc.ufl.edu/UFE0044648.

MLA Handbook (7th Edition):

Wang, Zhe. “Thermal-aware Task Scheduling on Multicore Processors.” 2012. Web. 22 Nov 2019.

Vancouver:

Wang Z. Thermal-aware Task Scheduling on Multicore Processors. [Internet] [Doctoral dissertation]. University of Florida; 2012. [cited 2019 Nov 22]. Available from: http://ufdc.ufl.edu/UFE0044648.

Council of Science Editors:

Wang Z. Thermal-aware Task Scheduling on Multicore Processors. [Doctoral Dissertation]. University of Florida; 2012. Available from: http://ufdc.ufl.edu/UFE0044648

14. ZHANG SHUHAO. SCALING DATA STREAM PROCESSING ON MULTICORE ARCHITECTURES.

Degree: 2019, National University of Singapore

Subjects/Keywords: Stream processing system; multicore processor; NUMA; concurrency control; profiling study

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APA (6th Edition):

SHUHAO, Z. (2019). SCALING DATA STREAM PROCESSING ON MULTICORE ARCHITECTURES. (Thesis). National University of Singapore. Retrieved from https://scholarbank.nus.edu.sg/handle/10635/161250

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

SHUHAO, ZHANG. “SCALING DATA STREAM PROCESSING ON MULTICORE ARCHITECTURES.” 2019. Thesis, National University of Singapore. Accessed November 22, 2019. https://scholarbank.nus.edu.sg/handle/10635/161250.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

SHUHAO, ZHANG. “SCALING DATA STREAM PROCESSING ON MULTICORE ARCHITECTURES.” 2019. Web. 22 Nov 2019.

Vancouver:

SHUHAO Z. SCALING DATA STREAM PROCESSING ON MULTICORE ARCHITECTURES. [Internet] [Thesis]. National University of Singapore; 2019. [cited 2019 Nov 22]. Available from: https://scholarbank.nus.edu.sg/handle/10635/161250.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

SHUHAO Z. SCALING DATA STREAM PROCESSING ON MULTICORE ARCHITECTURES. [Thesis]. National University of Singapore; 2019. Available from: https://scholarbank.nus.edu.sg/handle/10635/161250

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

15. Sikder, Md Ashif Iqbal. Emerging Technologies in On-Chip and Off-Chip Interconnection Network.

Degree: MS, Electrical Engineering (Engineering and Technology), 2016, Ohio University

 The number of processing cores on a chip is increasing with the scaling down of transistors to meet the computation demand. This increase requires a… (more)

Subjects/Keywords: Computer Engineering; Electrical Engineering; Network-on-Chip; wireless; photonics; DRAM; Chip Multicore Processor

processor trend-line. . . . . . . . . . . . . . . . . . . . . . An example of on-chip mesh network… …DOR Single-chip Cloud Computer SCC Multi-Purpose Processor Array MPPA Dynamic Voltage and… …As a result, a single, large complex processor is replaced by several small simple… …published at the time of this thesis submission. 0 12 Figure 1.1: General purpose processor… …processor examples. There are some commercial prototypes available that have implemented NoC as… 

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APA (6th Edition):

Sikder, M. A. I. (2016). Emerging Technologies in On-Chip and Off-Chip Interconnection Network. (Masters Thesis). Ohio University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1469028996

Chicago Manual of Style (16th Edition):

Sikder, Md Ashif Iqbal. “Emerging Technologies in On-Chip and Off-Chip Interconnection Network.” 2016. Masters Thesis, Ohio University. Accessed November 22, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1469028996.

MLA Handbook (7th Edition):

Sikder, Md Ashif Iqbal. “Emerging Technologies in On-Chip and Off-Chip Interconnection Network.” 2016. Web. 22 Nov 2019.

Vancouver:

Sikder MAI. Emerging Technologies in On-Chip and Off-Chip Interconnection Network. [Internet] [Masters thesis]. Ohio University; 2016. [cited 2019 Nov 22]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1469028996.

Council of Science Editors:

Sikder MAI. Emerging Technologies in On-Chip and Off-Chip Interconnection Network. [Masters Thesis]. Ohio University; 2016. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1469028996

16. 許, 允碩. 階層型キャッシュシステムにおける高効率なブロック配置法.

Degree: Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学

Supervisor:田中清史

情報科学研究科

修士

Subjects/Keywords: 階層型キャッシュ; Hierarchical cache; ブロック配置; Block distribution; マルチコア; Multicore processor

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APA (6th Edition):

許, . (n.d.). 階層型キャッシュシステムにおける高効率なブロック配置法. (Thesis). Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10119/9630

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

許, 允碩. “階層型キャッシュシステムにおける高効率なブロック配置法.” Thesis, Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学. Accessed November 22, 2019. http://hdl.handle.net/10119/9630.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

許, 允碩. “階層型キャッシュシステムにおける高効率なブロック配置法.” Web. 22 Nov 2019.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

許 . 階層型キャッシュシステムにおける高効率なブロック配置法. [Internet] [Thesis]. Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学; [cited 2019 Nov 22]. Available from: http://hdl.handle.net/10119/9630.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

許 . 階層型キャッシュシステムにおける高効率なブロック配置法. [Thesis]. Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学; Available from: http://hdl.handle.net/10119/9630

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.


University of Florida

17. Lovelly, Tyler M. Comparative Analysis of Space-Grade Processors.

Degree: PhD, Electrical and Computer Engineering, 2017, University of Florida

 Onboard computing demands for space missions are continually increasing due to the need for real-time sensor and autonomous processing combined with limited communication bandwidth to… (more)

Subjects/Keywords: afrl  – algorithm  – analysis  – application  – architecture  – autonomous  – bandwidth  – benchmark  – benchmarking  – chrec  – comparison  – computation  – computing  – cots  – cpu  – dsp  – dwarf  – efficiency  – fpga  – gpu  – hardened  – hardening  – manycore  – memory  – metric  – multicore  – nasa  – onboard  – optimization  – overhead  – parallel  – performance  – power  – processing  – processor  – radiation  – reconfigurable  – sensor  – space  – taxonomy

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APA (6th Edition):

Lovelly, T. M. (2017). Comparative Analysis of Space-Grade Processors. (Doctoral Dissertation). University of Florida. Retrieved from http://ufdc.ufl.edu/UFE0051836

Chicago Manual of Style (16th Edition):

Lovelly, Tyler M. “Comparative Analysis of Space-Grade Processors.” 2017. Doctoral Dissertation, University of Florida. Accessed November 22, 2019. http://ufdc.ufl.edu/UFE0051836.

MLA Handbook (7th Edition):

Lovelly, Tyler M. “Comparative Analysis of Space-Grade Processors.” 2017. Web. 22 Nov 2019.

Vancouver:

Lovelly TM. Comparative Analysis of Space-Grade Processors. [Internet] [Doctoral dissertation]. University of Florida; 2017. [cited 2019 Nov 22]. Available from: http://ufdc.ufl.edu/UFE0051836.

Council of Science Editors:

Lovelly TM. Comparative Analysis of Space-Grade Processors. [Doctoral Dissertation]. University of Florida; 2017. Available from: http://ufdc.ufl.edu/UFE0051836

18. Sarr, Abdoulaye. Viab-Cell, développement d'un logiciel viabiliste sur processeur multicoeurs pour la simulation de la morphogénèse : Development of a viabilist software on multi-core CPU for morhogenesis simulation.

Degree: Docteur es, Informatique, 2016, Brest

Ce travail présente un modèle théorique de morphogenèse animale, sous la forme d’un système complexe émergeant de nombreux comportements, processus internes, expressions et interactions cellulaires.… (more)

Subjects/Keywords: Système multicellulaire; Morphogenèse; Théorie de la viabilité; Biologie computationnelle; Automate cellulaire; Système multi-agents; Multicoeurs; Tumeurs; Multicellular system; Morphogenesis; Viability theory; Computational biology; Cellular automata; Multi-agent system; Multicore processor; Tumors; 571.833 011 3

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APA (6th Edition):

Sarr, A. (2016). Viab-Cell, développement d'un logiciel viabiliste sur processeur multicoeurs pour la simulation de la morphogénèse : Development of a viabilist software on multi-core CPU for morhogenesis simulation. (Doctoral Dissertation). Brest. Retrieved from http://www.theses.fr/2016BRES0105

Chicago Manual of Style (16th Edition):

Sarr, Abdoulaye. “Viab-Cell, développement d'un logiciel viabiliste sur processeur multicoeurs pour la simulation de la morphogénèse : Development of a viabilist software on multi-core CPU for morhogenesis simulation.” 2016. Doctoral Dissertation, Brest. Accessed November 22, 2019. http://www.theses.fr/2016BRES0105.

MLA Handbook (7th Edition):

Sarr, Abdoulaye. “Viab-Cell, développement d'un logiciel viabiliste sur processeur multicoeurs pour la simulation de la morphogénèse : Development of a viabilist software on multi-core CPU for morhogenesis simulation.” 2016. Web. 22 Nov 2019.

Vancouver:

Sarr A. Viab-Cell, développement d'un logiciel viabiliste sur processeur multicoeurs pour la simulation de la morphogénèse : Development of a viabilist software on multi-core CPU for morhogenesis simulation. [Internet] [Doctoral dissertation]. Brest; 2016. [cited 2019 Nov 22]. Available from: http://www.theses.fr/2016BRES0105.

Council of Science Editors:

Sarr A. Viab-Cell, développement d'un logiciel viabiliste sur processeur multicoeurs pour la simulation de la morphogénèse : Development of a viabilist software on multi-core CPU for morhogenesis simulation. [Doctoral Dissertation]. Brest; 2016. Available from: http://www.theses.fr/2016BRES0105


University of Vienna

19. Wimmer, Martin. Programming models for parallel computing.

Degree: 2010, University of Vienna

Mit dem Auftauchen von Multicore Prozessoren beginnt parallele Programmierung den Massenmarkt zu erobern. Derzeit ist der Parallelismus noch relativ eingeschränkt, da aktuelle Prozessoren nur über… (more)

Subjects/Keywords: 54.25 Parallele Datenverarbeitung; 54.53 Programmiersprachen; 54.31 Rechnerarchitektur; Parallelisierung / Programmiermodelle / Programmiersprachen / Verteilte Systeme / Multicore / GPU / Cell Prozessor / OpenMP / MPI / Cilk / TBB / HPF / Chapel / X10; parallelization / programming models / programming languages / distributed systems / multi-core / GPU / Cell processor / OpenMP / MPI / Cilk / TBB / HPF / Chapel / X10

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APA (6th Edition):

Wimmer, M. (2010). Programming models for parallel computing. (Thesis). University of Vienna. Retrieved from http://othes.univie.ac.at/8336/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wimmer, Martin. “Programming models for parallel computing.” 2010. Thesis, University of Vienna. Accessed November 22, 2019. http://othes.univie.ac.at/8336/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wimmer, Martin. “Programming models for parallel computing.” 2010. Web. 22 Nov 2019.

Vancouver:

Wimmer M. Programming models for parallel computing. [Internet] [Thesis]. University of Vienna; 2010. [cited 2019 Nov 22]. Available from: http://othes.univie.ac.at/8336/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wimmer M. Programming models for parallel computing. [Thesis]. University of Vienna; 2010. Available from: http://othes.univie.ac.at/8336/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

20. Kudlur, Manjunath V. Streamroller : A Unified Compilation and Synthesis System for Streaming Applications.

Degree: PhD, Computer Science & Engineering, 2008, University of Michigan

 The growing complexity of applications has increased the need for higher processing power. In the embedded domain, the convergence of audio, video, and networking on… (more)

Subjects/Keywords: Compiler; Stream Programming; Multicore; Scheduling; IBM Cell Processor; High Level Synthesis; Computer Science; Engineering

…the modulo schedule. . . . . . . . . . . . . . . . Example illustrating fission, processor… …consumer processor. . . . . . . . . . . . . . . . . . . . . . . vi 15 16 18 22 23 29 30 34 39… …the consumer, but not at the producer processor… …processor under different edge-cut minimization strategies… …the industry towards multicore systems. Many of the applications in these domains are… 

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APA (6th Edition):

Kudlur, M. V. (2008). Streamroller : A Unified Compilation and Synthesis System for Streaming Applications. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/61662

Chicago Manual of Style (16th Edition):

Kudlur, Manjunath V. “Streamroller : A Unified Compilation and Synthesis System for Streaming Applications.” 2008. Doctoral Dissertation, University of Michigan. Accessed November 22, 2019. http://hdl.handle.net/2027.42/61662.

MLA Handbook (7th Edition):

Kudlur, Manjunath V. “Streamroller : A Unified Compilation and Synthesis System for Streaming Applications.” 2008. Web. 22 Nov 2019.

Vancouver:

Kudlur MV. Streamroller : A Unified Compilation and Synthesis System for Streaming Applications. [Internet] [Doctoral dissertation]. University of Michigan; 2008. [cited 2019 Nov 22]. Available from: http://hdl.handle.net/2027.42/61662.

Council of Science Editors:

Kudlur MV. Streamroller : A Unified Compilation and Synthesis System for Streaming Applications. [Doctoral Dissertation]. University of Michigan; 2008. Available from: http://hdl.handle.net/2027.42/61662


Brno University of Technology

21. Matyáš, Jan. Problematika přechodu od jednojádrové k vícejádrové implementaci operačního systému .

Degree: 2014, Brno University of Technology

 Tato práce se zabývá úpravou MicroC/OS-II pro běh na vícejádrovém procesoru, konkrétně na Zynq 7000 All Programmable SoC, který obsahuje dvě jádra architektury ARM Cortex-A9. Jsou… (more)

Subjects/Keywords: MicroC/OS-II; ZedBoard; ARM; Cortex-A9; Zynq; vícejádrový procesor; paralelismus; boot; bootloader; AMP; SMP; real-time; operační systém; plánovač; přerušení; MicroC/OS-II; ZedBoard; ARM; Cortex-A9; Zynq; multicore processor; parallelism; boot; bootloader; AMP; SMP; real-time; operating system; scheduler; interrupt

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APA (6th Edition):

Matyáš, J. (2014). Problematika přechodu od jednojádrové k vícejádrové implementaci operačního systému . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/53331

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Matyáš, Jan. “Problematika přechodu od jednojádrové k vícejádrové implementaci operačního systému .” 2014. Thesis, Brno University of Technology. Accessed November 22, 2019. http://hdl.handle.net/11012/53331.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Matyáš, Jan. “Problematika přechodu od jednojádrové k vícejádrové implementaci operačního systému .” 2014. Web. 22 Nov 2019.

Vancouver:

Matyáš J. Problematika přechodu od jednojádrové k vícejádrové implementaci operačního systému . [Internet] [Thesis]. Brno University of Technology; 2014. [cited 2019 Nov 22]. Available from: http://hdl.handle.net/11012/53331.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Matyáš J. Problematika přechodu od jednojádrové k vícejádrové implementaci operačního systému . [Thesis]. Brno University of Technology; 2014. Available from: http://hdl.handle.net/11012/53331

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

22. Desai, Digant. Towards Energy Efficient Computing with Linux : Enabling Task Level Power Awareness and Support for Energy Efficient Accelerator.

Degree: MS, Electrical Engineering, 2013, Arizona State University

 With increasing transistor volume and reducing feature size, it has become a major design constraint to reduce power consumption also. This has given rise to… (more)

Subjects/Keywords: Engineering; Electrical engineering; Computer engineering; CGRA framework; Multicore Processor; Power Management; Task Power Profiler

…Even for a homogeneous multicore processor, there can be variation in core power consumption… …Bridge processor . . . . . . . 20 3.2 Processor factors used in modelling processor power… …4.2 Quadratic effect of P-states on processor on power consumption . . . . . . . . 24 4.3… …Quadratic effect of T-states on processor on power consumption . . . . . . . . 25 4.4 Linear… …the key challenge of processor design in every market segment – including battery-powered… 

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APA (6th Edition):

Desai, D. (2013). Towards Energy Efficient Computing with Linux : Enabling Task Level Power Awareness and Support for Energy Efficient Accelerator. (Masters Thesis). Arizona State University. Retrieved from http://repository.asu.edu/items/18116

Chicago Manual of Style (16th Edition):

Desai, Digant. “Towards Energy Efficient Computing with Linux : Enabling Task Level Power Awareness and Support for Energy Efficient Accelerator.” 2013. Masters Thesis, Arizona State University. Accessed November 22, 2019. http://repository.asu.edu/items/18116.

MLA Handbook (7th Edition):

Desai, Digant. “Towards Energy Efficient Computing with Linux : Enabling Task Level Power Awareness and Support for Energy Efficient Accelerator.” 2013. Web. 22 Nov 2019.

Vancouver:

Desai D. Towards Energy Efficient Computing with Linux : Enabling Task Level Power Awareness and Support for Energy Efficient Accelerator. [Internet] [Masters thesis]. Arizona State University; 2013. [cited 2019 Nov 22]. Available from: http://repository.asu.edu/items/18116.

Council of Science Editors:

Desai D. Towards Energy Efficient Computing with Linux : Enabling Task Level Power Awareness and Support for Energy Efficient Accelerator. [Masters Thesis]. Arizona State University; 2013. Available from: http://repository.asu.edu/items/18116

23. Marinković Vladimir. Прилог аутоматској паралелизацији секвенцијалног машинског кода.

Degree: 2018, University of Novi Sad

Докторска теза анализира подршку за вишејезгарне и многојезгарне системе у циљу повећања искоришћења њихове снаге. Предмет истраживања је проналажење решења које би без уплитања… (more)

Subjects/Keywords: Паралелне архитектуре, паралелно програмирање, вишејезгарна обрада, асемблер, распоређивање процеса, наменски системи, програмски алати; Paralelne arhitekture, paralelno programiranje, višejezgarna obrada, asembler, raspoređivanje procesa, namenski sistemi, programski alati; Parallel architectures, parallel programming, multicore processing, assembly,processor scheduling, embedded system, software tools

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APA (6th Edition):

Vladimir, M. (2018). Прилог аутоматској паралелизацији секвенцијалног машинског кода. (Thesis). University of Novi Sad. Retrieved from https://www.cris.uns.ac.rs/DownloadFileServlet/Disertacija153208071778835.pdf?controlNumber=(BISIS)107635&fileName=153208071778835.pdf&id=11760&source=OATD&language=en ; https://www.cris.uns.ac.rs/record.jsf?recordId=107635&source=OATD&language=en

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vladimir, Marinković. “Прилог аутоматској паралелизацији секвенцијалног машинског кода.” 2018. Thesis, University of Novi Sad. Accessed November 22, 2019. https://www.cris.uns.ac.rs/DownloadFileServlet/Disertacija153208071778835.pdf?controlNumber=(BISIS)107635&fileName=153208071778835.pdf&id=11760&source=OATD&language=en ; https://www.cris.uns.ac.rs/record.jsf?recordId=107635&source=OATD&language=en.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vladimir, Marinković. “Прилог аутоматској паралелизацији секвенцијалног машинског кода.” 2018. Web. 22 Nov 2019.

Vancouver:

Vladimir M. Прилог аутоматској паралелизацији секвенцијалног машинског кода. [Internet] [Thesis]. University of Novi Sad; 2018. [cited 2019 Nov 22]. Available from: https://www.cris.uns.ac.rs/DownloadFileServlet/Disertacija153208071778835.pdf?controlNumber=(BISIS)107635&fileName=153208071778835.pdf&id=11760&source=OATD&language=en ; https://www.cris.uns.ac.rs/record.jsf?recordId=107635&source=OATD&language=en.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vladimir M. Прилог аутоматској паралелизацији секвенцијалног машинског кода. [Thesis]. University of Novi Sad; 2018. Available from: https://www.cris.uns.ac.rs/DownloadFileServlet/Disertacija153208071778835.pdf?controlNumber=(BISIS)107635&fileName=153208071778835.pdf&id=11760&source=OATD&language=en ; https://www.cris.uns.ac.rs/record.jsf?recordId=107635&source=OATD&language=en

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

24. Truty, Wojciech J. Design and implementation of a floating point unit for rigel, a massively parallel accelerator.

Degree: MS, 1200, 2010, University of Illinois – Urbana-Champaign

 Scientific applications rely heavily on floating point data types. Floating point operations are complex and require complicated hardware that is both area and power intensive.… (more)

Subjects/Keywords: Floating point; Rigel; parallel; many core; multicore; processor; Accelerator; Floating point unit (FPU); floating point unit; IEEE Standard for Floating-Point Arithmetic (IEEE 754); Massively parallel

…I$ I$ Chip Level View Cluster View Figure 1.1: Diagram of the Rigel processor. cations… …massively parallel processor like Rigel, area and power concerns make it necessary to investigate… 

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APA (6th Edition):

Truty, W. J. (2010). Design and implementation of a floating point unit for rigel, a massively parallel accelerator. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/16472

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Truty, Wojciech J. “Design and implementation of a floating point unit for rigel, a massively parallel accelerator.” 2010. Thesis, University of Illinois – Urbana-Champaign. Accessed November 22, 2019. http://hdl.handle.net/2142/16472.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Truty, Wojciech J. “Design and implementation of a floating point unit for rigel, a massively parallel accelerator.” 2010. Web. 22 Nov 2019.

Vancouver:

Truty WJ. Design and implementation of a floating point unit for rigel, a massively parallel accelerator. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2010. [cited 2019 Nov 22]. Available from: http://hdl.handle.net/2142/16472.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Truty WJ. Design and implementation of a floating point unit for rigel, a massively parallel accelerator. [Thesis]. University of Illinois – Urbana-Champaign; 2010. Available from: http://hdl.handle.net/2142/16472

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

25. Yuan, Man. A SIMD Approach To Large-scale Real-time System Air Traffic Control Using Associative Processor and Consequences For Parallel Computing.

Degree: PhD, College of Arts and Sciences / Department of Computer Science, 2012, Kent State University

 This dissertation has two complementary focuses. First, it provides a solution to large scale real-time system air traffic Control (ATC) using an enhanced SIMD machine… (more)

Subjects/Keywords: Computer Science; Air Traffic Control (ATC); SIMD; MIMD; Real-Time Systems; Associative Processor (AP); Conflict Detection and Resolution (CDR); ClearSpeed CSX600; Multicore Processor; OpenMP; Federal Aviation Administration (FAA); Multiprocessor; NP-complete; Predictable

…the ATC system on an enhanced SIMD hardware system called an associative processor(AP… …the system and examples of ATC tasks. Section 2.4 gives an overview of associative processor… …processor to execute them to guarantee real-time properties. The current trend is to use MIMD… …benchmark. 2.4 An Associative Processor for ATC An associative processor (AP) [4… …processor at a fixed memory location. The processors whose value is maximal (respectively… 

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APA (6th Edition):

Yuan, M. (2012). A SIMD Approach To Large-scale Real-time System Air Traffic Control Using Associative Processor and Consequences For Parallel Computing. (Doctoral Dissertation). Kent State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=kent1345058186

Chicago Manual of Style (16th Edition):

Yuan, Man. “A SIMD Approach To Large-scale Real-time System Air Traffic Control Using Associative Processor and Consequences For Parallel Computing.” 2012. Doctoral Dissertation, Kent State University. Accessed November 22, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=kent1345058186.

MLA Handbook (7th Edition):

Yuan, Man. “A SIMD Approach To Large-scale Real-time System Air Traffic Control Using Associative Processor and Consequences For Parallel Computing.” 2012. Web. 22 Nov 2019.

Vancouver:

Yuan M. A SIMD Approach To Large-scale Real-time System Air Traffic Control Using Associative Processor and Consequences For Parallel Computing. [Internet] [Doctoral dissertation]. Kent State University; 2012. [cited 2019 Nov 22]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=kent1345058186.

Council of Science Editors:

Yuan M. A SIMD Approach To Large-scale Real-time System Air Traffic Control Using Associative Processor and Consequences For Parallel Computing. [Doctoral Dissertation]. Kent State University; 2012. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=kent1345058186

.