Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

Sorted by: relevance · author · university · dateNew search

You searched for subject:(multi core). Showing records 1 – 30 of 269 total matches.

[1] [2] [3] [4] [5] [6] [7] [8] [9]

Search Limiters

Last 2 Years | English Only

Degrees

Levels

Languages

Country

▼ Search Limiters


University of Edinburgh

1. Han, Wei. Multi-core architectures with coarse-grained dynamically reconfigurable processors for broadband wireless access technologies.

Degree: PhD, 2010, University of Edinburgh

 Broadband Wireless Access technologies have significant market potential, especially the WiMAX protocol which can deliver data rates of tens of Mbps. Strong demand for high… (more)

Subjects/Keywords: 621.382; multi-core; WiMAX; reconfigurable

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Han, W. (2010). Multi-core architectures with coarse-grained dynamically reconfigurable processors for broadband wireless access technologies. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/3812

Chicago Manual of Style (16th Edition):

Han, Wei. “Multi-core architectures with coarse-grained dynamically reconfigurable processors for broadband wireless access technologies.” 2010. Doctoral Dissertation, University of Edinburgh. Accessed April 01, 2020. http://hdl.handle.net/1842/3812.

MLA Handbook (7th Edition):

Han, Wei. “Multi-core architectures with coarse-grained dynamically reconfigurable processors for broadband wireless access technologies.” 2010. Web. 01 Apr 2020.

Vancouver:

Han W. Multi-core architectures with coarse-grained dynamically reconfigurable processors for broadband wireless access technologies. [Internet] [Doctoral dissertation]. University of Edinburgh; 2010. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/1842/3812.

Council of Science Editors:

Han W. Multi-core architectures with coarse-grained dynamically reconfigurable processors for broadband wireless access technologies. [Doctoral Dissertation]. University of Edinburgh; 2010. Available from: http://hdl.handle.net/1842/3812

2. Yussuf Ali. マルチコアおよびメニコアプロセッサのための並列パス遅延故障シミュレーション : Parallel Path Delay Fault Simulation for Multi/Many-Core Processors; マルチコア オヨビ メニコア プロセッサ ノ タメ ノ ヘイレツ パス チエン コショウ シミュレーション.

Degree: Nara Institute of Science and Technology / 奈良先端科学技術大学院大学

Subjects/Keywords: Multi-Core

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ali, Y. (n.d.). マルチコアおよびメニコアプロセッサのための並列パス遅延故障シミュレーション : Parallel Path Delay Fault Simulation for Multi/Many-Core Processors; マルチコア オヨビ メニコア プロセッサ ノ タメ ノ ヘイレツ パス チエン コショウ シミュレーション. (Thesis). Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10061/9468

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ali, Yussuf. “マルチコアおよびメニコアプロセッサのための並列パス遅延故障シミュレーション : Parallel Path Delay Fault Simulation for Multi/Many-Core Processors; マルチコア オヨビ メニコア プロセッサ ノ タメ ノ ヘイレツ パス チエン コショウ シミュレーション.” Thesis, Nara Institute of Science and Technology / 奈良先端科学技術大学院大学. Accessed April 01, 2020. http://hdl.handle.net/10061/9468.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ali, Yussuf. “マルチコアおよびメニコアプロセッサのための並列パス遅延故障シミュレーション : Parallel Path Delay Fault Simulation for Multi/Many-Core Processors; マルチコア オヨビ メニコア プロセッサ ノ タメ ノ ヘイレツ パス チエン コショウ シミュレーション.” Web. 01 Apr 2020.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

Ali Y. マルチコアおよびメニコアプロセッサのための並列パス遅延故障シミュレーション : Parallel Path Delay Fault Simulation for Multi/Many-Core Processors; マルチコア オヨビ メニコア プロセッサ ノ タメ ノ ヘイレツ パス チエン コショウ シミュレーション. [Internet] [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10061/9468.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

Ali Y. マルチコアおよびメニコアプロセッサのための並列パス遅延故障シミュレーション : Parallel Path Delay Fault Simulation for Multi/Many-Core Processors; マルチコア オヨビ メニコア プロセッサ ノ タメ ノ ヘイレツ パス チエン コショウ シミュレーション. [Thesis]. Nara Institute of Science and Technology / 奈良先端科学技術大学院大学; Available from: http://hdl.handle.net/10061/9468

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.


Uppsala University

3. Karlsson, Johan. Efficient use of Multi-core Technology in Interactive Desktop Applications.

Degree: Information Technology, 2015, Uppsala University

  The emergence of multi-core processors has successfully ended the era where applications could enjoy free and regular performance improvements without source code modifications. This… (more)

Subjects/Keywords: Multi-core processors; parallelism

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Karlsson, J. (2015). Efficient use of Multi-core Technology in Interactive Desktop Applications. (Thesis). Uppsala University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-246120

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Karlsson, Johan. “Efficient use of Multi-core Technology in Interactive Desktop Applications.” 2015. Thesis, Uppsala University. Accessed April 01, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-246120.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Karlsson, Johan. “Efficient use of Multi-core Technology in Interactive Desktop Applications.” 2015. Web. 01 Apr 2020.

Vancouver:

Karlsson J. Efficient use of Multi-core Technology in Interactive Desktop Applications. [Internet] [Thesis]. Uppsala University; 2015. [cited 2020 Apr 01]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-246120.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Karlsson J. Efficient use of Multi-core Technology in Interactive Desktop Applications. [Thesis]. Uppsala University; 2015. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-246120

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Tech

4. Zhang, Jing. Transforming and Optimizing Irregular Applications for Parallel Architectures.

Degree: PhD, Computer Science, 2018, Virginia Tech

 Parallel architectures, including multi-core processors, many-core processors, and multi-node systems, have become commonplace, as it is no longer feasible to improve single-core performance through increasing… (more)

Subjects/Keywords: Irregular Applications; Parallel Architectures; Multi-core; Many-core; Multi-node; Bioinformatics

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhang, J. (2018). Transforming and Optimizing Irregular Applications for Parallel Architectures. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/82069

Chicago Manual of Style (16th Edition):

Zhang, Jing. “Transforming and Optimizing Irregular Applications for Parallel Architectures.” 2018. Doctoral Dissertation, Virginia Tech. Accessed April 01, 2020. http://hdl.handle.net/10919/82069.

MLA Handbook (7th Edition):

Zhang, Jing. “Transforming and Optimizing Irregular Applications for Parallel Architectures.” 2018. Web. 01 Apr 2020.

Vancouver:

Zhang J. Transforming and Optimizing Irregular Applications for Parallel Architectures. [Internet] [Doctoral dissertation]. Virginia Tech; 2018. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10919/82069.

Council of Science Editors:

Zhang J. Transforming and Optimizing Irregular Applications for Parallel Architectures. [Doctoral Dissertation]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/82069


University of Edinburgh

5. Tournavitis, Georgios. Profile-driven parallelisation of sequential programs.

Degree: 2011, University of Edinburgh

 Traditional parallelism detection in compilers is performed by means of static analysis and more specifically data and control dependence analysis. The information that is available… (more)

Subjects/Keywords: 005.3; compiler; multi-core; parallelisation; pipeline

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tournavitis, G. (2011). Profile-driven parallelisation of sequential programs. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/5287

Chicago Manual of Style (16th Edition):

Tournavitis, Georgios. “Profile-driven parallelisation of sequential programs.” 2011. Doctoral Dissertation, University of Edinburgh. Accessed April 01, 2020. http://hdl.handle.net/1842/5287.

MLA Handbook (7th Edition):

Tournavitis, Georgios. “Profile-driven parallelisation of sequential programs.” 2011. Web. 01 Apr 2020.

Vancouver:

Tournavitis G. Profile-driven parallelisation of sequential programs. [Internet] [Doctoral dissertation]. University of Edinburgh; 2011. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/1842/5287.

Council of Science Editors:

Tournavitis G. Profile-driven parallelisation of sequential programs. [Doctoral Dissertation]. University of Edinburgh; 2011. Available from: http://hdl.handle.net/1842/5287


Rochester Institute of Technology

6. Sieber, Patrick. Reliability-aware multi-segmented bus architecture for photonic networks-on-chip.

Degree: Computer Engineering, 2013, Rochester Institute of Technology

 Network-on-chip (NoC) has emerged as an enabling platform for connecting hundreds of cores on a single chip, allowing for a structured, scalable system when compared… (more)

Subjects/Keywords: Multi-core; Network-on-chip; Photonic

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sieber, P. (2013). Reliability-aware multi-segmented bus architecture for photonic networks-on-chip. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/3160

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sieber, Patrick. “Reliability-aware multi-segmented bus architecture for photonic networks-on-chip.” 2013. Thesis, Rochester Institute of Technology. Accessed April 01, 2020. https://scholarworks.rit.edu/theses/3160.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sieber, Patrick. “Reliability-aware multi-segmented bus architecture for photonic networks-on-chip.” 2013. Web. 01 Apr 2020.

Vancouver:

Sieber P. Reliability-aware multi-segmented bus architecture for photonic networks-on-chip. [Internet] [Thesis]. Rochester Institute of Technology; 2013. [cited 2020 Apr 01]. Available from: https://scholarworks.rit.edu/theses/3160.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sieber P. Reliability-aware multi-segmented bus architecture for photonic networks-on-chip. [Thesis]. Rochester Institute of Technology; 2013. Available from: https://scholarworks.rit.edu/theses/3160

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Victoria

7. Berg, Celina. Building a foundation for the future of software practices within the multi-core domain.

Degree: Dept. of Computer Science, 2011, University of Victoria

Multi-core programming presents developers with a dramatic paradigm shift. Where the conceptual models of sequential programming largely supported the decoupling of source from underlying architecture,… (more)

Subjects/Keywords: software engineering; multi-core; parallel programming

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Berg, C. (2011). Building a foundation for the future of software practices within the multi-core domain. (Thesis). University of Victoria. Retrieved from http://hdl.handle.net/1828/3539

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Berg, Celina. “Building a foundation for the future of software practices within the multi-core domain.” 2011. Thesis, University of Victoria. Accessed April 01, 2020. http://hdl.handle.net/1828/3539.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Berg, Celina. “Building a foundation for the future of software practices within the multi-core domain.” 2011. Web. 01 Apr 2020.

Vancouver:

Berg C. Building a foundation for the future of software practices within the multi-core domain. [Internet] [Thesis]. University of Victoria; 2011. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/1828/3539.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Berg C. Building a foundation for the future of software practices within the multi-core domain. [Thesis]. University of Victoria; 2011. Available from: http://hdl.handle.net/1828/3539

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade Nova

8. Mariano, Paulo Alexandre Lima da Silva. RepComp - replicated software components for improved performance.

Degree: 2011, Universidade Nova

Trabalho apresentado no âmbito do Mestrado em Engenharia Informática, como requisito parcial para obtenção do grau de Mestre em Engenharia Informática

The current trend of… (more)

Subjects/Keywords: Diverse replication; Multi-core; Parallel programming; Performance

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mariano, P. A. L. d. S. (2011). RepComp - replicated software components for improved performance. (Thesis). Universidade Nova. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/5688

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mariano, Paulo Alexandre Lima da Silva. “RepComp - replicated software components for improved performance.” 2011. Thesis, Universidade Nova. Accessed April 01, 2020. http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/5688.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mariano, Paulo Alexandre Lima da Silva. “RepComp - replicated software components for improved performance.” 2011. Web. 01 Apr 2020.

Vancouver:

Mariano PALdS. RepComp - replicated software components for improved performance. [Internet] [Thesis]. Universidade Nova; 2011. [cited 2020 Apr 01]. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/5688.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mariano PALdS. RepComp - replicated software components for improved performance. [Thesis]. Universidade Nova; 2011. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/5688

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade Nova

9. Mourão, Diogo André Ribeiro. Um middleware independente da plataforma para computação paralela.

Degree: 2011, Universidade Nova

Dissertação para obtenção do Grau de Mestre em Engenharia Informática

A adoção generalizada dos processadores com vários núcleos (multi-core) requer modelos de programação que permitam… (more)

Subjects/Keywords: Programação paralela; Middleware; Arquiteturas multi-core

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mourão, D. A. R. (2011). Um middleware independente da plataforma para computação paralela. (Thesis). Universidade Nova. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/6322

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mourão, Diogo André Ribeiro. “Um middleware independente da plataforma para computação paralela.” 2011. Thesis, Universidade Nova. Accessed April 01, 2020. http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/6322.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mourão, Diogo André Ribeiro. “Um middleware independente da plataforma para computação paralela.” 2011. Web. 01 Apr 2020.

Vancouver:

Mourão DAR. Um middleware independente da plataforma para computação paralela. [Internet] [Thesis]. Universidade Nova; 2011. [cited 2020 Apr 01]. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/6322.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mourão DAR. Um middleware independente da plataforma para computação paralela. [Thesis]. Universidade Nova; 2011. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/6322

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Oslo

10. Wei, Wenjie. Effective use of multicore-based parallel computers for scientific computing.

Degree: 2012, University of Oslo

 This thesis studies how the multi-core hardware architecture can be efficiently used for real-world scientific applications that arise from computational cardiology and computational geoscience. The… (more)

Subjects/Keywords: multi-core; OpenMP; mixedprogramming; performancemodeling; VDP::420

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wei, W. (2012). Effective use of multicore-based parallel computers for scientific computing. (Thesis). University of Oslo. Retrieved from http://urn.nb.no/URN:NBN:no-33568 ; https://www.duo.uio.no/handle/10852/34824 ; Fulltext https://www.duo.uio.no/bitstream/handle/10852/34824/1/dravhandling-wei.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wei, Wenjie. “Effective use of multicore-based parallel computers for scientific computing.” 2012. Thesis, University of Oslo. Accessed April 01, 2020. http://urn.nb.no/URN:NBN:no-33568 ; https://www.duo.uio.no/handle/10852/34824 ; Fulltext https://www.duo.uio.no/bitstream/handle/10852/34824/1/dravhandling-wei.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wei, Wenjie. “Effective use of multicore-based parallel computers for scientific computing.” 2012. Web. 01 Apr 2020.

Vancouver:

Wei W. Effective use of multicore-based parallel computers for scientific computing. [Internet] [Thesis]. University of Oslo; 2012. [cited 2020 Apr 01]. Available from: http://urn.nb.no/URN:NBN:no-33568 ; https://www.duo.uio.no/handle/10852/34824 ; Fulltext https://www.duo.uio.no/bitstream/handle/10852/34824/1/dravhandling-wei.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wei W. Effective use of multicore-based parallel computers for scientific computing. [Thesis]. University of Oslo; 2012. Available from: http://urn.nb.no/URN:NBN:no-33568 ; https://www.duo.uio.no/handle/10852/34824 ; Fulltext https://www.duo.uio.no/bitstream/handle/10852/34824/1/dravhandling-wei.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

11. Narayana, S. Orchestrating Mixed-Criticality Melody: Reconciling Energy with Safety for Mixed-Criticality Embedded Real-Time Systems:.

Degree: 2015, Delft University of Technology

 Embedded systems are getting into various domains of our daily life as well as in many of the highly sophisticated large systems, such as air… (more)

Subjects/Keywords: mixed-criticality; criticality; energy minimization; multi-core

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Narayana, S. (2015). Orchestrating Mixed-Criticality Melody: Reconciling Energy with Safety for Mixed-Criticality Embedded Real-Time Systems:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:015312bf-905c-439a-a511-8b6f721888a5

Chicago Manual of Style (16th Edition):

Narayana, S. “Orchestrating Mixed-Criticality Melody: Reconciling Energy with Safety for Mixed-Criticality Embedded Real-Time Systems:.” 2015. Masters Thesis, Delft University of Technology. Accessed April 01, 2020. http://resolver.tudelft.nl/uuid:015312bf-905c-439a-a511-8b6f721888a5.

MLA Handbook (7th Edition):

Narayana, S. “Orchestrating Mixed-Criticality Melody: Reconciling Energy with Safety for Mixed-Criticality Embedded Real-Time Systems:.” 2015. Web. 01 Apr 2020.

Vancouver:

Narayana S. Orchestrating Mixed-Criticality Melody: Reconciling Energy with Safety for Mixed-Criticality Embedded Real-Time Systems:. [Internet] [Masters thesis]. Delft University of Technology; 2015. [cited 2020 Apr 01]. Available from: http://resolver.tudelft.nl/uuid:015312bf-905c-439a-a511-8b6f721888a5.

Council of Science Editors:

Narayana S. Orchestrating Mixed-Criticality Melody: Reconciling Energy with Safety for Mixed-Criticality Embedded Real-Time Systems:. [Masters Thesis]. Delft University of Technology; 2015. Available from: http://resolver.tudelft.nl/uuid:015312bf-905c-439a-a511-8b6f721888a5


The Ohio State University

12. Bao, Wenlei. Power Aware WCET Analysis.

Degree: MS, Electrical and Computer Engineering, 2014, The Ohio State University

 Worst case execution time (WCET) analysis is used to verify that real-time tasks on systems can be executed without violating any timing constraints. Power con-… (more)

Subjects/Keywords: Electrical Engineering; power, WCET, multi-core

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bao, W. (2014). Power Aware WCET Analysis. (Masters Thesis). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1398937286

Chicago Manual of Style (16th Edition):

Bao, Wenlei. “Power Aware WCET Analysis.” 2014. Masters Thesis, The Ohio State University. Accessed April 01, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=osu1398937286.

MLA Handbook (7th Edition):

Bao, Wenlei. “Power Aware WCET Analysis.” 2014. Web. 01 Apr 2020.

Vancouver:

Bao W. Power Aware WCET Analysis. [Internet] [Masters thesis]. The Ohio State University; 2014. [cited 2020 Apr 01]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1398937286.

Council of Science Editors:

Bao W. Power Aware WCET Analysis. [Masters Thesis]. The Ohio State University; 2014. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1398937286


University of Waterloo

13. Tegegn, Paulos. An Implementation of a Predictable Cache-coherent Multi-core System.

Degree: 2019, University of Waterloo

Multi-core platforms have entered the realm of the embedded systems to meet the ever growing performance requirements of the real-time embedded applications. Real-time applications leverage… (more)

Subjects/Keywords: real-time multi-core hardware on FPGA

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tegegn, P. (2019). An Implementation of a Predictable Cache-coherent Multi-core System. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/14647

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tegegn, Paulos. “An Implementation of a Predictable Cache-coherent Multi-core System.” 2019. Thesis, University of Waterloo. Accessed April 01, 2020. http://hdl.handle.net/10012/14647.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tegegn, Paulos. “An Implementation of a Predictable Cache-coherent Multi-core System.” 2019. Web. 01 Apr 2020.

Vancouver:

Tegegn P. An Implementation of a Predictable Cache-coherent Multi-core System. [Internet] [Thesis]. University of Waterloo; 2019. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10012/14647.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tegegn P. An Implementation of a Predictable Cache-coherent Multi-core System. [Thesis]. University of Waterloo; 2019. Available from: http://hdl.handle.net/10012/14647

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Arizona

14. Gajaria, Dhruv Mayur. DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors .

Degree: 2019, University of Arizona

 Spin-transfer torque RAMs (STT-RAMs) have been studied as a promising alternative to SRAMs in emerging caches and main memories due to their low leakage power… (more)

Subjects/Keywords: Caches; DVFS; Multi-Core Processors; STT-RAM

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gajaria, D. M. (2019). DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors . (Masters Thesis). University of Arizona. Retrieved from http://hdl.handle.net/10150/633246

Chicago Manual of Style (16th Edition):

Gajaria, Dhruv Mayur. “DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors .” 2019. Masters Thesis, University of Arizona. Accessed April 01, 2020. http://hdl.handle.net/10150/633246.

MLA Handbook (7th Edition):

Gajaria, Dhruv Mayur. “DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors .” 2019. Web. 01 Apr 2020.

Vancouver:

Gajaria DM. DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors . [Internet] [Masters thesis]. University of Arizona; 2019. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/10150/633246.

Council of Science Editors:

Gajaria DM. DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors . [Masters Thesis]. University of Arizona; 2019. Available from: http://hdl.handle.net/10150/633246


Washington University in St. Louis

15. Wun, Benjamin. High Speed Networking In The Multi-Core Era.

Degree: PhD, Computer Science and Engineering, 2011, Washington University in St. Louis

 High speed networking is a demanding task that has traditionally been performed in dedicated, purpose built hardware or specialized network processors. These platforms sacrifice flexibility… (more)

Subjects/Keywords: Computer engineering; Multi-core; Networking; Network Processor

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wun, B. (2011). High Speed Networking In The Multi-Core Era. (Doctoral Dissertation). Washington University in St. Louis. Retrieved from https://openscholarship.wustl.edu/etd/668

Chicago Manual of Style (16th Edition):

Wun, Benjamin. “High Speed Networking In The Multi-Core Era.” 2011. Doctoral Dissertation, Washington University in St. Louis. Accessed April 01, 2020. https://openscholarship.wustl.edu/etd/668.

MLA Handbook (7th Edition):

Wun, Benjamin. “High Speed Networking In The Multi-Core Era.” 2011. Web. 01 Apr 2020.

Vancouver:

Wun B. High Speed Networking In The Multi-Core Era. [Internet] [Doctoral dissertation]. Washington University in St. Louis; 2011. [cited 2020 Apr 01]. Available from: https://openscholarship.wustl.edu/etd/668.

Council of Science Editors:

Wun B. High Speed Networking In The Multi-Core Era. [Doctoral Dissertation]. Washington University in St. Louis; 2011. Available from: https://openscholarship.wustl.edu/etd/668


University of Southern California

16. Peng, Liu. Parallelization framework for scientific application kernels on multi-core/many-core platforms.

Degree: PhD, Computer Science, 2011, University of Southern California

 The advent of multi-core/many-core paradigm has provided unprecedented computing power, and it is of great significance to develop a parallelization framework for various scientific applications… (more)

Subjects/Keywords: multi/many core; parallel computing; scientific simulation

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Peng, L. (2011). Parallelization framework for scientific application kernels on multi-core/many-core platforms. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/624895/rec/4915

Chicago Manual of Style (16th Edition):

Peng, Liu. “Parallelization framework for scientific application kernels on multi-core/many-core platforms.” 2011. Doctoral Dissertation, University of Southern California. Accessed April 01, 2020. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/624895/rec/4915.

MLA Handbook (7th Edition):

Peng, Liu. “Parallelization framework for scientific application kernels on multi-core/many-core platforms.” 2011. Web. 01 Apr 2020.

Vancouver:

Peng L. Parallelization framework for scientific application kernels on multi-core/many-core platforms. [Internet] [Doctoral dissertation]. University of Southern California; 2011. [cited 2020 Apr 01]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/624895/rec/4915.

Council of Science Editors:

Peng L. Parallelization framework for scientific application kernels on multi-core/many-core platforms. [Doctoral Dissertation]. University of Southern California; 2011. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/624895/rec/4915

17. Méndez Real, Maria. Spatial Isolation against Logical Cache-based Side-Channel Attacks in Many-Core Architectures : Isolation physique contre les attaques logiques par canaux cachés basées sur le cache dans des architectures many-core.

Degree: Docteur es, Stic, 2017, Lorient

L’évolution technologique ainsi que l’augmentation incessante de la puissance de calcul requise par les applications font des architectures ”many-core” la nouvelle tendance dans la conception… (more)

Subjects/Keywords: Architectures many-core; Multi-core architectures; Open Virtual Platforms; 005.8

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Méndez Real, M. (2017). Spatial Isolation against Logical Cache-based Side-Channel Attacks in Many-Core Architectures : Isolation physique contre les attaques logiques par canaux cachés basées sur le cache dans des architectures many-core. (Doctoral Dissertation). Lorient. Retrieved from http://www.theses.fr/2017LORIS454

Chicago Manual of Style (16th Edition):

Méndez Real, Maria. “Spatial Isolation against Logical Cache-based Side-Channel Attacks in Many-Core Architectures : Isolation physique contre les attaques logiques par canaux cachés basées sur le cache dans des architectures many-core.” 2017. Doctoral Dissertation, Lorient. Accessed April 01, 2020. http://www.theses.fr/2017LORIS454.

MLA Handbook (7th Edition):

Méndez Real, Maria. “Spatial Isolation against Logical Cache-based Side-Channel Attacks in Many-Core Architectures : Isolation physique contre les attaques logiques par canaux cachés basées sur le cache dans des architectures many-core.” 2017. Web. 01 Apr 2020.

Vancouver:

Méndez Real M. Spatial Isolation against Logical Cache-based Side-Channel Attacks in Many-Core Architectures : Isolation physique contre les attaques logiques par canaux cachés basées sur le cache dans des architectures many-core. [Internet] [Doctoral dissertation]. Lorient; 2017. [cited 2020 Apr 01]. Available from: http://www.theses.fr/2017LORIS454.

Council of Science Editors:

Méndez Real M. Spatial Isolation against Logical Cache-based Side-Channel Attacks in Many-Core Architectures : Isolation physique contre les attaques logiques par canaux cachés basées sur le cache dans des architectures many-core. [Doctoral Dissertation]. Lorient; 2017. Available from: http://www.theses.fr/2017LORIS454

18. Tekić Jelena. Оптимизација CFD симулације на групама вишејезгарних хетерогених архитектура.

Degree: 2019, University of Novi Sad

Предмет  истраживања  тезе  је  из области  паралелног  програмирања, имплементација  CFD  (Computational Fluid  Dynamics)  методе  на  више хетерогених  вишејезгарних  уређаја истовремено.  У  раду  је  приказано… (more)

Subjects/Keywords: OpenCL; Lattice Boltzman; GPU; many-core; multi-core

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jelena, T. (2019). Оптимизација CFD симулације на групама вишејезгарних хетерогених архитектура. (Thesis). University of Novi Sad. Retrieved from https://www.cris.uns.ac.rs/DownloadFileServlet/Disertacija156386637550062.pdf?controlNumber=(BISIS)110976&fileName=156386637550062.pdf&id=13241&source=OATD&language=en ; https://www.cris.uns.ac.rs/record.jsf?recordId=110976&source=OATD&language=en

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jelena, Tekić. “Оптимизација CFD симулације на групама вишејезгарних хетерогених архитектура.” 2019. Thesis, University of Novi Sad. Accessed April 01, 2020. https://www.cris.uns.ac.rs/DownloadFileServlet/Disertacija156386637550062.pdf?controlNumber=(BISIS)110976&fileName=156386637550062.pdf&id=13241&source=OATD&language=en ; https://www.cris.uns.ac.rs/record.jsf?recordId=110976&source=OATD&language=en.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jelena, Tekić. “Оптимизација CFD симулације на групама вишејезгарних хетерогених архитектура.” 2019. Web. 01 Apr 2020.

Vancouver:

Jelena T. Оптимизација CFD симулације на групама вишејезгарних хетерогених архитектура. [Internet] [Thesis]. University of Novi Sad; 2019. [cited 2020 Apr 01]. Available from: https://www.cris.uns.ac.rs/DownloadFileServlet/Disertacija156386637550062.pdf?controlNumber=(BISIS)110976&fileName=156386637550062.pdf&id=13241&source=OATD&language=en ; https://www.cris.uns.ac.rs/record.jsf?recordId=110976&source=OATD&language=en.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jelena T. Оптимизација CFD симулације на групама вишејезгарних хетерогених архитектура. [Thesis]. University of Novi Sad; 2019. Available from: https://www.cris.uns.ac.rs/DownloadFileServlet/Disertacija156386637550062.pdf?controlNumber=(BISIS)110976&fileName=156386637550062.pdf&id=13241&source=OATD&language=en ; https://www.cris.uns.ac.rs/record.jsf?recordId=110976&source=OATD&language=en

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of New Mexico

19. Bezerra, George. Energy consumption in networks on chip : efficiency and scaling.

Degree: Department of Computer Science, 2012, University of New Mexico

 Computer architecture design is in a new era where performance is increased by replicating processing cores on a chip rather than making CPUs larger and… (more)

Subjects/Keywords: multi-core; many-core; energy consumption; communicaiton locality; scaling

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bezerra, G. (2012). Energy consumption in networks on chip : efficiency and scaling. (Doctoral Dissertation). University of New Mexico. Retrieved from http://hdl.handle.net/1928/21020

Chicago Manual of Style (16th Edition):

Bezerra, George. “Energy consumption in networks on chip : efficiency and scaling.” 2012. Doctoral Dissertation, University of New Mexico. Accessed April 01, 2020. http://hdl.handle.net/1928/21020.

MLA Handbook (7th Edition):

Bezerra, George. “Energy consumption in networks on chip : efficiency and scaling.” 2012. Web. 01 Apr 2020.

Vancouver:

Bezerra G. Energy consumption in networks on chip : efficiency and scaling. [Internet] [Doctoral dissertation]. University of New Mexico; 2012. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/1928/21020.

Council of Science Editors:

Bezerra G. Energy consumption in networks on chip : efficiency and scaling. [Doctoral Dissertation]. University of New Mexico; 2012. Available from: http://hdl.handle.net/1928/21020


NSYSU

20. Yang, Jyun-sheng. Design and Implementation of Multi-Port Shared Cache in Multi-core Systems.

Degree: Master, Computer Science and Engineering, 2016, NSYSU

Multi-port shared cache memory plays an important role in multi-core systems. Although single/dual-port SRAM can be realized using commercial standard cell library, multi-port shared cache… (more)

Subjects/Keywords: multi-port shared cache memory; multi-port shared cache memory generator; multi-core system

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yang, J. (2016). Design and Implementation of Multi-Port Shared Cache in Multi-core Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-150758

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yang, Jyun-sheng. “Design and Implementation of Multi-Port Shared Cache in Multi-core Systems.” 2016. Thesis, NSYSU. Accessed April 01, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-150758.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yang, Jyun-sheng. “Design and Implementation of Multi-Port Shared Cache in Multi-core Systems.” 2016. Web. 01 Apr 2020.

Vancouver:

Yang J. Design and Implementation of Multi-Port Shared Cache in Multi-core Systems. [Internet] [Thesis]. NSYSU; 2016. [cited 2020 Apr 01]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-150758.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yang J. Design and Implementation of Multi-Port Shared Cache in Multi-core Systems. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731116-150758

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

21. Lo, Moustapha. Application des architectures many core dans les systèmes embarqués temps réel : Implementing a Real-time Avionic application on a Many-core Processor.

Degree: Docteur es, Informatique, 2019, Grenoble Alpes

Les processeurs mono-coeurs traditionnels ne sont plus suffisants pour répondre aux besoins croissants en performance des fonctions avioniques. Les processeurs multi/many-coeurs ont emergé ces dernières… (more)

Subjects/Keywords: Many-Core; Temps-Réel; Determinisme; Multi-Core; Algorithmes globaux; Algorithmes incrémentaux; Many-Core; Real-Time; Determinism; Multi-Core; Global algorithms; Incremental Algorithms; 004

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lo, M. (2019). Application des architectures many core dans les systèmes embarqués temps réel : Implementing a Real-time Avionic application on a Many-core Processor. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2019GREAM002

Chicago Manual of Style (16th Edition):

Lo, Moustapha. “Application des architectures many core dans les systèmes embarqués temps réel : Implementing a Real-time Avionic application on a Many-core Processor.” 2019. Doctoral Dissertation, Grenoble Alpes. Accessed April 01, 2020. http://www.theses.fr/2019GREAM002.

MLA Handbook (7th Edition):

Lo, Moustapha. “Application des architectures many core dans les systèmes embarqués temps réel : Implementing a Real-time Avionic application on a Many-core Processor.” 2019. Web. 01 Apr 2020.

Vancouver:

Lo M. Application des architectures many core dans les systèmes embarqués temps réel : Implementing a Real-time Avionic application on a Many-core Processor. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2019. [cited 2020 Apr 01]. Available from: http://www.theses.fr/2019GREAM002.

Council of Science Editors:

Lo M. Application des architectures many core dans les systèmes embarqués temps réel : Implementing a Real-time Avionic application on a Many-core Processor. [Doctoral Dissertation]. Grenoble Alpes; 2019. Available from: http://www.theses.fr/2019GREAM002


University of Tennessee – Knoxville

22. Ma, Teng. Kernel-assisted and Topology-aware MPI Collective Communication among Multicore or Many-core Clusters.

Degree: 2012, University of Tennessee – Knoxville

 Multicore or many-core clusters have become the most prominent form of High Performance Computing (HPC) systems. Hardware complexity and hierarchies not only exist in the… (more)

Subjects/Keywords: MPI; kernel; hierarchical; collective; multi-core; many-core; Computational Engineering; Computer and Systems Architecture

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ma, T. (2012). Kernel-assisted and Topology-aware MPI Collective Communication among Multicore or Many-core Clusters. (Doctoral Dissertation). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_graddiss/1541

Chicago Manual of Style (16th Edition):

Ma, Teng. “Kernel-assisted and Topology-aware MPI Collective Communication among Multicore or Many-core Clusters.” 2012. Doctoral Dissertation, University of Tennessee – Knoxville. Accessed April 01, 2020. https://trace.tennessee.edu/utk_graddiss/1541.

MLA Handbook (7th Edition):

Ma, Teng. “Kernel-assisted and Topology-aware MPI Collective Communication among Multicore or Many-core Clusters.” 2012. Web. 01 Apr 2020.

Vancouver:

Ma T. Kernel-assisted and Topology-aware MPI Collective Communication among Multicore or Many-core Clusters. [Internet] [Doctoral dissertation]. University of Tennessee – Knoxville; 2012. [cited 2020 Apr 01]. Available from: https://trace.tennessee.edu/utk_graddiss/1541.

Council of Science Editors:

Ma T. Kernel-assisted and Topology-aware MPI Collective Communication among Multicore or Many-core Clusters. [Doctoral Dissertation]. University of Tennessee – Knoxville; 2012. Available from: https://trace.tennessee.edu/utk_graddiss/1541

23. Vargas Vallejo, Vanessa Carolina. Approche logicielle pour améliorer la fiabilité d’applications parallèles implémentées dans des processeurs multi-cœur et many-cœur : Software approach to improve the reliability of parallel applications implemented on multi-core and many-core processors.

Degree: Docteur es, Nano electronique et nano technologies, 2017, Grenoble Alpes

La grande capacité de calcul, flexibilité, faible consommation d'énergie, redondance intrinsèque et la haute performance fournie par les processeurs multi/many-cœur les rendent idéaux pour surmonter… (more)

Subjects/Keywords: Architectures parallèles; Multi-Cœur et many-Cœur; Fiabilité; Redondance; Multi-Processing mode; Injection de fautes; Parallel Architectures; Multi-Core and many-Core; Reliability; Redundancy; Multi-Processing mode; Fault injection; 620

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vargas Vallejo, V. C. (2017). Approche logicielle pour améliorer la fiabilité d’applications parallèles implémentées dans des processeurs multi-cœur et many-cœur : Software approach to improve the reliability of parallel applications implemented on multi-core and many-core processors. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2017GREAT042

Chicago Manual of Style (16th Edition):

Vargas Vallejo, Vanessa Carolina. “Approche logicielle pour améliorer la fiabilité d’applications parallèles implémentées dans des processeurs multi-cœur et many-cœur : Software approach to improve the reliability of parallel applications implemented on multi-core and many-core processors.” 2017. Doctoral Dissertation, Grenoble Alpes. Accessed April 01, 2020. http://www.theses.fr/2017GREAT042.

MLA Handbook (7th Edition):

Vargas Vallejo, Vanessa Carolina. “Approche logicielle pour améliorer la fiabilité d’applications parallèles implémentées dans des processeurs multi-cœur et many-cœur : Software approach to improve the reliability of parallel applications implemented on multi-core and many-core processors.” 2017. Web. 01 Apr 2020.

Vancouver:

Vargas Vallejo VC. Approche logicielle pour améliorer la fiabilité d’applications parallèles implémentées dans des processeurs multi-cœur et many-cœur : Software approach to improve the reliability of parallel applications implemented on multi-core and many-core processors. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2017. [cited 2020 Apr 01]. Available from: http://www.theses.fr/2017GREAT042.

Council of Science Editors:

Vargas Vallejo VC. Approche logicielle pour améliorer la fiabilité d’applications parallèles implémentées dans des processeurs multi-cœur et many-cœur : Software approach to improve the reliability of parallel applications implemented on multi-core and many-core processors. [Doctoral Dissertation]. Grenoble Alpes; 2017. Available from: http://www.theses.fr/2017GREAT042


Université de Montréal

24. Anane, Amine. Application du concept des transactions pour la modélisation et la simulation multicoeur des systèmes sur puce .

Degree: 2012, Université de Montréal

 Avec la complexité croissante des systèmes sur puce, de nouveaux défis ne cessent d’émerger dans la conception de ces systèmes en matière de vérification formelle… (more)

Subjects/Keywords: Modélisation; SOC Design; Simulation parallèle; Parallel Simulation; Transactions; Multi-coeur; Multi-core

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Anane, A. (2012). Application du concept des transactions pour la modélisation et la simulation multicoeur des systèmes sur puce . (Thesis). Université de Montréal. Retrieved from http://hdl.handle.net/1866/7097

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Anane, Amine. “Application du concept des transactions pour la modélisation et la simulation multicoeur des systèmes sur puce .” 2012. Thesis, Université de Montréal. Accessed April 01, 2020. http://hdl.handle.net/1866/7097.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Anane, Amine. “Application du concept des transactions pour la modélisation et la simulation multicoeur des systèmes sur puce .” 2012. Web. 01 Apr 2020.

Vancouver:

Anane A. Application du concept des transactions pour la modélisation et la simulation multicoeur des systèmes sur puce . [Internet] [Thesis]. Université de Montréal; 2012. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/1866/7097.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Anane A. Application du concept des transactions pour la modélisation et la simulation multicoeur des systèmes sur puce . [Thesis]. Université de Montréal; 2012. Available from: http://hdl.handle.net/1866/7097

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Université Paris-Sud – Paris XI

25. Bin, Jingyi. Controlling execution time variability using COTS for Safety-critical systems : Contrôler la variabilité du temps d’exécution en utilisant COTS pour les systèmes Safety-critical.

Degree: Docteur es, Physique (Systèmes Embarqués), 2014, Université Paris-Sud – Paris XI

Au cours de la dernière décennie, le domaine safety-critical s’appuie sur les Commercial Off-The-Shelf (COTS) architectures de mono-coeur malgré leur variabilité du temps d'exécution inhérent.… (more)

Subjects/Keywords: Safety-critical; Multi-coeur; WCET; Compteurs de performance; Safety-critical; Multi-core; WCET; Hardware counters

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bin, J. (2014). Controlling execution time variability using COTS for Safety-critical systems : Contrôler la variabilité du temps d’exécution en utilisant COTS pour les systèmes Safety-critical. (Doctoral Dissertation). Université Paris-Sud – Paris XI. Retrieved from http://www.theses.fr/2014PA112151

Chicago Manual of Style (16th Edition):

Bin, Jingyi. “Controlling execution time variability using COTS for Safety-critical systems : Contrôler la variabilité du temps d’exécution en utilisant COTS pour les systèmes Safety-critical.” 2014. Doctoral Dissertation, Université Paris-Sud – Paris XI. Accessed April 01, 2020. http://www.theses.fr/2014PA112151.

MLA Handbook (7th Edition):

Bin, Jingyi. “Controlling execution time variability using COTS for Safety-critical systems : Contrôler la variabilité du temps d’exécution en utilisant COTS pour les systèmes Safety-critical.” 2014. Web. 01 Apr 2020.

Vancouver:

Bin J. Controlling execution time variability using COTS for Safety-critical systems : Contrôler la variabilité du temps d’exécution en utilisant COTS pour les systèmes Safety-critical. [Internet] [Doctoral dissertation]. Université Paris-Sud – Paris XI; 2014. [cited 2020 Apr 01]. Available from: http://www.theses.fr/2014PA112151.

Council of Science Editors:

Bin J. Controlling execution time variability using COTS for Safety-critical systems : Contrôler la variabilité du temps d’exécution en utilisant COTS pour les systèmes Safety-critical. [Doctoral Dissertation]. Université Paris-Sud – Paris XI; 2014. Available from: http://www.theses.fr/2014PA112151


Georgia Tech

26. Xiao, He. A Multi-physics approach to the co-design of 3D multi-core processors.

Degree: PhD, Electrical and Computer Engineering, 2018, Georgia Tech

 The three-dimensional integrated circuit (3D IC) is a promising solution for processors in the post-Moore era. The 3D integration stacks multiple dies vertically in a… (more)

Subjects/Keywords: Performance; Energy efficiency; 3D IC; Multi-core systems; Multi-physics analysis; Microarchitecture co-design

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Xiao, H. (2018). A Multi-physics approach to the co-design of 3D multi-core processors. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/59810

Chicago Manual of Style (16th Edition):

Xiao, He. “A Multi-physics approach to the co-design of 3D multi-core processors.” 2018. Doctoral Dissertation, Georgia Tech. Accessed April 01, 2020. http://hdl.handle.net/1853/59810.

MLA Handbook (7th Edition):

Xiao, He. “A Multi-physics approach to the co-design of 3D multi-core processors.” 2018. Web. 01 Apr 2020.

Vancouver:

Xiao H. A Multi-physics approach to the co-design of 3D multi-core processors. [Internet] [Doctoral dissertation]. Georgia Tech; 2018. [cited 2020 Apr 01]. Available from: http://hdl.handle.net/1853/59810.

Council of Science Editors:

Xiao H. A Multi-physics approach to the co-design of 3D multi-core processors. [Doctoral Dissertation]. Georgia Tech; 2018. Available from: http://hdl.handle.net/1853/59810

27. Saidi, Salah Eddine. Approches de parallélisation automatique et d'ordonnancement pour la co-simulation de modèles numériques sur processeurs multi-coeurs : Automatic parallelization and scheduling approaches for co-simulation of numerical models on multi-core processors.

Degree: Docteur es, Informatique, 2018, Sorbonne université

Lors de la conception de systèmes cyber-physiques, des modèles issus de différents environnements de modélisation doivent être intégrés afin de simuler l'ensemble du système et… (more)

Subjects/Keywords: Co-Simulation; Multi-coeurs; Ordonnancement; Temps réel; Parallélisation; Accélération; Co-simulation; Multi-core; Scheduling; 004.35

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Saidi, S. E. (2018). Approches de parallélisation automatique et d'ordonnancement pour la co-simulation de modèles numériques sur processeurs multi-coeurs : Automatic parallelization and scheduling approaches for co-simulation of numerical models on multi-core processors. (Doctoral Dissertation). Sorbonne université. Retrieved from http://www.theses.fr/2018SORUS036

Chicago Manual of Style (16th Edition):

Saidi, Salah Eddine. “Approches de parallélisation automatique et d'ordonnancement pour la co-simulation de modèles numériques sur processeurs multi-coeurs : Automatic parallelization and scheduling approaches for co-simulation of numerical models on multi-core processors.” 2018. Doctoral Dissertation, Sorbonne université. Accessed April 01, 2020. http://www.theses.fr/2018SORUS036.

MLA Handbook (7th Edition):

Saidi, Salah Eddine. “Approches de parallélisation automatique et d'ordonnancement pour la co-simulation de modèles numériques sur processeurs multi-coeurs : Automatic parallelization and scheduling approaches for co-simulation of numerical models on multi-core processors.” 2018. Web. 01 Apr 2020.

Vancouver:

Saidi SE. Approches de parallélisation automatique et d'ordonnancement pour la co-simulation de modèles numériques sur processeurs multi-coeurs : Automatic parallelization and scheduling approaches for co-simulation of numerical models on multi-core processors. [Internet] [Doctoral dissertation]. Sorbonne université; 2018. [cited 2020 Apr 01]. Available from: http://www.theses.fr/2018SORUS036.

Council of Science Editors:

Saidi SE. Approches de parallélisation automatique et d'ordonnancement pour la co-simulation de modèles numériques sur processeurs multi-coeurs : Automatic parallelization and scheduling approaches for co-simulation of numerical models on multi-core processors. [Doctoral Dissertation]. Sorbonne université; 2018. Available from: http://www.theses.fr/2018SORUS036


Universidade do Rio Grande do Norte

28. Barros, Carlos Avelino de. Redução do consumo energético de aplicações paralelas em arquiteturas multi-core .

Degree: 2016, Universidade do Rio Grande do Norte

 The period that lasted from the advent of microprocessors until early this century was marked by the geometric expansion of their operating frequency. If on… (more)

Subjects/Keywords: Economia de energia; Modelagem de potência elétrica; Processadores multi-core

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Barros, C. A. d. (2016). Redução do consumo energético de aplicações paralelas em arquiteturas multi-core . (Doctoral Dissertation). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/21608

Chicago Manual of Style (16th Edition):

Barros, Carlos Avelino de. “Redução do consumo energético de aplicações paralelas em arquiteturas multi-core .” 2016. Doctoral Dissertation, Universidade do Rio Grande do Norte. Accessed April 01, 2020. http://repositorio.ufrn.br/handle/123456789/21608.

MLA Handbook (7th Edition):

Barros, Carlos Avelino de. “Redução do consumo energético de aplicações paralelas em arquiteturas multi-core .” 2016. Web. 01 Apr 2020.

Vancouver:

Barros CAd. Redução do consumo energético de aplicações paralelas em arquiteturas multi-core . [Internet] [Doctoral dissertation]. Universidade do Rio Grande do Norte; 2016. [cited 2020 Apr 01]. Available from: http://repositorio.ufrn.br/handle/123456789/21608.

Council of Science Editors:

Barros CAd. Redução do consumo energético de aplicações paralelas em arquiteturas multi-core . [Doctoral Dissertation]. Universidade do Rio Grande do Norte; 2016. Available from: http://repositorio.ufrn.br/handle/123456789/21608


The Ohio State University

29. Ding, Xiaoning. ADVANCEMENT OF OPERATING SYSTEM TO MANAGE CRITICAL RESOURCES IN INCREASINGLY COMPLEX COMPUTER ARCHITECTURE.

Degree: PhD, Computer Science and Engineering, 2010, The Ohio State University

  Computer systems are experiencing great changes with rapid technology advancements in multi-core processors and rapid workload pattern shifts from computing-intensive to highly data-intensive applications.… (more)

Subjects/Keywords: Computer Science; Operating System; Caching; Prefetching; Multi-core; Buffer Cache; Scalability

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ding, X. (2010). ADVANCEMENT OF OPERATING SYSTEM TO MANAGE CRITICAL RESOURCES IN INCREASINGLY COMPLEX COMPUTER ARCHITECTURE. (Doctoral Dissertation). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1280511004

Chicago Manual of Style (16th Edition):

Ding, Xiaoning. “ADVANCEMENT OF OPERATING SYSTEM TO MANAGE CRITICAL RESOURCES IN INCREASINGLY COMPLEX COMPUTER ARCHITECTURE.” 2010. Doctoral Dissertation, The Ohio State University. Accessed April 01, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=osu1280511004.

MLA Handbook (7th Edition):

Ding, Xiaoning. “ADVANCEMENT OF OPERATING SYSTEM TO MANAGE CRITICAL RESOURCES IN INCREASINGLY COMPLEX COMPUTER ARCHITECTURE.” 2010. Web. 01 Apr 2020.

Vancouver:

Ding X. ADVANCEMENT OF OPERATING SYSTEM TO MANAGE CRITICAL RESOURCES IN INCREASINGLY COMPLEX COMPUTER ARCHITECTURE. [Internet] [Doctoral dissertation]. The Ohio State University; 2010. [cited 2020 Apr 01]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1280511004.

Council of Science Editors:

Ding X. ADVANCEMENT OF OPERATING SYSTEM TO MANAGE CRITICAL RESOURCES IN INCREASINGLY COMPLEX COMPUTER ARCHITECTURE. [Doctoral Dissertation]. The Ohio State University; 2010. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1280511004


The Ohio State University

30. Van Valkenburgh, Kevin. Measuring and Improving the Potential Parallelism of Sequential Java Programs.

Degree: MS, Computer Science and Engineering, 2009, The Ohio State University

 There is a growing need for parallel algorithms and their implementations, due to the continued rise in the use of multi-core machines. When trying to… (more)

Subjects/Keywords: Computer Science; Java; parallelism; multi-core; potential parallelism

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Van Valkenburgh, K. (2009). Measuring and Improving the Potential Parallelism of Sequential Java Programs. (Masters Thesis). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1250594496

Chicago Manual of Style (16th Edition):

Van Valkenburgh, Kevin. “Measuring and Improving the Potential Parallelism of Sequential Java Programs.” 2009. Masters Thesis, The Ohio State University. Accessed April 01, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=osu1250594496.

MLA Handbook (7th Edition):

Van Valkenburgh, Kevin. “Measuring and Improving the Potential Parallelism of Sequential Java Programs.” 2009. Web. 01 Apr 2020.

Vancouver:

Van Valkenburgh K. Measuring and Improving the Potential Parallelism of Sequential Java Programs. [Internet] [Masters thesis]. The Ohio State University; 2009. [cited 2020 Apr 01]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1250594496.

Council of Science Editors:

Van Valkenburgh K. Measuring and Improving the Potential Parallelism of Sequential Java Programs. [Masters Thesis]. The Ohio State University; 2009. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1250594496

[1] [2] [3] [4] [5] [6] [7] [8] [9]

.