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You searched for subject:(multi clock). Showing records 1 – 16 of 16 total matches.

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NSYSU

1. Cheng, Chien-Kang. Multi-precision Function Interpolator for Multimedia Applications.

Degree: Master, Computer Science and Engineering, 2012, NSYSU

 A multi-precision function interpolator, which is fitted in with the IEEE-754 single precision floating point standard, is proposed in this paper. It provides logarithms, exponentials,… (more)

Subjects/Keywords: minimax approximation; multi-precision function interpolator; look-up table; clock gating; low power

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cheng, C. (2012). Multi-precision Function Interpolator for Multimedia Applications. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725112-112632

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Cheng, Chien-Kang. “Multi-precision Function Interpolator for Multimedia Applications.” 2012. Thesis, NSYSU. Accessed April 04, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725112-112632.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Cheng, Chien-Kang. “Multi-precision Function Interpolator for Multimedia Applications.” 2012. Web. 04 Apr 2020.

Vancouver:

Cheng C. Multi-precision Function Interpolator for Multimedia Applications. [Internet] [Thesis]. NSYSU; 2012. [cited 2020 Apr 04]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725112-112632.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Cheng C. Multi-precision Function Interpolator for Multimedia Applications. [Thesis]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0725112-112632

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

2. Chang, Ming-Fong. A Multi-functional Multi-precision 4D Dot Product Unit with SIMD Architecture.

Degree: Master, Computer Science and Engineering, 2015, NSYSU

 In modern graphics processing unit, the vertex shader is a quite important component. It is mainly responsible for the coordinate transformation and lightâs geometric operations.… (more)

Subjects/Keywords: Single Instruction Multiple Data; Multi-precision; 4D Dot Product; Clock Gating; Low Power

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APA (6th Edition):

Chang, M. (2015). A Multi-functional Multi-precision 4D Dot Product Unit with SIMD Architecture. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0630115-164853

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chang, Ming-Fong. “A Multi-functional Multi-precision 4D Dot Product Unit with SIMD Architecture.” 2015. Thesis, NSYSU. Accessed April 04, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0630115-164853.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chang, Ming-Fong. “A Multi-functional Multi-precision 4D Dot Product Unit with SIMD Architecture.” 2015. Web. 04 Apr 2020.

Vancouver:

Chang M. A Multi-functional Multi-precision 4D Dot Product Unit with SIMD Architecture. [Internet] [Thesis]. NSYSU; 2015. [cited 2020 Apr 04]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0630115-164853.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chang M. A Multi-functional Multi-precision 4D Dot Product Unit with SIMD Architecture. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0630115-164853

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Linköping University

3. Zadeh, Iman Esmaeil. A Study and Implementation of On-Chip EMC Techniques.

Degree: Electronic Devices, 2010, Linköping University

  ElectroMagnetic Interferences (EMI) are emerging problems in today's high speed circuits. There are several examples that these interferences affected the circuits and systems. This… (more)

Subjects/Keywords: ElectroMagnetic Interference; ElectroMagnetic Compatibility; Clock Spectrum; Clock Shaping; Multi-Segment Clocking; Electronics; Elektronik

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APA (6th Edition):

Zadeh, I. E. (2010). A Study and Implementation of On-Chip EMC Techniques. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-63914

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zadeh, Iman Esmaeil. “A Study and Implementation of On-Chip EMC Techniques.” 2010. Thesis, Linköping University. Accessed April 04, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-63914.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zadeh, Iman Esmaeil. “A Study and Implementation of On-Chip EMC Techniques.” 2010. Web. 04 Apr 2020.

Vancouver:

Zadeh IE. A Study and Implementation of On-Chip EMC Techniques. [Internet] [Thesis]. Linköping University; 2010. [cited 2020 Apr 04]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-63914.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zadeh IE. A Study and Implementation of On-Chip EMC Techniques. [Thesis]. Linköping University; 2010. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-63914

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

4. Ait Mansour, El Houssain. Numérisation rapide d'un système synchronisé en sortie d'antennes multi-réparties tel que le Radiohéliographe de Nançay : High speed digital synchronized system for antenna array such as Nançay Radioheliograph.

Degree: Docteur es, Astronomie et Astrophysique, 2018, Paris Sciences et Lettres

Le Radiohéliographe de Nançay est le seul instrument dédié à l'imagerie du soleil en ondes décimétriques-métriques. Il fonctionne sur le principe de l'interférométrie, en utilisant… (more)

Subjects/Keywords: Radiohéliographe; Numérisation rapide; Synchronisation d'horloge; Antennes multi-Réparties; Architecture numérique; Observation du soleil; Radioheliograph; High speed digitizer; Clock synchronization; Multi-Distributed Antennas; Digital Architecture; Solar observation; 520

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APA (6th Edition):

Ait Mansour, E. H. (2018). Numérisation rapide d'un système synchronisé en sortie d'antennes multi-réparties tel que le Radiohéliographe de Nançay : High speed digital synchronized system for antenna array such as Nançay Radioheliograph. (Doctoral Dissertation). Paris Sciences et Lettres. Retrieved from http://www.theses.fr/2018PSLEO001

Chicago Manual of Style (16th Edition):

Ait Mansour, El Houssain. “Numérisation rapide d'un système synchronisé en sortie d'antennes multi-réparties tel que le Radiohéliographe de Nançay : High speed digital synchronized system for antenna array such as Nançay Radioheliograph.” 2018. Doctoral Dissertation, Paris Sciences et Lettres. Accessed April 04, 2020. http://www.theses.fr/2018PSLEO001.

MLA Handbook (7th Edition):

Ait Mansour, El Houssain. “Numérisation rapide d'un système synchronisé en sortie d'antennes multi-réparties tel que le Radiohéliographe de Nançay : High speed digital synchronized system for antenna array such as Nançay Radioheliograph.” 2018. Web. 04 Apr 2020.

Vancouver:

Ait Mansour EH. Numérisation rapide d'un système synchronisé en sortie d'antennes multi-réparties tel que le Radiohéliographe de Nançay : High speed digital synchronized system for antenna array such as Nançay Radioheliograph. [Internet] [Doctoral dissertation]. Paris Sciences et Lettres; 2018. [cited 2020 Apr 04]. Available from: http://www.theses.fr/2018PSLEO001.

Council of Science Editors:

Ait Mansour EH. Numérisation rapide d'un système synchronisé en sortie d'antennes multi-réparties tel que le Radiohéliographe de Nançay : High speed digital synchronized system for antenna array such as Nançay Radioheliograph. [Doctoral Dissertation]. Paris Sciences et Lettres; 2018. Available from: http://www.theses.fr/2018PSLEO001


Texas A&M University

5. Ahmed, Ramy 1981-. Jitter-Tolerance and Blocker-Tolerance of Delta-Sigma Analog-to-Digital Converters for Saw-Less Multi-Standard Receivers.

Degree: 2012, Texas A&M University

 The quest for multi-standard and software-defined radio (SDR) receivers calls for high flexibility in the receiver building-blocks so that to accommodate several wireless services using… (more)

Subjects/Keywords: Delta-Sigma (??) modulators; analog-to-digital converter (ADC); blocker-tolerance; clock-jitter; continuous-time (CT) ??; multi-standard receivers; software-defined radio (SDR)

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APA (6th Edition):

Ahmed, R. 1. (2012). Jitter-Tolerance and Blocker-Tolerance of Delta-Sigma Analog-to-Digital Converters for Saw-Less Multi-Standard Receivers. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/148047

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ahmed, Ramy 1981-. “Jitter-Tolerance and Blocker-Tolerance of Delta-Sigma Analog-to-Digital Converters for Saw-Less Multi-Standard Receivers.” 2012. Thesis, Texas A&M University. Accessed April 04, 2020. http://hdl.handle.net/1969.1/148047.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ahmed, Ramy 1981-. “Jitter-Tolerance and Blocker-Tolerance of Delta-Sigma Analog-to-Digital Converters for Saw-Less Multi-Standard Receivers.” 2012. Web. 04 Apr 2020.

Vancouver:

Ahmed R1. Jitter-Tolerance and Blocker-Tolerance of Delta-Sigma Analog-to-Digital Converters for Saw-Less Multi-Standard Receivers. [Internet] [Thesis]. Texas A&M University; 2012. [cited 2020 Apr 04]. Available from: http://hdl.handle.net/1969.1/148047.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ahmed R1. Jitter-Tolerance and Blocker-Tolerance of Delta-Sigma Analog-to-Digital Converters for Saw-Less Multi-Standard Receivers. [Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/148047

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

6. Padyana, Aravind 1983-. Design Considerations for Wide Bandwidth Continuous-Time Low-Pass Delta-Sigma Analog-to-Digital Converters.

Degree: 2010, Texas A&M University

 Continuous-time (CT) delta-sigma (??) analog-to-digital converters (ADC) have emerged as the popular choice to achieve high resolution and large bandwidth due to their low cost,… (more)

Subjects/Keywords: self-calibration; dynamic element matching; multi-bit dac; digital-to-analog converter; clock jitter tolerance; delta-sigma adc; analog-to-digital converter

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APA (6th Edition):

Padyana, A. 1. (2010). Design Considerations for Wide Bandwidth Continuous-Time Low-Pass Delta-Sigma Analog-to-Digital Converters. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/148453

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Padyana, Aravind 1983-. “Design Considerations for Wide Bandwidth Continuous-Time Low-Pass Delta-Sigma Analog-to-Digital Converters.” 2010. Thesis, Texas A&M University. Accessed April 04, 2020. http://hdl.handle.net/1969.1/148453.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Padyana, Aravind 1983-. “Design Considerations for Wide Bandwidth Continuous-Time Low-Pass Delta-Sigma Analog-to-Digital Converters.” 2010. Web. 04 Apr 2020.

Vancouver:

Padyana A1. Design Considerations for Wide Bandwidth Continuous-Time Low-Pass Delta-Sigma Analog-to-Digital Converters. [Internet] [Thesis]. Texas A&M University; 2010. [cited 2020 Apr 04]. Available from: http://hdl.handle.net/1969.1/148453.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Padyana A1. Design Considerations for Wide Bandwidth Continuous-Time Low-Pass Delta-Sigma Analog-to-Digital Converters. [Thesis]. Texas A&M University; 2010. Available from: http://hdl.handle.net/1969.1/148453

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

7. Plassan, Guillaume. Conclusive formal verification of clock domain crossing properties : Vérification formelle concluante des propriétés des systèmes multi-horloges.

Degree: Docteur es, Nano electronique et nano technologies, 2018, Grenoble Alpes

Les circuits microélectroniques récents intègrent des dizaines d'horloges afin d'optimiser leur consommation et leur performance. Le nombre de traversées de domaines d'horloges (CDC) et la… (more)

Subjects/Keywords: Méthodes formelles; Systèmes multi-Horloges; Système sur puce; Vérification de modèles; Validation functionnelle; Formal methods; Clock domain crossing; System on Chip; Model checking; Hardware verification; 004

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APA (6th Edition):

Plassan, G. (2018). Conclusive formal verification of clock domain crossing properties : Vérification formelle concluante des propriétés des systèmes multi-horloges. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2018GREAT021

Chicago Manual of Style (16th Edition):

Plassan, Guillaume. “Conclusive formal verification of clock domain crossing properties : Vérification formelle concluante des propriétés des systèmes multi-horloges.” 2018. Doctoral Dissertation, Grenoble Alpes. Accessed April 04, 2020. http://www.theses.fr/2018GREAT021.

MLA Handbook (7th Edition):

Plassan, Guillaume. “Conclusive formal verification of clock domain crossing properties : Vérification formelle concluante des propriétés des systèmes multi-horloges.” 2018. Web. 04 Apr 2020.

Vancouver:

Plassan G. Conclusive formal verification of clock domain crossing properties : Vérification formelle concluante des propriétés des systèmes multi-horloges. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2018. [cited 2020 Apr 04]. Available from: http://www.theses.fr/2018GREAT021.

Council of Science Editors:

Plassan G. Conclusive formal verification of clock domain crossing properties : Vérification formelle concluante des propriétés des systèmes multi-horloges. [Doctoral Dissertation]. Grenoble Alpes; 2018. Available from: http://www.theses.fr/2018GREAT021

8. LaCara, Benjamin Michael. Multi-Frequency Resonant Clocks.

Degree: Computer Engineering, 2014, University of California – Santa Cruz

Clock distribution networks consume a significant portion of total chip powerin high-performance designs. Of many proposed solutions to this drain, clock resonancehas been shown to… (more)

Subjects/Keywords: Computer engineering; Clock distribution network; Multi-frequency; Resonant

…Abstract Multi-Frequency Resonant Clocks by Benjamin Michael LaCara Clock distribution… …proposed solutions to this drain, clock resonance has been shown to be an effective method for… …number of required clock buffers. Current resonant solutions come with the limitation of… …first scheme to produce a clock distribution network with a tunable resonant frequency… …saving up to 41% power on the clock distribution network when compared to the non-resonant… 

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APA (6th Edition):

LaCara, B. M. (2014). Multi-Frequency Resonant Clocks. (Thesis). University of California – Santa Cruz. Retrieved from http://www.escholarship.org/uc/item/3qj5x81r

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

LaCara, Benjamin Michael. “Multi-Frequency Resonant Clocks.” 2014. Thesis, University of California – Santa Cruz. Accessed April 04, 2020. http://www.escholarship.org/uc/item/3qj5x81r.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

LaCara, Benjamin Michael. “Multi-Frequency Resonant Clocks.” 2014. Web. 04 Apr 2020.

Vancouver:

LaCara BM. Multi-Frequency Resonant Clocks. [Internet] [Thesis]. University of California – Santa Cruz; 2014. [cited 2020 Apr 04]. Available from: http://www.escholarship.org/uc/item/3qj5x81r.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

LaCara BM. Multi-Frequency Resonant Clocks. [Thesis]. University of California – Santa Cruz; 2014. Available from: http://www.escholarship.org/uc/item/3qj5x81r

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

9. Korniienko, Anton. Réseau de PLLs distribuées pour synthèse automatique d'horloge de MPSOCs synchrones : Distributed PLL network for automatic clock synthesis of synchronous MPSOCs.

Degree: Docteur es, Informatique Automatique, 2011, Ecully, Ecole centrale de Lyon

 Les arbres classiques de distribution du signal d’horloge au sein des microprocesseurs synchrones présentent un certain nombre de limitations : skew, jitter, limitation de la… (more)

Subjects/Keywords: Systèmes en réseau; Système multi-agents; Commande décentralisée; Commande H∞; Dissipativité; Optimisation LMI; Conception du réseau de PLLs; Synchronisation; Distribution active du signal d'horloge; Networked systems; Multi-agents systems; Decentralized control; H∞ control; Dissipativity; LMI optimization; PLL network design; Synchronization; Active clock distribution

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APA (6th Edition):

Korniienko, A. (2011). Réseau de PLLs distribuées pour synthèse automatique d'horloge de MPSOCs synchrones : Distributed PLL network for automatic clock synthesis of synchronous MPSOCs. (Doctoral Dissertation). Ecully, Ecole centrale de Lyon. Retrieved from http://www.theses.fr/2011ECDL0040

Chicago Manual of Style (16th Edition):

Korniienko, Anton. “Réseau de PLLs distribuées pour synthèse automatique d'horloge de MPSOCs synchrones : Distributed PLL network for automatic clock synthesis of synchronous MPSOCs.” 2011. Doctoral Dissertation, Ecully, Ecole centrale de Lyon. Accessed April 04, 2020. http://www.theses.fr/2011ECDL0040.

MLA Handbook (7th Edition):

Korniienko, Anton. “Réseau de PLLs distribuées pour synthèse automatique d'horloge de MPSOCs synchrones : Distributed PLL network for automatic clock synthesis of synchronous MPSOCs.” 2011. Web. 04 Apr 2020.

Vancouver:

Korniienko A. Réseau de PLLs distribuées pour synthèse automatique d'horloge de MPSOCs synchrones : Distributed PLL network for automatic clock synthesis of synchronous MPSOCs. [Internet] [Doctoral dissertation]. Ecully, Ecole centrale de Lyon; 2011. [cited 2020 Apr 04]. Available from: http://www.theses.fr/2011ECDL0040.

Council of Science Editors:

Korniienko A. Réseau de PLLs distribuées pour synthèse automatique d'horloge de MPSOCs synchrones : Distributed PLL network for automatic clock synthesis of synchronous MPSOCs. [Doctoral Dissertation]. Ecully, Ecole centrale de Lyon; 2011. Available from: http://www.theses.fr/2011ECDL0040


University of Illinois – Urbana-Champaign

10. Lucas, Gregory M. Timing Analysis and Behavioral Synthesis with Process Variation.

Degree: MS, Electrical and Computer Engineering, 2009, University of Illinois – Urbana-Champaign

 The move to deep submicron processes has brought about new problems that designers must contend with in order to obtain functional circuits. Process variation has… (more)

Subjects/Keywords: process variation; high-level synthesis; behavioral synthesis; statistical static timing analysis; SSTA; multi-cycle; multi-clock

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APA (6th Edition):

Lucas, G. M. (2009). Timing Analysis and Behavioral Synthesis with Process Variation. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/11966

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lucas, Gregory M. “Timing Analysis and Behavioral Synthesis with Process Variation.” 2009. Thesis, University of Illinois – Urbana-Champaign. Accessed April 04, 2020. http://hdl.handle.net/2142/11966.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lucas, Gregory M. “Timing Analysis and Behavioral Synthesis with Process Variation.” 2009. Web. 04 Apr 2020.

Vancouver:

Lucas GM. Timing Analysis and Behavioral Synthesis with Process Variation. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2009. [cited 2020 Apr 04]. Available from: http://hdl.handle.net/2142/11966.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lucas GM. Timing Analysis and Behavioral Synthesis with Process Variation. [Thesis]. University of Illinois – Urbana-Champaign; 2009. Available from: http://hdl.handle.net/2142/11966

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

11. Hadke, Tejas. Low power design implementation and verification.

Degree: MS, Electrical and Electronic Engineering, 2014, California State University – Sacramento

 According to Moore???s law, the number of transistors on integrated circuits (ICs) double approximately every two years. Over the years, this growth in number of… (more)

Subjects/Keywords: Clock gating; Multi Vt; Power gating; Low power SoC; Lowe power system on chip; Multi Vdd

…reduction techniques 3. Clock Gating 4. Frequency scaling, dynamic voltage scaling 5. Use of multi… …be later achieved during physical design flow. After clock gating, we focused on multi VDD… …5 2.3 Clock Gating… …7 2.3.1 Architectural clock gating technique… …8 2.3.2 Gate level clock gating… 

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APA (6th Edition):

Hadke, T. (2014). Low power design implementation and verification. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.3/131724

Chicago Manual of Style (16th Edition):

Hadke, Tejas. “Low power design implementation and verification.” 2014. Masters Thesis, California State University – Sacramento. Accessed April 04, 2020. http://hdl.handle.net/10211.3/131724.

MLA Handbook (7th Edition):

Hadke, Tejas. “Low power design implementation and verification.” 2014. Web. 04 Apr 2020.

Vancouver:

Hadke T. Low power design implementation and verification. [Internet] [Masters thesis]. California State University – Sacramento; 2014. [cited 2020 Apr 04]. Available from: http://hdl.handle.net/10211.3/131724.

Council of Science Editors:

Hadke T. Low power design implementation and verification. [Masters Thesis]. California State University – Sacramento; 2014. Available from: http://hdl.handle.net/10211.3/131724

12. Ponniah, Jonathan. A clean slate approach to secure wireless networking.

Degree: PhD, 1200, 2014, University of Illinois – Urbana-Champaign

 Traditionally, wireless network protocols have been developed for performance. Subsequently, as attacks are identified, patches or defenses have been developed. This has led to an… (more)

Subjects/Keywords: Multi-hop wireless networks; Utility maximization; Game theory; Security; Secure clock synchronization

…69 CHAPTER 4 SECURE CLOCK SYNCHRONIZATION 4.1 Problem Framework and Assumptions… …system theoretic approach to security of ad hoc multi-hop wireless networks. Traditionally… …focus is on ad-hoc, multi-hop, wireless networks. These are a class of wireless networks… …broadcast [4]. Routing protocols determine the multi-hop path that packets must follow… …to a centralized reference clock. In practice however, wireless nodes have only their local… 

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APA (6th Edition):

Ponniah, J. (2014). A clean slate approach to secure wireless networking. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/46565

Chicago Manual of Style (16th Edition):

Ponniah, Jonathan. “A clean slate approach to secure wireless networking.” 2014. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 04, 2020. http://hdl.handle.net/2142/46565.

MLA Handbook (7th Edition):

Ponniah, Jonathan. “A clean slate approach to secure wireless networking.” 2014. Web. 04 Apr 2020.

Vancouver:

Ponniah J. A clean slate approach to secure wireless networking. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2014. [cited 2020 Apr 04]. Available from: http://hdl.handle.net/2142/46565.

Council of Science Editors:

Ponniah J. A clean slate approach to secure wireless networking. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2014. Available from: http://hdl.handle.net/2142/46565


Université de Lorraine

13. Monot, Aurélien. Vérification des contraintes temporelles de bout-en-bout dans le contexte AutoSar : Verification of end-to-end real-time constraints in the context of AutoSar.

Degree: Docteur es, Informatique, 2012, Université de Lorraine

Les systèmes électroniques embarqués dans les véhicules ont une complexité sans cesse croissante. Cependant, il est crucial d'en maîtriser le comportement temporel afin de garantir… (more)

Subjects/Keywords: Systèmes temps-réel; Électronique embarquée; Autosar; Ordonnancement; Calculateurs multi-coeurs; Réseaux CAN; Offsets; Lissage de charge; Distribution de temps de réponse; Dérive d'horloge; Real-time embedded systems; Autosar; Scheduling; Multicore controllers; CAN network; Offsets; Load balancing; Response time distribution; Clock drift; 004.33; 629.89

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Monot, A. (2012). Vérification des contraintes temporelles de bout-en-bout dans le contexte AutoSar : Verification of end-to-end real-time constraints in the context of AutoSar. (Doctoral Dissertation). Université de Lorraine. Retrieved from http://www.theses.fr/2012LORR0384

Chicago Manual of Style (16th Edition):

Monot, Aurélien. “Vérification des contraintes temporelles de bout-en-bout dans le contexte AutoSar : Verification of end-to-end real-time constraints in the context of AutoSar.” 2012. Doctoral Dissertation, Université de Lorraine. Accessed April 04, 2020. http://www.theses.fr/2012LORR0384.

MLA Handbook (7th Edition):

Monot, Aurélien. “Vérification des contraintes temporelles de bout-en-bout dans le contexte AutoSar : Verification of end-to-end real-time constraints in the context of AutoSar.” 2012. Web. 04 Apr 2020.

Vancouver:

Monot A. Vérification des contraintes temporelles de bout-en-bout dans le contexte AutoSar : Verification of end-to-end real-time constraints in the context of AutoSar. [Internet] [Doctoral dissertation]. Université de Lorraine; 2012. [cited 2020 Apr 04]. Available from: http://www.theses.fr/2012LORR0384.

Council of Science Editors:

Monot A. Vérification des contraintes temporelles de bout-en-bout dans le contexte AutoSar : Verification of end-to-end real-time constraints in the context of AutoSar. [Doctoral Dissertation]. Université de Lorraine; 2012. Available from: http://www.theses.fr/2012LORR0384

14. Κουλουμέντας, Χρήστος. Οπτικά κυκλώματα μη γραμμικών ινών για την υλοποίηση σύνθετων διαδικασιών επεξεργασίας σήματος σε οπτικά δίκτυα επικοινωνιών.

Degree: 2010, National Technical University of Athens (NTUA); Εθνικό Μετσόβιο Πολυτεχνείο (ΕΜΠ)

 The development of all-optical signal processing techniques and circuits has attracted particular interest over the last decades, aiming at the enhancement of optical networks transparency… (more)

Subjects/Keywords: Αμιγώς οπτική επεξεργασία σήματος; Υψηλά μη γραμμική ίνα; Μη γραμμική ίνα οξειδίου του βισμουθίου; Ινα αναίρεσης διασποράς; Διαχείριση διασποράς; Πολυκυματική αναγέννηση; Αναγεννητής Mamyshev; Ανάκτηση ρολογιού; All-optical signal processing; Highly-nonlinear fiber; Bismuth-oxide nonlinear fiber; Dispersion compensating fiber; Dispersion management; Multi-wavelength regeneration; Mamyshev regenerator; Clock recovery

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Κουλουμέντας, . . (2010). Οπτικά κυκλώματα μη γραμμικών ινών για την υλοποίηση σύνθετων διαδικασιών επεξεργασίας σήματος σε οπτικά δίκτυα επικοινωνιών. (Thesis). National Technical University of Athens (NTUA); Εθνικό Μετσόβιο Πολυτεχνείο (ΕΜΠ). Retrieved from http://hdl.handle.net/10442/hedi/24793

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Κουλουμέντας, Χρήστος. “Οπτικά κυκλώματα μη γραμμικών ινών για την υλοποίηση σύνθετων διαδικασιών επεξεργασίας σήματος σε οπτικά δίκτυα επικοινωνιών.” 2010. Thesis, National Technical University of Athens (NTUA); Εθνικό Μετσόβιο Πολυτεχνείο (ΕΜΠ). Accessed April 04, 2020. http://hdl.handle.net/10442/hedi/24793.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Κουλουμέντας, Χρήστος. “Οπτικά κυκλώματα μη γραμμικών ινών για την υλοποίηση σύνθετων διαδικασιών επεξεργασίας σήματος σε οπτικά δίκτυα επικοινωνιών.” 2010. Web. 04 Apr 2020.

Vancouver:

Κουλουμέντας . Οπτικά κυκλώματα μη γραμμικών ινών για την υλοποίηση σύνθετων διαδικασιών επεξεργασίας σήματος σε οπτικά δίκτυα επικοινωνιών. [Internet] [Thesis]. National Technical University of Athens (NTUA); Εθνικό Μετσόβιο Πολυτεχνείο (ΕΜΠ); 2010. [cited 2020 Apr 04]. Available from: http://hdl.handle.net/10442/hedi/24793.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Κουλουμέντας . Οπτικά κυκλώματα μη γραμμικών ινών για την υλοποίηση σύνθετων διαδικασιών επεξεργασίας σήματος σε οπτικά δίκτυα επικοινωνιών. [Thesis]. National Technical University of Athens (NTUA); Εθνικό Μετσόβιο Πολυτεχνείο (ΕΜΠ); 2010. Available from: http://hdl.handle.net/10442/hedi/24793

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

15. Cho, Sunghwan. Cooperative analog and digital (CANDI) time synchronization protocol for large multi-hop networks.

Degree: MS, Electrical and Computer Engineering, 2011, Georgia Tech

 For large multihop networks, the time synchronization (TS) error accumulates as the hop number increases with conventional methods, such as Timing-sync Protocol for Sensor Networks… (more)

Subjects/Keywords: Time synchronization; Sensor networks; Multi-hop; Clock synchronization; WSNs; Frequency; CANDI; CCT; Concurrent cooperative communication; SCSF; Semi-cooperative spectrum fusion; Wireless sensor networks; Microelectromechanical systems

…14 7 Multi-hop distributed concurrent cooperative transmission . . . . . . 16 8 CANDI… …synchronization (TS) protocol for large multi-hop wireless sensor networks (WSNs)… …digital TS packet in orthogonal channels that experience independent multi-path fading. Each… …Multi-hop communication can reduce the cost of such a network by not requiring that every… …sensor be within one hop of the higher-functioning and more expensive sink nodes. Multi-hop… 

Page 1 Page 2 Page 3 Page 4 Page 5 Page 6 Page 7

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cho, S. (2011). Cooperative analog and digital (CANDI) time synchronization protocol for large multi-hop networks. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/42915

Chicago Manual of Style (16th Edition):

Cho, Sunghwan. “Cooperative analog and digital (CANDI) time synchronization protocol for large multi-hop networks.” 2011. Masters Thesis, Georgia Tech. Accessed April 04, 2020. http://hdl.handle.net/1853/42915.

MLA Handbook (7th Edition):

Cho, Sunghwan. “Cooperative analog and digital (CANDI) time synchronization protocol for large multi-hop networks.” 2011. Web. 04 Apr 2020.

Vancouver:

Cho S. Cooperative analog and digital (CANDI) time synchronization protocol for large multi-hop networks. [Internet] [Masters thesis]. Georgia Tech; 2011. [cited 2020 Apr 04]. Available from: http://hdl.handle.net/1853/42915.

Council of Science Editors:

Cho S. Cooperative analog and digital (CANDI) time synchronization protocol for large multi-hop networks. [Masters Thesis]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/42915

16. Huang, Pingli. SHA-less pipeline ADC design with sampling clock skew calibration.

Degree: PhD, 1200, 2012, University of Illinois – Urbana-Champaign

 The power efficiency of pipeline analog-to-digital converters (ADCs) can be substantially improved by eliminating the front-end sample-and-hold amplifier (SHA). However, in a SHA-less architecture the… (more)

Subjects/Keywords: Sample-and-hold amplifier (SHA); SHA-less; pipelined ADC; multi-bit pipeline architecture; sampling clock skew; skew calibration.; analog-to-digital converters (ADCs)

…ranging ADCs resolve a partial word per clock cycle. They break a high resolution conversion… …frequencies. In addition, the sampling clock must meet stringent low jitter requirements. Random… …high input frequencies. 1.3 Motivation In pipeline ADCs, a multi-bit front-end is known to… …noise. In such cases, it is beneficial to choose a multi-bit front-end to enable capacitor… …the downside of the multi-bit architecture is the loss of architectural redundancy as the… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Huang, P. (2012). SHA-less pipeline ADC design with sampling clock skew calibration. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/29565

Chicago Manual of Style (16th Edition):

Huang, Pingli. “SHA-less pipeline ADC design with sampling clock skew calibration.” 2012. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 04, 2020. http://hdl.handle.net/2142/29565.

MLA Handbook (7th Edition):

Huang, Pingli. “SHA-less pipeline ADC design with sampling clock skew calibration.” 2012. Web. 04 Apr 2020.

Vancouver:

Huang P. SHA-less pipeline ADC design with sampling clock skew calibration. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2012. [cited 2020 Apr 04]. Available from: http://hdl.handle.net/2142/29565.

Council of Science Editors:

Huang P. SHA-less pipeline ADC design with sampling clock skew calibration. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2012. Available from: http://hdl.handle.net/2142/29565

.