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You searched for subject:(multi chip module). Showing records 1 – 5 of 5 total matches.

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North Carolina State University

1. Gadfort, Peter. Low Power Interconnect Circuits using Silicon Carriers.

Degree: MS, Electrical Engineering, 2009, North Carolina State University

 Due to the ever-increasing complexity of the tasks that modern electronic devices are expected to carry out, many devices incorporate multiple chips linked via input/output… (more)

Subjects/Keywords: Multi-chip module; Pre-emphasis; Off-chip drivers; Low-power; Silicon carrier

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gadfort, P. (2009). Low Power Interconnect Circuits using Silicon Carriers. (Thesis). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/2517

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gadfort, Peter. “Low Power Interconnect Circuits using Silicon Carriers.” 2009. Thesis, North Carolina State University. Accessed January 26, 2021. http://www.lib.ncsu.edu/resolver/1840.16/2517.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gadfort, Peter. “Low Power Interconnect Circuits using Silicon Carriers.” 2009. Web. 26 Jan 2021.

Vancouver:

Gadfort P. Low Power Interconnect Circuits using Silicon Carriers. [Internet] [Thesis]. North Carolina State University; 2009. [cited 2021 Jan 26]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/2517.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gadfort P. Low Power Interconnect Circuits using Silicon Carriers. [Thesis]. North Carolina State University; 2009. Available from: http://www.lib.ncsu.edu/resolver/1840.16/2517

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Tech

2. Jiang, Li. Electrical and Thermal Characterizations of IGBT Module with Pressure-Free Large-Area Sintered Joints.

Degree: MS, Electrical Engineering, 2013, Virginia Tech

 Silver sintering technology has received considerable attention in recent years because it has the potential to be a suitable interconnection material for high-temperature power electronic… (more)

Subjects/Keywords: chip-attach joints; large-area; IGBT multi-chip module; pressure-free sintering; switching performance; thermal impedance

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APA (6th Edition):

Jiang, L. (2013). Electrical and Thermal Characterizations of IGBT Module with Pressure-Free Large-Area Sintered Joints. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/23903

Chicago Manual of Style (16th Edition):

Jiang, Li. “Electrical and Thermal Characterizations of IGBT Module with Pressure-Free Large-Area Sintered Joints.” 2013. Masters Thesis, Virginia Tech. Accessed January 26, 2021. http://hdl.handle.net/10919/23903.

MLA Handbook (7th Edition):

Jiang, Li. “Electrical and Thermal Characterizations of IGBT Module with Pressure-Free Large-Area Sintered Joints.” 2013. Web. 26 Jan 2021.

Vancouver:

Jiang L. Electrical and Thermal Characterizations of IGBT Module with Pressure-Free Large-Area Sintered Joints. [Internet] [Masters thesis]. Virginia Tech; 2013. [cited 2021 Jan 26]. Available from: http://hdl.handle.net/10919/23903.

Council of Science Editors:

Jiang L. Electrical and Thermal Characterizations of IGBT Module with Pressure-Free Large-Area Sintered Joints. [Masters Thesis]. Virginia Tech; 2013. Available from: http://hdl.handle.net/10919/23903


Virginia Tech

3. Watt, Grace R. Impact of Device Parametric Tolerances on Current Sharing Behavior of a SiC Half-Bridge Power Module.

Degree: MS, Electrical Engineering, 2020, Virginia Tech

 This paper describes the design, construction, and testing of advanced power devices for use in electric vehicles. Power devices are necessary to supply electricity to… (more)

Subjects/Keywords: SiC MOSFET; power module packaging; flexible PCB; current sharing; symmetrical direct bonded copper (DBC) layout; diode-less module; multi-chip module; device parametric tolerances; package parasitics; vertical GaN

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Watt, G. R. (2020). Impact of Device Parametric Tolerances on Current Sharing Behavior of a SiC Half-Bridge Power Module. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/96559

Chicago Manual of Style (16th Edition):

Watt, Grace R. “Impact of Device Parametric Tolerances on Current Sharing Behavior of a SiC Half-Bridge Power Module.” 2020. Masters Thesis, Virginia Tech. Accessed January 26, 2021. http://hdl.handle.net/10919/96559.

MLA Handbook (7th Edition):

Watt, Grace R. “Impact of Device Parametric Tolerances on Current Sharing Behavior of a SiC Half-Bridge Power Module.” 2020. Web. 26 Jan 2021.

Vancouver:

Watt GR. Impact of Device Parametric Tolerances on Current Sharing Behavior of a SiC Half-Bridge Power Module. [Internet] [Masters thesis]. Virginia Tech; 2020. [cited 2021 Jan 26]. Available from: http://hdl.handle.net/10919/96559.

Council of Science Editors:

Watt GR. Impact of Device Parametric Tolerances on Current Sharing Behavior of a SiC Half-Bridge Power Module. [Masters Thesis]. Virginia Tech; 2020. Available from: http://hdl.handle.net/10919/96559


University of Arkansas

4. Gong, Zihao. Thermal and Electrical Parasitic Modeling for Multi-Chip Power Module Layout Synthesis.

Degree: MSEE, 2012, University of Arkansas

  This thesis presents thermal and electrical parasitic modeling approaches for layout synthesis of Multi-Chip Power Modules (MCPMs). MCPMs integrate power semiconductor devices and drive… (more)

Subjects/Keywords: Applied sciences; Electrical parasitics; Multi-chip power module; Thermal modeling; Electrical and Electronics; Power and Energy

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APA (6th Edition):

Gong, Z. (2012). Thermal and Electrical Parasitic Modeling for Multi-Chip Power Module Layout Synthesis. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/635

Chicago Manual of Style (16th Edition):

Gong, Zihao. “Thermal and Electrical Parasitic Modeling for Multi-Chip Power Module Layout Synthesis.” 2012. Masters Thesis, University of Arkansas. Accessed January 26, 2021. https://scholarworks.uark.edu/etd/635.

MLA Handbook (7th Edition):

Gong, Zihao. “Thermal and Electrical Parasitic Modeling for Multi-Chip Power Module Layout Synthesis.” 2012. Web. 26 Jan 2021.

Vancouver:

Gong Z. Thermal and Electrical Parasitic Modeling for Multi-Chip Power Module Layout Synthesis. [Internet] [Masters thesis]. University of Arkansas; 2012. [cited 2021 Jan 26]. Available from: https://scholarworks.uark.edu/etd/635.

Council of Science Editors:

Gong Z. Thermal and Electrical Parasitic Modeling for Multi-Chip Power Module Layout Synthesis. [Masters Thesis]. University of Arkansas; 2012. Available from: https://scholarworks.uark.edu/etd/635


Université de Bordeaux I

5. Jullien, Jean-Baptiste. Etude de fiabilité et définition de modèles théoriques de vieillissement en très haute température pour des systèmes électronique et microélectronique : Creation and validation of a school refusal screening questionnaire in secondary school : the SChool REfusal EvaluatioN (SCREEN).

Degree: Docteur es, Electronique, 2012, Université de Bordeaux I

Ce travail s'intègre dans les domaines de l'analyse et de la prédiction de la fiabilité des assemblages Multi-Chip Module. Il présente l'étude de fiabilité de… (more)

Subjects/Keywords: Multi-Chip Module; Hautes températures; Vieillissements accélérés; Microcâblages filaires; Fiabilité; Simulation par éléments finis; Analyses de défaillances; Joints collés; Multi-Chip Module; High temperature; Accelerated aging; Wire bonding; Reliability; FEM simulations; Failure analysis; Adhesive joints; Reliability

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jullien, J. (2012). Etude de fiabilité et définition de modèles théoriques de vieillissement en très haute température pour des systèmes électronique et microélectronique : Creation and validation of a school refusal screening questionnaire in secondary school : the SChool REfusal EvaluatioN (SCREEN). (Doctoral Dissertation). Université de Bordeaux I. Retrieved from http://www.theses.fr/2012BOR14604

Chicago Manual of Style (16th Edition):

Jullien, Jean-Baptiste. “Etude de fiabilité et définition de modèles théoriques de vieillissement en très haute température pour des systèmes électronique et microélectronique : Creation and validation of a school refusal screening questionnaire in secondary school : the SChool REfusal EvaluatioN (SCREEN).” 2012. Doctoral Dissertation, Université de Bordeaux I. Accessed January 26, 2021. http://www.theses.fr/2012BOR14604.

MLA Handbook (7th Edition):

Jullien, Jean-Baptiste. “Etude de fiabilité et définition de modèles théoriques de vieillissement en très haute température pour des systèmes électronique et microélectronique : Creation and validation of a school refusal screening questionnaire in secondary school : the SChool REfusal EvaluatioN (SCREEN).” 2012. Web. 26 Jan 2021.

Vancouver:

Jullien J. Etude de fiabilité et définition de modèles théoriques de vieillissement en très haute température pour des systèmes électronique et microélectronique : Creation and validation of a school refusal screening questionnaire in secondary school : the SChool REfusal EvaluatioN (SCREEN). [Internet] [Doctoral dissertation]. Université de Bordeaux I; 2012. [cited 2021 Jan 26]. Available from: http://www.theses.fr/2012BOR14604.

Council of Science Editors:

Jullien J. Etude de fiabilité et définition de modèles théoriques de vieillissement en très haute température pour des systèmes électronique et microélectronique : Creation and validation of a school refusal screening questionnaire in secondary school : the SChool REfusal EvaluatioN (SCREEN). [Doctoral Dissertation]. Université de Bordeaux I; 2012. Available from: http://www.theses.fr/2012BOR14604

.