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You searched for subject:(memory hierarchy). Showing records 1 – 30 of 68 total matches.

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University of Edinburgh

1. Huang, Cheng-Chieh. Optimizing cache utilization in modern cache hierarchies.

Degree: PhD, 2016, University of Edinburgh

Memory wall is one of the major performance bottlenecks in modern computer systems. SRAM caches have been used to successfully bridge the performance gap between… (more)

Subjects/Keywords: 004.5; cache; DRAM; memory hierarchy

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APA (6th Edition):

Huang, C. (2016). Optimizing cache utilization in modern cache hierarchies. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/19571

Chicago Manual of Style (16th Edition):

Huang, Cheng-Chieh. “Optimizing cache utilization in modern cache hierarchies.” 2016. Doctoral Dissertation, University of Edinburgh. Accessed November 12, 2019. http://hdl.handle.net/1842/19571.

MLA Handbook (7th Edition):

Huang, Cheng-Chieh. “Optimizing cache utilization in modern cache hierarchies.” 2016. Web. 12 Nov 2019.

Vancouver:

Huang C. Optimizing cache utilization in modern cache hierarchies. [Internet] [Doctoral dissertation]. University of Edinburgh; 2016. [cited 2019 Nov 12]. Available from: http://hdl.handle.net/1842/19571.

Council of Science Editors:

Huang C. Optimizing cache utilization in modern cache hierarchies. [Doctoral Dissertation]. University of Edinburgh; 2016. Available from: http://hdl.handle.net/1842/19571


Penn State University

2. Muralidhara, Sai Prashanth. Reducing Interference in Memory Hierarchy Resources Using Application Aware Management.

Degree: PhD, Computer Science and Engineering, 2011, Penn State University

 Aggressive technology scaling has resulted in an increase in number of cores being integrated on-chip. While on-chip cores are increasing at a fast rate, the… (more)

Subjects/Keywords: Multicores; memory hierarchy; caches; DRAM

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APA (6th Edition):

Muralidhara, S. P. (2011). Reducing Interference in Memory Hierarchy Resources Using Application Aware Management. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/12150

Chicago Manual of Style (16th Edition):

Muralidhara, Sai Prashanth. “Reducing Interference in Memory Hierarchy Resources Using Application Aware Management.” 2011. Doctoral Dissertation, Penn State University. Accessed November 12, 2019. https://etda.libraries.psu.edu/catalog/12150.

MLA Handbook (7th Edition):

Muralidhara, Sai Prashanth. “Reducing Interference in Memory Hierarchy Resources Using Application Aware Management.” 2011. Web. 12 Nov 2019.

Vancouver:

Muralidhara SP. Reducing Interference in Memory Hierarchy Resources Using Application Aware Management. [Internet] [Doctoral dissertation]. Penn State University; 2011. [cited 2019 Nov 12]. Available from: https://etda.libraries.psu.edu/catalog/12150.

Council of Science Editors:

Muralidhara SP. Reducing Interference in Memory Hierarchy Resources Using Application Aware Management. [Doctoral Dissertation]. Penn State University; 2011. Available from: https://etda.libraries.psu.edu/catalog/12150


Princeton University

3. Ham, Tae Jun. Data Access Optimization in Accelerator-Oriented Heterogeneous Architecture through Decoupling and Memory Hierarchy Specialization .

Degree: PhD, 2018, Princeton University

 For the past fifty years, Moore's Law and Dennard Scaling have been playing important roles in both performance and energy efficiency of computer systems. Unfortunately,… (more)

Subjects/Keywords: Accelerators; Decoupled Architecture; Memory Hierarchy

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APA (6th Edition):

Ham, T. J. (2018). Data Access Optimization in Accelerator-Oriented Heterogeneous Architecture through Decoupling and Memory Hierarchy Specialization . (Doctoral Dissertation). Princeton University. Retrieved from http://arks.princeton.edu/ark:/88435/dsp012n49t440b

Chicago Manual of Style (16th Edition):

Ham, Tae Jun. “Data Access Optimization in Accelerator-Oriented Heterogeneous Architecture through Decoupling and Memory Hierarchy Specialization .” 2018. Doctoral Dissertation, Princeton University. Accessed November 12, 2019. http://arks.princeton.edu/ark:/88435/dsp012n49t440b.

MLA Handbook (7th Edition):

Ham, Tae Jun. “Data Access Optimization in Accelerator-Oriented Heterogeneous Architecture through Decoupling and Memory Hierarchy Specialization .” 2018. Web. 12 Nov 2019.

Vancouver:

Ham TJ. Data Access Optimization in Accelerator-Oriented Heterogeneous Architecture through Decoupling and Memory Hierarchy Specialization . [Internet] [Doctoral dissertation]. Princeton University; 2018. [cited 2019 Nov 12]. Available from: http://arks.princeton.edu/ark:/88435/dsp012n49t440b.

Council of Science Editors:

Ham TJ. Data Access Optimization in Accelerator-Oriented Heterogeneous Architecture through Decoupling and Memory Hierarchy Specialization . [Doctoral Dissertation]. Princeton University; 2018. Available from: http://arks.princeton.edu/ark:/88435/dsp012n49t440b

4. Senni, Sophiane. Exploration of non-volatile magnetic memory for processor architecture : Exploration d'architecture de processeur à technologie mémoire non volatile MRAM.

Degree: Docteur es, Systèmes automatiques et micro-électroniques, 2015, Montpellier

De par la réduction continuelle des dimensions du transistor CMOS, concevoir des systèmes sur puce (SoC) à la fois très denses et énergétiquement efficients devient… (more)

Subjects/Keywords: Mram; Processeur embarqué; Memory hierarchy; Mram; Embedded processor; Memory hierarchy

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APA (6th Edition):

Senni, S. (2015). Exploration of non-volatile magnetic memory for processor architecture : Exploration d'architecture de processeur à technologie mémoire non volatile MRAM. (Doctoral Dissertation). Montpellier. Retrieved from http://www.theses.fr/2015MONTS264

Chicago Manual of Style (16th Edition):

Senni, Sophiane. “Exploration of non-volatile magnetic memory for processor architecture : Exploration d'architecture de processeur à technologie mémoire non volatile MRAM.” 2015. Doctoral Dissertation, Montpellier. Accessed November 12, 2019. http://www.theses.fr/2015MONTS264.

MLA Handbook (7th Edition):

Senni, Sophiane. “Exploration of non-volatile magnetic memory for processor architecture : Exploration d'architecture de processeur à technologie mémoire non volatile MRAM.” 2015. Web. 12 Nov 2019.

Vancouver:

Senni S. Exploration of non-volatile magnetic memory for processor architecture : Exploration d'architecture de processeur à technologie mémoire non volatile MRAM. [Internet] [Doctoral dissertation]. Montpellier; 2015. [cited 2019 Nov 12]. Available from: http://www.theses.fr/2015MONTS264.

Council of Science Editors:

Senni S. Exploration of non-volatile magnetic memory for processor architecture : Exploration d'architecture de processeur à technologie mémoire non volatile MRAM. [Doctoral Dissertation]. Montpellier; 2015. Available from: http://www.theses.fr/2015MONTS264


Penn State University

5. Jadidi, Amin. ARCHITECTURAL TECHNIQUES TO ENABLE RELIABLE AND HIGH PERFORMANCE MEMORY HIERARCHY IN CHIP MULTI-PROCESSORS.

Degree: 2018, Penn State University

 Constant technology scaling has enabled modern computing systems to achieve high degrees of thread-level parallelism, making the design of a highly scalable and dense memory(more)

Subjects/Keywords: Memory Hierarchy; Non-volatile Memory Technologies; Hybrid Memory Hierarchy; Reliability; High Performance; Chip Multi-Processors

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APA (6th Edition):

Jadidi, A. (2018). ARCHITECTURAL TECHNIQUES TO ENABLE RELIABLE AND HIGH PERFORMANCE MEMORY HIERARCHY IN CHIP MULTI-PROCESSORS. (Thesis). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/15383axj945

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jadidi, Amin. “ARCHITECTURAL TECHNIQUES TO ENABLE RELIABLE AND HIGH PERFORMANCE MEMORY HIERARCHY IN CHIP MULTI-PROCESSORS.” 2018. Thesis, Penn State University. Accessed November 12, 2019. https://etda.libraries.psu.edu/catalog/15383axj945.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jadidi, Amin. “ARCHITECTURAL TECHNIQUES TO ENABLE RELIABLE AND HIGH PERFORMANCE MEMORY HIERARCHY IN CHIP MULTI-PROCESSORS.” 2018. Web. 12 Nov 2019.

Vancouver:

Jadidi A. ARCHITECTURAL TECHNIQUES TO ENABLE RELIABLE AND HIGH PERFORMANCE MEMORY HIERARCHY IN CHIP MULTI-PROCESSORS. [Internet] [Thesis]. Penn State University; 2018. [cited 2019 Nov 12]. Available from: https://etda.libraries.psu.edu/catalog/15383axj945.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jadidi A. ARCHITECTURAL TECHNIQUES TO ENABLE RELIABLE AND HIGH PERFORMANCE MEMORY HIERARCHY IN CHIP MULTI-PROCESSORS. [Thesis]. Penn State University; 2018. Available from: https://etda.libraries.psu.edu/catalog/15383axj945

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universitat Politècnica de València

6. Candel Margaix, Francisco. Efficient L2 Cache Management to Boost GPGPU Performance .

Degree: 2019, Universitat Politècnica de València

 [ES] En los últimos años, la creciente necesidad de la capacidad de cómputo ha supuesto un reto que ha llevado a la industria a buscar… (more)

Subjects/Keywords: GPU; MEMORY HIERARCHY; L2 CACHE MANAGEMENT

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APA (6th Edition):

Candel Margaix, F. (2019). Efficient L2 Cache Management to Boost GPGPU Performance . (Doctoral Dissertation). Universitat Politècnica de València. Retrieved from http://hdl.handle.net/10251/125477

Chicago Manual of Style (16th Edition):

Candel Margaix, Francisco. “Efficient L2 Cache Management to Boost GPGPU Performance .” 2019. Doctoral Dissertation, Universitat Politècnica de València. Accessed November 12, 2019. http://hdl.handle.net/10251/125477.

MLA Handbook (7th Edition):

Candel Margaix, Francisco. “Efficient L2 Cache Management to Boost GPGPU Performance .” 2019. Web. 12 Nov 2019.

Vancouver:

Candel Margaix F. Efficient L2 Cache Management to Boost GPGPU Performance . [Internet] [Doctoral dissertation]. Universitat Politècnica de València; 2019. [cited 2019 Nov 12]. Available from: http://hdl.handle.net/10251/125477.

Council of Science Editors:

Candel Margaix F. Efficient L2 Cache Management to Boost GPGPU Performance . [Doctoral Dissertation]. Universitat Politècnica de València; 2019. Available from: http://hdl.handle.net/10251/125477


Penn State University

7. Zhao, Jishen. Rethinking the memory hierarchy design with nonvolatile memory technologies.

Degree: PhD, Computer Science and Engineering, 2014, Penn State University

 The memory hierarchy, including processor caches and the main memory, is an important component of various computer systems. The memory hierarchy is becoming a fundamental… (more)

Subjects/Keywords: Memory hierarchy; Nonvolatile memory; Persistence; Memory/storage stack; Energy efficiency; Graphics memory; CMP; GPU

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhao, J. (2014). Rethinking the memory hierarchy design with nonvolatile memory technologies. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/21345

Chicago Manual of Style (16th Edition):

Zhao, Jishen. “Rethinking the memory hierarchy design with nonvolatile memory technologies.” 2014. Doctoral Dissertation, Penn State University. Accessed November 12, 2019. https://etda.libraries.psu.edu/catalog/21345.

MLA Handbook (7th Edition):

Zhao, Jishen. “Rethinking the memory hierarchy design with nonvolatile memory technologies.” 2014. Web. 12 Nov 2019.

Vancouver:

Zhao J. Rethinking the memory hierarchy design with nonvolatile memory technologies. [Internet] [Doctoral dissertation]. Penn State University; 2014. [cited 2019 Nov 12]. Available from: https://etda.libraries.psu.edu/catalog/21345.

Council of Science Editors:

Zhao J. Rethinking the memory hierarchy design with nonvolatile memory technologies. [Doctoral Dissertation]. Penn State University; 2014. Available from: https://etda.libraries.psu.edu/catalog/21345


Universidade do Rio Grande do Sul

8. Bonatto, Alexsandro Cristóvão. Controle adaptativo para acesso à memória compartilhada em sistemas em chip.

Degree: 2014, Universidade do Rio Grande do Sul

Acessos simultâneos gerados por Elementos de Processamento (EP) contidos nos Sistemas em Chip (SoC) para um único canal de memória externa coloca desafios que requerem… (more)

Subjects/Keywords: Microeletrônica; Memory subsystem; Circuitos integrados; Integrated circuits; Memory hierarchy; System-on-chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bonatto, A. C. (2014). Controle adaptativo para acesso à memória compartilhada em sistemas em chip. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/109193

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bonatto, Alexsandro Cristóvão. “Controle adaptativo para acesso à memória compartilhada em sistemas em chip.” 2014. Thesis, Universidade do Rio Grande do Sul. Accessed November 12, 2019. http://hdl.handle.net/10183/109193.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bonatto, Alexsandro Cristóvão. “Controle adaptativo para acesso à memória compartilhada em sistemas em chip.” 2014. Web. 12 Nov 2019.

Vancouver:

Bonatto AC. Controle adaptativo para acesso à memória compartilhada em sistemas em chip. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2014. [cited 2019 Nov 12]. Available from: http://hdl.handle.net/10183/109193.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bonatto AC. Controle adaptativo para acesso à memória compartilhada em sistemas em chip. [Thesis]. Universidade do Rio Grande do Sul; 2014. Available from: http://hdl.handle.net/10183/109193

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Rochester

9. Shriraman, Arrvindh. Architectural techniques for memory oversight in multiprocessors.

Degree: PhD, 2011, University of Rochester

 Computer architects have exploited the transistors afforded by Moore’s law to provide software developers with high performance computing resources. Software has translated this growth in… (more)

Subjects/Keywords: Memory hierarchy; Caches; Cache coherence; Monitoring; Isolation; Protection; Transactional memory; RTM; FlexTM; Sentry

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APA (6th Edition):

Shriraman, A. (2011). Architectural techniques for memory oversight in multiprocessors. (Doctoral Dissertation). University of Rochester. Retrieved from http://hdl.handle.net/1802/14180

Chicago Manual of Style (16th Edition):

Shriraman, Arrvindh. “Architectural techniques for memory oversight in multiprocessors.” 2011. Doctoral Dissertation, University of Rochester. Accessed November 12, 2019. http://hdl.handle.net/1802/14180.

MLA Handbook (7th Edition):

Shriraman, Arrvindh. “Architectural techniques for memory oversight in multiprocessors.” 2011. Web. 12 Nov 2019.

Vancouver:

Shriraman A. Architectural techniques for memory oversight in multiprocessors. [Internet] [Doctoral dissertation]. University of Rochester; 2011. [cited 2019 Nov 12]. Available from: http://hdl.handle.net/1802/14180.

Council of Science Editors:

Shriraman A. Architectural techniques for memory oversight in multiprocessors. [Doctoral Dissertation]. University of Rochester; 2011. Available from: http://hdl.handle.net/1802/14180


Texas A&M University

10. Backes Drault, Luna B. Evaluation of Cache Inclusion Policies in Cache Management.

Degree: MS, Computer Engineering, 2017, Texas A&M University

 Processor speed has been increasing at a higher rate than the speed of memories over the last years. Caches were designed to mitigate this gap… (more)

Subjects/Keywords: cache management; inclusion policy; replacement policy; prefetching; memory hierarchy

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APA (6th Edition):

Backes Drault, L. B. (2017). Evaluation of Cache Inclusion Policies in Cache Management. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/166081

Chicago Manual of Style (16th Edition):

Backes Drault, Luna B. “Evaluation of Cache Inclusion Policies in Cache Management.” 2017. Masters Thesis, Texas A&M University. Accessed November 12, 2019. http://hdl.handle.net/1969.1/166081.

MLA Handbook (7th Edition):

Backes Drault, Luna B. “Evaluation of Cache Inclusion Policies in Cache Management.” 2017. Web. 12 Nov 2019.

Vancouver:

Backes Drault LB. Evaluation of Cache Inclusion Policies in Cache Management. [Internet] [Masters thesis]. Texas A&M University; 2017. [cited 2019 Nov 12]. Available from: http://hdl.handle.net/1969.1/166081.

Council of Science Editors:

Backes Drault LB. Evaluation of Cache Inclusion Policies in Cache Management. [Masters Thesis]. Texas A&M University; 2017. Available from: http://hdl.handle.net/1969.1/166081

11. Lima Pilla, Laércio. Topology-aware load balancing for performance portability over parallel high performance systems : Équilibrage de charge prenant en compte la topologie des plates-formes de calcul parallèle pour la portabilité des performances.

Degree: Docteur es, Mathématiques et Informatique, 2014, Grenoble; Universidade Federal do Rio Grande do Sul (Brésil)

 Cette thèse présente nos travaux de recherche qui ont comme principal objectif d'assurer la portabilité des performances et le passage à l'échelle des applications scientifiques… (more)

Subjects/Keywords: Ordonnancement; Architectures parallèles; Hiérarchie mémoire; Scheduling; Parallel architectures; Memory hierarchy; 004

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lima Pilla, L. (2014). Topology-aware load balancing for performance portability over parallel high performance systems : Équilibrage de charge prenant en compte la topologie des plates-formes de calcul parallèle pour la portabilité des performances. (Doctoral Dissertation). Grenoble; Universidade Federal do Rio Grande do Sul (Brésil). Retrieved from http://www.theses.fr/2014GRENM028

Chicago Manual of Style (16th Edition):

Lima Pilla, Laércio. “Topology-aware load balancing for performance portability over parallel high performance systems : Équilibrage de charge prenant en compte la topologie des plates-formes de calcul parallèle pour la portabilité des performances.” 2014. Doctoral Dissertation, Grenoble; Universidade Federal do Rio Grande do Sul (Brésil). Accessed November 12, 2019. http://www.theses.fr/2014GRENM028.

MLA Handbook (7th Edition):

Lima Pilla, Laércio. “Topology-aware load balancing for performance portability over parallel high performance systems : Équilibrage de charge prenant en compte la topologie des plates-formes de calcul parallèle pour la portabilité des performances.” 2014. Web. 12 Nov 2019.

Vancouver:

Lima Pilla L. Topology-aware load balancing for performance portability over parallel high performance systems : Équilibrage de charge prenant en compte la topologie des plates-formes de calcul parallèle pour la portabilité des performances. [Internet] [Doctoral dissertation]. Grenoble; Universidade Federal do Rio Grande do Sul (Brésil); 2014. [cited 2019 Nov 12]. Available from: http://www.theses.fr/2014GRENM028.

Council of Science Editors:

Lima Pilla L. Topology-aware load balancing for performance portability over parallel high performance systems : Équilibrage de charge prenant en compte la topologie des plates-formes de calcul parallèle pour la portabilité des performances. [Doctoral Dissertation]. Grenoble; Universidade Federal do Rio Grande do Sul (Brésil); 2014. Available from: http://www.theses.fr/2014GRENM028


University of Central Florida

12. Xiang, Ping. Analyzing Instructtion Based Cache Replacement Policies.

Degree: 2010, University of Central Florida

 The increasing speed gap between microprocessors and off-chip DRAM makes last-level caches (LLCs) a critical component for computer performance. Multi core processors aggravate the problem… (more)

Subjects/Keywords: memory hierarchy; cache; replacement policy; Computer Engineering; Engineering

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APA (6th Edition):

Xiang, P. (2010). Analyzing Instructtion Based Cache Replacement Policies. (Masters Thesis). University of Central Florida. Retrieved from https://stars.library.ucf.edu/etd/4441

Chicago Manual of Style (16th Edition):

Xiang, Ping. “Analyzing Instructtion Based Cache Replacement Policies.” 2010. Masters Thesis, University of Central Florida. Accessed November 12, 2019. https://stars.library.ucf.edu/etd/4441.

MLA Handbook (7th Edition):

Xiang, Ping. “Analyzing Instructtion Based Cache Replacement Policies.” 2010. Web. 12 Nov 2019.

Vancouver:

Xiang P. Analyzing Instructtion Based Cache Replacement Policies. [Internet] [Masters thesis]. University of Central Florida; 2010. [cited 2019 Nov 12]. Available from: https://stars.library.ucf.edu/etd/4441.

Council of Science Editors:

Xiang P. Analyzing Instructtion Based Cache Replacement Policies. [Masters Thesis]. University of Central Florida; 2010. Available from: https://stars.library.ucf.edu/etd/4441


Northeastern University

13. Courville, Brad J. Improved simulation of the Nvidia Kepler memory hierarchy through microbenchmarking.

Degree: MS, Department of Electrical and Computer Engineering, 2017, Northeastern University

 General Purpose Graphics Processing Unit (GPGPU)s are frequently used to accelerate the performance of many types of parallel scientific and engineering workloads. The advent of… (more)

Subjects/Keywords: cache structure; graphics processing units; Kepler; memory hierarchy; microbenchmarking; multi2sim

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APA (6th Edition):

Courville, B. J. (2017). Improved simulation of the Nvidia Kepler memory hierarchy through microbenchmarking. (Masters Thesis). Northeastern University. Retrieved from http://hdl.handle.net/2047/D20249908

Chicago Manual of Style (16th Edition):

Courville, Brad J. “Improved simulation of the Nvidia Kepler memory hierarchy through microbenchmarking.” 2017. Masters Thesis, Northeastern University. Accessed November 12, 2019. http://hdl.handle.net/2047/D20249908.

MLA Handbook (7th Edition):

Courville, Brad J. “Improved simulation of the Nvidia Kepler memory hierarchy through microbenchmarking.” 2017. Web. 12 Nov 2019.

Vancouver:

Courville BJ. Improved simulation of the Nvidia Kepler memory hierarchy through microbenchmarking. [Internet] [Masters thesis]. Northeastern University; 2017. [cited 2019 Nov 12]. Available from: http://hdl.handle.net/2047/D20249908.

Council of Science Editors:

Courville BJ. Improved simulation of the Nvidia Kepler memory hierarchy through microbenchmarking. [Masters Thesis]. Northeastern University; 2017. Available from: http://hdl.handle.net/2047/D20249908


University of Illinois – Urbana-Champaign

14. Jain, Prabhat. Refrint: intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies.

Degree: MS, 0112, 2012, University of Illinois – Urbana-Champaign

 As manycores use dynamic energy ever more efficiently, static power consumption becomes a major concern. In particular, in a large manycore running at a low… (more)

Subjects/Keywords: Static random-access memory (SRAM); Embedded dynamic random-access memory (eDRAM); memory hierarchy; computer architecture; leakage; refresh power

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APA (6th Edition):

Jain, P. (2012). Refrint: intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/34585

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jain, Prabhat. “Refrint: intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies.” 2012. Thesis, University of Illinois – Urbana-Champaign. Accessed November 12, 2019. http://hdl.handle.net/2142/34585.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jain, Prabhat. “Refrint: intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies.” 2012. Web. 12 Nov 2019.

Vancouver:

Jain P. Refrint: intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2012. [cited 2019 Nov 12]. Available from: http://hdl.handle.net/2142/34585.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jain P. Refrint: intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies. [Thesis]. University of Illinois – Urbana-Champaign; 2012. Available from: http://hdl.handle.net/2142/34585

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of California – Berkeley

15. Cook, Henry Cook. Productive Design of Extensible On-Chip Memory Hierarchies.

Degree: Electrical Engineering & Computer Sciences, 2016, University of California – Berkeley

 As Moore’s Law slows and process scaling yields only small returns, computer architecture and design are poised to undergo a renaissance. This thesis brings the… (more)

Subjects/Keywords: Computer science; Computer engineering; Agile Development; Cache Coherence; Hardware Design; Memory Hierarchy; RISC-V; TileLink

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APA (6th Edition):

Cook, H. C. (2016). Productive Design of Extensible On-Chip Memory Hierarchies. (Thesis). University of California – Berkeley. Retrieved from http://www.escholarship.org/uc/item/26h8p428

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Cook, Henry Cook. “Productive Design of Extensible On-Chip Memory Hierarchies.” 2016. Thesis, University of California – Berkeley. Accessed November 12, 2019. http://www.escholarship.org/uc/item/26h8p428.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Cook, Henry Cook. “Productive Design of Extensible On-Chip Memory Hierarchies.” 2016. Web. 12 Nov 2019.

Vancouver:

Cook HC. Productive Design of Extensible On-Chip Memory Hierarchies. [Internet] [Thesis]. University of California – Berkeley; 2016. [cited 2019 Nov 12]. Available from: http://www.escholarship.org/uc/item/26h8p428.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Cook HC. Productive Design of Extensible On-Chip Memory Hierarchies. [Thesis]. University of California – Berkeley; 2016. Available from: http://www.escholarship.org/uc/item/26h8p428

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Rochester

16. Balasubramonian, Rajeev. Dynamic Management of Microarchitecture Resources in Future Microprocessors.

Degree: PhD, 2009, University of Rochester

 Improvements in technology have resulted in steadily improving microprocessor performance. However, the shrinking of process technologies and increasing clock speeds introduce new bottlenecks to performance,… (more)

Subjects/Keywords: low-power microarchitectures; data caches; register files; clustered processors; high-performance microprocessors; memory hierarchy bottlenecks

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APA (6th Edition):

Balasubramonian, R. (2009). Dynamic Management of Microarchitecture Resources in Future Microprocessors. (Doctoral Dissertation). University of Rochester. Retrieved from http://hdl.handle.net/1802/821

Chicago Manual of Style (16th Edition):

Balasubramonian, Rajeev. “Dynamic Management of Microarchitecture Resources in Future Microprocessors.” 2009. Doctoral Dissertation, University of Rochester. Accessed November 12, 2019. http://hdl.handle.net/1802/821.

MLA Handbook (7th Edition):

Balasubramonian, Rajeev. “Dynamic Management of Microarchitecture Resources in Future Microprocessors.” 2009. Web. 12 Nov 2019.

Vancouver:

Balasubramonian R. Dynamic Management of Microarchitecture Resources in Future Microprocessors. [Internet] [Doctoral dissertation]. University of Rochester; 2009. [cited 2019 Nov 12]. Available from: http://hdl.handle.net/1802/821.

Council of Science Editors:

Balasubramonian R. Dynamic Management of Microarchitecture Resources in Future Microprocessors. [Doctoral Dissertation]. University of Rochester; 2009. Available from: http://hdl.handle.net/1802/821


Northeastern University

17. Ziabari, Amir Kavyan. Improving the global memory efficiency in GPU-based systems.

Degree: PhD, Department of Electrical and Computer Engineering, 2016, Northeastern University

 Graphics Processing Units (GPUs) have been used in a wide range of high performance computing domains. Unfortunately, computing with GPU devices presents its own challenges,… (more)

Subjects/Keywords: DRAM cache; GPU; memory hierarchy; multiGPU; network on chip; silicon-photonic link technology

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APA (6th Edition):

Ziabari, A. K. (2016). Improving the global memory efficiency in GPU-based systems. (Doctoral Dissertation). Northeastern University. Retrieved from http://hdl.handle.net/2047/D20251225

Chicago Manual of Style (16th Edition):

Ziabari, Amir Kavyan. “Improving the global memory efficiency in GPU-based systems.” 2016. Doctoral Dissertation, Northeastern University. Accessed November 12, 2019. http://hdl.handle.net/2047/D20251225.

MLA Handbook (7th Edition):

Ziabari, Amir Kavyan. “Improving the global memory efficiency in GPU-based systems.” 2016. Web. 12 Nov 2019.

Vancouver:

Ziabari AK. Improving the global memory efficiency in GPU-based systems. [Internet] [Doctoral dissertation]. Northeastern University; 2016. [cited 2019 Nov 12]. Available from: http://hdl.handle.net/2047/D20251225.

Council of Science Editors:

Ziabari AK. Improving the global memory efficiency in GPU-based systems. [Doctoral Dissertation]. Northeastern University; 2016. Available from: http://hdl.handle.net/2047/D20251225

18. WANG JIANXING. ARCHITECTING EMERGING MEMORY TECHNOLOGIES FOR ENERGY-EFFICIENT COMPUTING IN MODERN PROCESSORS.

Degree: 2015, National University of Singapore

Subjects/Keywords: processor architecture; memory hierarchy; cache; emerging memory; GPGPU; energy

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APA (6th Edition):

JIANXING, W. (2015). ARCHITECTING EMERGING MEMORY TECHNOLOGIES FOR ENERGY-EFFICIENT COMPUTING IN MODERN PROCESSORS. (Thesis). National University of Singapore. Retrieved from http://scholarbank.nus.edu.sg/handle/10635/122004

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

JIANXING, WANG. “ARCHITECTING EMERGING MEMORY TECHNOLOGIES FOR ENERGY-EFFICIENT COMPUTING IN MODERN PROCESSORS.” 2015. Thesis, National University of Singapore. Accessed November 12, 2019. http://scholarbank.nus.edu.sg/handle/10635/122004.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

JIANXING, WANG. “ARCHITECTING EMERGING MEMORY TECHNOLOGIES FOR ENERGY-EFFICIENT COMPUTING IN MODERN PROCESSORS.” 2015. Web. 12 Nov 2019.

Vancouver:

JIANXING W. ARCHITECTING EMERGING MEMORY TECHNOLOGIES FOR ENERGY-EFFICIENT COMPUTING IN MODERN PROCESSORS. [Internet] [Thesis]. National University of Singapore; 2015. [cited 2019 Nov 12]. Available from: http://scholarbank.nus.edu.sg/handle/10635/122004.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

JIANXING W. ARCHITECTING EMERGING MEMORY TECHNOLOGIES FOR ENERGY-EFFICIENT COMPUTING IN MODERN PROCESSORS. [Thesis]. National University of Singapore; 2015. Available from: http://scholarbank.nus.edu.sg/handle/10635/122004

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

19. Pottier, Loïc. Co-scheduling for large-scale applications : memory and resilience : Ordonnancement concurrent d’applications à grande échelle : mémoire et résilience.

Degree: Docteur es, Informatique, 2018, Lyon

Cette thèse explore les problèmes liés à l'ordonnancement concurrent dans le contexte des applications massivement parallèle, de deux points de vue: le coté mémoire (en… (more)

Subjects/Keywords: Ordonnancement concurrent; Hiérarchie mémoire; Algorithme d’ordonnancement; Résilience; Informatique haute performance; HPC; Antémémoire; Co-scheduling algorithm; Memory hierarchy; Cache memory; Scheduling; Resilience; High performance computing; HPC; Memory; Many-core

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APA (6th Edition):

Pottier, L. (2018). Co-scheduling for large-scale applications : memory and resilience : Ordonnancement concurrent d’applications à grande échelle : mémoire et résilience. (Doctoral Dissertation). Lyon. Retrieved from http://www.theses.fr/2018LYSEN039

Chicago Manual of Style (16th Edition):

Pottier, Loïc. “Co-scheduling for large-scale applications : memory and resilience : Ordonnancement concurrent d’applications à grande échelle : mémoire et résilience.” 2018. Doctoral Dissertation, Lyon. Accessed November 12, 2019. http://www.theses.fr/2018LYSEN039.

MLA Handbook (7th Edition):

Pottier, Loïc. “Co-scheduling for large-scale applications : memory and resilience : Ordonnancement concurrent d’applications à grande échelle : mémoire et résilience.” 2018. Web. 12 Nov 2019.

Vancouver:

Pottier L. Co-scheduling for large-scale applications : memory and resilience : Ordonnancement concurrent d’applications à grande échelle : mémoire et résilience. [Internet] [Doctoral dissertation]. Lyon; 2018. [cited 2019 Nov 12]. Available from: http://www.theses.fr/2018LYSEN039.

Council of Science Editors:

Pottier L. Co-scheduling for large-scale applications : memory and resilience : Ordonnancement concurrent d’applications à grande échelle : mémoire et résilience. [Doctoral Dissertation]. Lyon; 2018. Available from: http://www.theses.fr/2018LYSEN039


Northeastern University

20. Zhang, Chulian. Inter-warp divergence aware execution on GPUs.

Degree: MS, Department of Electrical and Computer Engineering, 2016, Northeastern University

 GPUs have appeared as very efficient many-core platform to execute applications with massive thread-level parallelism. GPUs achieve high throughput by running many threads concurrently and… (more)

Subjects/Keywords: GPU; instruction cache; inter-warp divergence; warp progression similarity; Cache memory; Memory hierarchy (Computer science); Memory management (Computer science); Graphics processing units; Threads (Computer programs); Computer architecture

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APA (6th Edition):

Zhang, C. (2016). Inter-warp divergence aware execution on GPUs. (Masters Thesis). Northeastern University. Retrieved from http://hdl.handle.net/2047/D20213291

Chicago Manual of Style (16th Edition):

Zhang, Chulian. “Inter-warp divergence aware execution on GPUs.” 2016. Masters Thesis, Northeastern University. Accessed November 12, 2019. http://hdl.handle.net/2047/D20213291.

MLA Handbook (7th Edition):

Zhang, Chulian. “Inter-warp divergence aware execution on GPUs.” 2016. Web. 12 Nov 2019.

Vancouver:

Zhang C. Inter-warp divergence aware execution on GPUs. [Internet] [Masters thesis]. Northeastern University; 2016. [cited 2019 Nov 12]. Available from: http://hdl.handle.net/2047/D20213291.

Council of Science Editors:

Zhang C. Inter-warp divergence aware execution on GPUs. [Masters Thesis]. Northeastern University; 2016. Available from: http://hdl.handle.net/2047/D20213291


University of Cincinnati

21. SOHONI, SOHUM. IMPROVING L2 CACHE PERFORMANCE THROUGH STREAM-DIRECTED OPTIMIZATIONS.

Degree: PhD, Engineering : Computer Science and Engineering, 2004, University of Cincinnati

 Research on caches has traditionally concentrated on the L1 cache. Most of the improvements in the design of L2 caches have been rather simple: increase… (more)

Subjects/Keywords: Computer Science; Prefetching; caching; memory hierarchy; computer architecture

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

SOHONI, S. (2004). IMPROVING L2 CACHE PERFORMANCE THROUGH STREAM-DIRECTED OPTIMIZATIONS. (Doctoral Dissertation). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1092932892

Chicago Manual of Style (16th Edition):

SOHONI, SOHUM. “IMPROVING L2 CACHE PERFORMANCE THROUGH STREAM-DIRECTED OPTIMIZATIONS.” 2004. Doctoral Dissertation, University of Cincinnati. Accessed November 12, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1092932892.

MLA Handbook (7th Edition):

SOHONI, SOHUM. “IMPROVING L2 CACHE PERFORMANCE THROUGH STREAM-DIRECTED OPTIMIZATIONS.” 2004. Web. 12 Nov 2019.

Vancouver:

SOHONI S. IMPROVING L2 CACHE PERFORMANCE THROUGH STREAM-DIRECTED OPTIMIZATIONS. [Internet] [Doctoral dissertation]. University of Cincinnati; 2004. [cited 2019 Nov 12]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1092932892.

Council of Science Editors:

SOHONI S. IMPROVING L2 CACHE PERFORMANCE THROUGH STREAM-DIRECTED OPTIMIZATIONS. [Doctoral Dissertation]. University of Cincinnati; 2004. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1092932892


Penn State University

22. Ozturk, Ozcan. COMPILER DIRECTED MEMORY HIERARCHY.

Degree: PhD, Computer Science and Engineering, 2007, Penn State University

 Two trends, namely, increasing importance of memory subsystems and increasing use of chip multiprocessing, motivate conducting research on memory hierarchy optimization for chip multiprocessors. One… (more)

Subjects/Keywords: memory; compiler; management; chip; multiprocessor; computer; hierarchy; design

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APA (6th Edition):

Ozturk, O. (2007). COMPILER DIRECTED MEMORY HIERARCHY. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/7478

Chicago Manual of Style (16th Edition):

Ozturk, Ozcan. “COMPILER DIRECTED MEMORY HIERARCHY.” 2007. Doctoral Dissertation, Penn State University. Accessed November 12, 2019. https://etda.libraries.psu.edu/catalog/7478.

MLA Handbook (7th Edition):

Ozturk, Ozcan. “COMPILER DIRECTED MEMORY HIERARCHY.” 2007. Web. 12 Nov 2019.

Vancouver:

Ozturk O. COMPILER DIRECTED MEMORY HIERARCHY. [Internet] [Doctoral dissertation]. Penn State University; 2007. [cited 2019 Nov 12]. Available from: https://etda.libraries.psu.edu/catalog/7478.

Council of Science Editors:

Ozturk O. COMPILER DIRECTED MEMORY HIERARCHY. [Doctoral Dissertation]. Penn State University; 2007. Available from: https://etda.libraries.psu.edu/catalog/7478


University of Southern California

23. Chen, Chun. Model-guided empirical optimization for memory hierarchy.

Degree: PhD, Computer Science, 2007, University of Southern California

 We are facing an increasing performance gap between processor and memory speed on today's architectures. To bridge this performance gap, various architectural features, such as… (more)

Subjects/Keywords: compilers; empirical optimization; loop transformation; memory hierarchy; BLAS

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APA (6th Edition):

Chen, C. (2007). Model-guided empirical optimization for memory hierarchy. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/477131/rec/4113

Chicago Manual of Style (16th Edition):

Chen, Chun. “Model-guided empirical optimization for memory hierarchy.” 2007. Doctoral Dissertation, University of Southern California. Accessed November 12, 2019. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/477131/rec/4113.

MLA Handbook (7th Edition):

Chen, Chun. “Model-guided empirical optimization for memory hierarchy.” 2007. Web. 12 Nov 2019.

Vancouver:

Chen C. Model-guided empirical optimization for memory hierarchy. [Internet] [Doctoral dissertation]. University of Southern California; 2007. [cited 2019 Nov 12]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/477131/rec/4113.

Council of Science Editors:

Chen C. Model-guided empirical optimization for memory hierarchy. [Doctoral Dissertation]. University of Southern California; 2007. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/477131/rec/4113


Ryerson University

24. Khorramnejad, Kaveh; Anpalagan, Alagan (Author). Performance analysis of time and cost efficient data pre-fetching in mobile cloud computing.

Degree: 2017, Ryerson University

 Recently, many methods and algorithms have been proposed in pre-fetching area. However, pre-fetching integrated with workload scheduling approaches have not been investigated as much. Initially,… (more)

Subjects/Keywords: Information storage and retrieval systems  – Design.; Cloud computing.; Mobile computing.; Memory hierarchy (Computer science); Computer scheduling.

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APA (6th Edition):

Khorramnejad, Kaveh; Anpalagan, A. (. (2017). Performance analysis of time and cost efficient data pre-fetching in mobile cloud computing. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A6886

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Khorramnejad, Kaveh; Anpalagan, Alagan (Author). “Performance analysis of time and cost efficient data pre-fetching in mobile cloud computing.” 2017. Thesis, Ryerson University. Accessed November 12, 2019. https://digital.library.ryerson.ca/islandora/object/RULA%3A6886.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Khorramnejad, Kaveh; Anpalagan, Alagan (Author). “Performance analysis of time and cost efficient data pre-fetching in mobile cloud computing.” 2017. Web. 12 Nov 2019.

Vancouver:

Khorramnejad, Kaveh; Anpalagan A(. Performance analysis of time and cost efficient data pre-fetching in mobile cloud computing. [Internet] [Thesis]. Ryerson University; 2017. [cited 2019 Nov 12]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6886.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Khorramnejad, Kaveh; Anpalagan A(. Performance analysis of time and cost efficient data pre-fetching in mobile cloud computing. [Thesis]. Ryerson University; 2017. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6886

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universitat Politècnica de Catalunya

25. Jiménez Castells, Marta. Multilevel tiling for non-rectangular interation spaces.

Degree: Departament d'Arquitectura de Computadors, 1999, Universitat Politècnica de Catalunya

 The main motivation of this thesis is to develop new compilation techniques that address the lack of performance of complex numerical codes consisting of loop… (more)

Subjects/Keywords: register tiling; memory hierarchy; compiler optimization; multilevel tiling

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APA (6th Edition):

Jiménez Castells, M. (1999). Multilevel tiling for non-rectangular interation spaces. (Thesis). Universitat Politècnica de Catalunya. Retrieved from http://hdl.handle.net/10803/6007

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jiménez Castells, Marta. “Multilevel tiling for non-rectangular interation spaces.” 1999. Thesis, Universitat Politècnica de Catalunya. Accessed November 12, 2019. http://hdl.handle.net/10803/6007.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jiménez Castells, Marta. “Multilevel tiling for non-rectangular interation spaces.” 1999. Web. 12 Nov 2019.

Vancouver:

Jiménez Castells M. Multilevel tiling for non-rectangular interation spaces. [Internet] [Thesis]. Universitat Politècnica de Catalunya; 1999. [cited 2019 Nov 12]. Available from: http://hdl.handle.net/10803/6007.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jiménez Castells M. Multilevel tiling for non-rectangular interation spaces. [Thesis]. Universitat Politècnica de Catalunya; 1999. Available from: http://hdl.handle.net/10803/6007

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Arkansas

26. Cartwright, Eugene Anthony, III. Extending the HybridThread SMP Model for Distributed Memory Systems.

Degree: MSCmpE, 2012, University of Arkansas

Memory Hierarchy is of growing importance in system design today. As Moore's Law allows system designers to include more processors within their designs, data… (more)

Subjects/Keywords: Applied sciences; FPGA; Memory hierarchy; Multiprocessor; Reconfigurable computing; Digital Communications and Networking; Graphics and Human Computer Interfaces

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APA (6th Edition):

Cartwright, Eugene Anthony, I. (2012). Extending the HybridThread SMP Model for Distributed Memory Systems. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/400

Chicago Manual of Style (16th Edition):

Cartwright, Eugene Anthony, III. “Extending the HybridThread SMP Model for Distributed Memory Systems.” 2012. Masters Thesis, University of Arkansas. Accessed November 12, 2019. https://scholarworks.uark.edu/etd/400.

MLA Handbook (7th Edition):

Cartwright, Eugene Anthony, III. “Extending the HybridThread SMP Model for Distributed Memory Systems.” 2012. Web. 12 Nov 2019.

Vancouver:

Cartwright, Eugene Anthony I. Extending the HybridThread SMP Model for Distributed Memory Systems. [Internet] [Masters thesis]. University of Arkansas; 2012. [cited 2019 Nov 12]. Available from: https://scholarworks.uark.edu/etd/400.

Council of Science Editors:

Cartwright, Eugene Anthony I. Extending the HybridThread SMP Model for Distributed Memory Systems. [Masters Thesis]. University of Arkansas; 2012. Available from: https://scholarworks.uark.edu/etd/400

27. Kerfonta, Andrew. A novel memory-based pattern recognition system.

Degree: 2013, Western Carolina University

 This thesis proposes a novel method for learning and pattern recognition. The algorithm presented relies entirely on memory arranged in a custom hierarchical data structure… (more)

Subjects/Keywords: Pattern recognition systems; Memory hierarchy (Computer science)

…ABSTRACT A NOVEL MEMORY-BASED PATTERN RECOGNITION SYSTEM Andrew Kerfonta, M.S.T. Western… …method for learning and pattern recognition. The algorithm presented relies entirely on memory… …memory. The structure and functionality draw on biology and neuroscience for inspiration while… …not losing sight of the inherent strengths and limitations of modern computers. A hierarchy… …complicated math or statistics. Recognition and prediction are inherent to the hierarchy and require… 

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APA (6th Edition):

Kerfonta, A. (2013). A novel memory-based pattern recognition system. (Masters Thesis). Western Carolina University. Retrieved from http://libres.uncg.edu/ir/listing.aspx?styp=ti&id=16543

Chicago Manual of Style (16th Edition):

Kerfonta, Andrew. “A novel memory-based pattern recognition system.” 2013. Masters Thesis, Western Carolina University. Accessed November 12, 2019. http://libres.uncg.edu/ir/listing.aspx?styp=ti&id=16543.

MLA Handbook (7th Edition):

Kerfonta, Andrew. “A novel memory-based pattern recognition system.” 2013. Web. 12 Nov 2019.

Vancouver:

Kerfonta A. A novel memory-based pattern recognition system. [Internet] [Masters thesis]. Western Carolina University; 2013. [cited 2019 Nov 12]. Available from: http://libres.uncg.edu/ir/listing.aspx?styp=ti&id=16543.

Council of Science Editors:

Kerfonta A. A novel memory-based pattern recognition system. [Masters Thesis]. Western Carolina University; 2013. Available from: http://libres.uncg.edu/ir/listing.aspx?styp=ti&id=16543

28. VIGNESH SURESH. FABRICATION AND PATTERNING OF METAL AND METAL OXIDE NANOSTRUCTURES FOR ELECTRONIC APPLICATIONS.

Degree: 2013, National University of Singapore

Subjects/Keywords: Nanopatterning; ZnO; Hierarchy; Lithography; Self Assembly; Flash Memory

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APA (6th Edition):

SURESH, V. (2013). FABRICATION AND PATTERNING OF METAL AND METAL OXIDE NANOSTRUCTURES FOR ELECTRONIC APPLICATIONS. (Thesis). National University of Singapore. Retrieved from http://scholarbank.nus.edu.sg/handle/10635/48866

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

SURESH, VIGNESH. “FABRICATION AND PATTERNING OF METAL AND METAL OXIDE NANOSTRUCTURES FOR ELECTRONIC APPLICATIONS.” 2013. Thesis, National University of Singapore. Accessed November 12, 2019. http://scholarbank.nus.edu.sg/handle/10635/48866.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

SURESH, VIGNESH. “FABRICATION AND PATTERNING OF METAL AND METAL OXIDE NANOSTRUCTURES FOR ELECTRONIC APPLICATIONS.” 2013. Web. 12 Nov 2019.

Vancouver:

SURESH V. FABRICATION AND PATTERNING OF METAL AND METAL OXIDE NANOSTRUCTURES FOR ELECTRONIC APPLICATIONS. [Internet] [Thesis]. National University of Singapore; 2013. [cited 2019 Nov 12]. Available from: http://scholarbank.nus.edu.sg/handle/10635/48866.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

SURESH V. FABRICATION AND PATTERNING OF METAL AND METAL OXIDE NANOSTRUCTURES FOR ELECTRONIC APPLICATIONS. [Thesis]. National University of Singapore; 2013. Available from: http://scholarbank.nus.edu.sg/handle/10635/48866

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Université Montpellier II

29. Cargnini, Luís Vitório. Applications des technologies mémoires MRAM appliquées aux processeurs embarqués : MRAM applied to Embedded Processors Architecture and Memory Hierarchy.

Degree: Docteur es, SYAM - Systèmes Automatiques et Microélectroniques, 2013, Université Montpellier II

 Le secteur Semi-conducteurs avec l'avènement de fabrication submicroniques coule dessous de 45 nm ont commencé à relever de nouveaux défis pour continuer à évoluer en… (more)

Subjects/Keywords: Architecture de Processeur; Mram; Vlsi; Hiérarchie Mémoire; Semiconductors; Systèmes sur Puce; Processor Architecture; Mram; Vlsi; Memory Hierarchy; Semiconductors; System on Chip

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APA (6th Edition):

Cargnini, L. V. (2013). Applications des technologies mémoires MRAM appliquées aux processeurs embarqués : MRAM applied to Embedded Processors Architecture and Memory Hierarchy. (Doctoral Dissertation). Université Montpellier II. Retrieved from http://www.theses.fr/2013MON20091

Chicago Manual of Style (16th Edition):

Cargnini, Luís Vitório. “Applications des technologies mémoires MRAM appliquées aux processeurs embarqués : MRAM applied to Embedded Processors Architecture and Memory Hierarchy.” 2013. Doctoral Dissertation, Université Montpellier II. Accessed November 12, 2019. http://www.theses.fr/2013MON20091.

MLA Handbook (7th Edition):

Cargnini, Luís Vitório. “Applications des technologies mémoires MRAM appliquées aux processeurs embarqués : MRAM applied to Embedded Processors Architecture and Memory Hierarchy.” 2013. Web. 12 Nov 2019.

Vancouver:

Cargnini LV. Applications des technologies mémoires MRAM appliquées aux processeurs embarqués : MRAM applied to Embedded Processors Architecture and Memory Hierarchy. [Internet] [Doctoral dissertation]. Université Montpellier II; 2013. [cited 2019 Nov 12]. Available from: http://www.theses.fr/2013MON20091.

Council of Science Editors:

Cargnini LV. Applications des technologies mémoires MRAM appliquées aux processeurs embarqués : MRAM applied to Embedded Processors Architecture and Memory Hierarchy. [Doctoral Dissertation]. Université Montpellier II; 2013. Available from: http://www.theses.fr/2013MON20091

30. Péneau, Pierre-Yves. Intégration de technologies de mémoires non volatiles émergentes dans la hiérarchie de caches pour améliorer l'efficacité énergétique : Integration of emerging non volatile memory technologies in cache hierarchy for improving energy-efficiency.

Degree: Docteur es, Systèmes automatiques et micro-électroniques, 2018, Montpellier

De nos jours, des efforts majeurs pour la conception de systèmes sur puces performants et efficaces énergétiquement sont en cours. Le déclin de la loi… (more)

Subjects/Keywords: Efficacité énergétique; Stt-Mram; Hiérarchie mémoire; Caches; Llc; Energy-Efficiency; Stt-Mram; Memory hierarchy; Caches; Llc

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Péneau, P. (2018). Intégration de technologies de mémoires non volatiles émergentes dans la hiérarchie de caches pour améliorer l'efficacité énergétique : Integration of emerging non volatile memory technologies in cache hierarchy for improving energy-efficiency. (Doctoral Dissertation). Montpellier. Retrieved from http://www.theses.fr/2018MONTS108

Chicago Manual of Style (16th Edition):

Péneau, Pierre-Yves. “Intégration de technologies de mémoires non volatiles émergentes dans la hiérarchie de caches pour améliorer l'efficacité énergétique : Integration of emerging non volatile memory technologies in cache hierarchy for improving energy-efficiency.” 2018. Doctoral Dissertation, Montpellier. Accessed November 12, 2019. http://www.theses.fr/2018MONTS108.

MLA Handbook (7th Edition):

Péneau, Pierre-Yves. “Intégration de technologies de mémoires non volatiles émergentes dans la hiérarchie de caches pour améliorer l'efficacité énergétique : Integration of emerging non volatile memory technologies in cache hierarchy for improving energy-efficiency.” 2018. Web. 12 Nov 2019.

Vancouver:

Péneau P. Intégration de technologies de mémoires non volatiles émergentes dans la hiérarchie de caches pour améliorer l'efficacité énergétique : Integration of emerging non volatile memory technologies in cache hierarchy for improving energy-efficiency. [Internet] [Doctoral dissertation]. Montpellier; 2018. [cited 2019 Nov 12]. Available from: http://www.theses.fr/2018MONTS108.

Council of Science Editors:

Péneau P. Intégration de technologies de mémoires non volatiles émergentes dans la hiérarchie de caches pour améliorer l'efficacité énergétique : Integration of emerging non volatile memory technologies in cache hierarchy for improving energy-efficiency. [Doctoral Dissertation]. Montpellier; 2018. Available from: http://www.theses.fr/2018MONTS108

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