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You searched for subject:(memory allocation). Showing records 1 – 30 of 43 total matches.

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University of Waterloo

1. Prakash, Aayush. An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture.

Degree: 2012, University of Waterloo

 This work presents a static instruction allocation scheme for the precision timed architecture’s (PRET) scratchpad memory. Since PRET provides timing instructions to control the temporal… (more)

Subjects/Keywords: memory allocation; precision timed architecture; scratchpad memory

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Prakash, A. (2012). An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/7159

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Prakash, Aayush. “An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture.” 2012. Thesis, University of Waterloo. Accessed January 18, 2020. http://hdl.handle.net/10012/7159.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Prakash, Aayush. “An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture.” 2012. Web. 18 Jan 2020.

Vancouver:

Prakash A. An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture. [Internet] [Thesis]. University of Waterloo; 2012. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/10012/7159.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Prakash A. An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture. [Thesis]. University of Waterloo; 2012. Available from: http://hdl.handle.net/10012/7159

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Toronto

2. Jacob, Alexander Douglas. Coallocation of Appetitive and Aversive Memories in the Lateral Amygdala.

Degree: 2016, University of Toronto

The amygdala plays a key role in representing memories for both fear and reward. However, it is currently not understood how neurons in this structure… (more)

Subjects/Keywords: Amygdala; Memory; Memory allocation; Valence; 0621

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APA (6th Edition):

Jacob, A. D. (2016). Coallocation of Appetitive and Aversive Memories in the Lateral Amygdala. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/79743

Chicago Manual of Style (16th Edition):

Jacob, Alexander Douglas. “Coallocation of Appetitive and Aversive Memories in the Lateral Amygdala.” 2016. Masters Thesis, University of Toronto. Accessed January 18, 2020. http://hdl.handle.net/1807/79743.

MLA Handbook (7th Edition):

Jacob, Alexander Douglas. “Coallocation of Appetitive and Aversive Memories in the Lateral Amygdala.” 2016. Web. 18 Jan 2020.

Vancouver:

Jacob AD. Coallocation of Appetitive and Aversive Memories in the Lateral Amygdala. [Internet] [Masters thesis]. University of Toronto; 2016. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/1807/79743.

Council of Science Editors:

Jacob AD. Coallocation of Appetitive and Aversive Memories in the Lateral Amygdala. [Masters Thesis]. University of Toronto; 2016. Available from: http://hdl.handle.net/1807/79743


University of North Texas

3. Janjusic, Tomislav. Framework for Evaluating Dynamic Memory Allocators Including a New Equivalence Class Based Cache-conscious Allocator.

Degree: 2013, University of North Texas

 Software applications’ performance is hindered by a variety of factors, but most notably by the well-known CPU-memory speed gap (often known as the memory wall).… (more)

Subjects/Keywords: Binary instrumentation; application profiling; memory allocation

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APA (6th Edition):

Janjusic, T. (2013). Framework for Evaluating Dynamic Memory Allocators Including a New Equivalence Class Based Cache-conscious Allocator. (Thesis). University of North Texas. Retrieved from https://digital.library.unt.edu/ark:/67531/metadc500151/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Janjusic, Tomislav. “Framework for Evaluating Dynamic Memory Allocators Including a New Equivalence Class Based Cache-conscious Allocator.” 2013. Thesis, University of North Texas. Accessed January 18, 2020. https://digital.library.unt.edu/ark:/67531/metadc500151/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Janjusic, Tomislav. “Framework for Evaluating Dynamic Memory Allocators Including a New Equivalence Class Based Cache-conscious Allocator.” 2013. Web. 18 Jan 2020.

Vancouver:

Janjusic T. Framework for Evaluating Dynamic Memory Allocators Including a New Equivalence Class Based Cache-conscious Allocator. [Internet] [Thesis]. University of North Texas; 2013. [cited 2020 Jan 18]. Available from: https://digital.library.unt.edu/ark:/67531/metadc500151/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Janjusic T. Framework for Evaluating Dynamic Memory Allocators Including a New Equivalence Class Based Cache-conscious Allocator. [Thesis]. University of North Texas; 2013. Available from: https://digital.library.unt.edu/ark:/67531/metadc500151/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

4. Bhandari, Kumud. General-purpose Programming Techniques for Emerging Systems with Non-volatile Byte-addressable Random Access Memory.

Degree: PhD, Engineering, 2018, Rice University

 Emerging byte-addressable non-volatile random access memory (NVRAM) technologies allow persistent data to be accessed and manipulated using CPU load and store instructions. The persistent data… (more)

Subjects/Keywords: NVRAM; persistence; programming; memory allocation; garbage collection

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APA (6th Edition):

Bhandari, K. (2018). General-purpose Programming Techniques for Emerging Systems with Non-volatile Byte-addressable Random Access Memory. (Doctoral Dissertation). Rice University. Retrieved from http://hdl.handle.net/1911/105656

Chicago Manual of Style (16th Edition):

Bhandari, Kumud. “General-purpose Programming Techniques for Emerging Systems with Non-volatile Byte-addressable Random Access Memory.” 2018. Doctoral Dissertation, Rice University. Accessed January 18, 2020. http://hdl.handle.net/1911/105656.

MLA Handbook (7th Edition):

Bhandari, Kumud. “General-purpose Programming Techniques for Emerging Systems with Non-volatile Byte-addressable Random Access Memory.” 2018. Web. 18 Jan 2020.

Vancouver:

Bhandari K. General-purpose Programming Techniques for Emerging Systems with Non-volatile Byte-addressable Random Access Memory. [Internet] [Doctoral dissertation]. Rice University; 2018. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/1911/105656.

Council of Science Editors:

Bhandari K. General-purpose Programming Techniques for Emerging Systems with Non-volatile Byte-addressable Random Access Memory. [Doctoral Dissertation]. Rice University; 2018. Available from: http://hdl.handle.net/1911/105656


NSYSU

5. Wu, Cheng-Ying. A Stack-Optimized Scratchpad Memory Allocator for Reducing Either the Average-Case or the Worst-Case Execution Time.

Degree: Master, Computer Science and Engineering, 2009, NSYSU

 Scratchpad memory (SPM) is popular for real-time embedded systems. Whereas caches use a memory management unit (MMU) to control which data accesses go to the… (more)

Subjects/Keywords: memory allocation; WCET; ACET; scratchpad memory; real-time systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu, C. (2009). A Stack-Optimized Scratchpad Memory Allocator for Reducing Either the Average-Case or the Worst-Case Execution Time. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0810109-230024

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Cheng-Ying. “A Stack-Optimized Scratchpad Memory Allocator for Reducing Either the Average-Case or the Worst-Case Execution Time.” 2009. Thesis, NSYSU. Accessed January 18, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0810109-230024.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Cheng-Ying. “A Stack-Optimized Scratchpad Memory Allocator for Reducing Either the Average-Case or the Worst-Case Execution Time.” 2009. Web. 18 Jan 2020.

Vancouver:

Wu C. A Stack-Optimized Scratchpad Memory Allocator for Reducing Either the Average-Case or the Worst-Case Execution Time. [Internet] [Thesis]. NSYSU; 2009. [cited 2020 Jan 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0810109-230024.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu C. A Stack-Optimized Scratchpad Memory Allocator for Reducing Either the Average-Case or the Worst-Case Execution Time. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0810109-230024

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

6. Fang, Hsin-Jan. Efficient Memory Allocation for User and Library Variables in Recursive Programs with WCET/ACET Tunable Performance.

Degree: Master, Computer Science and Engineering, 2012, NSYSU

 Scratchpad Memory (SPM) is an alternative to cache. With SPM, the CPUâs fast internal memory (ie, the SRAM) is directly mapped into the memory address… (more)

Subjects/Keywords: memory modeling; memory allocation; library variables; WCET; SPM

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APA (6th Edition):

Fang, H. (2012). Efficient Memory Allocation for User and Library Variables in Recursive Programs with WCET/ACET Tunable Performance. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0209112-190129

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fang, Hsin-Jan. “Efficient Memory Allocation for User and Library Variables in Recursive Programs with WCET/ACET Tunable Performance.” 2012. Thesis, NSYSU. Accessed January 18, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0209112-190129.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fang, Hsin-Jan. “Efficient Memory Allocation for User and Library Variables in Recursive Programs with WCET/ACET Tunable Performance.” 2012. Web. 18 Jan 2020.

Vancouver:

Fang H. Efficient Memory Allocation for User and Library Variables in Recursive Programs with WCET/ACET Tunable Performance. [Internet] [Thesis]. NSYSU; 2012. [cited 2020 Jan 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0209112-190129.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fang H. Efficient Memory Allocation for User and Library Variables in Recursive Programs with WCET/ACET Tunable Performance. [Thesis]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0209112-190129

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

7. De Klerk, J. Cache Balancer: A communication latency and utilization aware resource manager:.

Degree: 2014, Delft University of Technology

 The increasing number of processors in today's many-core architectures has lead to new issues regarding memory management. The performance of many-core processors is often limited… (more)

Subjects/Keywords: many-core processor; memory allocation; memory access latency

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APA (6th Edition):

De Klerk, J. (2014). Cache Balancer: A communication latency and utilization aware resource manager:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:e0fe8916-1196-45bf-bc84-4316e9c97982

Chicago Manual of Style (16th Edition):

De Klerk, J. “Cache Balancer: A communication latency and utilization aware resource manager:.” 2014. Masters Thesis, Delft University of Technology. Accessed January 18, 2020. http://resolver.tudelft.nl/uuid:e0fe8916-1196-45bf-bc84-4316e9c97982.

MLA Handbook (7th Edition):

De Klerk, J. “Cache Balancer: A communication latency and utilization aware resource manager:.” 2014. Web. 18 Jan 2020.

Vancouver:

De Klerk J. Cache Balancer: A communication latency and utilization aware resource manager:. [Internet] [Masters thesis]. Delft University of Technology; 2014. [cited 2020 Jan 18]. Available from: http://resolver.tudelft.nl/uuid:e0fe8916-1196-45bf-bc84-4316e9c97982.

Council of Science Editors:

De Klerk J. Cache Balancer: A communication latency and utilization aware resource manager:. [Masters Thesis]. Delft University of Technology; 2014. Available from: http://resolver.tudelft.nl/uuid:e0fe8916-1196-45bf-bc84-4316e9c97982

8. Brunie, Hugo. Optimisation des allocations de données pour des applications du Calcul Haute Performance sur une architecture à mémoires hétérogènes : Data Allocation Optimisation for High Performance Computing Application on Heterogeneous Architecture.

Degree: Docteur es, Informatique, 2019, Bordeaux

Le Calcul Haute Performance, regroupant l’ensemble des acteurs responsables de l’amélioration des performances de calcul des applications scientifiques sur supercalculateurs, s’est donné pour objectif d’atteindre… (more)

Subjects/Keywords: Profilage; Allocation de données; Memoires hétérogènes; Optimisation combinatoire; Data allocation; Memory management; Heterogeneous Memory Architecture; Profiling; Combinatorial optimization

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Brunie, H. (2019). Optimisation des allocations de données pour des applications du Calcul Haute Performance sur une architecture à mémoires hétérogènes : Data Allocation Optimisation for High Performance Computing Application on Heterogeneous Architecture. (Doctoral Dissertation). Bordeaux. Retrieved from http://www.theses.fr/2019BORD0014

Chicago Manual of Style (16th Edition):

Brunie, Hugo. “Optimisation des allocations de données pour des applications du Calcul Haute Performance sur une architecture à mémoires hétérogènes : Data Allocation Optimisation for High Performance Computing Application on Heterogeneous Architecture.” 2019. Doctoral Dissertation, Bordeaux. Accessed January 18, 2020. http://www.theses.fr/2019BORD0014.

MLA Handbook (7th Edition):

Brunie, Hugo. “Optimisation des allocations de données pour des applications du Calcul Haute Performance sur une architecture à mémoires hétérogènes : Data Allocation Optimisation for High Performance Computing Application on Heterogeneous Architecture.” 2019. Web. 18 Jan 2020.

Vancouver:

Brunie H. Optimisation des allocations de données pour des applications du Calcul Haute Performance sur une architecture à mémoires hétérogènes : Data Allocation Optimisation for High Performance Computing Application on Heterogeneous Architecture. [Internet] [Doctoral dissertation]. Bordeaux; 2019. [cited 2020 Jan 18]. Available from: http://www.theses.fr/2019BORD0014.

Council of Science Editors:

Brunie H. Optimisation des allocations de données pour des applications du Calcul Haute Performance sur une architecture à mémoires hétérogènes : Data Allocation Optimisation for High Performance Computing Application on Heterogeneous Architecture. [Doctoral Dissertation]. Bordeaux; 2019. Available from: http://www.theses.fr/2019BORD0014


NSYSU

9. tseng, ying-sang. Software Design of A Static Memory Synthesis Method.

Degree: Master, Electrical Engineering, 2004, NSYSU

 Along with process technology advancement, we can integrate more and more on-chip memory in an SOC. Memory intensive applications, such as image processing and digital… (more)

Subjects/Keywords: memory synthesis; memory allocation and assignment

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APA (6th Edition):

tseng, y. (2004). Software Design of A Static Memory Synthesis Method. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715104-151221

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

tseng, ying-sang. “Software Design of A Static Memory Synthesis Method.” 2004. Thesis, NSYSU. Accessed January 18, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715104-151221.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

tseng, ying-sang. “Software Design of A Static Memory Synthesis Method.” 2004. Web. 18 Jan 2020.

Vancouver:

tseng y. Software Design of A Static Memory Synthesis Method. [Internet] [Thesis]. NSYSU; 2004. [cited 2020 Jan 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715104-151221.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

tseng y. Software Design of A Static Memory Synthesis Method. [Thesis]. NSYSU; 2004. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0715104-151221

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Exeter

10. Nguyen, Anh Thi Hoang. Long memory conditional volatility and dynamic asset allocation.

Degree: PhD, 2011, University of Exeter

 The thesis evaluates the benefit of allowing for long memory volatility dynamics in forecasts of the variance-covariance matrix for asset allocation. First, I compare the… (more)

Subjects/Keywords: 332; Conditional volatility : Long memory : Asset allocation : Factor structure

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APA (6th Edition):

Nguyen, A. T. H. (2011). Long memory conditional volatility and dynamic asset allocation. (Doctoral Dissertation). University of Exeter. Retrieved from http://hdl.handle.net/10036/3279

Chicago Manual of Style (16th Edition):

Nguyen, Anh Thi Hoang. “Long memory conditional volatility and dynamic asset allocation.” 2011. Doctoral Dissertation, University of Exeter. Accessed January 18, 2020. http://hdl.handle.net/10036/3279.

MLA Handbook (7th Edition):

Nguyen, Anh Thi Hoang. “Long memory conditional volatility and dynamic asset allocation.” 2011. Web. 18 Jan 2020.

Vancouver:

Nguyen ATH. Long memory conditional volatility and dynamic asset allocation. [Internet] [Doctoral dissertation]. University of Exeter; 2011. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/10036/3279.

Council of Science Editors:

Nguyen ATH. Long memory conditional volatility and dynamic asset allocation. [Doctoral Dissertation]. University of Exeter; 2011. Available from: http://hdl.handle.net/10036/3279


University of Illinois – Urbana-Champaign

11. Huang, Xiaohuang. Xmalloc: a scalable lock-free dynamic memory allocator for many-core machines.

Degree: MS, 0112, 2010, University of Illinois – Urbana-Champaign

 There are two venues for many-core machines to gain higher performance: increasing the number of processors and number of vector units in one SIMD processor.… (more)

Subjects/Keywords: General-purpose computing on graphics processing units (GPGPU); Memory Allocation

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APA (6th Edition):

Huang, X. (2010). Xmalloc: a scalable lock-free dynamic memory allocator for many-core machines. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/16137

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Xiaohuang. “Xmalloc: a scalable lock-free dynamic memory allocator for many-core machines.” 2010. Thesis, University of Illinois – Urbana-Champaign. Accessed January 18, 2020. http://hdl.handle.net/2142/16137.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Xiaohuang. “Xmalloc: a scalable lock-free dynamic memory allocator for many-core machines.” 2010. Web. 18 Jan 2020.

Vancouver:

Huang X. Xmalloc: a scalable lock-free dynamic memory allocator for many-core machines. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2010. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/2142/16137.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang X. Xmalloc: a scalable lock-free dynamic memory allocator for many-core machines. [Thesis]. University of Illinois – Urbana-Champaign; 2010. Available from: http://hdl.handle.net/2142/16137

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


UCLA

12. Rogerson, Thomas William Arundel. Insights into the Mechanism of Memory Allocation Through the Trapping and Activating of Emotional Memories.

Degree: Neurobiology, 2013, UCLA

 While the molecular and cellular mechanisms underlying the acquisition, consolidation, reconsolidation and retrieval of memory have attracted a considerable amount of attention in neuroscience, very… (more)

Subjects/Keywords: Neurosciences; Auditory-fear conditioning; CREB; Memory Allocation; Optogenetics

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APA (6th Edition):

Rogerson, T. W. A. (2013). Insights into the Mechanism of Memory Allocation Through the Trapping and Activating of Emotional Memories. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/97r969tc

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Rogerson, Thomas William Arundel. “Insights into the Mechanism of Memory Allocation Through the Trapping and Activating of Emotional Memories.” 2013. Thesis, UCLA. Accessed January 18, 2020. http://www.escholarship.org/uc/item/97r969tc.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Rogerson, Thomas William Arundel. “Insights into the Mechanism of Memory Allocation Through the Trapping and Activating of Emotional Memories.” 2013. Web. 18 Jan 2020.

Vancouver:

Rogerson TWA. Insights into the Mechanism of Memory Allocation Through the Trapping and Activating of Emotional Memories. [Internet] [Thesis]. UCLA; 2013. [cited 2020 Jan 18]. Available from: http://www.escholarship.org/uc/item/97r969tc.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Rogerson TWA. Insights into the Mechanism of Memory Allocation Through the Trapping and Activating of Emotional Memories. [Thesis]. UCLA; 2013. Available from: http://www.escholarship.org/uc/item/97r969tc

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Missouri – Columbia

13. Wu, Nan, 1978-. How can they remember it?: the effect of presentation format and information density on mulitmedia message processing.

Degree: 2012, University of Missouri – Columbia

 [ACCESS RESTRICTED TO THE UNIVERSITY OF MISSOURI AT AUTHOR'S REQUEST.] This study explores how presentation format and information density affect resource allocation and memory. A… (more)

Subjects/Keywords: resource allocation; resource memory; secondary task reaction time; multimedia messages

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APA (6th Edition):

Wu, Nan, 1. (2012). How can they remember it?: the effect of presentation format and information density on mulitmedia message processing. (Thesis). University of Missouri – Columbia. Retrieved from http://hdl.handle.net/10355/33255

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Nan, 1978-. “How can they remember it?: the effect of presentation format and information density on mulitmedia message processing.” 2012. Thesis, University of Missouri – Columbia. Accessed January 18, 2020. http://hdl.handle.net/10355/33255.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Nan, 1978-. “How can they remember it?: the effect of presentation format and information density on mulitmedia message processing.” 2012. Web. 18 Jan 2020.

Vancouver:

Wu, Nan 1. How can they remember it?: the effect of presentation format and information density on mulitmedia message processing. [Internet] [Thesis]. University of Missouri – Columbia; 2012. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/10355/33255.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu, Nan 1. How can they remember it?: the effect of presentation format and information density on mulitmedia message processing. [Thesis]. University of Missouri – Columbia; 2012. Available from: http://hdl.handle.net/10355/33255

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

14. Isoard, Alexandre. Extending Polyhedral Techniques towards Parallel Specifications and Approximations : Extension des Techniques Polyedriques vers les Specifications Parallelles et les Approximations.

Degree: Docteur es, Informatique, 2016, Lyon

Les techniques polyédriques permettent d’appliquer des analyses et transformations de code sur des structures multidimensionnelles telles que boucles imbriquées et tableaux. Elles sont en général… (more)

Subjects/Keywords: Modèle polyédrique; Déchargement de noyau de calcul; Tuilage paramétrique; Allocation mémoire; Polyhedral Model; Kernel Offloading; Parametric Tiling; Memory Allocation

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APA (6th Edition):

Isoard, A. (2016). Extending Polyhedral Techniques towards Parallel Specifications and Approximations : Extension des Techniques Polyedriques vers les Specifications Parallelles et les Approximations. (Doctoral Dissertation). Lyon. Retrieved from http://www.theses.fr/2016LYSEN011

Chicago Manual of Style (16th Edition):

Isoard, Alexandre. “Extending Polyhedral Techniques towards Parallel Specifications and Approximations : Extension des Techniques Polyedriques vers les Specifications Parallelles et les Approximations.” 2016. Doctoral Dissertation, Lyon. Accessed January 18, 2020. http://www.theses.fr/2016LYSEN011.

MLA Handbook (7th Edition):

Isoard, Alexandre. “Extending Polyhedral Techniques towards Parallel Specifications and Approximations : Extension des Techniques Polyedriques vers les Specifications Parallelles et les Approximations.” 2016. Web. 18 Jan 2020.

Vancouver:

Isoard A. Extending Polyhedral Techniques towards Parallel Specifications and Approximations : Extension des Techniques Polyedriques vers les Specifications Parallelles et les Approximations. [Internet] [Doctoral dissertation]. Lyon; 2016. [cited 2020 Jan 18]. Available from: http://www.theses.fr/2016LYSEN011.

Council of Science Editors:

Isoard A. Extending Polyhedral Techniques towards Parallel Specifications and Approximations : Extension des Techniques Polyedriques vers les Specifications Parallelles et les Approximations. [Doctoral Dissertation]. Lyon; 2016. Available from: http://www.theses.fr/2016LYSEN011


Indian Institute of Science

15. Panwar, Ashish. A Memory Allocation Framework for Optimizing Power Consumption and Controlling Fragmentation.

Degree: 2015, Indian Institute of Science

 Large physical memory modules are necessary to meet performance demands of today's ap- plications but can be a major bottleneck in terms of power consumption… (more)

Subjects/Keywords: Optimizing Power Consumption; Memory Power Consumption; Memory Modules Controlling Fragmentation; Memory-Hotplug; Linux Memory Manager; Bank-Buddy Allocator; Pool-Buddy; Memory Allocation Framework; Computer Science and Automation

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APA (6th Edition):

Panwar, A. (2015). A Memory Allocation Framework for Optimizing Power Consumption and Controlling Fragmentation. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/2005/3873 ; http://etd.iisc.ernet.in/abstracts/4745/G27274-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Panwar, Ashish. “A Memory Allocation Framework for Optimizing Power Consumption and Controlling Fragmentation.” 2015. Thesis, Indian Institute of Science. Accessed January 18, 2020. http://etd.iisc.ernet.in/2005/3873 ; http://etd.iisc.ernet.in/abstracts/4745/G27274-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Panwar, Ashish. “A Memory Allocation Framework for Optimizing Power Consumption and Controlling Fragmentation.” 2015. Web. 18 Jan 2020.

Vancouver:

Panwar A. A Memory Allocation Framework for Optimizing Power Consumption and Controlling Fragmentation. [Internet] [Thesis]. Indian Institute of Science; 2015. [cited 2020 Jan 18]. Available from: http://etd.iisc.ernet.in/2005/3873 ; http://etd.iisc.ernet.in/abstracts/4745/G27274-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Panwar A. A Memory Allocation Framework for Optimizing Power Consumption and Controlling Fragmentation. [Thesis]. Indian Institute of Science; 2015. Available from: http://etd.iisc.ernet.in/2005/3873 ; http://etd.iisc.ernet.in/abstracts/4745/G27274-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universitat Politècnica de València

16. Serrano Gómez, Mónica. Scheduling Local and Remote Memory in Cluster Computers .

Degree: 2013, Universitat Politècnica de València

 Los cl'usters de computadores representan una soluci'on alternativa a los supercomputadores. En este tipo de sistemas, se suele restringir el espacio de direccionamiento de memoria… (more)

Subjects/Keywords: Cluster computers; Memory allocation; Interleaved memory; Memory management; Workload characterization; Memory scheduling; Remote memory assignment; Performance estimation; Quality of service; Analysis of performance

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APA (6th Edition):

Serrano Gómez, M. (2013). Scheduling Local and Remote Memory in Cluster Computers . (Doctoral Dissertation). Universitat Politècnica de València. Retrieved from http://hdl.handle.net/10251/31639

Chicago Manual of Style (16th Edition):

Serrano Gómez, Mónica. “Scheduling Local and Remote Memory in Cluster Computers .” 2013. Doctoral Dissertation, Universitat Politècnica de València. Accessed January 18, 2020. http://hdl.handle.net/10251/31639.

MLA Handbook (7th Edition):

Serrano Gómez, Mónica. “Scheduling Local and Remote Memory in Cluster Computers .” 2013. Web. 18 Jan 2020.

Vancouver:

Serrano Gómez M. Scheduling Local and Remote Memory in Cluster Computers . [Internet] [Doctoral dissertation]. Universitat Politècnica de València; 2013. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/10251/31639.

Council of Science Editors:

Serrano Gómez M. Scheduling Local and Remote Memory in Cluster Computers . [Doctoral Dissertation]. Universitat Politècnica de València; 2013. Available from: http://hdl.handle.net/10251/31639


Université Paris-Sud – Paris XI

17. Diouf, Boubacar. Decoupled approaches to register and software controlled memory allocations : Approches découplées aux problèmes d'allocations de registres et de mémoires locales.

Degree: Docteur es, Informatique, 2011, Université Paris-Sud – Paris XI

Malgré la hiérarchie mémoire utilisée dans les ordinateurs modernes, il convient toujours d'optimiser l'utilisation des registres du processeur et des mémoires locales gérées de manières… (more)

Subjects/Keywords: Compilation; Allocation de registres; Allocation de mémoire; Scratchpad; Coloration de graphes pondérés; Problème de submarine-building; Compilation; Register allocation; Memory allocations; Scratchpad; Weighted graphs coloring; Submarine-building problem

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APA (6th Edition):

Diouf, B. (2011). Decoupled approaches to register and software controlled memory allocations : Approches découplées aux problèmes d'allocations de registres et de mémoires locales. (Doctoral Dissertation). Université Paris-Sud – Paris XI. Retrieved from http://www.theses.fr/2011PA112349

Chicago Manual of Style (16th Edition):

Diouf, Boubacar. “Decoupled approaches to register and software controlled memory allocations : Approches découplées aux problèmes d'allocations de registres et de mémoires locales.” 2011. Doctoral Dissertation, Université Paris-Sud – Paris XI. Accessed January 18, 2020. http://www.theses.fr/2011PA112349.

MLA Handbook (7th Edition):

Diouf, Boubacar. “Decoupled approaches to register and software controlled memory allocations : Approches découplées aux problèmes d'allocations de registres et de mémoires locales.” 2011. Web. 18 Jan 2020.

Vancouver:

Diouf B. Decoupled approaches to register and software controlled memory allocations : Approches découplées aux problèmes d'allocations de registres et de mémoires locales. [Internet] [Doctoral dissertation]. Université Paris-Sud – Paris XI; 2011. [cited 2020 Jan 18]. Available from: http://www.theses.fr/2011PA112349.

Council of Science Editors:

Diouf B. Decoupled approaches to register and software controlled memory allocations : Approches découplées aux problèmes d'allocations de registres et de mémoires locales. [Doctoral Dissertation]. Université Paris-Sud – Paris XI; 2011. Available from: http://www.theses.fr/2011PA112349

18. Simmons, Patrick A. Palloc: parallel dynamic memory allocation.

Degree: MS, 0112, 2011, University of Illinois – Urbana-Champaign

 In this thesis, we describe two related memory allocators, each with novel properties. PALLOC1 contributes a unique strategy based on the traversal of a parallel… (more)

Subjects/Keywords: malloc; memory allocation; palloc; palloc1; palloc2; dynamic memory allocation

Page 1 Page 2 Page 3 Page 4 Page 5 Page 6 Page 7

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APA (6th Edition):

Simmons, P. A. (2011). Palloc: parallel dynamic memory allocation. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/24135

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Simmons, Patrick A. “Palloc: parallel dynamic memory allocation.” 2011. Thesis, University of Illinois – Urbana-Champaign. Accessed January 18, 2020. http://hdl.handle.net/2142/24135.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Simmons, Patrick A. “Palloc: parallel dynamic memory allocation.” 2011. Web. 18 Jan 2020.

Vancouver:

Simmons PA. Palloc: parallel dynamic memory allocation. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2011. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/2142/24135.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Simmons PA. Palloc: parallel dynamic memory allocation. [Thesis]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/24135

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

19. Karthikeyan V. Real time algorithms for efficient dynamic memory allocation preemptive scheduler and searching using openmp;.

Degree: 2015, INFLIBNET

This thesis entitled REAL TIME ALGORITHMS FOR EFFICIENT DYNAMIC MEMORY ALLOCATION PREEMPTIVE SCHEDULER AND SEARCHING USING OPENMP is concerned with Algorithms for Real time systems… (more)

Subjects/Keywords: Dynamic Memory Allocation Scheduler Multicore OpenMP Searching and Sorting RTOS µCOS II

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APA (6th Edition):

V, K. (2015). Real time algorithms for efficient dynamic memory allocation preemptive scheduler and searching using openmp;. (Thesis). INFLIBNET. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/45327

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

V, Karthikeyan. “Real time algorithms for efficient dynamic memory allocation preemptive scheduler and searching using openmp;.” 2015. Thesis, INFLIBNET. Accessed January 18, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/45327.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

V, Karthikeyan. “Real time algorithms for efficient dynamic memory allocation preemptive scheduler and searching using openmp;.” 2015. Web. 18 Jan 2020.

Vancouver:

V K. Real time algorithms for efficient dynamic memory allocation preemptive scheduler and searching using openmp;. [Internet] [Thesis]. INFLIBNET; 2015. [cited 2020 Jan 18]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/45327.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

V K. Real time algorithms for efficient dynamic memory allocation preemptive scheduler and searching using openmp;. [Thesis]. INFLIBNET; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/45327

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

20. Finley, Jason R. Adaptive and qualitative changes in encoding strategy with experience: evidence from the test expectancy method.

Degree: MA, 0338, 2010, University of Illinois – Urbana-Champaign

 Three experiments demonstrated undergraduate participants??? abilities to adaptively and qualitatively accommodate their encoding strategies to the demands of an upcoming test as they gained experience… (more)

Subjects/Keywords: encoding strategy; study-time allocation; metacognition; self-regulated learning; recall; memory; metamemory

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APA (6th Edition):

Finley, J. R. (2010). Adaptive and qualitative changes in encoding strategy with experience: evidence from the test expectancy method. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/16217

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Finley, Jason R. “Adaptive and qualitative changes in encoding strategy with experience: evidence from the test expectancy method.” 2010. Thesis, University of Illinois – Urbana-Champaign. Accessed January 18, 2020. http://hdl.handle.net/2142/16217.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Finley, Jason R. “Adaptive and qualitative changes in encoding strategy with experience: evidence from the test expectancy method.” 2010. Web. 18 Jan 2020.

Vancouver:

Finley JR. Adaptive and qualitative changes in encoding strategy with experience: evidence from the test expectancy method. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2010. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/2142/16217.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Finley JR. Adaptive and qualitative changes in encoding strategy with experience: evidence from the test expectancy method. [Thesis]. University of Illinois – Urbana-Champaign; 2010. Available from: http://hdl.handle.net/2142/16217

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


The Ohio State University

21. Liang, Shuang. Algorithms Designs and Implementations for Page Allocation in SSD Firmware and SSD Caching in Storage Systems.

Degree: MS, Computer Science and Engineering, 2010, The Ohio State University

  The emerging flash memory based SSD technology poses a new challenge for us to effectively use it in storage systems. Despite of its many… (more)

Subjects/Keywords: Computer Science; flash memory; disk cache; cache algorithms; page allocation algorithm; firmware

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APA (6th Edition):

Liang, S. (2010). Algorithms Designs and Implementations for Page Allocation in SSD Firmware and SSD Caching in Storage Systems. (Masters Thesis). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1268420517

Chicago Manual of Style (16th Edition):

Liang, Shuang. “Algorithms Designs and Implementations for Page Allocation in SSD Firmware and SSD Caching in Storage Systems.” 2010. Masters Thesis, The Ohio State University. Accessed January 18, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=osu1268420517.

MLA Handbook (7th Edition):

Liang, Shuang. “Algorithms Designs and Implementations for Page Allocation in SSD Firmware and SSD Caching in Storage Systems.” 2010. Web. 18 Jan 2020.

Vancouver:

Liang S. Algorithms Designs and Implementations for Page Allocation in SSD Firmware and SSD Caching in Storage Systems. [Internet] [Masters thesis]. The Ohio State University; 2010. [cited 2020 Jan 18]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1268420517.

Council of Science Editors:

Liang S. Algorithms Designs and Implementations for Page Allocation in SSD Firmware and SSD Caching in Storage Systems. [Masters Thesis]. The Ohio State University; 2010. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1268420517


NSYSU

22. Wu, Jhih-Yong. Bus Topology Exploration and Memory Allocation for Heterogeneous Systems.

Degree: Master, Computer Science and Engineering, 2007, NSYSU

 Since semiconductor process is constantly being improved, the complexity of system-on-chip is rising daily and we can place more and more elements on the same… (more)

Subjects/Keywords: allocation; exploration; memory; bus; heterogeneous system

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APA (6th Edition):

Wu, J. (2007). Bus Topology Exploration and Memory Allocation for Heterogeneous Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0802107-155041

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Jhih-Yong. “Bus Topology Exploration and Memory Allocation for Heterogeneous Systems.” 2007. Thesis, NSYSU. Accessed January 18, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0802107-155041.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Jhih-Yong. “Bus Topology Exploration and Memory Allocation for Heterogeneous Systems.” 2007. Web. 18 Jan 2020.

Vancouver:

Wu J. Bus Topology Exploration and Memory Allocation for Heterogeneous Systems. [Internet] [Thesis]. NSYSU; 2007. [cited 2020 Jan 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0802107-155041.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu J. Bus Topology Exploration and Memory Allocation for Heterogeneous Systems. [Thesis]. NSYSU; 2007. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0802107-155041

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of California – Irvine

23. Lam, Jenny. Cache Optimization for the Modern Web.

Degree: Computer Science, 2015, University of California – Irvine

 Key-value stores are used by companies such as Facebook and Twitter to improve the performance of web applications with a high read-to-write ratio. They operate… (more)

Subjects/Keywords: Computer science; caching; eviction policy; fragmentation; key-value store; memory allocation; replacement policy

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APA (6th Edition):

Lam, J. (2015). Cache Optimization for the Modern Web. (Thesis). University of California – Irvine. Retrieved from http://www.escholarship.org/uc/item/555925rp

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lam, Jenny. “Cache Optimization for the Modern Web.” 2015. Thesis, University of California – Irvine. Accessed January 18, 2020. http://www.escholarship.org/uc/item/555925rp.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lam, Jenny. “Cache Optimization for the Modern Web.” 2015. Web. 18 Jan 2020.

Vancouver:

Lam J. Cache Optimization for the Modern Web. [Internet] [Thesis]. University of California – Irvine; 2015. [cited 2020 Jan 18]. Available from: http://www.escholarship.org/uc/item/555925rp.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lam J. Cache Optimization for the Modern Web. [Thesis]. University of California – Irvine; 2015. Available from: http://www.escholarship.org/uc/item/555925rp

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Waterloo

24. Wasik, Ayelet. Features of a Multi-Threaded Memory Allocator.

Degree: 2008, University of Waterloo

 Multi-processor computers are becoming increasingly popular and are important for improving application performance. Providing high-performance memory-management is important for multi-threaded programs. This thesis looks at… (more)

Subjects/Keywords: memory allocation; multi-threaded; programming languages

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APA (6th Edition):

Wasik, A. (2008). Features of a Multi-Threaded Memory Allocator. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/3501

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wasik, Ayelet. “Features of a Multi-Threaded Memory Allocator.” 2008. Thesis, University of Waterloo. Accessed January 18, 2020. http://hdl.handle.net/10012/3501.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wasik, Ayelet. “Features of a Multi-Threaded Memory Allocator.” 2008. Web. 18 Jan 2020.

Vancouver:

Wasik A. Features of a Multi-Threaded Memory Allocator. [Internet] [Thesis]. University of Waterloo; 2008. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/10012/3501.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wasik A. Features of a Multi-Threaded Memory Allocator. [Thesis]. University of Waterloo; 2008. Available from: http://hdl.handle.net/10012/3501

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

25. Llull, Qiuyun. Microeconomic Models for Managing Shared Datacenters .

Degree: 2017, Duke University

  As demands for users’ applications’ data increase, the world’s computing platforms are moving towards more capable machines – servers and warehouse-scale datacenters. Diverse users… (more)

Subjects/Keywords: Computer engineering; Computer science; Datacenter; Memory System; Performance Prediction; Resource Allocation; Scheduling; System Management

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APA (6th Edition):

Llull, Q. (2017). Microeconomic Models for Managing Shared Datacenters . (Thesis). Duke University. Retrieved from http://hdl.handle.net/10161/14447

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Llull, Qiuyun. “Microeconomic Models for Managing Shared Datacenters .” 2017. Thesis, Duke University. Accessed January 18, 2020. http://hdl.handle.net/10161/14447.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Llull, Qiuyun. “Microeconomic Models for Managing Shared Datacenters .” 2017. Web. 18 Jan 2020.

Vancouver:

Llull Q. Microeconomic Models for Managing Shared Datacenters . [Internet] [Thesis]. Duke University; 2017. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/10161/14447.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Llull Q. Microeconomic Models for Managing Shared Datacenters . [Thesis]. Duke University; 2017. Available from: http://hdl.handle.net/10161/14447

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

26. Müller, Petr. Nástroj pro analýzu výkonu alokátorů paměti v operačním systému Linux .

Degree: 2010, Brno University of Technology

 Tato diplomová práce prezentuje nástroj, který umožňuje analýzu vlastností dynamických paměťových alokátorů se zaměřením na jejich výkon. Práce identifikuje důležité výkonnostní metriky paměťových alokátorů a… (more)

Subjects/Keywords: dynamická alokace paměti; malloc; výkon; paměť; lokalita; fragmentace; dynamic memory allocation; malloc; performance; memory; locality; fragmentation

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APA (6th Edition):

Müller, P. (2010). Nástroj pro analýzu výkonu alokátorů paměti v operačním systému Linux . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/54417

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Müller, Petr. “Nástroj pro analýzu výkonu alokátorů paměti v operačním systému Linux .” 2010. Thesis, Brno University of Technology. Accessed January 18, 2020. http://hdl.handle.net/11012/54417.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Müller, Petr. “Nástroj pro analýzu výkonu alokátorů paměti v operačním systému Linux .” 2010. Web. 18 Jan 2020.

Vancouver:

Müller P. Nástroj pro analýzu výkonu alokátorů paměti v operačním systému Linux . [Internet] [Thesis]. Brno University of Technology; 2010. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/11012/54417.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Müller P. Nástroj pro analýzu výkonu alokátorů paměti v operačním systému Linux . [Thesis]. Brno University of Technology; 2010. Available from: http://hdl.handle.net/11012/54417

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

27. Ben Abbes, Mohamed Aymen. La sélection attentionnelle et le traitement multiples dans la Mémoire Visuelle à Court-Terme : Sports and body practices of the French prisoners of war, the deported people and the forced workers during the Second World War.

Degree: Docteur es, Psychologie, 2012, Aix Marseille Université

Ce travail est divisé en deux parties : la première partie concerne l'évaluation de la sélection attentionnelle dans une tâche de Mémoire visuelle à Court-Terme.… (more)

Subjects/Keywords: Attention; Allocation attentionnelle; Traitement; Organisation spatiale; Division de l’attention; Mémoire Visuelle à Court-Terme; Attention; Attentional allocation; Processing; Spatial organization; Division of attention; Visual Short-Term Memory

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ben Abbes, M. A. (2012). La sélection attentionnelle et le traitement multiples dans la Mémoire Visuelle à Court-Terme : Sports and body practices of the French prisoners of war, the deported people and the forced workers during the Second World War. (Doctoral Dissertation). Aix Marseille Université. Retrieved from http://www.theses.fr/2012AIXM3014

Chicago Manual of Style (16th Edition):

Ben Abbes, Mohamed Aymen. “La sélection attentionnelle et le traitement multiples dans la Mémoire Visuelle à Court-Terme : Sports and body practices of the French prisoners of war, the deported people and the forced workers during the Second World War.” 2012. Doctoral Dissertation, Aix Marseille Université. Accessed January 18, 2020. http://www.theses.fr/2012AIXM3014.

MLA Handbook (7th Edition):

Ben Abbes, Mohamed Aymen. “La sélection attentionnelle et le traitement multiples dans la Mémoire Visuelle à Court-Terme : Sports and body practices of the French prisoners of war, the deported people and the forced workers during the Second World War.” 2012. Web. 18 Jan 2020.

Vancouver:

Ben Abbes MA. La sélection attentionnelle et le traitement multiples dans la Mémoire Visuelle à Court-Terme : Sports and body practices of the French prisoners of war, the deported people and the forced workers during the Second World War. [Internet] [Doctoral dissertation]. Aix Marseille Université 2012. [cited 2020 Jan 18]. Available from: http://www.theses.fr/2012AIXM3014.

Council of Science Editors:

Ben Abbes MA. La sélection attentionnelle et le traitement multiples dans la Mémoire Visuelle à Court-Terme : Sports and body practices of the French prisoners of war, the deported people and the forced workers during the Second World War. [Doctoral Dissertation]. Aix Marseille Université 2012. Available from: http://www.theses.fr/2012AIXM3014


Universitat Politècnica de València

28. Selfa Oliver, Vicent. Adaptive Prefetching and Cache Partitioning for Multicore Processors .

Degree: 2018, Universitat Politècnica de València

 El acceso a la memoria principal en los procesadores actuales supone un importante cuello de botella para las prestaciones, dado que los diferentes núcleos compiten… (more)

Subjects/Keywords: cache; cache partitioning; multicore; processors; prefetcher; memory; selective prefetcher; prefetching; caching; intel; cache allocation technology; cat

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Selfa Oliver, V. (2018). Adaptive Prefetching and Cache Partitioning for Multicore Processors . (Doctoral Dissertation). Universitat Politècnica de València. Retrieved from http://hdl.handle.net/10251/112423

Chicago Manual of Style (16th Edition):

Selfa Oliver, Vicent. “Adaptive Prefetching and Cache Partitioning for Multicore Processors .” 2018. Doctoral Dissertation, Universitat Politècnica de València. Accessed January 18, 2020. http://hdl.handle.net/10251/112423.

MLA Handbook (7th Edition):

Selfa Oliver, Vicent. “Adaptive Prefetching and Cache Partitioning for Multicore Processors .” 2018. Web. 18 Jan 2020.

Vancouver:

Selfa Oliver V. Adaptive Prefetching and Cache Partitioning for Multicore Processors . [Internet] [Doctoral dissertation]. Universitat Politècnica de València; 2018. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/10251/112423.

Council of Science Editors:

Selfa Oliver V. Adaptive Prefetching and Cache Partitioning for Multicore Processors . [Doctoral Dissertation]. Universitat Politècnica de València; 2018. Available from: http://hdl.handle.net/10251/112423

29. Jula, Alin Narcis. Improving locality with dynamic memory allocation.

Degree: 2009, Texas A&M University

 Dynamic memory allocators are a determining factor of an application's performanceand have the opportunity to improve a major performance bottleneck ontoday's computer hardware: data locality.… (more)

Subjects/Keywords: locality improving; dynamic memory allocation; locality hint; adjustable locality; generic memory allocation; hint; hintless

…viii CHAPTER Page A. Locality Considerations for Memory Allocation . . . . . . . 1… …78 79 80 85 85 88 90 92 94 GENERIC MEMORY ALLOCATION . . . . . . . . . . . . . . . 98 A… …Generic Memory Management and Allocation . . . . . 1. Attributes of a Block… …e. Simultaneous Partitions . . . . . . . . . . . . 3. Memory Allocation… …B. A Formalism for the Generic Memory Management and Allocation Problem… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jula, A. N. (2009). Improving locality with dynamic memory allocation. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2910

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jula, Alin Narcis. “Improving locality with dynamic memory allocation.” 2009. Thesis, Texas A&M University. Accessed January 18, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2910.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jula, Alin Narcis. “Improving locality with dynamic memory allocation.” 2009. Web. 18 Jan 2020.

Vancouver:

Jula AN. Improving locality with dynamic memory allocation. [Internet] [Thesis]. Texas A&M University; 2009. [cited 2020 Jan 18]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2910.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jula AN. Improving locality with dynamic memory allocation. [Thesis]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2910

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

30. Bessieres, Benjamin. Implication fonctionnelle des récepteurs NMDA corticaux au cours des processus de consolidation systémique et d’oubli de la mémoire associative chez le rat : Functional dynamics of cortical NMDA receptors during systems-level memory consolidation and forgetting.

Degree: Docteur es, Neurosciences, 2016, Bordeaux

Initialement encodés dans l’hippocampe, les nouveaux souvenirs déclaratifs deviennent progressivement dépendants d’un réseau distribué de neurones corticaux au cours de leur maturation dans le temps.… (more)

Subjects/Keywords: Consolidation mnésique; Mémoire associative; Récepteur NMDA; Réseaux corticaux; Hippocampe; Plasticité synaptique; Dynamique de surface; Allocation neuronale; Oubli; Systems-level consolidation; Remote associative memory; NMDA receptor; Cortical network; Hippocampus; Synaptic plasticity; Surface dynamics; Memory allocation; Forgetting

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bessieres, B. (2016). Implication fonctionnelle des récepteurs NMDA corticaux au cours des processus de consolidation systémique et d’oubli de la mémoire associative chez le rat : Functional dynamics of cortical NMDA receptors during systems-level memory consolidation and forgetting. (Doctoral Dissertation). Bordeaux. Retrieved from http://www.theses.fr/2016BORD0039

Chicago Manual of Style (16th Edition):

Bessieres, Benjamin. “Implication fonctionnelle des récepteurs NMDA corticaux au cours des processus de consolidation systémique et d’oubli de la mémoire associative chez le rat : Functional dynamics of cortical NMDA receptors during systems-level memory consolidation and forgetting.” 2016. Doctoral Dissertation, Bordeaux. Accessed January 18, 2020. http://www.theses.fr/2016BORD0039.

MLA Handbook (7th Edition):

Bessieres, Benjamin. “Implication fonctionnelle des récepteurs NMDA corticaux au cours des processus de consolidation systémique et d’oubli de la mémoire associative chez le rat : Functional dynamics of cortical NMDA receptors during systems-level memory consolidation and forgetting.” 2016. Web. 18 Jan 2020.

Vancouver:

Bessieres B. Implication fonctionnelle des récepteurs NMDA corticaux au cours des processus de consolidation systémique et d’oubli de la mémoire associative chez le rat : Functional dynamics of cortical NMDA receptors during systems-level memory consolidation and forgetting. [Internet] [Doctoral dissertation]. Bordeaux; 2016. [cited 2020 Jan 18]. Available from: http://www.theses.fr/2016BORD0039.

Council of Science Editors:

Bessieres B. Implication fonctionnelle des récepteurs NMDA corticaux au cours des processus de consolidation systémique et d’oubli de la mémoire associative chez le rat : Functional dynamics of cortical NMDA receptors during systems-level memory consolidation and forgetting. [Doctoral Dissertation]. Bordeaux; 2016. Available from: http://www.theses.fr/2016BORD0039

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