Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

Sorted by: relevance · author · university · dateNew search

You searched for subject:(low power). Showing records 1 – 30 of 1386 total matches.

[1] [2] [3] [4] [5] … [47]

Search Limiters

Last 2 Years | English Only

Degrees

Levels

Languages

Country

▼ Search Limiters

1. Bengtsson, Mikael. A clock driver with reduced EMI.

Degree: The Institute of Technology, 2014, Linköping UniversityLinköping University

  A clock driver that works on the principle of charging and discharging the clock network in a VLSI circuit in two steps is investigated… (more)

Subjects/Keywords: low-power; clock driver; low EMI

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bengtsson, M. (2014). A clock driver with reduced EMI. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-105673

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bengtsson, Mikael. “A clock driver with reduced EMI.” 2014. Thesis, Linköping UniversityLinköping University. Accessed October 26, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-105673.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bengtsson, Mikael. “A clock driver with reduced EMI.” 2014. Web. 26 Oct 2020.

Vancouver:

Bengtsson M. A clock driver with reduced EMI. [Internet] [Thesis]. Linköping UniversityLinköping University; 2014. [cited 2020 Oct 26]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-105673.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bengtsson M. A clock driver with reduced EMI. [Thesis]. Linköping UniversityLinköping University; 2014. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-105673

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

2. Lu, Dao. K-hot pipelining.

Degree: MS, Electrical & Computer Engr, 2016, University of Illinois – Urbana-Champaign

 Computing systems in almost every application domain now support techniques to trade off power and performance. Such techniques are used to enforce power and thermal… (more)

Subjects/Keywords: Low-Energy and Low-Power Technologies; Microarchitecture

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lu, D. (2016). K-hot pipelining. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/93032

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lu, Dao. “K-hot pipelining.” 2016. Thesis, University of Illinois – Urbana-Champaign. Accessed October 26, 2020. http://hdl.handle.net/2142/93032.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lu, Dao. “K-hot pipelining.” 2016. Web. 26 Oct 2020.

Vancouver:

Lu D. K-hot pipelining. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2016. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/2142/93032.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lu D. K-hot pipelining. [Thesis]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/93032

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rochester Institute of Technology

3. Fitzgerald, Brendan. Drowsy cache partitioning for reduced static and dynamic energy in the cache hierarchy.

Degree: Computer Engineering, 2012, Rochester Institute of Technology

Power consumption in computing today has lead the industry towards energy efficient computing. As transistor technology shrinks, new techniques have to be developed to keep… (more)

Subjects/Keywords: Cache; Energy; Low-power

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Fitzgerald, B. (2012). Drowsy cache partitioning for reduced static and dynamic energy in the cache hierarchy. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/4600

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fitzgerald, Brendan. “Drowsy cache partitioning for reduced static and dynamic energy in the cache hierarchy.” 2012. Thesis, Rochester Institute of Technology. Accessed October 26, 2020. https://scholarworks.rit.edu/theses/4600.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fitzgerald, Brendan. “Drowsy cache partitioning for reduced static and dynamic energy in the cache hierarchy.” 2012. Web. 26 Oct 2020.

Vancouver:

Fitzgerald B. Drowsy cache partitioning for reduced static and dynamic energy in the cache hierarchy. [Internet] [Thesis]. Rochester Institute of Technology; 2012. [cited 2020 Oct 26]. Available from: https://scholarworks.rit.edu/theses/4600.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fitzgerald B. Drowsy cache partitioning for reduced static and dynamic energy in the cache hierarchy. [Thesis]. Rochester Institute of Technology; 2012. Available from: https://scholarworks.rit.edu/theses/4600

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Université de Neuchâtel

4. Shi, Xintian. Design of low phase noise low power CMOS phase locked loops.

Degree: 2008, Université de Neuchâtel

 Phase locked loop (PLL) is one of the most critical devices in modern electronic systems. PLLs are widely used as clock generator or frequency synthesis… (more)

Subjects/Keywords: low power

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shi, X. (2008). Design of low phase noise low power CMOS phase locked loops. (Thesis). Université de Neuchâtel. Retrieved from http://doc.rero.ch/record/11990

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shi, Xintian. “Design of low phase noise low power CMOS phase locked loops.” 2008. Thesis, Université de Neuchâtel. Accessed October 26, 2020. http://doc.rero.ch/record/11990.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shi, Xintian. “Design of low phase noise low power CMOS phase locked loops.” 2008. Web. 26 Oct 2020.

Vancouver:

Shi X. Design of low phase noise low power CMOS phase locked loops. [Internet] [Thesis]. Université de Neuchâtel; 2008. [cited 2020 Oct 26]. Available from: http://doc.rero.ch/record/11990.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shi X. Design of low phase noise low power CMOS phase locked loops. [Thesis]. Université de Neuchâtel; 2008. Available from: http://doc.rero.ch/record/11990

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

5. Xu, Kai. Merging of RF Oscillator and Power Amplifier to Enable Fully Integrated Transmitters for Internet-of-Things.

Degree: 2020, RIAN

 To facilitate the ever-increasing influx of the Internet-of-Things (IoT) wireless connectivity, the investigation for power efficient and cost effective wireless devices together with the trend… (more)

Subjects/Keywords: Ultra-low-power transceiver

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Xu, K. (2020). Merging of RF Oscillator and Power Amplifier to Enable Fully Integrated Transmitters for Internet-of-Things. (Thesis). RIAN. Retrieved from http://hdl.handle.net/10197/11358

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Xu, Kai. “Merging of RF Oscillator and Power Amplifier to Enable Fully Integrated Transmitters for Internet-of-Things.” 2020. Thesis, RIAN. Accessed October 26, 2020. http://hdl.handle.net/10197/11358.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Xu, Kai. “Merging of RF Oscillator and Power Amplifier to Enable Fully Integrated Transmitters for Internet-of-Things.” 2020. Web. 26 Oct 2020.

Vancouver:

Xu K. Merging of RF Oscillator and Power Amplifier to Enable Fully Integrated Transmitters for Internet-of-Things. [Internet] [Thesis]. RIAN; 2020. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/10197/11358.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Xu K. Merging of RF Oscillator and Power Amplifier to Enable Fully Integrated Transmitters for Internet-of-Things. [Thesis]. RIAN; 2020. Available from: http://hdl.handle.net/10197/11358

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

6. Cao, J. (author). Power efficient digital correlator in the scope of an UWB baseband design.

Degree: 2012, Delft University of Technology

Ultra Wideband (UWB) radio represents a promising way of communication for low power applications in interference-prone environments. For achieving a low power solution the digital… (more)

Subjects/Keywords: Low power; UWB; correlator

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cao, J. (. (2012). Power efficient digital correlator in the scope of an UWB baseband design. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:a36ab768-4bae-4729-b874-e1c92dc4380f

Chicago Manual of Style (16th Edition):

Cao, J (author). “Power efficient digital correlator in the scope of an UWB baseband design.” 2012. Masters Thesis, Delft University of Technology. Accessed October 26, 2020. http://resolver.tudelft.nl/uuid:a36ab768-4bae-4729-b874-e1c92dc4380f.

MLA Handbook (7th Edition):

Cao, J (author). “Power efficient digital correlator in the scope of an UWB baseband design.” 2012. Web. 26 Oct 2020.

Vancouver:

Cao J(. Power efficient digital correlator in the scope of an UWB baseband design. [Internet] [Masters thesis]. Delft University of Technology; 2012. [cited 2020 Oct 26]. Available from: http://resolver.tudelft.nl/uuid:a36ab768-4bae-4729-b874-e1c92dc4380f.

Council of Science Editors:

Cao J(. Power efficient digital correlator in the scope of an UWB baseband design. [Masters Thesis]. Delft University of Technology; 2012. Available from: http://resolver.tudelft.nl/uuid:a36ab768-4bae-4729-b874-e1c92dc4380f


University of Illinois – Urbana-Champaign

7. Sun, Zelei. VAST-LP: clock gating in high-level synthesis.

Degree: MS, Electrical & Computer Engr, 2016, University of Illinois – Urbana-Champaign

 High-level synthesis (HLS) promises high-quality hardware with minimal develop- ment e ort. In this thesis, we evaluate the current state-of-the-art HLS engine VAST and propose… (more)

Subjects/Keywords: low power; high level synthesis

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sun, Z. (2016). VAST-LP: clock gating in high-level synthesis. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/90970

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sun, Zelei. “VAST-LP: clock gating in high-level synthesis.” 2016. Thesis, University of Illinois – Urbana-Champaign. Accessed October 26, 2020. http://hdl.handle.net/2142/90970.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sun, Zelei. “VAST-LP: clock gating in high-level synthesis.” 2016. Web. 26 Oct 2020.

Vancouver:

Sun Z. VAST-LP: clock gating in high-level synthesis. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2016. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/2142/90970.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sun Z. VAST-LP: clock gating in high-level synthesis. [Thesis]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/90970

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

8. Yap, Wui Chung. 2D material devices for low power logic and memory applications.

Degree: MS, Electrical & Computer Engr, 2016, University of Illinois – Urbana-Champaign

 This thesis investigates low power tunneling field effect transistors (task 1) and low power ferroelectric memory devices (task 2) based on two-dimensional (2D) materials. In… (more)

Subjects/Keywords: 2D materials; Low power

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yap, W. C. (2016). 2D material devices for low power logic and memory applications. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/95528

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yap, Wui Chung. “2D material devices for low power logic and memory applications.” 2016. Thesis, University of Illinois – Urbana-Champaign. Accessed October 26, 2020. http://hdl.handle.net/2142/95528.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yap, Wui Chung. “2D material devices for low power logic and memory applications.” 2016. Web. 26 Oct 2020.

Vancouver:

Yap WC. 2D material devices for low power logic and memory applications. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2016. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/2142/95528.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yap WC. 2D material devices for low power logic and memory applications. [Thesis]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/95528

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

9. Hsu, Hua-Shan. Design and Implementation of Power Management Policy on 3D Graphics System-On-Chip.

Degree: Master, Computer Science and Engineering, 2008, NSYSU

 The 3D applications, until recently restricted to the desktops and workstations, are expanding into the mobile platforms, such as cellular phones and PDAs. Similar to… (more)

Subjects/Keywords: power management; low power; workload estimation

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hsu, H. (2008). Design and Implementation of Power Management Policy on 3D Graphics System-On-Chip. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0825108-165911

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hsu, Hua-Shan. “Design and Implementation of Power Management Policy on 3D Graphics System-On-Chip.” 2008. Thesis, NSYSU. Accessed October 26, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0825108-165911.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hsu, Hua-Shan. “Design and Implementation of Power Management Policy on 3D Graphics System-On-Chip.” 2008. Web. 26 Oct 2020.

Vancouver:

Hsu H. Design and Implementation of Power Management Policy on 3D Graphics System-On-Chip. [Internet] [Thesis]. NSYSU; 2008. [cited 2020 Oct 26]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0825108-165911.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsu H. Design and Implementation of Power Management Policy on 3D Graphics System-On-Chip. [Thesis]. NSYSU; 2008. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0825108-165911

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

10. Liao, Chi-Sheng. Body-Raised Punch Through CMOS for Low Power Supply Applications.

Degree: Master, Electrical Engineering, 2018, NSYSU

 In this thesis, we propose a punch through complementary metal oxide semiconductor (PTCMOS) with a raised body for suppressing diffusion current (BR-PTCMOS) in low power(more)

Subjects/Keywords: low power dissipation; punch through transistor; power-delay product; CMOS; low power supply

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liao, C. (2018). Body-Raised Punch Through CMOS for Low Power Supply Applications. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0717118-160311

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liao, Chi-Sheng. “Body-Raised Punch Through CMOS for Low Power Supply Applications.” 2018. Thesis, NSYSU. Accessed October 26, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0717118-160311.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liao, Chi-Sheng. “Body-Raised Punch Through CMOS for Low Power Supply Applications.” 2018. Web. 26 Oct 2020.

Vancouver:

Liao C. Body-Raised Punch Through CMOS for Low Power Supply Applications. [Internet] [Thesis]. NSYSU; 2018. [cited 2020 Oct 26]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0717118-160311.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liao C. Body-Raised Punch Through CMOS for Low Power Supply Applications. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0717118-160311

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

11. Chou, Hung-I. System level power estimation for power manageable System-on-chip.

Degree: Master, Computer Science and Engineering, 2009, NSYSU

 The modern handheld devices have become smaller and more complex nowadays. However, the requirements for its performance and functions have also become higher, which means… (more)

Subjects/Keywords: power management; low-power; framework; power estimation; SystemC; system level

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chou, H. (2009). System level power estimation for power manageable System-on-chip. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0805109-102151

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chou, Hung-I. “System level power estimation for power manageable System-on-chip.” 2009. Thesis, NSYSU. Accessed October 26, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0805109-102151.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chou, Hung-I. “System level power estimation for power manageable System-on-chip.” 2009. Web. 26 Oct 2020.

Vancouver:

Chou H. System level power estimation for power manageable System-on-chip. [Internet] [Thesis]. NSYSU; 2009. [cited 2020 Oct 26]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0805109-102151.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chou H. System level power estimation for power manageable System-on-chip. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0805109-102151

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Colorado State University

12. Soman, Sachin. Analysis and characterization of wireless smart power meter.

Degree: MS(M.S.), Electrical and Computer Engineering, 2014, Colorado State University

 Recent increases in the demand for and price of electricity has stimulated interest in monitoring energy usage and improving efficiency. This research work supports development… (more)

Subjects/Keywords: condition monitoring; wireless power meter; smart power meter; power meter; low cost power meter

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Soman, S. (2014). Analysis and characterization of wireless smart power meter. (Masters Thesis). Colorado State University. Retrieved from http://hdl.handle.net/10217/84583

Chicago Manual of Style (16th Edition):

Soman, Sachin. “Analysis and characterization of wireless smart power meter.” 2014. Masters Thesis, Colorado State University. Accessed October 26, 2020. http://hdl.handle.net/10217/84583.

MLA Handbook (7th Edition):

Soman, Sachin. “Analysis and characterization of wireless smart power meter.” 2014. Web. 26 Oct 2020.

Vancouver:

Soman S. Analysis and characterization of wireless smart power meter. [Internet] [Masters thesis]. Colorado State University; 2014. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/10217/84583.

Council of Science Editors:

Soman S. Analysis and characterization of wireless smart power meter. [Masters Thesis]. Colorado State University; 2014. Available from: http://hdl.handle.net/10217/84583


NSYSU

13. Wang, Jiun-ping. Power and Error Reduction Techniques of Multipliers for Multimedia Applications.

Degree: PhD, Computer Science and Engineering, 2010, NSYSU

 Recently, multimedia applications are used widely in many embedded and portable systems, such as mobile phones, MP3 player and PDA, which require lower power consumption… (more)

Subjects/Keywords: low power; multiplier; error compensation circuit

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, J. (2010). Power and Error Reduction Techniques of Multipliers for Multimedia Applications. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0203110-142928

Chicago Manual of Style (16th Edition):

Wang, Jiun-ping. “Power and Error Reduction Techniques of Multipliers for Multimedia Applications.” 2010. Doctoral Dissertation, NSYSU. Accessed October 26, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0203110-142928.

MLA Handbook (7th Edition):

Wang, Jiun-ping. “Power and Error Reduction Techniques of Multipliers for Multimedia Applications.” 2010. Web. 26 Oct 2020.

Vancouver:

Wang J. Power and Error Reduction Techniques of Multipliers for Multimedia Applications. [Internet] [Doctoral dissertation]. NSYSU; 2010. [cited 2020 Oct 26]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0203110-142928.

Council of Science Editors:

Wang J. Power and Error Reduction Techniques of Multipliers for Multimedia Applications. [Doctoral Dissertation]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0203110-142928


NSYSU

14. Guo, Cang-yuan. Multiple Precision Iterative Floating-Point Multiplier for Low-Power Applications.

Degree: Master, Computer Science and Engineering, 2010, NSYSU

 In many multimedia applications, a little error in the output results is allowable. Therefore, this thesis presents an iterative floating-point multiplier with multiple precision to… (more)

Subjects/Keywords: multiple precision; multiplier; iterative; Low power

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Guo, C. (2010). Multiple Precision Iterative Floating-Point Multiplier for Low-Power Applications. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0203110-215114

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Guo, Cang-yuan. “Multiple Precision Iterative Floating-Point Multiplier for Low-Power Applications.” 2010. Thesis, NSYSU. Accessed October 26, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0203110-215114.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Guo, Cang-yuan. “Multiple Precision Iterative Floating-Point Multiplier for Low-Power Applications.” 2010. Web. 26 Oct 2020.

Vancouver:

Guo C. Multiple Precision Iterative Floating-Point Multiplier for Low-Power Applications. [Internet] [Thesis]. NSYSU; 2010. [cited 2020 Oct 26]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0203110-215114.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Guo C. Multiple Precision Iterative Floating-Point Multiplier for Low-Power Applications. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0203110-215114

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

15. Pereira dos Santos, Rodolfo. Mecanismo de otimização para redução de potência estática de circuitos integrados baseado na técnica Dual-VTH .

Degree: 2010, Universidade Federal de Pernambuco

 Com o advento de novas tecnologias de fabricação, a complexidade e a capacidade de processamento dos sistemas microeletrônicos tornaram-se cada vez maiores. Contudo devido às… (more)

Subjects/Keywords: Potência estática; CMOS; VLSI; Low-power

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pereira dos Santos, R. (2010). Mecanismo de otimização para redução de potência estática de circuitos integrados baseado na técnica Dual-VTH . (Thesis). Universidade Federal de Pernambuco. Retrieved from http://repositorio.ufpe.br/handle/123456789/2443

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pereira dos Santos, Rodolfo. “Mecanismo de otimização para redução de potência estática de circuitos integrados baseado na técnica Dual-VTH .” 2010. Thesis, Universidade Federal de Pernambuco. Accessed October 26, 2020. http://repositorio.ufpe.br/handle/123456789/2443.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pereira dos Santos, Rodolfo. “Mecanismo de otimização para redução de potência estática de circuitos integrados baseado na técnica Dual-VTH .” 2010. Web. 26 Oct 2020.

Vancouver:

Pereira dos Santos R. Mecanismo de otimização para redução de potência estática de circuitos integrados baseado na técnica Dual-VTH . [Internet] [Thesis]. Universidade Federal de Pernambuco; 2010. [cited 2020 Oct 26]. Available from: http://repositorio.ufpe.br/handle/123456789/2443.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pereira dos Santos R. Mecanismo de otimização para redução de potência estática de circuitos integrados baseado na técnica Dual-VTH . [Thesis]. Universidade Federal de Pernambuco; 2010. Available from: http://repositorio.ufpe.br/handle/123456789/2443

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of California – Berkeley

16. Bowonder, Anupama. Low Power Band to Band Tunnel Transistors.

Degree: Electrical Engineering & Computer Sciences, 2010, University of California – Berkeley

 As scaling continues, the number of transistors per unit area and power density are both on the rise. A reduction in Vdd is highly desirable… (more)

Subjects/Keywords: Electrical Engineering; Heterostructure; Low power; Tunneling

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bowonder, A. (2010). Low Power Band to Band Tunnel Transistors. (Thesis). University of California – Berkeley. Retrieved from http://www.escholarship.org/uc/item/8pr4h19x

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bowonder, Anupama. “Low Power Band to Band Tunnel Transistors.” 2010. Thesis, University of California – Berkeley. Accessed October 26, 2020. http://www.escholarship.org/uc/item/8pr4h19x.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bowonder, Anupama. “Low Power Band to Band Tunnel Transistors.” 2010. Web. 26 Oct 2020.

Vancouver:

Bowonder A. Low Power Band to Band Tunnel Transistors. [Internet] [Thesis]. University of California – Berkeley; 2010. [cited 2020 Oct 26]. Available from: http://www.escholarship.org/uc/item/8pr4h19x.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bowonder A. Low Power Band to Band Tunnel Transistors. [Thesis]. University of California – Berkeley; 2010. Available from: http://www.escholarship.org/uc/item/8pr4h19x

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

17. Singh, Amrinder. Case Studies on Variation Tolerant and Low Power Design Using Planar Asymmetric Double Gate Transistor.

Degree: MS, Computer Engineering, 2011, Texas A&M University

 In nanometer technologies, process variation control and low power have emerged as the first order design goal after high performance. Process variations cause high variability… (more)

Subjects/Keywords: process variation; double gate; low power

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Singh, A. (2011). Case Studies on Variation Tolerant and Low Power Design Using Planar Asymmetric Double Gate Transistor. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8488

Chicago Manual of Style (16th Edition):

Singh, Amrinder. “Case Studies on Variation Tolerant and Low Power Design Using Planar Asymmetric Double Gate Transistor.” 2011. Masters Thesis, Texas A&M University. Accessed October 26, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8488.

MLA Handbook (7th Edition):

Singh, Amrinder. “Case Studies on Variation Tolerant and Low Power Design Using Planar Asymmetric Double Gate Transistor.” 2011. Web. 26 Oct 2020.

Vancouver:

Singh A. Case Studies on Variation Tolerant and Low Power Design Using Planar Asymmetric Double Gate Transistor. [Internet] [Masters thesis]. Texas A&M University; 2011. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8488.

Council of Science Editors:

Singh A. Case Studies on Variation Tolerant and Low Power Design Using Planar Asymmetric Double Gate Transistor. [Masters Thesis]. Texas A&M University; 2011. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8488


Texas A&M University

18. Gao, Zhuoyang. Comparative Study on Performance and Variation Tolerance of Low Power Circuit.

Degree: MS, Computer Engineering, 2015, Texas A&M University

 The demand for low-power electronic devices is increasing rapidly in current VLSI technology. Instead of conventional CMOS circuit operating at nominal supply voltage, several kinds… (more)

Subjects/Keywords: low power; adiabatic circuit; near-threshold computing

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gao, Z. (2015). Comparative Study on Performance and Variation Tolerance of Low Power Circuit. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/156528

Chicago Manual of Style (16th Edition):

Gao, Zhuoyang. “Comparative Study on Performance and Variation Tolerance of Low Power Circuit.” 2015. Masters Thesis, Texas A&M University. Accessed October 26, 2020. http://hdl.handle.net/1969.1/156528.

MLA Handbook (7th Edition):

Gao, Zhuoyang. “Comparative Study on Performance and Variation Tolerance of Low Power Circuit.” 2015. Web. 26 Oct 2020.

Vancouver:

Gao Z. Comparative Study on Performance and Variation Tolerance of Low Power Circuit. [Internet] [Masters thesis]. Texas A&M University; 2015. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/1969.1/156528.

Council of Science Editors:

Gao Z. Comparative Study on Performance and Variation Tolerance of Low Power Circuit. [Masters Thesis]. Texas A&M University; 2015. Available from: http://hdl.handle.net/1969.1/156528


Penn State University

19. Chatterjee, Nivedita. The FCC's low power FM policy: Station personnel's interpretation of policy objectives and its impact on implementation.

Degree: 2013, Penn State University

 Social policies are means by which the government ensures every member of the community certain minimum standards of living and a degree of equality in… (more)

Subjects/Keywords: LPFMs; media policy evaluation; low power radio

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chatterjee, N. (2013). The FCC's low power FM policy: Station personnel's interpretation of policy objectives and its impact on implementation. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/17603

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chatterjee, Nivedita. “The FCC's low power FM policy: Station personnel's interpretation of policy objectives and its impact on implementation.” 2013. Thesis, Penn State University. Accessed October 26, 2020. https://submit-etda.libraries.psu.edu/catalog/17603.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chatterjee, Nivedita. “The FCC's low power FM policy: Station personnel's interpretation of policy objectives and its impact on implementation.” 2013. Web. 26 Oct 2020.

Vancouver:

Chatterjee N. The FCC's low power FM policy: Station personnel's interpretation of policy objectives and its impact on implementation. [Internet] [Thesis]. Penn State University; 2013. [cited 2020 Oct 26]. Available from: https://submit-etda.libraries.psu.edu/catalog/17603.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chatterjee N. The FCC's low power FM policy: Station personnel's interpretation of policy objectives and its impact on implementation. [Thesis]. Penn State University; 2013. Available from: https://submit-etda.libraries.psu.edu/catalog/17603

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

20. Mukundrajan, Ravindhiran. Tunnel FET based Field Programmable Gate Arrays .

Degree: 2011, Penn State University

 The proliferation of mobile computing systems has created a new segment in the semiconductor ecosystem where energy e�ciency is the most critical design parameter. Moreover,… (more)

Subjects/Keywords: Emerging nanotech; Tunnel FET; FPGA; Low Power

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mukundrajan, R. (2011). Tunnel FET based Field Programmable Gate Arrays . (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/12004

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mukundrajan, Ravindhiran. “Tunnel FET based Field Programmable Gate Arrays .” 2011. Thesis, Penn State University. Accessed October 26, 2020. https://submit-etda.libraries.psu.edu/catalog/12004.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mukundrajan, Ravindhiran. “Tunnel FET based Field Programmable Gate Arrays .” 2011. Web. 26 Oct 2020.

Vancouver:

Mukundrajan R. Tunnel FET based Field Programmable Gate Arrays . [Internet] [Thesis]. Penn State University; 2011. [cited 2020 Oct 26]. Available from: https://submit-etda.libraries.psu.edu/catalog/12004.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mukundrajan R. Tunnel FET based Field Programmable Gate Arrays . [Thesis]. Penn State University; 2011. Available from: https://submit-etda.libraries.psu.edu/catalog/12004

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


North Carolina State University

21. Iyer, Balaji Viswanathan. Length Adaptive Processors: A Solution for the Energy/Performance Dilemma in Embedded Systems.

Degree: PhD, Computer Engineering, 2009, North Carolina State University

 Embedded-handheld devices are the predominant computing platform today. These devices are required to perform complex tasks yet run on batteries. Some architects use ASIC to… (more)

Subjects/Keywords: Energy Reduction Low-Power Embedded Processors Len

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Iyer, B. V. (2009). Length Adaptive Processors: A Solution for the Energy/Performance Dilemma in Embedded Systems. (Doctoral Dissertation). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/4680

Chicago Manual of Style (16th Edition):

Iyer, Balaji Viswanathan. “Length Adaptive Processors: A Solution for the Energy/Performance Dilemma in Embedded Systems.” 2009. Doctoral Dissertation, North Carolina State University. Accessed October 26, 2020. http://www.lib.ncsu.edu/resolver/1840.16/4680.

MLA Handbook (7th Edition):

Iyer, Balaji Viswanathan. “Length Adaptive Processors: A Solution for the Energy/Performance Dilemma in Embedded Systems.” 2009. Web. 26 Oct 2020.

Vancouver:

Iyer BV. Length Adaptive Processors: A Solution for the Energy/Performance Dilemma in Embedded Systems. [Internet] [Doctoral dissertation]. North Carolina State University; 2009. [cited 2020 Oct 26]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/4680.

Council of Science Editors:

Iyer BV. Length Adaptive Processors: A Solution for the Energy/Performance Dilemma in Embedded Systems. [Doctoral Dissertation]. North Carolina State University; 2009. Available from: http://www.lib.ncsu.edu/resolver/1840.16/4680


University of Toronto

22. Sharifymoghaddam, Sayeh. Low-swing Signaling for FPGA Interconnect Power Reduction.

Degree: 2015, University of Toronto

FPGAs are widely used in digital circuits implementation because of their lower non-recurring engineering cost and shorter time-to-market in comparison with ASICs. However, there are… (more)

Subjects/Keywords: FPGA; Interconnect; low-swing signaling; Power; 0544

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sharifymoghaddam, S. (2015). Low-swing Signaling for FPGA Interconnect Power Reduction. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/72600

Chicago Manual of Style (16th Edition):

Sharifymoghaddam, Sayeh. “Low-swing Signaling for FPGA Interconnect Power Reduction.” 2015. Masters Thesis, University of Toronto. Accessed October 26, 2020. http://hdl.handle.net/1807/72600.

MLA Handbook (7th Edition):

Sharifymoghaddam, Sayeh. “Low-swing Signaling for FPGA Interconnect Power Reduction.” 2015. Web. 26 Oct 2020.

Vancouver:

Sharifymoghaddam S. Low-swing Signaling for FPGA Interconnect Power Reduction. [Internet] [Masters thesis]. University of Toronto; 2015. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/1807/72600.

Council of Science Editors:

Sharifymoghaddam S. Low-swing Signaling for FPGA Interconnect Power Reduction. [Masters Thesis]. University of Toronto; 2015. Available from: http://hdl.handle.net/1807/72600


ETH Zürich

23. Schnider, Raphael. Pushing the Internet to the Edge.

Degree: 2020, ETH Zürich

 In recent years the trend has been to connect any device to the internet to remotely sense or actuate objects, a concept called "Internet of… (more)

Subjects/Keywords: Synchronous transmissions; Low-power Wireless Communication

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Schnider, R. (2020). Pushing the Internet to the Edge. (Thesis). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/401663

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Schnider, Raphael. “Pushing the Internet to the Edge.” 2020. Thesis, ETH Zürich. Accessed October 26, 2020. http://hdl.handle.net/20.500.11850/401663.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Schnider, Raphael. “Pushing the Internet to the Edge.” 2020. Web. 26 Oct 2020.

Vancouver:

Schnider R. Pushing the Internet to the Edge. [Internet] [Thesis]. ETH Zürich; 2020. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/20.500.11850/401663.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Schnider R. Pushing the Internet to the Edge. [Thesis]. ETH Zürich; 2020. Available from: http://hdl.handle.net/20.500.11850/401663

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Chicago

24. Onyema, Emmanuel C. Design and CMOS Technology Optimization of a Low Power MEMS Pierce Oscillator.

Degree: 2014, University of Illinois – Chicago

 Particulate matter (PM) consists of air pollutants such as dust, smoke, diesel exhaust and tobacco fumes. A subset of these pollutants, which are PM particles… (more)

Subjects/Keywords: MEMS; Low Power; Optimization; Pierce Oscillator

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Onyema, E. C. (2014). Design and CMOS Technology Optimization of a Low Power MEMS Pierce Oscillator. (Thesis). University of Illinois – Chicago. Retrieved from http://hdl.handle.net/10027/19073

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Onyema, Emmanuel C. “Design and CMOS Technology Optimization of a Low Power MEMS Pierce Oscillator.” 2014. Thesis, University of Illinois – Chicago. Accessed October 26, 2020. http://hdl.handle.net/10027/19073.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Onyema, Emmanuel C. “Design and CMOS Technology Optimization of a Low Power MEMS Pierce Oscillator.” 2014. Web. 26 Oct 2020.

Vancouver:

Onyema EC. Design and CMOS Technology Optimization of a Low Power MEMS Pierce Oscillator. [Internet] [Thesis]. University of Illinois – Chicago; 2014. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/10027/19073.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Onyema EC. Design and CMOS Technology Optimization of a Low Power MEMS Pierce Oscillator. [Thesis]. University of Illinois – Chicago; 2014. Available from: http://hdl.handle.net/10027/19073

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


King Abdullah University of Science and Technology

25. Lechuga Aranda, Jesus Javier. Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits.

Degree: 2016, King Abdullah University of Science and Technology

 Since the introduction of Complementary-Metal-Oxide-Semiconductor (CMOS) technology, the chip industry has enjoyed many benefits of transistor feature size scaling, including higher speed and device density… (more)

Subjects/Keywords: NEMS; Relay; Low power; Verilog-a

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lechuga Aranda, J. J. (2016). Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits. (Thesis). King Abdullah University of Science and Technology. Retrieved from http://hdl.handle.net/10754/609468

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lechuga Aranda, Jesus Javier. “Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits.” 2016. Thesis, King Abdullah University of Science and Technology. Accessed October 26, 2020. http://hdl.handle.net/10754/609468.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lechuga Aranda, Jesus Javier. “Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits.” 2016. Web. 26 Oct 2020.

Vancouver:

Lechuga Aranda JJ. Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits. [Internet] [Thesis]. King Abdullah University of Science and Technology; 2016. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/10754/609468.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lechuga Aranda JJ. Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits. [Thesis]. King Abdullah University of Science and Technology; 2016. Available from: http://hdl.handle.net/10754/609468

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Colorado State University

26. Wilson, William. Low-noise, low-power transimpedance amplifier for integrated electrochemical biosensor applications.

Degree: MS(M.S.), Electrical and Computer Engineering, 2014, Colorado State University

 Biosensor devices have found an increasingly broad range of applications including clinical, biological, and even pharmaceutical research and testing. These devices are useful for detecting… (more)

Subjects/Keywords: biosensor; transimpedance; low-power; integrated; electrochemistry

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wilson, W. (2014). Low-noise, low-power transimpedance amplifier for integrated electrochemical biosensor applications. (Masters Thesis). Colorado State University. Retrieved from http://hdl.handle.net/10217/84578

Chicago Manual of Style (16th Edition):

Wilson, William. “Low-noise, low-power transimpedance amplifier for integrated electrochemical biosensor applications.” 2014. Masters Thesis, Colorado State University. Accessed October 26, 2020. http://hdl.handle.net/10217/84578.

MLA Handbook (7th Edition):

Wilson, William. “Low-noise, low-power transimpedance amplifier for integrated electrochemical biosensor applications.” 2014. Web. 26 Oct 2020.

Vancouver:

Wilson W. Low-noise, low-power transimpedance amplifier for integrated electrochemical biosensor applications. [Internet] [Masters thesis]. Colorado State University; 2014. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/10217/84578.

Council of Science Editors:

Wilson W. Low-noise, low-power transimpedance amplifier for integrated electrochemical biosensor applications. [Masters Thesis]. Colorado State University; 2014. Available from: http://hdl.handle.net/10217/84578


University of Adelaide

27. Tian, Geng. A study of low power and high performance cache hierarchy for multi-core processor.

Degree: 2015, University of Adelaide

 The increasing levels of transistor density have enabled integration of an increasing number of cores and cache resources on a single chip. However, power, as… (more)

Subjects/Keywords: CMPs; cache; low power; replacement policy

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tian, G. (2015). A study of low power and high performance cache hierarchy for multi-core processor. (Thesis). University of Adelaide. Retrieved from http://hdl.handle.net/2440/96726

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tian, Geng. “A study of low power and high performance cache hierarchy for multi-core processor.” 2015. Thesis, University of Adelaide. Accessed October 26, 2020. http://hdl.handle.net/2440/96726.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tian, Geng. “A study of low power and high performance cache hierarchy for multi-core processor.” 2015. Web. 26 Oct 2020.

Vancouver:

Tian G. A study of low power and high performance cache hierarchy for multi-core processor. [Internet] [Thesis]. University of Adelaide; 2015. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/2440/96726.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tian G. A study of low power and high performance cache hierarchy for multi-core processor. [Thesis]. University of Adelaide; 2015. Available from: http://hdl.handle.net/2440/96726

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Northeastern University

28. He, Yixuan. Evaluations Of Electronic Neuron Model For Low Power Vlsi Implementation.

Degree: MS, Department of Electrical and Computer Engineering, 2019, Northeastern University

 The brain is a powerful system on computing and learning. Also, it is probably the most complex and interesting system in the world at the… (more)

Subjects/Keywords: Low Power; Neuron Model; VLSI; Electrical engineering

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

He, Y. (2019). Evaluations Of Electronic Neuron Model For Low Power Vlsi Implementation. (Masters Thesis). Northeastern University. Retrieved from http://hdl.handle.net/2047/D20317890

Chicago Manual of Style (16th Edition):

He, Yixuan. “Evaluations Of Electronic Neuron Model For Low Power Vlsi Implementation.” 2019. Masters Thesis, Northeastern University. Accessed October 26, 2020. http://hdl.handle.net/2047/D20317890.

MLA Handbook (7th Edition):

He, Yixuan. “Evaluations Of Electronic Neuron Model For Low Power Vlsi Implementation.” 2019. Web. 26 Oct 2020.

Vancouver:

He Y. Evaluations Of Electronic Neuron Model For Low Power Vlsi Implementation. [Internet] [Masters thesis]. Northeastern University; 2019. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/2047/D20317890.

Council of Science Editors:

He Y. Evaluations Of Electronic Neuron Model For Low Power Vlsi Implementation. [Masters Thesis]. Northeastern University; 2019. Available from: http://hdl.handle.net/2047/D20317890


University of Illinois – Chicago

29. Gianelli, Alberto. A Low Power Look Up Table-Free Gaussian Mixture Model Based Speaker Classifier.

Degree: 2018, University of Illinois – Chicago

 In this thesis an ASIC design of an hardware GMM-Based Speaker Classifier is presented.The Classifier is a fundamental component of a Speaker Identification system, that… (more)

Subjects/Keywords: GMM; speaker recognition; low power; ASIC

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gianelli, A. (2018). A Low Power Look Up Table-Free Gaussian Mixture Model Based Speaker Classifier. (Thesis). University of Illinois – Chicago. Retrieved from http://hdl.handle.net/10027/22958

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gianelli, Alberto. “A Low Power Look Up Table-Free Gaussian Mixture Model Based Speaker Classifier.” 2018. Thesis, University of Illinois – Chicago. Accessed October 26, 2020. http://hdl.handle.net/10027/22958.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gianelli, Alberto. “A Low Power Look Up Table-Free Gaussian Mixture Model Based Speaker Classifier.” 2018. Web. 26 Oct 2020.

Vancouver:

Gianelli A. A Low Power Look Up Table-Free Gaussian Mixture Model Based Speaker Classifier. [Internet] [Thesis]. University of Illinois – Chicago; 2018. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/10027/22958.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gianelli A. A Low Power Look Up Table-Free Gaussian Mixture Model Based Speaker Classifier. [Thesis]. University of Illinois – Chicago; 2018. Available from: http://hdl.handle.net/10027/22958

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University College Cork

30. O'Connell, Eoin. Networking protocols for long life wireless sensor networks.

Degree: 2014, University College Cork

 My original contribution to knowledge is the creation of a WSN system that further improves the functionality of existing technology, whilst achieving improved power consumption… (more)

Subjects/Keywords: WSN low-power networking; Wireless sensor networks

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

O'Connell, E. (2014). Networking protocols for long life wireless sensor networks. (Thesis). University College Cork. Retrieved from http://hdl.handle.net/10468/1896

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

O'Connell, Eoin. “Networking protocols for long life wireless sensor networks.” 2014. Thesis, University College Cork. Accessed October 26, 2020. http://hdl.handle.net/10468/1896.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

O'Connell, Eoin. “Networking protocols for long life wireless sensor networks.” 2014. Web. 26 Oct 2020.

Vancouver:

O'Connell E. Networking protocols for long life wireless sensor networks. [Internet] [Thesis]. University College Cork; 2014. [cited 2020 Oct 26]. Available from: http://hdl.handle.net/10468/1896.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

O'Connell E. Networking protocols for long life wireless sensor networks. [Thesis]. University College Cork; 2014. Available from: http://hdl.handle.net/10468/1896

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

[1] [2] [3] [4] [5] … [47]

.