Advanced search options

Advanced Search Options 🞨

Browse by author name (“Author name starts with…”).

Find ETDs with:

in
/  
in
/  
in
/  
in

Written in Published in Earliest date Latest date

Sorted by

Results per page:

Sorted by: relevance · author · university · dateNew search

You searched for subject:(low power). Showing records 1 – 30 of 1258 total matches.

[1] [2] [3] [4] [5] … [42]

Search Limiters

Last 2 Years | English Only

Degrees

Levels

Languages

Country

▼ Search Limiters


University of Canterbury

1. Harding, Thomas. Low power wireless monitoring for wildlife management.

Degree: Engineering Management, 2013, University of Canterbury

 Animal monitoring devices are deployed by the Department of Conservation (DOC) in remote areas. Currently this requires field workers to visit each device on a… (more)

Subjects/Keywords: Wireless; low power

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Harding, T. (2013). Low power wireless monitoring for wildlife management. (Thesis). University of Canterbury. Retrieved from http://hdl.handle.net/10092/7554

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Harding, Thomas. “Low power wireless monitoring for wildlife management.” 2013. Thesis, University of Canterbury. Accessed September 23, 2019. http://hdl.handle.net/10092/7554.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Harding, Thomas. “Low power wireless monitoring for wildlife management.” 2013. Web. 23 Sep 2019.

Vancouver:

Harding T. Low power wireless monitoring for wildlife management. [Internet] [Thesis]. University of Canterbury; 2013. [cited 2019 Sep 23]. Available from: http://hdl.handle.net/10092/7554.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Harding T. Low power wireless monitoring for wildlife management. [Thesis]. University of Canterbury; 2013. Available from: http://hdl.handle.net/10092/7554

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Notre Dame

2. Kamal M Karda. Low Power Bistable-Body Tunnel SRAM</h1>.

Degree: MSin Electrical Engineering, Electrical Engineering, 2009, University of Notre Dame

  A bistable-body tunnel SRAM is proposed and validated using simulations. This cell, using one transistor and two tunnel diodes, is a high speed, low(more)

Subjects/Keywords: SRAM; low power

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Karda, K. M. (2009). Low Power Bistable-Body Tunnel SRAM</h1>. (Masters Thesis). University of Notre Dame. Retrieved from https://curate.nd.edu/show/6395w66534w

Chicago Manual of Style (16th Edition):

Karda, Kamal M. “Low Power Bistable-Body Tunnel SRAM</h1>.” 2009. Masters Thesis, University of Notre Dame. Accessed September 23, 2019. https://curate.nd.edu/show/6395w66534w.

MLA Handbook (7th Edition):

Karda, Kamal M. “Low Power Bistable-Body Tunnel SRAM</h1>.” 2009. Web. 23 Sep 2019.

Vancouver:

Karda KM. Low Power Bistable-Body Tunnel SRAM</h1>. [Internet] [Masters thesis]. University of Notre Dame; 2009. [cited 2019 Sep 23]. Available from: https://curate.nd.edu/show/6395w66534w.

Council of Science Editors:

Karda KM. Low Power Bistable-Body Tunnel SRAM</h1>. [Masters Thesis]. University of Notre Dame; 2009. Available from: https://curate.nd.edu/show/6395w66534w

3. Bengtsson, Mikael. A clock driver with reduced EMI.

Degree: The Institute of Technology, 2014, Linköping UniversityLinköping University

  A clock driver that works on the principle of charging and discharging the clock network in a VLSI circuit in two steps is investigated… (more)

Subjects/Keywords: low-power; clock driver; low EMI

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bengtsson, M. (2014). A clock driver with reduced EMI. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-105673

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bengtsson, Mikael. “A clock driver with reduced EMI.” 2014. Thesis, Linköping UniversityLinköping University. Accessed September 23, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-105673.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bengtsson, Mikael. “A clock driver with reduced EMI.” 2014. Web. 23 Sep 2019.

Vancouver:

Bengtsson M. A clock driver with reduced EMI. [Internet] [Thesis]. Linköping UniversityLinköping University; 2014. [cited 2019 Sep 23]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-105673.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bengtsson M. A clock driver with reduced EMI. [Thesis]. Linköping UniversityLinköping University; 2014. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-105673

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

4. Lu, Dao. K-hot pipelining.

Degree: MS, Electrical & Computer Engr, 2016, University of Illinois – Urbana-Champaign

 Computing systems in almost every application domain now support techniques to trade off power and performance. Such techniques are used to enforce power and thermal… (more)

Subjects/Keywords: Low-Energy and Low-Power Technologies; Microarchitecture

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lu, D. (2016). K-hot pipelining. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/93032

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lu, Dao. “K-hot pipelining.” 2016. Thesis, University of Illinois – Urbana-Champaign. Accessed September 23, 2019. http://hdl.handle.net/2142/93032.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lu, Dao. “K-hot pipelining.” 2016. Web. 23 Sep 2019.

Vancouver:

Lu D. K-hot pipelining. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2016. [cited 2019 Sep 23]. Available from: http://hdl.handle.net/2142/93032.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lu D. K-hot pipelining. [Thesis]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/93032

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

5. Wang, Weihuang. Low power low-density parity-checking (ldpc) codes decoder design using dynamic voltage and frequency scaling.

Degree: 2009, Texas A&M University

 This thesis presents a low-power LDPC decoder design based on speculative scheduling of energy necessary to decode dynamically varying data frame in both block-fading channels… (more)

Subjects/Keywords: VLSI; LDPC; low power

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, W. (2009). Low power low-density parity-checking (ldpc) codes decoder design using dynamic voltage and frequency scaling. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2504

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Weihuang. “Low power low-density parity-checking (ldpc) codes decoder design using dynamic voltage and frequency scaling.” 2009. Thesis, Texas A&M University. Accessed September 23, 2019. http://hdl.handle.net/1969.1/ETD-TAMU-2504.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Weihuang. “Low power low-density parity-checking (ldpc) codes decoder design using dynamic voltage and frequency scaling.” 2009. Web. 23 Sep 2019.

Vancouver:

Wang W. Low power low-density parity-checking (ldpc) codes decoder design using dynamic voltage and frequency scaling. [Internet] [Thesis]. Texas A&M University; 2009. [cited 2019 Sep 23]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2504.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang W. Low power low-density parity-checking (ldpc) codes decoder design using dynamic voltage and frequency scaling. [Thesis]. Texas A&M University; 2009. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2504

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Cincinnati

6. QI, BIN. PERFORMANCE ANALYSIS OF LOCATION CACHE FOR LOW POWER CACHE SYSTEM.

Degree: MS, Engineering : Computer Engineering, 2007, University of Cincinnati

 In modern microprocessors, more memory hierarchy and larger caches are integrated on chip to bridge the performance gap between high-speed CPU core and low speed… (more)

Subjects/Keywords: cache; low power; L2 cache

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

QI, B. (2007). PERFORMANCE ANALYSIS OF LOCATION CACHE FOR LOW POWER CACHE SYSTEM. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1191423845

Chicago Manual of Style (16th Edition):

QI, BIN. “PERFORMANCE ANALYSIS OF LOCATION CACHE FOR LOW POWER CACHE SYSTEM.” 2007. Masters Thesis, University of Cincinnati. Accessed September 23, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1191423845.

MLA Handbook (7th Edition):

QI, BIN. “PERFORMANCE ANALYSIS OF LOCATION CACHE FOR LOW POWER CACHE SYSTEM.” 2007. Web. 23 Sep 2019.

Vancouver:

QI B. PERFORMANCE ANALYSIS OF LOCATION CACHE FOR LOW POWER CACHE SYSTEM. [Internet] [Masters thesis]. University of Cincinnati; 2007. [cited 2019 Sep 23]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1191423845.

Council of Science Editors:

QI B. PERFORMANCE ANALYSIS OF LOCATION CACHE FOR LOW POWER CACHE SYSTEM. [Masters Thesis]. University of Cincinnati; 2007. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1191423845


University of Southern California

7. Shiring, Kenneth J. Gated Multi-Level Domino: a high-speed, low power asynchronous circuit template.

Degree: MS, Computer Engineering, 2010, University of Southern California

 Existing techniques that translate synchronous gate-level circuits into asynchronous counterparts do not adequately support gated clocks and consequently can incur unnecessary switching activity. This thesis… (more)

Subjects/Keywords: asynchronous; low power; de-synchronization

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shiring, K. J. (2010). Gated Multi-Level Domino: a high-speed, low power asynchronous circuit template. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/23581/rec/2961

Chicago Manual of Style (16th Edition):

Shiring, Kenneth J. “Gated Multi-Level Domino: a high-speed, low power asynchronous circuit template.” 2010. Doctoral Dissertation, University of Southern California. Accessed September 23, 2019. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/23581/rec/2961.

MLA Handbook (7th Edition):

Shiring, Kenneth J. “Gated Multi-Level Domino: a high-speed, low power asynchronous circuit template.” 2010. Web. 23 Sep 2019.

Vancouver:

Shiring KJ. Gated Multi-Level Domino: a high-speed, low power asynchronous circuit template. [Internet] [Doctoral dissertation]. University of Southern California; 2010. [cited 2019 Sep 23]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/23581/rec/2961.

Council of Science Editors:

Shiring KJ. Gated Multi-Level Domino: a high-speed, low power asynchronous circuit template. [Doctoral Dissertation]. University of Southern California; 2010. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/23581/rec/2961


University of Illinois – Urbana-Champaign

8. Yap, Wui Chung. 2D material devices for low power logic and memory applications.

Degree: MS, Electrical & Computer Engr, 2016, University of Illinois – Urbana-Champaign

 This thesis investigates low power tunneling field effect transistors (task 1) and low power ferroelectric memory devices (task 2) based on two-dimensional (2D) materials. In… (more)

Subjects/Keywords: 2D materials; Low power

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yap, W. C. (2016). 2D material devices for low power logic and memory applications. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/95528

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yap, Wui Chung. “2D material devices for low power logic and memory applications.” 2016. Thesis, University of Illinois – Urbana-Champaign. Accessed September 23, 2019. http://hdl.handle.net/2142/95528.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yap, Wui Chung. “2D material devices for low power logic and memory applications.” 2016. Web. 23 Sep 2019.

Vancouver:

Yap WC. 2D material devices for low power logic and memory applications. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2016. [cited 2019 Sep 23]. Available from: http://hdl.handle.net/2142/95528.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yap WC. 2D material devices for low power logic and memory applications. [Thesis]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/95528

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

9. Benjaminsen, R.E. Low Power Evaluation for Arbitration and MPSoC:.

Degree: 2010, Delft University of Technology

 This thesis presents a power analysis for various arbitration schemes. We chose variations on the round-robin and time-division multiplexing schemes as our arbiter configurations. The… (more)

Subjects/Keywords: low power; arbitration; mpsoc

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Benjaminsen, R. E. (2010). Low Power Evaluation for Arbitration and MPSoC:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:32f5e7d4-54b5-4fc1-9c46-9da21d17f0d4

Chicago Manual of Style (16th Edition):

Benjaminsen, R E. “Low Power Evaluation for Arbitration and MPSoC:.” 2010. Masters Thesis, Delft University of Technology. Accessed September 23, 2019. http://resolver.tudelft.nl/uuid:32f5e7d4-54b5-4fc1-9c46-9da21d17f0d4.

MLA Handbook (7th Edition):

Benjaminsen, R E. “Low Power Evaluation for Arbitration and MPSoC:.” 2010. Web. 23 Sep 2019.

Vancouver:

Benjaminsen RE. Low Power Evaluation for Arbitration and MPSoC:. [Internet] [Masters thesis]. Delft University of Technology; 2010. [cited 2019 Sep 23]. Available from: http://resolver.tudelft.nl/uuid:32f5e7d4-54b5-4fc1-9c46-9da21d17f0d4.

Council of Science Editors:

Benjaminsen RE. Low Power Evaluation for Arbitration and MPSoC:. [Masters Thesis]. Delft University of Technology; 2010. Available from: http://resolver.tudelft.nl/uuid:32f5e7d4-54b5-4fc1-9c46-9da21d17f0d4


Delft University of Technology

10. Cao, J. Power efficient digital correlator in the scope of an UWB baseband design:.

Degree: 2012, Delft University of Technology

 Ultra Wideband (UWB) radio represents a promising way of communication for low power applications in interference-prone environments. For achieving a low power solution the digital… (more)

Subjects/Keywords: Low power; UWB; correlator

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cao, J. (2012). Power efficient digital correlator in the scope of an UWB baseband design:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:a36ab768-4bae-4729-b874-e1c92dc4380f

Chicago Manual of Style (16th Edition):

Cao, J. “Power efficient digital correlator in the scope of an UWB baseband design:.” 2012. Masters Thesis, Delft University of Technology. Accessed September 23, 2019. http://resolver.tudelft.nl/uuid:a36ab768-4bae-4729-b874-e1c92dc4380f.

MLA Handbook (7th Edition):

Cao, J. “Power efficient digital correlator in the scope of an UWB baseband design:.” 2012. Web. 23 Sep 2019.

Vancouver:

Cao J. Power efficient digital correlator in the scope of an UWB baseband design:. [Internet] [Masters thesis]. Delft University of Technology; 2012. [cited 2019 Sep 23]. Available from: http://resolver.tudelft.nl/uuid:a36ab768-4bae-4729-b874-e1c92dc4380f.

Council of Science Editors:

Cao J. Power efficient digital correlator in the scope of an UWB baseband design:. [Masters Thesis]. Delft University of Technology; 2012. Available from: http://resolver.tudelft.nl/uuid:a36ab768-4bae-4729-b874-e1c92dc4380f


University of Illinois – Urbana-Champaign

11. Sun, Zelei. VAST-LP: clock gating in high-level synthesis.

Degree: MS, Electrical & Computer Engr, 2016, University of Illinois – Urbana-Champaign

 High-level synthesis (HLS) promises high-quality hardware with minimal develop- ment e ort. In this thesis, we evaluate the current state-of-the-art HLS engine VAST and propose… (more)

Subjects/Keywords: low power; high level synthesis

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sun, Z. (2016). VAST-LP: clock gating in high-level synthesis. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/90970

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sun, Zelei. “VAST-LP: clock gating in high-level synthesis.” 2016. Thesis, University of Illinois – Urbana-Champaign. Accessed September 23, 2019. http://hdl.handle.net/2142/90970.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sun, Zelei. “VAST-LP: clock gating in high-level synthesis.” 2016. Web. 23 Sep 2019.

Vancouver:

Sun Z. VAST-LP: clock gating in high-level synthesis. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2016. [cited 2019 Sep 23]. Available from: http://hdl.handle.net/2142/90970.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sun Z. VAST-LP: clock gating in high-level synthesis. [Thesis]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/90970

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rochester Institute of Technology

12. Fitzgerald, Brendan. Drowsy cache partitioning for reduced static and dynamic energy in the cache hierarchy.

Degree: Computer Engineering, 2012, Rochester Institute of Technology

Power consumption in computing today has lead the industry towards energy efficient computing. As transistor technology shrinks, new techniques have to be developed to keep… (more)

Subjects/Keywords: Cache; Energy; Low-power

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Fitzgerald, B. (2012). Drowsy cache partitioning for reduced static and dynamic energy in the cache hierarchy. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/4600

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fitzgerald, Brendan. “Drowsy cache partitioning for reduced static and dynamic energy in the cache hierarchy.” 2012. Thesis, Rochester Institute of Technology. Accessed September 23, 2019. https://scholarworks.rit.edu/theses/4600.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fitzgerald, Brendan. “Drowsy cache partitioning for reduced static and dynamic energy in the cache hierarchy.” 2012. Web. 23 Sep 2019.

Vancouver:

Fitzgerald B. Drowsy cache partitioning for reduced static and dynamic energy in the cache hierarchy. [Internet] [Thesis]. Rochester Institute of Technology; 2012. [cited 2019 Sep 23]. Available from: https://scholarworks.rit.edu/theses/4600.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fitzgerald B. Drowsy cache partitioning for reduced static and dynamic energy in the cache hierarchy. [Thesis]. Rochester Institute of Technology; 2012. Available from: https://scholarworks.rit.edu/theses/4600

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Université de Neuchâtel

13. Shi, Xintian. Design of low phase noise low power CMOS phase locked loops.

Degree: 2008, Université de Neuchâtel

 Phase locked loop (PLL) is one of the most critical devices in modern electronic systems. PLLs are widely used as clock generator or frequency synthesis… (more)

Subjects/Keywords: low power

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shi, X. (2008). Design of low phase noise low power CMOS phase locked loops. (Thesis). Université de Neuchâtel. Retrieved from http://doc.rero.ch/record/11990

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shi, Xintian. “Design of low phase noise low power CMOS phase locked loops.” 2008. Thesis, Université de Neuchâtel. Accessed September 23, 2019. http://doc.rero.ch/record/11990.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shi, Xintian. “Design of low phase noise low power CMOS phase locked loops.” 2008. Web. 23 Sep 2019.

Vancouver:

Shi X. Design of low phase noise low power CMOS phase locked loops. [Internet] [Thesis]. Université de Neuchâtel; 2008. [cited 2019 Sep 23]. Available from: http://doc.rero.ch/record/11990.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shi X. Design of low phase noise low power CMOS phase locked loops. [Thesis]. Université de Neuchâtel; 2008. Available from: http://doc.rero.ch/record/11990

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

14. Hsu, Hua-Shan. Design and Implementation of Power Management Policy on 3D Graphics System-On-Chip.

Degree: Master, Computer Science and Engineering, 2008, NSYSU

 The 3D applications, until recently restricted to the desktops and workstations, are expanding into the mobile platforms, such as cellular phones and PDAs. Similar to… (more)

Subjects/Keywords: power management; low power; workload estimation

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hsu, H. (2008). Design and Implementation of Power Management Policy on 3D Graphics System-On-Chip. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0825108-165911

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hsu, Hua-Shan. “Design and Implementation of Power Management Policy on 3D Graphics System-On-Chip.” 2008. Thesis, NSYSU. Accessed September 23, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0825108-165911.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hsu, Hua-Shan. “Design and Implementation of Power Management Policy on 3D Graphics System-On-Chip.” 2008. Web. 23 Sep 2019.

Vancouver:

Hsu H. Design and Implementation of Power Management Policy on 3D Graphics System-On-Chip. [Internet] [Thesis]. NSYSU; 2008. [cited 2019 Sep 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0825108-165911.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hsu H. Design and Implementation of Power Management Policy on 3D Graphics System-On-Chip. [Thesis]. NSYSU; 2008. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0825108-165911

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

15. Liao, Chi-Sheng. Body-Raised Punch Through CMOS for Low Power Supply Applications.

Degree: Master, Electrical Engineering, 2018, NSYSU

 In this thesis, we propose a punch through complementary metal oxide semiconductor (PTCMOS) with a raised body for suppressing diffusion current (BR-PTCMOS) in low power(more)

Subjects/Keywords: low power dissipation; punch through transistor; power-delay product; CMOS; low power supply

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liao, C. (2018). Body-Raised Punch Through CMOS for Low Power Supply Applications. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0717118-160311

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liao, Chi-Sheng. “Body-Raised Punch Through CMOS for Low Power Supply Applications.” 2018. Thesis, NSYSU. Accessed September 23, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0717118-160311.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liao, Chi-Sheng. “Body-Raised Punch Through CMOS for Low Power Supply Applications.” 2018. Web. 23 Sep 2019.

Vancouver:

Liao C. Body-Raised Punch Through CMOS for Low Power Supply Applications. [Internet] [Thesis]. NSYSU; 2018. [cited 2019 Sep 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0717118-160311.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liao C. Body-Raised Punch Through CMOS for Low Power Supply Applications. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0717118-160311

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

16. Chou, Hung-I. System level power estimation for power manageable System-on-chip.

Degree: Master, Computer Science and Engineering, 2009, NSYSU

 The modern handheld devices have become smaller and more complex nowadays. However, the requirements for its performance and functions have also become higher, which means… (more)

Subjects/Keywords: power management; low-power; framework; power estimation; SystemC; system level

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chou, H. (2009). System level power estimation for power manageable System-on-chip. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0805109-102151

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chou, Hung-I. “System level power estimation for power manageable System-on-chip.” 2009. Thesis, NSYSU. Accessed September 23, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0805109-102151.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chou, Hung-I. “System level power estimation for power manageable System-on-chip.” 2009. Web. 23 Sep 2019.

Vancouver:

Chou H. System level power estimation for power manageable System-on-chip. [Internet] [Thesis]. NSYSU; 2009. [cited 2019 Sep 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0805109-102151.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chou H. System level power estimation for power manageable System-on-chip. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0805109-102151

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

17. ZARIFAKIS, MARIOS. Transient Stability of Power Generating Stations synchronously connected to Low Inertia Electrical Power systems.

Degree: School of Engineering. Discipline of Electronic & Elect. Engineering, 2018, Trinity College Dublin

 The ever-present requirement to decarbonize energy generation, consequently the impetus to increase energy levels from sustainable sources means that wind turbines and solar photovoltaic installations… (more)

Subjects/Keywords: Power Generation; Frequency Stability; Low Inertia Power Systems; Power Transmission; Generators

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

ZARIFAKIS, M. (2018). Transient Stability of Power Generating Stations synchronously connected to Low Inertia Electrical Power systems. (Thesis). Trinity College Dublin. Retrieved from http://hdl.handle.net/2262/82682

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

ZARIFAKIS, MARIOS. “Transient Stability of Power Generating Stations synchronously connected to Low Inertia Electrical Power systems.” 2018. Thesis, Trinity College Dublin. Accessed September 23, 2019. http://hdl.handle.net/2262/82682.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

ZARIFAKIS, MARIOS. “Transient Stability of Power Generating Stations synchronously connected to Low Inertia Electrical Power systems.” 2018. Web. 23 Sep 2019.

Vancouver:

ZARIFAKIS M. Transient Stability of Power Generating Stations synchronously connected to Low Inertia Electrical Power systems. [Internet] [Thesis]. Trinity College Dublin; 2018. [cited 2019 Sep 23]. Available from: http://hdl.handle.net/2262/82682.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

ZARIFAKIS M. Transient Stability of Power Generating Stations synchronously connected to Low Inertia Electrical Power systems. [Thesis]. Trinity College Dublin; 2018. Available from: http://hdl.handle.net/2262/82682

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

18. Gao, Zhuoyang. Comparative Study on Performance and Variation Tolerance of Low Power Circuit.

Degree: 2015, Texas A&M University

 The demand for low-power electronic devices is increasing rapidly in current VLSI technology. Instead of conventional CMOS circuit operating at nominal supply voltage, several kinds… (more)

Subjects/Keywords: low power; adiabatic circuit; near-threshold computing

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gao, Z. (2015). Comparative Study on Performance and Variation Tolerance of Low Power Circuit. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/156528

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gao, Zhuoyang. “Comparative Study on Performance and Variation Tolerance of Low Power Circuit.” 2015. Thesis, Texas A&M University. Accessed September 23, 2019. http://hdl.handle.net/1969.1/156528.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gao, Zhuoyang. “Comparative Study on Performance and Variation Tolerance of Low Power Circuit.” 2015. Web. 23 Sep 2019.

Vancouver:

Gao Z. Comparative Study on Performance and Variation Tolerance of Low Power Circuit. [Internet] [Thesis]. Texas A&M University; 2015. [cited 2019 Sep 23]. Available from: http://hdl.handle.net/1969.1/156528.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gao Z. Comparative Study on Performance and Variation Tolerance of Low Power Circuit. [Thesis]. Texas A&M University; 2015. Available from: http://hdl.handle.net/1969.1/156528

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

19. Singh, Amrinder. Case Studies on Variation Tolerant and Low Power Design Using Planar Asymmetric Double Gate Transistor.

Degree: 2011, Texas A&M University

 In nanometer technologies, process variation control and low power have emerged as the first order design goal after high performance. Process variations cause high variability… (more)

Subjects/Keywords: process variation; double gate; low power

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Singh, A. (2011). Case Studies on Variation Tolerant and Low Power Design Using Planar Asymmetric Double Gate Transistor. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8488

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Singh, Amrinder. “Case Studies on Variation Tolerant and Low Power Design Using Planar Asymmetric Double Gate Transistor.” 2011. Thesis, Texas A&M University. Accessed September 23, 2019. http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8488.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Singh, Amrinder. “Case Studies on Variation Tolerant and Low Power Design Using Planar Asymmetric Double Gate Transistor.” 2011. Web. 23 Sep 2019.

Vancouver:

Singh A. Case Studies on Variation Tolerant and Low Power Design Using Planar Asymmetric Double Gate Transistor. [Internet] [Thesis]. Texas A&M University; 2011. [cited 2019 Sep 23]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8488.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Singh A. Case Studies on Variation Tolerant and Low Power Design Using Planar Asymmetric Double Gate Transistor. [Thesis]. Texas A&M University; 2011. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8488

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Edinburgh

20. Khan, Zahid. Optimization of advanced telecommunication algorithms from power and performance perspective.

Degree: 2011, University of Edinburgh

 This thesis investigates optimization of advanced telecommunication algorithms from power and performance perspectives. The algorithms chosen are MIMO and LDPC. MIMO is implemented in custom… (more)

Subjects/Keywords: 621.382; MIMO; LDPC; low power; VBLAST

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Khan, Z. (2011). Optimization of advanced telecommunication algorithms from power and performance perspective. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/5784

Chicago Manual of Style (16th Edition):

Khan, Zahid. “Optimization of advanced telecommunication algorithms from power and performance perspective.” 2011. Doctoral Dissertation, University of Edinburgh. Accessed September 23, 2019. http://hdl.handle.net/1842/5784.

MLA Handbook (7th Edition):

Khan, Zahid. “Optimization of advanced telecommunication algorithms from power and performance perspective.” 2011. Web. 23 Sep 2019.

Vancouver:

Khan Z. Optimization of advanced telecommunication algorithms from power and performance perspective. [Internet] [Doctoral dissertation]. University of Edinburgh; 2011. [cited 2019 Sep 23]. Available from: http://hdl.handle.net/1842/5784.

Council of Science Editors:

Khan Z. Optimization of advanced telecommunication algorithms from power and performance perspective. [Doctoral Dissertation]. University of Edinburgh; 2011. Available from: http://hdl.handle.net/1842/5784


The Ohio State University

21. Mulyana, Ridwan S. A Low Voltage, Low Power 4th Order Continuous-time Butterworth Filter for Electroencephalography Signal Recognition.

Degree: MS, Electrical and Computer Engineering, 2010, The Ohio State University

 Operational Transconductance Amplifier filter (OTA-C) in biomedical devices have been explored significantly because of its advantages in low power and low voltage design which is… (more)

Subjects/Keywords: Electrical Engineering; ota; eeg filter; low power

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mulyana, R. S. (2010). A Low Voltage, Low Power 4th Order Continuous-time Butterworth Filter for Electroencephalography Signal Recognition. (Masters Thesis). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1281981810

Chicago Manual of Style (16th Edition):

Mulyana, Ridwan S. “A Low Voltage, Low Power 4th Order Continuous-time Butterworth Filter for Electroencephalography Signal Recognition.” 2010. Masters Thesis, The Ohio State University. Accessed September 23, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=osu1281981810.

MLA Handbook (7th Edition):

Mulyana, Ridwan S. “A Low Voltage, Low Power 4th Order Continuous-time Butterworth Filter for Electroencephalography Signal Recognition.” 2010. Web. 23 Sep 2019.

Vancouver:

Mulyana RS. A Low Voltage, Low Power 4th Order Continuous-time Butterworth Filter for Electroencephalography Signal Recognition. [Internet] [Masters thesis]. The Ohio State University; 2010. [cited 2019 Sep 23]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1281981810.

Council of Science Editors:

Mulyana RS. A Low Voltage, Low Power 4th Order Continuous-time Butterworth Filter for Electroencephalography Signal Recognition. [Masters Thesis]. The Ohio State University; 2010. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1281981810


NSYSU

22. Wang, Jiun-ping. Power and Error Reduction Techniques of Multipliers for Multimedia Applications.

Degree: PhD, Computer Science and Engineering, 2010, NSYSU

 Recently, multimedia applications are used widely in many embedded and portable systems, such as mobile phones, MP3 player and PDA, which require lower power consumption… (more)

Subjects/Keywords: low power; multiplier; error compensation circuit

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, J. (2010). Power and Error Reduction Techniques of Multipliers for Multimedia Applications. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0203110-142928

Chicago Manual of Style (16th Edition):

Wang, Jiun-ping. “Power and Error Reduction Techniques of Multipliers for Multimedia Applications.” 2010. Doctoral Dissertation, NSYSU. Accessed September 23, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0203110-142928.

MLA Handbook (7th Edition):

Wang, Jiun-ping. “Power and Error Reduction Techniques of Multipliers for Multimedia Applications.” 2010. Web. 23 Sep 2019.

Vancouver:

Wang J. Power and Error Reduction Techniques of Multipliers for Multimedia Applications. [Internet] [Doctoral dissertation]. NSYSU; 2010. [cited 2019 Sep 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0203110-142928.

Council of Science Editors:

Wang J. Power and Error Reduction Techniques of Multipliers for Multimedia Applications. [Doctoral Dissertation]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0203110-142928


NSYSU

23. Guo, Cang-yuan. Multiple Precision Iterative Floating-Point Multiplier for Low-Power Applications.

Degree: Master, Computer Science and Engineering, 2010, NSYSU

 In many multimedia applications, a little error in the output results is allowable. Therefore, this thesis presents an iterative floating-point multiplier with multiple precision to… (more)

Subjects/Keywords: multiple precision; multiplier; iterative; Low power

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Guo, C. (2010). Multiple Precision Iterative Floating-Point Multiplier for Low-Power Applications. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0203110-215114

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Guo, Cang-yuan. “Multiple Precision Iterative Floating-Point Multiplier for Low-Power Applications.” 2010. Thesis, NSYSU. Accessed September 23, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0203110-215114.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Guo, Cang-yuan. “Multiple Precision Iterative Floating-Point Multiplier for Low-Power Applications.” 2010. Web. 23 Sep 2019.

Vancouver:

Guo C. Multiple Precision Iterative Floating-Point Multiplier for Low-Power Applications. [Internet] [Thesis]. NSYSU; 2010. [cited 2019 Sep 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0203110-215114.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Guo C. Multiple Precision Iterative Floating-Point Multiplier for Low-Power Applications. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0203110-215114

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

24. Pereira dos Santos, Rodolfo. Mecanismo de otimização para redução de potência estática de circuitos integrados baseado na técnica Dual-VTH .

Degree: 2010, Universidade Federal de Pernambuco

 Com o advento de novas tecnologias de fabricação, a complexidade e a capacidade de processamento dos sistemas microeletrônicos tornaram-se cada vez maiores. Contudo devido às… (more)

Subjects/Keywords: Potência estática; CMOS; VLSI; Low-power

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pereira dos Santos, R. (2010). Mecanismo de otimização para redução de potência estática de circuitos integrados baseado na técnica Dual-VTH . (Thesis). Universidade Federal de Pernambuco. Retrieved from http://repositorio.ufpe.br/handle/123456789/2443

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pereira dos Santos, Rodolfo. “Mecanismo de otimização para redução de potência estática de circuitos integrados baseado na técnica Dual-VTH .” 2010. Thesis, Universidade Federal de Pernambuco. Accessed September 23, 2019. http://repositorio.ufpe.br/handle/123456789/2443.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pereira dos Santos, Rodolfo. “Mecanismo de otimização para redução de potência estática de circuitos integrados baseado na técnica Dual-VTH .” 2010. Web. 23 Sep 2019.

Vancouver:

Pereira dos Santos R. Mecanismo de otimização para redução de potência estática de circuitos integrados baseado na técnica Dual-VTH . [Internet] [Thesis]. Universidade Federal de Pernambuco; 2010. [cited 2019 Sep 23]. Available from: http://repositorio.ufpe.br/handle/123456789/2443.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pereira dos Santos R. Mecanismo de otimização para redução de potência estática de circuitos integrados baseado na técnica Dual-VTH . [Thesis]. Universidade Federal de Pernambuco; 2010. Available from: http://repositorio.ufpe.br/handle/123456789/2443

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University College Cork

25. O'Connell, Eoin. Networking protocols for long life wireless sensor networks.

Degree: 2014, University College Cork

 My original contribution to knowledge is the creation of a WSN system that further improves the functionality of existing technology, whilst achieving improved power consumption… (more)

Subjects/Keywords: WSN low-power networking; Wireless sensor networks

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

O'Connell, E. (2014). Networking protocols for long life wireless sensor networks. (Thesis). University College Cork. Retrieved from http://hdl.handle.net/10468/1896

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

O'Connell, Eoin. “Networking protocols for long life wireless sensor networks.” 2014. Thesis, University College Cork. Accessed September 23, 2019. http://hdl.handle.net/10468/1896.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

O'Connell, Eoin. “Networking protocols for long life wireless sensor networks.” 2014. Web. 23 Sep 2019.

Vancouver:

O'Connell E. Networking protocols for long life wireless sensor networks. [Internet] [Thesis]. University College Cork; 2014. [cited 2019 Sep 23]. Available from: http://hdl.handle.net/10468/1896.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

O'Connell E. Networking protocols for long life wireless sensor networks. [Thesis]. University College Cork; 2014. Available from: http://hdl.handle.net/10468/1896

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

26. Mukundrajan, Ravindhiran. Tunnel FET based Field Programmable Gate Arrays.

Degree: MS, Computer Science and Engineering, 2011, Penn State University

 The proliferation of mobile computing systems has created a new segment in the semiconductor ecosystem where energy eciency is the most critical design parameter. Moreover,… (more)

Subjects/Keywords: Emerging nanotech; Tunnel FET; FPGA; Low Power

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mukundrajan, R. (2011). Tunnel FET based Field Programmable Gate Arrays. (Masters Thesis). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/12004

Chicago Manual of Style (16th Edition):

Mukundrajan, Ravindhiran. “Tunnel FET based Field Programmable Gate Arrays.” 2011. Masters Thesis, Penn State University. Accessed September 23, 2019. https://etda.libraries.psu.edu/catalog/12004.

MLA Handbook (7th Edition):

Mukundrajan, Ravindhiran. “Tunnel FET based Field Programmable Gate Arrays.” 2011. Web. 23 Sep 2019.

Vancouver:

Mukundrajan R. Tunnel FET based Field Programmable Gate Arrays. [Internet] [Masters thesis]. Penn State University; 2011. [cited 2019 Sep 23]. Available from: https://etda.libraries.psu.edu/catalog/12004.

Council of Science Editors:

Mukundrajan R. Tunnel FET based Field Programmable Gate Arrays. [Masters Thesis]. Penn State University; 2011. Available from: https://etda.libraries.psu.edu/catalog/12004


University of California – Berkeley

27. Bowonder, Anupama. Low Power Band to Band Tunnel Transistors.

Degree: Electrical Engineering & Computer Sciences, 2010, University of California – Berkeley

 As scaling continues, the number of transistors per unit area and power density are both on the rise. A reduction in Vdd is highly desirable… (more)

Subjects/Keywords: Electrical Engineering; Heterostructure; Low power; Tunneling

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bowonder, A. (2010). Low Power Band to Band Tunnel Transistors. (Thesis). University of California – Berkeley. Retrieved from http://www.escholarship.org/uc/item/8pr4h19x

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bowonder, Anupama. “Low Power Band to Band Tunnel Transistors.” 2010. Thesis, University of California – Berkeley. Accessed September 23, 2019. http://www.escholarship.org/uc/item/8pr4h19x.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bowonder, Anupama. “Low Power Band to Band Tunnel Transistors.” 2010. Web. 23 Sep 2019.

Vancouver:

Bowonder A. Low Power Band to Band Tunnel Transistors. [Internet] [Thesis]. University of California – Berkeley; 2010. [cited 2019 Sep 23]. Available from: http://www.escholarship.org/uc/item/8pr4h19x.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bowonder A. Low Power Band to Band Tunnel Transistors. [Thesis]. University of California – Berkeley; 2010. Available from: http://www.escholarship.org/uc/item/8pr4h19x

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Tennessee – Knoxville

28. Yuan, Song. A Flexible, Highly Integrated, Low Power pH Readout.

Degree: 2018, University of Tennessee – Knoxville

 Medical devices are widely employed in everyday life as wearable and implantable technologies make more and more technological breakthroughs. Implantable biosensors can be implanted into… (more)

Subjects/Keywords: low power; pH measurement; integrated circuit

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Yuan, S. (2018). A Flexible, Highly Integrated, Low Power pH Readout. (Doctoral Dissertation). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_graddiss/4935

Chicago Manual of Style (16th Edition):

Yuan, Song. “A Flexible, Highly Integrated, Low Power pH Readout.” 2018. Doctoral Dissertation, University of Tennessee – Knoxville. Accessed September 23, 2019. https://trace.tennessee.edu/utk_graddiss/4935.

MLA Handbook (7th Edition):

Yuan, Song. “A Flexible, Highly Integrated, Low Power pH Readout.” 2018. Web. 23 Sep 2019.

Vancouver:

Yuan S. A Flexible, Highly Integrated, Low Power pH Readout. [Internet] [Doctoral dissertation]. University of Tennessee – Knoxville; 2018. [cited 2019 Sep 23]. Available from: https://trace.tennessee.edu/utk_graddiss/4935.

Council of Science Editors:

Yuan S. A Flexible, Highly Integrated, Low Power pH Readout. [Doctoral Dissertation]. University of Tennessee – Knoxville; 2018. Available from: https://trace.tennessee.edu/utk_graddiss/4935


University of Illinois – Chicago

29. Onyema, Emmanuel C. Design and CMOS Technology Optimization of a Low Power MEMS Pierce Oscillator.

Degree: 2014, University of Illinois – Chicago

 Particulate matter (PM) consists of air pollutants such as dust, smoke, diesel exhaust and tobacco fumes. A subset of these pollutants, which are PM particles… (more)

Subjects/Keywords: MEMS; Low Power; Optimization; Pierce Oscillator

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Onyema, E. C. (2014). Design and CMOS Technology Optimization of a Low Power MEMS Pierce Oscillator. (Thesis). University of Illinois – Chicago. Retrieved from http://hdl.handle.net/10027/19073

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Onyema, Emmanuel C. “Design and CMOS Technology Optimization of a Low Power MEMS Pierce Oscillator.” 2014. Thesis, University of Illinois – Chicago. Accessed September 23, 2019. http://hdl.handle.net/10027/19073.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Onyema, Emmanuel C. “Design and CMOS Technology Optimization of a Low Power MEMS Pierce Oscillator.” 2014. Web. 23 Sep 2019.

Vancouver:

Onyema EC. Design and CMOS Technology Optimization of a Low Power MEMS Pierce Oscillator. [Internet] [Thesis]. University of Illinois – Chicago; 2014. [cited 2019 Sep 23]. Available from: http://hdl.handle.net/10027/19073.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Onyema EC. Design and CMOS Technology Optimization of a Low Power MEMS Pierce Oscillator. [Thesis]. University of Illinois – Chicago; 2014. Available from: http://hdl.handle.net/10027/19073

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Tech

30. Vivekraja, Vignesh. Low-Power, Stable and Secure On-Chip Identifiers Design.

Degree: MS, Electrical and Computer Engineering, 2010, Virginia Tech

 Trustworthy authentication of an object is of extreme importance for secure protocols. Traditional methods of storing the identity of an object using non-volatile memory is… (more)

Subjects/Keywords: Hardware Security; Low Power; Process Variation; PUF

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vivekraja, V. (2010). Low-Power, Stable and Secure On-Chip Identifiers Design. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34854

Chicago Manual of Style (16th Edition):

Vivekraja, Vignesh. “Low-Power, Stable and Secure On-Chip Identifiers Design.” 2010. Masters Thesis, Virginia Tech. Accessed September 23, 2019. http://hdl.handle.net/10919/34854.

MLA Handbook (7th Edition):

Vivekraja, Vignesh. “Low-Power, Stable and Secure On-Chip Identifiers Design.” 2010. Web. 23 Sep 2019.

Vancouver:

Vivekraja V. Low-Power, Stable and Secure On-Chip Identifiers Design. [Internet] [Masters thesis]. Virginia Tech; 2010. [cited 2019 Sep 23]. Available from: http://hdl.handle.net/10919/34854.

Council of Science Editors:

Vivekraja V. Low-Power, Stable and Secure On-Chip Identifiers Design. [Masters Thesis]. Virginia Tech; 2010. Available from: http://hdl.handle.net/10919/34854

[1] [2] [3] [4] [5] … [42]

.