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You searched for subject:(input offset voltage). Showing records 1 – 3 of 3 total matches.

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California State University – Sacramento

1. Pham, Hao Qui. Intergration of a dynamic offset testbench to measure comparator offsets in 0.18um CMOS.

Degree: MS, Electrical and Electronic Engineering, 2020, California State University – Sacramento

High-speed latching comparators are important building blocks in analog and mixed-signal integrated circuits (ICs) such as analog-to-digital converters. A key performance parameter of these comparators is the input offset voltage. A simulation technique called the dynamic offset test bench (DOTB) is used to obtain the input offset voltage during the design process. In simulations, a transistor-level design of the comparator to be fabricated is connected to the DOTB. The DOTB is used in simulations comprises idealized virtual components and therefore cannot be fabricated. This project comprises the transistor-level design and simulation of a DOTB for fabrication in a particular IC design process. The eventual goal is to use a DOTB to test real comparators (i.e., comparators in silicon rather than in simulations). The data gathered can be used to create more accurate models of comparator performance. Important performance aspects of the silicon DOTB have been determined from simulations and indicate that it is practical to construct and will be useful for testing. Simulations testing the DOTB performance have been performed across process, supply voltage, and temperature (PVT) variations. An issue that could affect accuracy has been detected, and the mechanism causing it has been identified. Advisors/Committee Members: Heedley, Perry L..

Subjects/Keywords: Input referred offset voltage of comparator; Top-level DOTB design and simulations; Fully-differential DOTB

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APA (6th Edition):

Pham, H. Q. (2020). Intergration of a dynamic offset testbench to measure comparator offsets in 0.18um CMOS. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.3/216894

Chicago Manual of Style (16th Edition):

Pham, Hao Qui. “Intergration of a dynamic offset testbench to measure comparator offsets in 0.18um CMOS.” 2020. Masters Thesis, California State University – Sacramento. Accessed September 20, 2020. http://hdl.handle.net/10211.3/216894.

MLA Handbook (7th Edition):

Pham, Hao Qui. “Intergration of a dynamic offset testbench to measure comparator offsets in 0.18um CMOS.” 2020. Web. 20 Sep 2020.

Vancouver:

Pham HQ. Intergration of a dynamic offset testbench to measure comparator offsets in 0.18um CMOS. [Internet] [Masters thesis]. California State University – Sacramento; 2020. [cited 2020 Sep 20]. Available from: http://hdl.handle.net/10211.3/216894.

Council of Science Editors:

Pham HQ. Intergration of a dynamic offset testbench to measure comparator offsets in 0.18um CMOS. [Masters Thesis]. California State University – Sacramento; 2020. Available from: http://hdl.handle.net/10211.3/216894

2. Bommireddipalli, Aditya Vighnesh Ramakanth. Design of a Precision Low Voltage Resistor Multiplying Digital-to-Analog Converter.

Degree: MS, Electrical Engineering, 2017, Texas A&M University

This work aims to model the effect of the input offset voltage of an operational amplifier on the performance of a high-precision, voltage-mode, resistor-based multiplying digital-to-analog converter (M-DAC). Based on the model, a high precision current buffer is proposed to isolate the resistor ladder from the operational amplifier. A 14-bit M-DAC operating with a ±1V reference of the proposed architecture. Post-layout simulations show that the proposed architecture reduces the offset voltage to an offset error in the DAC transfer function. The maximum DNL is maintained at -0.385 LSB for an input offset voltage of up to 60mV (1024 LSB). The current buffer also introduces an inversion of the output voltage, yielding a non-inverted output. This alleviates the need for an additional high precision op-amp to invert the output voltage. Advisors/Committee Members: Karsilayan, Aydin I (advisor), Silva-Martinez, Jose (advisor), Khatri, Sunil (committee member), Hur, Pilwon (committee member).

Subjects/Keywords: DAC; input offset voltage; high-precision; current buffer

…currents (≤1pA). The input offset voltage is defined in [14] as the voltage… …transistors and components during fabrication. In CMOS amplifiers the input offset voltage is… …x29; from the TIA making the DAC insensitive to the amplifier’s input offset voltage… …offset voltage reduced to offset error . . . . . . . . . . . . . . . . . 34 4.6 Step… …converts a multi-bit digital input signal to an analog output voltage or current. In most cases… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bommireddipalli, A. V. R. (2017). Design of a Precision Low Voltage Resistor Multiplying Digital-to-Analog Converter. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/165708

Chicago Manual of Style (16th Edition):

Bommireddipalli, Aditya Vighnesh Ramakanth. “Design of a Precision Low Voltage Resistor Multiplying Digital-to-Analog Converter.” 2017. Masters Thesis, Texas A&M University. Accessed September 20, 2020. http://hdl.handle.net/1969.1/165708.

MLA Handbook (7th Edition):

Bommireddipalli, Aditya Vighnesh Ramakanth. “Design of a Precision Low Voltage Resistor Multiplying Digital-to-Analog Converter.” 2017. Web. 20 Sep 2020.

Vancouver:

Bommireddipalli AVR. Design of a Precision Low Voltage Resistor Multiplying Digital-to-Analog Converter. [Internet] [Masters thesis]. Texas A&M University; 2017. [cited 2020 Sep 20]. Available from: http://hdl.handle.net/1969.1/165708.

Council of Science Editors:

Bommireddipalli AVR. Design of a Precision Low Voltage Resistor Multiplying Digital-to-Analog Converter. [Masters Thesis]. Texas A&M University; 2017. Available from: http://hdl.handle.net/1969.1/165708

3. Khan, M.A. On improving dependability of analog and mixed-signal SoCs: A system-level approach.

Degree: 2014, University of Twente

Dependability of electronic systems, being an indispensable part of our civilian, industrial and military applications, has become increasingly important as a result of continuous technology scaling. The dependability or human reliance on these electronic systems has decreased as a result of new technologies which are far less mature as compared to older technologies. The electrical characteristics of the transistors and the wires will vary statistically in a spatial and temporal manner, directly translating into design uncertainty during fabrication and even during operational life. This combined impact of manufacturing uncertainty (e.g. process variability) and temporal degradation (aging) results in time-dependent variability and hence the means to impact the functionality and dependability of electronic systems. Unfortunately, traditional worst-case design slacks or margins are not sufficient anymore to capture the time-dependent system variability, especially in new technology nodes, and would result in over-pessimistic implementations with significant penalties in terms of area/delay/energy. As a result, time-dependent uncertainties become a great threat to the design of complex systems-on-chip (SoC) implementations and their dependability. It becomes extremely important in case of safety- or mission-critical systems because the dependability failure of these systems may result in enormous cost damage or even loss of human lives. Therefore, maintaining or achieving high system dependability in safety- or mission-critical systems is the most important property. Analog and mixed-signal front/back ends, being an important part of most critical systems especially in safety-critical (e.g. automotive, medical etc.) and mission-critical (e.g. military, space etc.) systems have received relatively little attention with regard to dependability. The dependability of these analog and mixed-signal front/back ends is essential in order to have a dependable interface between the real world and digital world. This is the main goal of the current research where new system-level strategies have been explored and investigated in order to enhance the dependability of analog and mixed-signal front ends especially during their operational life. Advisors/Committee Members: Smit, Gerardus Johannes Maria, Kerkhoff, Hans Gerard.

Subjects/Keywords: METIS-306179; IR-92381; Analog and mixed-signal dependability; Markov analysis; Degradation modelling; Dependable systems; Sensitivity analysis; offset voltage; design space exploration for dependable system; behavioral modeling; input signal monitoring; charge-redistribution SAR ADC; temperature monitoring; lifetime prediction; self-diagnosis; dependability characterization; dependability recovery scheme; dependable IPs; dependable design; EWI-25253; CAES-TDT: Testable Design and Test; self-calibration hardware redundancy; time befor failure

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Khan, M. A. (2014). On improving dependability of analog and mixed-signal SoCs: A system-level approach. (Doctoral Dissertation). University of Twente. Retrieved from https://research.utwente.nl/en/publications/on-improving-dependability-of-analog-and-mixedsignal-socs-a-systemlevel-approach(15f74800-7d1b-4f1d-9df4-517dbf28d17e).html ; urn:nbn:nl:ui:28-92381 ; 15f74800-7d1b-4f1d-9df4-517dbf28d17e ; 10.3990/1.9789036537773 ; urn:isbn:978-90-365-3777-3 ; urn:nbn:nl:ui:28-92381 ; https://research.utwente.nl/en/publications/on-improving-dependability-of-analog-and-mixedsignal-socs-a-systemlevel-approach(15f74800-7d1b-4f1d-9df4-517dbf28d17e).html

Chicago Manual of Style (16th Edition):

Khan, M A. “On improving dependability of analog and mixed-signal SoCs: A system-level approach.” 2014. Doctoral Dissertation, University of Twente. Accessed September 20, 2020. https://research.utwente.nl/en/publications/on-improving-dependability-of-analog-and-mixedsignal-socs-a-systemlevel-approach(15f74800-7d1b-4f1d-9df4-517dbf28d17e).html ; urn:nbn:nl:ui:28-92381 ; 15f74800-7d1b-4f1d-9df4-517dbf28d17e ; 10.3990/1.9789036537773 ; urn:isbn:978-90-365-3777-3 ; urn:nbn:nl:ui:28-92381 ; https://research.utwente.nl/en/publications/on-improving-dependability-of-analog-and-mixedsignal-socs-a-systemlevel-approach(15f74800-7d1b-4f1d-9df4-517dbf28d17e).html.

MLA Handbook (7th Edition):

Khan, M A. “On improving dependability of analog and mixed-signal SoCs: A system-level approach.” 2014. Web. 20 Sep 2020.

Vancouver:

Khan MA. On improving dependability of analog and mixed-signal SoCs: A system-level approach. [Internet] [Doctoral dissertation]. University of Twente; 2014. [cited 2020 Sep 20]. Available from: https://research.utwente.nl/en/publications/on-improving-dependability-of-analog-and-mixedsignal-socs-a-systemlevel-approach(15f74800-7d1b-4f1d-9df4-517dbf28d17e).html ; urn:nbn:nl:ui:28-92381 ; 15f74800-7d1b-4f1d-9df4-517dbf28d17e ; 10.3990/1.9789036537773 ; urn:isbn:978-90-365-3777-3 ; urn:nbn:nl:ui:28-92381 ; https://research.utwente.nl/en/publications/on-improving-dependability-of-analog-and-mixedsignal-socs-a-systemlevel-approach(15f74800-7d1b-4f1d-9df4-517dbf28d17e).html.

Council of Science Editors:

Khan MA. On improving dependability of analog and mixed-signal SoCs: A system-level approach. [Doctoral Dissertation]. University of Twente; 2014. Available from: https://research.utwente.nl/en/publications/on-improving-dependability-of-analog-and-mixedsignal-socs-a-systemlevel-approach(15f74800-7d1b-4f1d-9df4-517dbf28d17e).html ; urn:nbn:nl:ui:28-92381 ; 15f74800-7d1b-4f1d-9df4-517dbf28d17e ; 10.3990/1.9789036537773 ; urn:isbn:978-90-365-3777-3 ; urn:nbn:nl:ui:28-92381 ; https://research.utwente.nl/en/publications/on-improving-dependability-of-analog-and-mixedsignal-socs-a-systemlevel-approach(15f74800-7d1b-4f1d-9df4-517dbf28d17e).html

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