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California State University – Sacramento

1. Pham, Hao Qui. Intergration of a dynamic offset testbench to measure comparator offsets in 0.18um CMOS.

Degree: MS, Electrical and Electronic Engineering, 2020, California State University – Sacramento

High-speed latching comparators are important building blocks in analog and mixed-signal integrated circuits (ICs) such as analog-to-digital converters. A key performance parameter of these comparators is the input offset voltage. A simulation technique called the dynamic offset test bench (DOTB) is used to obtain the input offset voltage during the design process. In simulations, a transistor-level design of the comparator to be fabricated is connected to the DOTB. The DOTB is used in simulations comprises idealized virtual components and therefore cannot be fabricated. This project comprises the transistor-level design and simulation of a DOTB for fabrication in a particular IC design process. The eventual goal is to use a DOTB to test real comparators (i.e., comparators in silicon rather than in simulations). The data gathered can be used to create more accurate models of comparator performance. Important performance aspects of the silicon DOTB have been determined from simulations and indicate that it is practical to construct and will be useful for testing. Simulations testing the DOTB performance have been performed across process, supply voltage, and temperature (PVT) variations. An issue that could affect accuracy has been detected, and the mechanism causing it has been identified. Advisors/Committee Members: Heedley, Perry L..

Subjects/Keywords: Input referred offset voltage of comparator; Top-level DOTB design and simulations; Fully-differential DOTB

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pham, H. Q. (2020). Intergration of a dynamic offset testbench to measure comparator offsets in 0.18um CMOS. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.3/216894

Chicago Manual of Style (16th Edition):

Pham, Hao Qui. “Intergration of a dynamic offset testbench to measure comparator offsets in 0.18um CMOS.” 2020. Masters Thesis, California State University – Sacramento. Accessed September 20, 2020. http://hdl.handle.net/10211.3/216894.

MLA Handbook (7th Edition):

Pham, Hao Qui. “Intergration of a dynamic offset testbench to measure comparator offsets in 0.18um CMOS.” 2020. Web. 20 Sep 2020.

Vancouver:

Pham HQ. Intergration of a dynamic offset testbench to measure comparator offsets in 0.18um CMOS. [Internet] [Masters thesis]. California State University – Sacramento; 2020. [cited 2020 Sep 20]. Available from: http://hdl.handle.net/10211.3/216894.

Council of Science Editors:

Pham HQ. Intergration of a dynamic offset testbench to measure comparator offsets in 0.18um CMOS. [Masters Thesis]. California State University – Sacramento; 2020. Available from: http://hdl.handle.net/10211.3/216894

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