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You searched for subject:(heterogeneous memory). Showing records 1 – 30 of 37 total matches.

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University of North Texas

1. Islam, Mahzabeen. A Study on Flat-Address-Space Heterogeneous Memory Architectures.

Degree: 2019, University of North Texas

 In this dissertation, we present a number of studies that primarily focus on data movement challenges among different types of memories (viz., 3D-DRAM, DDRx DRAM… (more)

Subjects/Keywords: heterogeneous memory; flat-address memory; non-volatile memory; prefetching; page migration

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APA (6th Edition):

Islam, M. (2019). A Study on Flat-Address-Space Heterogeneous Memory Architectures. (Thesis). University of North Texas. Retrieved from https://digital.library.unt.edu/ark:/67531/metadc1505134/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Islam, Mahzabeen. “A Study on Flat-Address-Space Heterogeneous Memory Architectures.” 2019. Thesis, University of North Texas. Accessed October 14, 2019. https://digital.library.unt.edu/ark:/67531/metadc1505134/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Islam, Mahzabeen. “A Study on Flat-Address-Space Heterogeneous Memory Architectures.” 2019. Web. 14 Oct 2019.

Vancouver:

Islam M. A Study on Flat-Address-Space Heterogeneous Memory Architectures. [Internet] [Thesis]. University of North Texas; 2019. [cited 2019 Oct 14]. Available from: https://digital.library.unt.edu/ark:/67531/metadc1505134/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Islam M. A Study on Flat-Address-Space Heterogeneous Memory Architectures. [Thesis]. University of North Texas; 2019. Available from: https://digital.library.unt.edu/ark:/67531/metadc1505134/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

2. Alsop, Johnathan R. Specialization without complexity in heterogeneous memory systems.

Degree: PhD, Electrical & Computer Engr, 2018, University of Illinois – Urbana-Champaign

 The end of Dennard scaling and Moore's law has motivated a rise in the use of parallelism and hardware specialization in computer system design. Across… (more)

Subjects/Keywords: heterogeneous computing; coherence; consistency; memory systems; GPU

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APA (6th Edition):

Alsop, J. R. (2018). Specialization without complexity in heterogeneous memory systems. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/102480

Chicago Manual of Style (16th Edition):

Alsop, Johnathan R. “Specialization without complexity in heterogeneous memory systems.” 2018. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed October 14, 2019. http://hdl.handle.net/2142/102480.

MLA Handbook (7th Edition):

Alsop, Johnathan R. “Specialization without complexity in heterogeneous memory systems.” 2018. Web. 14 Oct 2019.

Vancouver:

Alsop JR. Specialization without complexity in heterogeneous memory systems. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2018. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/2142/102480.

Council of Science Editors:

Alsop JR. Specialization without complexity in heterogeneous memory systems. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2018. Available from: http://hdl.handle.net/2142/102480


University of Tennessee – Knoxville

3. Teague, Joseph Townley. Low-Overhead Migration of Read-Only and Read-Mostly Data for Adapting Applications to Hybrid Memory Systems.

Degree: MS, Computer Science, 2018, University of Tennessee – Knoxville

Memory systems containing different types of memory with varying capacity, latency, and bandwidth are rapidly becoming mainstream. Conventional memory management techniques do not suffice for… (more)

Subjects/Keywords: memory management; heterogeneous memory architectures; hybrid memory architectures; page migration; migration overhead; translation lookaside buffer

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APA (6th Edition):

Teague, J. T. (2018). Low-Overhead Migration of Read-Only and Read-Mostly Data for Adapting Applications to Hybrid Memory Systems. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/5379

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Teague, Joseph Townley. “Low-Overhead Migration of Read-Only and Read-Mostly Data for Adapting Applications to Hybrid Memory Systems.” 2018. Thesis, University of Tennessee – Knoxville. Accessed October 14, 2019. https://trace.tennessee.edu/utk_gradthes/5379.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Teague, Joseph Townley. “Low-Overhead Migration of Read-Only and Read-Mostly Data for Adapting Applications to Hybrid Memory Systems.” 2018. Web. 14 Oct 2019.

Vancouver:

Teague JT. Low-Overhead Migration of Read-Only and Read-Mostly Data for Adapting Applications to Hybrid Memory Systems. [Internet] [Thesis]. University of Tennessee – Knoxville; 2018. [cited 2019 Oct 14]. Available from: https://trace.tennessee.edu/utk_gradthes/5379.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Teague JT. Low-Overhead Migration of Read-Only and Read-Mostly Data for Adapting Applications to Hybrid Memory Systems. [Thesis]. University of Tennessee – Knoxville; 2018. Available from: https://trace.tennessee.edu/utk_gradthes/5379

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Kansas

4. Sengupta, Saikat. Understanding Memory Access Behavior for Heterogeneous Memory Systems.

Degree: MS, Electrical Engineering & Computer Science, 2018, University of Kansas

 Present day manufacturers have invented different memory technologies with distinct bandwidth, energy and cost trade-offs. Systems with such heterogeneous memory technologies can only achieve the… (more)

Subjects/Keywords: Computer engineering; Computer science; Access behavior; Heterogeneous Memory; Intel pinplay; Memory; Memory Pages; Similarity Metric

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APA (6th Edition):

Sengupta, S. (2018). Understanding Memory Access Behavior for Heterogeneous Memory Systems. (Masters Thesis). University of Kansas. Retrieved from http://hdl.handle.net/1808/27768

Chicago Manual of Style (16th Edition):

Sengupta, Saikat. “Understanding Memory Access Behavior for Heterogeneous Memory Systems.” 2018. Masters Thesis, University of Kansas. Accessed October 14, 2019. http://hdl.handle.net/1808/27768.

MLA Handbook (7th Edition):

Sengupta, Saikat. “Understanding Memory Access Behavior for Heterogeneous Memory Systems.” 2018. Web. 14 Oct 2019.

Vancouver:

Sengupta S. Understanding Memory Access Behavior for Heterogeneous Memory Systems. [Internet] [Masters thesis]. University of Kansas; 2018. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/1808/27768.

Council of Science Editors:

Sengupta S. Understanding Memory Access Behavior for Heterogeneous Memory Systems. [Masters Thesis]. University of Kansas; 2018. Available from: http://hdl.handle.net/1808/27768


University of Illinois – Chicago

5. Ghiozzi, Fabio. Priority-Based Memory Access Scheduling for CPU-GPU Workloads.

Degree: 2015, University of Illinois – Chicago

 This thesis work is developed to design and implement a brand new Memory Access Scheduling Algorithm for CPU-GPU heterogeneous architectures. The ultimate goal is to… (more)

Subjects/Keywords: Heterogeneous Systems; Computer Architectures; CPU; GPU; Main Memory; Memory Controller; Memory Accesses Scheduling; Memory Scheduling Algorithm

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APA (6th Edition):

Ghiozzi, F. (2015). Priority-Based Memory Access Scheduling for CPU-GPU Workloads. (Thesis). University of Illinois – Chicago. Retrieved from http://hdl.handle.net/10027/19844

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ghiozzi, Fabio. “Priority-Based Memory Access Scheduling for CPU-GPU Workloads.” 2015. Thesis, University of Illinois – Chicago. Accessed October 14, 2019. http://hdl.handle.net/10027/19844.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ghiozzi, Fabio. “Priority-Based Memory Access Scheduling for CPU-GPU Workloads.” 2015. Web. 14 Oct 2019.

Vancouver:

Ghiozzi F. Priority-Based Memory Access Scheduling for CPU-GPU Workloads. [Internet] [Thesis]. University of Illinois – Chicago; 2015. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/10027/19844.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ghiozzi F. Priority-Based Memory Access Scheduling for CPU-GPU Workloads. [Thesis]. University of Illinois – Chicago; 2015. Available from: http://hdl.handle.net/10027/19844

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

6. Kannan, Sudarsun. OS support for heterogeneous memory.

Degree: PhD, Computer Science, 2016, Georgia Tech

 To address the 'memory wall' problem of future systems, vendors are creating heterogeneous memory structures, supplementing DRAM with on-chip stacked 3D-RAM and high capacity non-volatile… (more)

Subjects/Keywords: Heterogeneous memory; OS memory management; NVM; Cache; Persistence; Object storage; ACID; Energy

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APA (6th Edition):

Kannan, S. (2016). OS support for heterogeneous memory. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55660

Chicago Manual of Style (16th Edition):

Kannan, Sudarsun. “OS support for heterogeneous memory.” 2016. Doctoral Dissertation, Georgia Tech. Accessed October 14, 2019. http://hdl.handle.net/1853/55660.

MLA Handbook (7th Edition):

Kannan, Sudarsun. “OS support for heterogeneous memory.” 2016. Web. 14 Oct 2019.

Vancouver:

Kannan S. OS support for heterogeneous memory. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/1853/55660.

Council of Science Editors:

Kannan S. OS support for heterogeneous memory. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/55660


University of California – San Diego

7. Song, Yang. On Quality-of-Service and Memory Efficiency in Heterogeneous MPSoCs.

Degree: Electrical and Computer Engineering, 2019, University of California – San Diego

 Due to their energy efficiency, heterogeneous Multi-Processor Systems-on-Chip (MPSoCs) are widely deployed as the engines for modern-day smart devices. As smart devices prevail, heterogeneous MPSoCs… (more)

Subjects/Keywords: Computer engineering; Heterogeneous systems; Memory efficiency; Memory subsystem; Quality-of-service; SoC

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APA (6th Edition):

Song, Y. (2019). On Quality-of-Service and Memory Efficiency in Heterogeneous MPSoCs. (Thesis). University of California – San Diego. Retrieved from http://www.escholarship.org/uc/item/72x5j5vg

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Song, Yang. “On Quality-of-Service and Memory Efficiency in Heterogeneous MPSoCs.” 2019. Thesis, University of California – San Diego. Accessed October 14, 2019. http://www.escholarship.org/uc/item/72x5j5vg.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Song, Yang. “On Quality-of-Service and Memory Efficiency in Heterogeneous MPSoCs.” 2019. Web. 14 Oct 2019.

Vancouver:

Song Y. On Quality-of-Service and Memory Efficiency in Heterogeneous MPSoCs. [Internet] [Thesis]. University of California – San Diego; 2019. [cited 2019 Oct 14]. Available from: http://www.escholarship.org/uc/item/72x5j5vg.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Song Y. On Quality-of-Service and Memory Efficiency in Heterogeneous MPSoCs. [Thesis]. University of California – San Diego; 2019. Available from: http://www.escholarship.org/uc/item/72x5j5vg

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

8. Khasanvis, Santosh. Heterogeneous Graphene Nanoribbon-CMOS Multi-State Volatile Random Access Memory Fabric.

Degree: MS, Electrical & Computer Engineering, 2012, University of Massachusetts

  CMOS SRAM area scaling is slowing down due to several challenges faced by transistors at nanoscale such as increased leakage. This calls for new… (more)

Subjects/Keywords: Graphene; GNTRAM; heterogeneous memory; multistate memory; graphene nanoribbons; Computer Engineering; Nanoscience and Nanotechnology

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APA (6th Edition):

Khasanvis, S. (2012). Heterogeneous Graphene Nanoribbon-CMOS Multi-State Volatile Random Access Memory Fabric. (Masters Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/theses/919

Chicago Manual of Style (16th Edition):

Khasanvis, Santosh. “Heterogeneous Graphene Nanoribbon-CMOS Multi-State Volatile Random Access Memory Fabric.” 2012. Masters Thesis, University of Massachusetts. Accessed October 14, 2019. https://scholarworks.umass.edu/theses/919.

MLA Handbook (7th Edition):

Khasanvis, Santosh. “Heterogeneous Graphene Nanoribbon-CMOS Multi-State Volatile Random Access Memory Fabric.” 2012. Web. 14 Oct 2019.

Vancouver:

Khasanvis S. Heterogeneous Graphene Nanoribbon-CMOS Multi-State Volatile Random Access Memory Fabric. [Internet] [Masters thesis]. University of Massachusetts; 2012. [cited 2019 Oct 14]. Available from: https://scholarworks.umass.edu/theses/919.

Council of Science Editors:

Khasanvis S. Heterogeneous Graphene Nanoribbon-CMOS Multi-State Volatile Random Access Memory Fabric. [Masters Thesis]. University of Massachusetts; 2012. Available from: https://scholarworks.umass.edu/theses/919

9. Lustig, Daniel Joseph. Specifying, Verifying, and Translating Between Memory Consistency Models .

Degree: PhD, 2015, Princeton University

 In modern hardware, inter-core communication takes place through shared virtual memory and according to the memory consistency model – the set of rules and guarantees about… (more)

Subjects/Keywords: Computer Architecture; Heterogeneous Systems; Memory Consistency Models; Parallel Computing

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APA (6th Edition):

Lustig, D. J. (2015). Specifying, Verifying, and Translating Between Memory Consistency Models . (Doctoral Dissertation). Princeton University. Retrieved from http://arks.princeton.edu/ark:/88435/dsp01nz806207p

Chicago Manual of Style (16th Edition):

Lustig, Daniel Joseph. “Specifying, Verifying, and Translating Between Memory Consistency Models .” 2015. Doctoral Dissertation, Princeton University. Accessed October 14, 2019. http://arks.princeton.edu/ark:/88435/dsp01nz806207p.

MLA Handbook (7th Edition):

Lustig, Daniel Joseph. “Specifying, Verifying, and Translating Between Memory Consistency Models .” 2015. Web. 14 Oct 2019.

Vancouver:

Lustig DJ. Specifying, Verifying, and Translating Between Memory Consistency Models . [Internet] [Doctoral dissertation]. Princeton University; 2015. [cited 2019 Oct 14]. Available from: http://arks.princeton.edu/ark:/88435/dsp01nz806207p.

Council of Science Editors:

Lustig DJ. Specifying, Verifying, and Translating Between Memory Consistency Models . [Doctoral Dissertation]. Princeton University; 2015. Available from: http://arks.princeton.edu/ark:/88435/dsp01nz806207p


NSYSU

10. Wu, Jhih-Yong. Bus Topology Exploration and Memory Allocation for Heterogeneous Systems.

Degree: Master, Computer Science and Engineering, 2007, NSYSU

 Since semiconductor process is constantly being improved, the complexity of system-on-chip is rising daily and we can place more and more elements on the same… (more)

Subjects/Keywords: allocation; exploration; memory; bus; heterogeneous system

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APA (6th Edition):

Wu, J. (2007). Bus Topology Exploration and Memory Allocation for Heterogeneous Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0802107-155041

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Jhih-Yong. “Bus Topology Exploration and Memory Allocation for Heterogeneous Systems.” 2007. Thesis, NSYSU. Accessed October 14, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0802107-155041.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Jhih-Yong. “Bus Topology Exploration and Memory Allocation for Heterogeneous Systems.” 2007. Web. 14 Oct 2019.

Vancouver:

Wu J. Bus Topology Exploration and Memory Allocation for Heterogeneous Systems. [Internet] [Thesis]. NSYSU; 2007. [cited 2019 Oct 14]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0802107-155041.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu J. Bus Topology Exploration and Memory Allocation for Heterogeneous Systems. [Thesis]. NSYSU; 2007. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0802107-155041

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Tennessee – Knoxville

11. Howard, Adam Palmer. Automated Program Profiling and Analysis for Managing Heterogeneous Memory Systems.

Degree: MS, Computer Science, 2017, University of Tennessee – Knoxville

  Many promising memory technologies, such as non-volatile, storage-class memories and high-bandwidth, on-chip RAMs, are beginning to emerge. Since each of these new technologies present… (more)

Subjects/Keywords: heterogeneous memory; high-bandwidth memory; program profiling; performance; Computer and Systems Architecture; Programming Languages and Compilers; Systems Architecture

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APA (6th Edition):

Howard, A. P. (2017). Automated Program Profiling and Analysis for Managing Heterogeneous Memory Systems. (Thesis). University of Tennessee – Knoxville. Retrieved from https://trace.tennessee.edu/utk_gradthes/4949

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Howard, Adam Palmer. “Automated Program Profiling and Analysis for Managing Heterogeneous Memory Systems.” 2017. Thesis, University of Tennessee – Knoxville. Accessed October 14, 2019. https://trace.tennessee.edu/utk_gradthes/4949.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Howard, Adam Palmer. “Automated Program Profiling and Analysis for Managing Heterogeneous Memory Systems.” 2017. Web. 14 Oct 2019.

Vancouver:

Howard AP. Automated Program Profiling and Analysis for Managing Heterogeneous Memory Systems. [Internet] [Thesis]. University of Tennessee – Knoxville; 2017. [cited 2019 Oct 14]. Available from: https://trace.tennessee.edu/utk_gradthes/4949.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Howard AP. Automated Program Profiling and Analysis for Managing Heterogeneous Memory Systems. [Thesis]. University of Tennessee – Knoxville; 2017. Available from: https://trace.tennessee.edu/utk_gradthes/4949

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

12. Sinclair, Matthew David. Efficient coherence and consistency for specialized memory hierarchies.

Degree: PhD, Computer Science, 2017, University of Illinois – Urbana-Champaign

 As the benefits from transistor scaling slow down, specialization is becoming increasingly important for a wide range of applications. Although traditional heterogeneous systems work well… (more)

Subjects/Keywords: Shared memory; Heterogeneous systems; General purpose graphics processing unit (GPGPU); Caches memories; Cache coherence; Memory consistency; Scratchpads; Fine-grained synchronization

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APA (6th Edition):

Sinclair, M. D. (2017). Efficient coherence and consistency for specialized memory hierarchies. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99316

Chicago Manual of Style (16th Edition):

Sinclair, Matthew David. “Efficient coherence and consistency for specialized memory hierarchies.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed October 14, 2019. http://hdl.handle.net/2142/99316.

MLA Handbook (7th Edition):

Sinclair, Matthew David. “Efficient coherence and consistency for specialized memory hierarchies.” 2017. Web. 14 Oct 2019.

Vancouver:

Sinclair MD. Efficient coherence and consistency for specialized memory hierarchies. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/2142/99316.

Council of Science Editors:

Sinclair MD. Efficient coherence and consistency for specialized memory hierarchies. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99316

13. Brunie, Hugo. Optimisation des allocations de données pour des applications du Calcul Haute Performance sur une architecture à mémoires hétérogènes : Data Allocation Optimisation for High Performance Computing Application on Heterogeneous Architecture.

Degree: Docteur es, Informatique, 2019, Bordeaux

Le Calcul Haute Performance, regroupant l’ensemble des acteurs responsables de l’amélioration des performances de calcul des applications scientifiques sur supercalculateurs, s’est donné pour objectif d’atteindre… (more)

Subjects/Keywords: Profilage; Allocation de données; Memoires hétérogènes; Optimisation combinatoire; Data allocation; Memory management; Heterogeneous Memory Architecture; Profiling; Combinatorial optimization

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APA (6th Edition):

Brunie, H. (2019). Optimisation des allocations de données pour des applications du Calcul Haute Performance sur une architecture à mémoires hétérogènes : Data Allocation Optimisation for High Performance Computing Application on Heterogeneous Architecture. (Doctoral Dissertation). Bordeaux. Retrieved from http://www.theses.fr/2019BORD0014

Chicago Manual of Style (16th Edition):

Brunie, Hugo. “Optimisation des allocations de données pour des applications du Calcul Haute Performance sur une architecture à mémoires hétérogènes : Data Allocation Optimisation for High Performance Computing Application on Heterogeneous Architecture.” 2019. Doctoral Dissertation, Bordeaux. Accessed October 14, 2019. http://www.theses.fr/2019BORD0014.

MLA Handbook (7th Edition):

Brunie, Hugo. “Optimisation des allocations de données pour des applications du Calcul Haute Performance sur une architecture à mémoires hétérogènes : Data Allocation Optimisation for High Performance Computing Application on Heterogeneous Architecture.” 2019. Web. 14 Oct 2019.

Vancouver:

Brunie H. Optimisation des allocations de données pour des applications du Calcul Haute Performance sur une architecture à mémoires hétérogènes : Data Allocation Optimisation for High Performance Computing Application on Heterogeneous Architecture. [Internet] [Doctoral dissertation]. Bordeaux; 2019. [cited 2019 Oct 14]. Available from: http://www.theses.fr/2019BORD0014.

Council of Science Editors:

Brunie H. Optimisation des allocations de données pour des applications du Calcul Haute Performance sur une architecture à mémoires hétérogènes : Data Allocation Optimisation for High Performance Computing Application on Heterogeneous Architecture. [Doctoral Dissertation]. Bordeaux; 2019. Available from: http://www.theses.fr/2019BORD0014


ETH Zürich

14. Vogel, Pirmin. Shared Virtual Memory for Heterogeneous Embedded Systems on Chip.

Degree: 2018, ETH Zürich

 Modern embedded systems on chip (SoCs) are heavily based on heterogeneous architectures that combine feature-rich, general-purpose, multi-core host processors with massively-parallel and programmable many-core accelerators… (more)

Subjects/Keywords: Shared Virtual Memory; virtual memory management; Heterogeneous systems-on-chip (SoC); embedded systems; Many-core accelerators

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APA (6th Edition):

Vogel, P. (2018). Shared Virtual Memory for Heterogeneous Embedded Systems on Chip. (Doctoral Dissertation). ETH Zürich. Retrieved from http://hdl.handle.net/20.500.11850/292606

Chicago Manual of Style (16th Edition):

Vogel, Pirmin. “Shared Virtual Memory for Heterogeneous Embedded Systems on Chip.” 2018. Doctoral Dissertation, ETH Zürich. Accessed October 14, 2019. http://hdl.handle.net/20.500.11850/292606.

MLA Handbook (7th Edition):

Vogel, Pirmin. “Shared Virtual Memory for Heterogeneous Embedded Systems on Chip.” 2018. Web. 14 Oct 2019.

Vancouver:

Vogel P. Shared Virtual Memory for Heterogeneous Embedded Systems on Chip. [Internet] [Doctoral dissertation]. ETH Zürich; 2018. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/20.500.11850/292606.

Council of Science Editors:

Vogel P. Shared Virtual Memory for Heterogeneous Embedded Systems on Chip. [Doctoral Dissertation]. ETH Zürich; 2018. Available from: http://hdl.handle.net/20.500.11850/292606


Georgia Tech

15. Giardino, Michael Joseph. A Software Framework for Application-Guided Power-Aware Control Systems.

Degree: PhD, Electrical and Computer Engineering, 2019, Georgia Tech

 This dissertation describes a system for proactive management of power and performance trade-offs through greater cooperation between applications and hardware. To enable such a management… (more)

Subjects/Keywords: power-aware computing; operating systems; power-aware control systems; heterogeneous memory; heterogeneous computing; bumpless transfer; transient management; machine learning; q-learning; reinforcement learning; dynamic power management; linux

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APA (6th Edition):

Giardino, M. J. (2019). A Software Framework for Application-Guided Power-Aware Control Systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/61212

Chicago Manual of Style (16th Edition):

Giardino, Michael Joseph. “A Software Framework for Application-Guided Power-Aware Control Systems.” 2019. Doctoral Dissertation, Georgia Tech. Accessed October 14, 2019. http://hdl.handle.net/1853/61212.

MLA Handbook (7th Edition):

Giardino, Michael Joseph. “A Software Framework for Application-Guided Power-Aware Control Systems.” 2019. Web. 14 Oct 2019.

Vancouver:

Giardino MJ. A Software Framework for Application-Guided Power-Aware Control Systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2019. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/1853/61212.

Council of Science Editors:

Giardino MJ. A Software Framework for Application-Guided Power-Aware Control Systems. [Doctoral Dissertation]. Georgia Tech; 2019. Available from: http://hdl.handle.net/1853/61212

16. Alsop, Johnathan R. GSI: a GPU stall inspector to characterize the sources of memory stalls for tightly coupled GPUs.

Degree: MS, Electrical & Computer Engr, 2016, University of Illinois – Urbana-Champaign

 In recent years the power wall has prevented the continued scaling of single core performance. This has led to the rise of dark silicon and… (more)

Subjects/Keywords: GPUs; performance analysis; memory systems; heterogeneous computing

heterogeneous memory systems. First, we compare a hybrid, hardware-software coherence protocol for… …significant source of inefficiency. As innovations in heterogeneous memory systems emerge to address… …Heterogeneous-Race-Free Memory Models,” in Proceedings of the 19th International Conference on… …are applied only to discrete GPUs and have a very basic classification of memory stalls… …In a tightly coupled CPU-GPU system there can be multiple possible reasons for a memory… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Alsop, J. R. (2016). GSI: a GPU stall inspector to characterize the sources of memory stalls for tightly coupled GPUs. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/90587

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Alsop, Johnathan R. “GSI: a GPU stall inspector to characterize the sources of memory stalls for tightly coupled GPUs.” 2016. Thesis, University of Illinois – Urbana-Champaign. Accessed October 14, 2019. http://hdl.handle.net/2142/90587.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Alsop, Johnathan R. “GSI: a GPU stall inspector to characterize the sources of memory stalls for tightly coupled GPUs.” 2016. Web. 14 Oct 2019.

Vancouver:

Alsop JR. GSI: a GPU stall inspector to characterize the sources of memory stalls for tightly coupled GPUs. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2016. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/2142/90587.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Alsop JR. GSI: a GPU stall inspector to characterize the sources of memory stalls for tightly coupled GPUs. [Thesis]. University of Illinois – Urbana-Champaign; 2016. Available from: http://hdl.handle.net/2142/90587

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Tech

17. Su, Chun-Yi. Energy-aware Thread and Data Management in Heterogeneous Multi-Core, Multi-Memory Systems.

Degree: PhD, Computer Science, 2015, Virginia Tech

 By 2004, microprocessor design focused on multicore scaling"increasing the number of cores per die in each generation "as the primary strategy for improving performance. These… (more)

Subjects/Keywords: Thread Management; Multi-core Processors; Performance Modeling and Analysis; Power-Aware Computing; Heterogeneous Memory; Data Management

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APA (6th Edition):

Su, C. (2015). Energy-aware Thread and Data Management in Heterogeneous Multi-Core, Multi-Memory Systems. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/51255

Chicago Manual of Style (16th Edition):

Su, Chun-Yi. “Energy-aware Thread and Data Management in Heterogeneous Multi-Core, Multi-Memory Systems.” 2015. Doctoral Dissertation, Virginia Tech. Accessed October 14, 2019. http://hdl.handle.net/10919/51255.

MLA Handbook (7th Edition):

Su, Chun-Yi. “Energy-aware Thread and Data Management in Heterogeneous Multi-Core, Multi-Memory Systems.” 2015. Web. 14 Oct 2019.

Vancouver:

Su C. Energy-aware Thread and Data Management in Heterogeneous Multi-Core, Multi-Memory Systems. [Internet] [Doctoral dissertation]. Virginia Tech; 2015. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/10919/51255.

Council of Science Editors:

Su C. Energy-aware Thread and Data Management in Heterogeneous Multi-Core, Multi-Memory Systems. [Doctoral Dissertation]. Virginia Tech; 2015. Available from: http://hdl.handle.net/10919/51255


University of Southern California

18. Haji, Babak. Queueing loss system with heterogeneous servers and discriminating arrivals.

Degree: PhD, Industrial and Systems Engineering, 2015, University of Southern California

 My PhD thesis studies a queuing loss model having Poisson arrivals and n heterogeneous skill based servers with arbitrary service distributions. Arrivals are discriminating in… (more)

Subjects/Keywords: heterogeneous servers; queuing loss system; limiting probabilities; no-memory policies; method of stages; reverse chain; equilibrium distribution; Gibbs sampler

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APA (6th Edition):

Haji, B. (2015). Queueing loss system with heterogeneous servers and discriminating arrivals. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/567125/rec/5370

Chicago Manual of Style (16th Edition):

Haji, Babak. “Queueing loss system with heterogeneous servers and discriminating arrivals.” 2015. Doctoral Dissertation, University of Southern California. Accessed October 14, 2019. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/567125/rec/5370.

MLA Handbook (7th Edition):

Haji, Babak. “Queueing loss system with heterogeneous servers and discriminating arrivals.” 2015. Web. 14 Oct 2019.

Vancouver:

Haji B. Queueing loss system with heterogeneous servers and discriminating arrivals. [Internet] [Doctoral dissertation]. University of Southern California; 2015. [cited 2019 Oct 14]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/567125/rec/5370.

Council of Science Editors:

Haji B. Queueing loss system with heterogeneous servers and discriminating arrivals. [Doctoral Dissertation]. University of Southern California; 2015. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/567125/rec/5370

19. Lee, Jaekyu. Shared resource management for efficient heterogeneous computing.

Degree: PhD, Computer Science, 2013, Georgia Tech

 The demand for heterogeneous computing, because of its performance and energy efficiency, has made on-chip heterogeneous chip multi-processors (HCMP) become the mainstream computing platform, as… (more)

Subjects/Keywords: Resource management; Heterogeneous architecture; Shared cache; On-chip network; Graphics processing units; Heterogeneous computing; Cache memory

…66 5.2.4 Homogeneous or Heterogeneous Link Configuration . . . . 67 5.2.5 Placement… …104 6.3.3 Step 3. Memory Throttling . . . . . . . . . . . . . . . . . . . . 105 6.3.4… …7.3 7.4 7.5 7.6 7.2.1 Disciplined Memory Model in GPUs . . . . . . . . . . . . . . 128… …7.2.2 Memory Objects and Kernel Arguments . . . . . . . . . . . . 129 GREEN Cache… …131 7.3.1 Disciplined Memory Model and GPU Hardware . . . . . . . 131 7.3.2 Exploiting… 

Page 1 Page 2 Page 3 Page 4 Page 5 Page 6 Page 7

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lee, J. (2013). Shared resource management for efficient heterogeneous computing. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/50217

Chicago Manual of Style (16th Edition):

Lee, Jaekyu. “Shared resource management for efficient heterogeneous computing.” 2013. Doctoral Dissertation, Georgia Tech. Accessed October 14, 2019. http://hdl.handle.net/1853/50217.

MLA Handbook (7th Edition):

Lee, Jaekyu. “Shared resource management for efficient heterogeneous computing.” 2013. Web. 14 Oct 2019.

Vancouver:

Lee J. Shared resource management for efficient heterogeneous computing. [Internet] [Doctoral dissertation]. Georgia Tech; 2013. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/1853/50217.

Council of Science Editors:

Lee J. Shared resource management for efficient heterogeneous computing. [Doctoral Dissertation]. Georgia Tech; 2013. Available from: http://hdl.handle.net/1853/50217

20. Diego Souza de Paiva. (Por) entre pedra e tela: a construção de uma memória republicana (Natal - 1906-1919).

Degree: 2011, Universidade Federal do Rio Grande do Norte

O presente trabalho, partindo de uma perspectiva que pensa o espaço como categoria histórica e, sobretudo, como relação na qual se destaca o papel dos… (more)

Subjects/Keywords: Redes Heterogêneas; Natal/Brasil; Sociologia das Associações.; HISTORIA; History and Spaces; Republican memory; heterogeneous networks; História e Espaços; Memória republicana; Natal/Brasil; Sociology associations.

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Paiva, D. S. d. (2011). (Por) entre pedra e tela: a construção de uma memória republicana (Natal - 1906-1919). (Thesis). Universidade Federal do Rio Grande do Norte. Retrieved from http://bdtd.bczm.ufrn.br/tedesimplificado//tde_busca/arquivo.php?codArquivo=4852

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Paiva, Diego Souza de. “(Por) entre pedra e tela: a construção de uma memória republicana (Natal - 1906-1919).” 2011. Thesis, Universidade Federal do Rio Grande do Norte. Accessed October 14, 2019. http://bdtd.bczm.ufrn.br/tedesimplificado//tde_busca/arquivo.php?codArquivo=4852.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Paiva, Diego Souza de. “(Por) entre pedra e tela: a construção de uma memória republicana (Natal - 1906-1919).” 2011. Web. 14 Oct 2019.

Vancouver:

Paiva DSd. (Por) entre pedra e tela: a construção de uma memória republicana (Natal - 1906-1919). [Internet] [Thesis]. Universidade Federal do Rio Grande do Norte; 2011. [cited 2019 Oct 14]. Available from: http://bdtd.bczm.ufrn.br/tedesimplificado//tde_busca/arquivo.php?codArquivo=4852.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Paiva DSd. (Por) entre pedra e tela: a construção de uma memória republicana (Natal - 1906-1919). [Thesis]. Universidade Federal do Rio Grande do Norte; 2011. Available from: http://bdtd.bczm.ufrn.br/tedesimplificado//tde_busca/arquivo.php?codArquivo=4852

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Norte

21. Paiva, Diego Souza de. (Por) entre pedra e tela: a construção de uma memória republicana (Natal - 1906-1919) .

Degree: 2011, Universidade do Rio Grande do Norte

 This work, from a perspective that thinks the space as a historical category, and especially as a relationship which stresses the role of objects, proposes… (more)

Subjects/Keywords: História e Espaços; Memória republicana; Redes Heterogêneas; Natal/Brasil; Sociologia das Associações.; History and Spaces; Republican memory; heterogeneous networks; Natal/Brasil; Sociology associations.

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Paiva, D. S. d. (2011). (Por) entre pedra e tela: a construção de uma memória republicana (Natal - 1906-1919) . (Masters Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/16951

Chicago Manual of Style (16th Edition):

Paiva, Diego Souza de. “(Por) entre pedra e tela: a construção de uma memória republicana (Natal - 1906-1919) .” 2011. Masters Thesis, Universidade do Rio Grande do Norte. Accessed October 14, 2019. http://repositorio.ufrn.br/handle/123456789/16951.

MLA Handbook (7th Edition):

Paiva, Diego Souza de. “(Por) entre pedra e tela: a construção de uma memória republicana (Natal - 1906-1919) .” 2011. Web. 14 Oct 2019.

Vancouver:

Paiva DSd. (Por) entre pedra e tela: a construção de uma memória republicana (Natal - 1906-1919) . [Internet] [Masters thesis]. Universidade do Rio Grande do Norte; 2011. [cited 2019 Oct 14]. Available from: http://repositorio.ufrn.br/handle/123456789/16951.

Council of Science Editors:

Paiva DSd. (Por) entre pedra e tela: a construção de uma memória republicana (Natal - 1906-1919) . [Masters Thesis]. Universidade do Rio Grande do Norte; 2011. Available from: http://repositorio.ufrn.br/handle/123456789/16951


Universidade do Rio Grande do Norte

22. Paiva, Diego Souza de. (Por) entre pedra e tela: a construção de uma memória republicana (Natal - 1906-1919) .

Degree: 2011, Universidade do Rio Grande do Norte

 This work, from a perspective that thinks the space as a historical category, and especially as a relationship which stresses the role of objects, proposes… (more)

Subjects/Keywords: História e Espaços; Memória republicana; Redes Heterogêneas; Natal/Brasil; Sociologia das Associações.; History and Spaces; Republican memory; heterogeneous networks; Natal/Brasil; Sociology associations.

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Paiva, D. S. d. (2011). (Por) entre pedra e tela: a construção de uma memória republicana (Natal - 1906-1919) . (Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/16951

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Paiva, Diego Souza de. “(Por) entre pedra e tela: a construção de uma memória republicana (Natal - 1906-1919) .” 2011. Thesis, Universidade do Rio Grande do Norte. Accessed October 14, 2019. http://repositorio.ufrn.br/handle/123456789/16951.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Paiva, Diego Souza de. “(Por) entre pedra e tela: a construção de uma memória republicana (Natal - 1906-1919) .” 2011. Web. 14 Oct 2019.

Vancouver:

Paiva DSd. (Por) entre pedra e tela: a construção de uma memória republicana (Natal - 1906-1919) . [Internet] [Thesis]. Universidade do Rio Grande do Norte; 2011. [cited 2019 Oct 14]. Available from: http://repositorio.ufrn.br/handle/123456789/16951.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Paiva DSd. (Por) entre pedra e tela: a construção de uma memória republicana (Natal - 1906-1919) . [Thesis]. Universidade do Rio Grande do Norte; 2011. Available from: http://repositorio.ufrn.br/handle/123456789/16951

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Texas – Austin

23. Khubaib. Performance and energy efficiency via an adaptive MorphCore architecture.

Degree: PhD, Electrical and Computer Engineering, 2014, University of Texas – Austin

 The level of Thread-Level Parallelism (TLP), Instruction-Level Parallelism (ILP), and Memory-Level Parallelism (MLP) varies across programs and across program phases. Hence, every program requires different… (more)

Subjects/Keywords: Computer architecture; Microprocessor; Thread-level parallelism; Instruction-level parallelism; Memory-level parallelism; Adaptive microprocessor; Energy efficiency; High performance; Power efficiency; Chip-multiprocessor; Heterogeneous computing

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APA (6th Edition):

Khubaib. (2014). Performance and energy efficiency via an adaptive MorphCore architecture. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/25092

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Chicago Manual of Style (16th Edition):

Khubaib. “Performance and energy efficiency via an adaptive MorphCore architecture.” 2014. Doctoral Dissertation, University of Texas – Austin. Accessed October 14, 2019. http://hdl.handle.net/2152/25092.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

MLA Handbook (7th Edition):

Khubaib. “Performance and energy efficiency via an adaptive MorphCore architecture.” 2014. Web. 14 Oct 2019.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

Khubaib. Performance and energy efficiency via an adaptive MorphCore architecture. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2014. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/2152/25092.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Council of Science Editors:

Khubaib. Performance and energy efficiency via an adaptive MorphCore architecture. [Doctoral Dissertation]. University of Texas – Austin; 2014. Available from: http://hdl.handle.net/2152/25092

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete


Delft University of Technology

24. Ashraf, I. Communication Driven Mapping of Applications on Multicore Platforms.

Degree: 2016, Delft University of Technology

 Though transistor scaling yields more transistors per chip, however, the consistent performance gain due to frequency scaling is no more feasible due to physical limits.… (more)

Subjects/Keywords: data-communication profiling; heterogeneous computing; binary instrumentation; code parallelization; shadow memory

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APA (6th Edition):

Ashraf, I. (2016). Communication Driven Mapping of Applications on Multicore Platforms. (Doctoral Dissertation). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:7fbff4c6-7803-435e-a441-8e3483b8a21e ; urn:NBN:nl:ui:24-uuid:7fbff4c6-7803-435e-a441-8e3483b8a21e ; 7fbff4c6-7803-435e-a441-8e3483b8a21e ; 10.4233/uuid:uuid:7fbff4c6-7803-435e-a441-8e3483b8a21e ; urn:isbn:978-94-6186-633-2 ; urn:NBN:nl:ui:24-uuid:7fbff4c6-7803-435e-a441-8e3483b8a21e ; http://resolver.tudelft.nl/uuid:7fbff4c6-7803-435e-a441-8e3483b8a21e

Chicago Manual of Style (16th Edition):

Ashraf, I. “Communication Driven Mapping of Applications on Multicore Platforms.” 2016. Doctoral Dissertation, Delft University of Technology. Accessed October 14, 2019. http://resolver.tudelft.nl/uuid:7fbff4c6-7803-435e-a441-8e3483b8a21e ; urn:NBN:nl:ui:24-uuid:7fbff4c6-7803-435e-a441-8e3483b8a21e ; 7fbff4c6-7803-435e-a441-8e3483b8a21e ; 10.4233/uuid:uuid:7fbff4c6-7803-435e-a441-8e3483b8a21e ; urn:isbn:978-94-6186-633-2 ; urn:NBN:nl:ui:24-uuid:7fbff4c6-7803-435e-a441-8e3483b8a21e ; http://resolver.tudelft.nl/uuid:7fbff4c6-7803-435e-a441-8e3483b8a21e.

MLA Handbook (7th Edition):

Ashraf, I. “Communication Driven Mapping of Applications on Multicore Platforms.” 2016. Web. 14 Oct 2019.

Vancouver:

Ashraf I. Communication Driven Mapping of Applications on Multicore Platforms. [Internet] [Doctoral dissertation]. Delft University of Technology; 2016. [cited 2019 Oct 14]. Available from: http://resolver.tudelft.nl/uuid:7fbff4c6-7803-435e-a441-8e3483b8a21e ; urn:NBN:nl:ui:24-uuid:7fbff4c6-7803-435e-a441-8e3483b8a21e ; 7fbff4c6-7803-435e-a441-8e3483b8a21e ; 10.4233/uuid:uuid:7fbff4c6-7803-435e-a441-8e3483b8a21e ; urn:isbn:978-94-6186-633-2 ; urn:NBN:nl:ui:24-uuid:7fbff4c6-7803-435e-a441-8e3483b8a21e ; http://resolver.tudelft.nl/uuid:7fbff4c6-7803-435e-a441-8e3483b8a21e.

Council of Science Editors:

Ashraf I. Communication Driven Mapping of Applications on Multicore Platforms. [Doctoral Dissertation]. Delft University of Technology; 2016. Available from: http://resolver.tudelft.nl/uuid:7fbff4c6-7803-435e-a441-8e3483b8a21e ; urn:NBN:nl:ui:24-uuid:7fbff4c6-7803-435e-a441-8e3483b8a21e ; 7fbff4c6-7803-435e-a441-8e3483b8a21e ; 10.4233/uuid:uuid:7fbff4c6-7803-435e-a441-8e3483b8a21e ; urn:isbn:978-94-6186-633-2 ; urn:NBN:nl:ui:24-uuid:7fbff4c6-7803-435e-a441-8e3483b8a21e ; http://resolver.tudelft.nl/uuid:7fbff4c6-7803-435e-a441-8e3483b8a21e

25. Jacquelin, Mathias. Memory-aware algorithms : from multicores to large scale platforms : Algorithmes orientés mémoire : des processeurs multi-cœurs aux plates-formes à grande échelle.

Degree: Docteur es, Informatique, 2011, Lyon, École normale supérieure

Cette thèse s’intéresse aux algorithmes adaptés aux architectures mémoire hiérarchiques, rencontrées notamment dans le contexte des processeurs multi-cœurs.Nous étudions d’abord le produit de matrices sur… (more)

Subjects/Keywords: Hiérarchies mémoire; Ordonnancement; Régime permanent; Plates-formes hétérogènes; Méthodes heuristiques; Optimisation; Programmes linéaires; Maximisation du débit; Contraintes mémoire; Multicoeur; Memory hierarchy; Scheduling; Steady-state; Heterogeneous platforms; Heuristics; Optimization; Linear algebra; Throughput maximization; Memory constraints; Multicore

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jacquelin, M. (2011). Memory-aware algorithms : from multicores to large scale platforms : Algorithmes orientés mémoire : des processeurs multi-cœurs aux plates-formes à grande échelle. (Doctoral Dissertation). Lyon, École normale supérieure. Retrieved from http://www.theses.fr/2011ENSL0633

Chicago Manual of Style (16th Edition):

Jacquelin, Mathias. “Memory-aware algorithms : from multicores to large scale platforms : Algorithmes orientés mémoire : des processeurs multi-cœurs aux plates-formes à grande échelle.” 2011. Doctoral Dissertation, Lyon, École normale supérieure. Accessed October 14, 2019. http://www.theses.fr/2011ENSL0633.

MLA Handbook (7th Edition):

Jacquelin, Mathias. “Memory-aware algorithms : from multicores to large scale platforms : Algorithmes orientés mémoire : des processeurs multi-cœurs aux plates-formes à grande échelle.” 2011. Web. 14 Oct 2019.

Vancouver:

Jacquelin M. Memory-aware algorithms : from multicores to large scale platforms : Algorithmes orientés mémoire : des processeurs multi-cœurs aux plates-formes à grande échelle. [Internet] [Doctoral dissertation]. Lyon, École normale supérieure; 2011. [cited 2019 Oct 14]. Available from: http://www.theses.fr/2011ENSL0633.

Council of Science Editors:

Jacquelin M. Memory-aware algorithms : from multicores to large scale platforms : Algorithmes orientés mémoire : des processeurs multi-cœurs aux plates-formes à grande échelle. [Doctoral Dissertation]. Lyon, École normale supérieure; 2011. Available from: http://www.theses.fr/2011ENSL0633

26. Sim, Jae Woong. Architecting heterogeneous memory systems with 3D die-stacked memory.

Degree: PhD, Electrical and Computer Engineering, 2015, Georgia Tech

 The main objective of this research is to efficiently enable 3D die-stacked memory and heterogeneous memory systems. 3D die-stacking is an emerging technology that allows… (more)

Subjects/Keywords: Stacked DRAM; Die-stacking; Memory systems; Heterogeneous memory; Hardware management; Computer architecture

heterogeneous memory systems. 3D die-stacking is an emerging technology that allows for large amounts… …Efficiently Architecting Die-Stacked Memory and Heterogeneous Memory Systems Among emerging memory… …of how to manage resulting heterogeneous memory systems.1 3D die-stacking is an emerging… …memory systems are expected to be heterogeneous—gigabytes of memory structures on-chip that… …heterogeneous memory systems in a practical manner. So, the question is how to make efficient use of… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sim, J. W. (2015). Architecting heterogeneous memory systems with 3D die-stacked memory. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/53835

Chicago Manual of Style (16th Edition):

Sim, Jae Woong. “Architecting heterogeneous memory systems with 3D die-stacked memory.” 2015. Doctoral Dissertation, Georgia Tech. Accessed October 14, 2019. http://hdl.handle.net/1853/53835.

MLA Handbook (7th Edition):

Sim, Jae Woong. “Architecting heterogeneous memory systems with 3D die-stacked memory.” 2015. Web. 14 Oct 2019.

Vancouver:

Sim JW. Architecting heterogeneous memory systems with 3D die-stacked memory. [Internet] [Doctoral dissertation]. Georgia Tech; 2015. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/1853/53835.

Council of Science Editors:

Sim JW. Architecting heterogeneous memory systems with 3D die-stacked memory. [Doctoral Dissertation]. Georgia Tech; 2015. Available from: http://hdl.handle.net/1853/53835

27. Chou, Chia-Chen. Architecting high-performance, efficient, and scalable heterogeneous memory systems with 3D-DRAM.

Degree: PhD, Electrical and Computer Engineering, 2017, Georgia Tech

 Advancements in packaging technology enable high-bandwidth 3D-DRAM that mitigates the memory bandwidth wall. With the integration of 3D-DRAM and high-capacity memory, heterogeneous memory systems are… (more)

Subjects/Keywords: Microarchitecture; DRAM cache; Heterogeneous memory systems; 3D-DRAM; High-bandwidth memory; Bandwidth efficiency

…49 Chapter 5: Maximizing the System-bandwidth Utilization of Heterogeneous Memory Systems… …of Coherent DRAM Caches . . . . . . . . . . 126 8.2.3 Low-power Heterogeneous Memory… …System Configuration for PCM-based Heterogeneous Memory Systems . . 47 5.1 Baseline System… …heterogeneous memory systems are able to satisfy the high memory bandwidth demand of processors… …efficient for heterogeneous memory systems with highbandwidth 3D-DRAM. This dissertation… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chou, C. (2017). Architecting high-performance, efficient, and scalable heterogeneous memory systems with 3D-DRAM. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/58299

Chicago Manual of Style (16th Edition):

Chou, Chia-Chen. “Architecting high-performance, efficient, and scalable heterogeneous memory systems with 3D-DRAM.” 2017. Doctoral Dissertation, Georgia Tech. Accessed October 14, 2019. http://hdl.handle.net/1853/58299.

MLA Handbook (7th Edition):

Chou, Chia-Chen. “Architecting high-performance, efficient, and scalable heterogeneous memory systems with 3D-DRAM.” 2017. Web. 14 Oct 2019.

Vancouver:

Chou C. Architecting high-performance, efficient, and scalable heterogeneous memory systems with 3D-DRAM. [Internet] [Doctoral dissertation]. Georgia Tech; 2017. [cited 2019 Oct 14]. Available from: http://hdl.handle.net/1853/58299.

Council of Science Editors:

Chou C. Architecting high-performance, efficient, and scalable heterogeneous memory systems with 3D-DRAM. [Doctoral Dissertation]. Georgia Tech; 2017. Available from: http://hdl.handle.net/1853/58299


University of Vienna

28. Stoffregen, Jan Clemens. HybChive - experimental programming framework for heterogeneous architectures.

Degree: 2018, University of Vienna

High Performance Architekturen werden immer heterogener. Der Benutzer einer solchen Architektur muss verschiedene Programmiersprachen beherrschen, um alle Computing - Devices parallel nutzen zu können. Oft… (more)

Subjects/Keywords: 54.25 Parallele Datenverarbeitung; 54.52 Software engineering; Heterogene Architekturen / Shared Memory Segments / Component Tuning / Compute-Bound Algorithms / Portability / Collaborative Framework; Heterogeneous Architectures / Shared Memory Segments´/ Component Tuning / Compute-Bound Algorithms / Portability / Collaborative Framework

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APA (6th Edition):

Stoffregen, J. C. (2018). HybChive - experimental programming framework for heterogeneous architectures. (Thesis). University of Vienna. Retrieved from http://othes.univie.ac.at/53756/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Stoffregen, Jan Clemens. “HybChive - experimental programming framework for heterogeneous architectures.” 2018. Thesis, University of Vienna. Accessed October 14, 2019. http://othes.univie.ac.at/53756/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Stoffregen, Jan Clemens. “HybChive - experimental programming framework for heterogeneous architectures.” 2018. Web. 14 Oct 2019.

Vancouver:

Stoffregen JC. HybChive - experimental programming framework for heterogeneous architectures. [Internet] [Thesis]. University of Vienna; 2018. [cited 2019 Oct 14]. Available from: http://othes.univie.ac.at/53756/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Stoffregen JC. HybChive - experimental programming framework for heterogeneous architectures. [Thesis]. University of Vienna; 2018. Available from: http://othes.univie.ac.at/53756/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

29. Coulon, Jérôme. Mémoire longue, volatilité et gestion de portefeuille : Long memory, volatility and portfolio management.

Degree: Docteur es, Sciences de gestion, 2009, Université Claude Bernard – Lyon I

Cette thèse porte sur l’étude de la mémoire longue de la volatilité des rendements d’actions. Dans une première partie, nous apportons une interprétation de la… (more)

Subjects/Keywords: Mémoire longue; Volatilité réalisée; Modèle de volatilité; Agents hétérogènes; Rationalité limitée; Mouvement brownien fractionnaire; Modèle de choix de portefeuille; Long memory; Realized volatility; Volatility modelling; Heterogeneous agents; Bounded rationality; Fractional brownian motion; Portfolio modelling

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Coulon, J. (2009). Mémoire longue, volatilité et gestion de portefeuille : Long memory, volatility and portfolio management. (Doctoral Dissertation). Université Claude Bernard – Lyon I. Retrieved from http://www.theses.fr/2009LYO10068

Chicago Manual of Style (16th Edition):

Coulon, Jérôme. “Mémoire longue, volatilité et gestion de portefeuille : Long memory, volatility and portfolio management.” 2009. Doctoral Dissertation, Université Claude Bernard – Lyon I. Accessed October 14, 2019. http://www.theses.fr/2009LYO10068.

MLA Handbook (7th Edition):

Coulon, Jérôme. “Mémoire longue, volatilité et gestion de portefeuille : Long memory, volatility and portfolio management.” 2009. Web. 14 Oct 2019.

Vancouver:

Coulon J. Mémoire longue, volatilité et gestion de portefeuille : Long memory, volatility and portfolio management. [Internet] [Doctoral dissertation]. Université Claude Bernard – Lyon I; 2009. [cited 2019 Oct 14]. Available from: http://www.theses.fr/2009LYO10068.

Council of Science Editors:

Coulon J. Mémoire longue, volatilité et gestion de portefeuille : Long memory, volatility and portfolio management. [Doctoral Dissertation]. Université Claude Bernard – Lyon I; 2009. Available from: http://www.theses.fr/2009LYO10068

30. Lopez, Florent. Task-based multifrontal QR solver for heterogeneous architectures : Solveur multifrontal QR à base de tâches pour architectures hétérogènes.

Degree: Docteur es, Sureté du logiciel et calcul haute preformance, 2015, Université Toulouse III – Paul Sabatier

Afin de s'adapter aux architectures multicoeurs et aux machines de plus en plus complexes, les modèles de programmations basés sur un parallélisme de tâche ont… (more)

Subjects/Keywords: Méthodes directes de résolution de systèmes linéaires; Méthode multifrontale; Multicœur; Moteurs d'exécutions; Ordonnancement, algorithmes d'ordonnancement sous contraintes mémoire; Architectures hétérogènes; Calcul haute performance; GPU; Sparse direct solvers; Multifrontal method; Multicores; Runtime systems; Scheduling; Memory-aware algorythms; Heterogeneous architectures; High-performance computing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lopez, F. (2015). Task-based multifrontal QR solver for heterogeneous architectures : Solveur multifrontal QR à base de tâches pour architectures hétérogènes. (Doctoral Dissertation). Université Toulouse III – Paul Sabatier. Retrieved from http://www.theses.fr/2015TOU30303

Chicago Manual of Style (16th Edition):

Lopez, Florent. “Task-based multifrontal QR solver for heterogeneous architectures : Solveur multifrontal QR à base de tâches pour architectures hétérogènes.” 2015. Doctoral Dissertation, Université Toulouse III – Paul Sabatier. Accessed October 14, 2019. http://www.theses.fr/2015TOU30303.

MLA Handbook (7th Edition):

Lopez, Florent. “Task-based multifrontal QR solver for heterogeneous architectures : Solveur multifrontal QR à base de tâches pour architectures hétérogènes.” 2015. Web. 14 Oct 2019.

Vancouver:

Lopez F. Task-based multifrontal QR solver for heterogeneous architectures : Solveur multifrontal QR à base de tâches pour architectures hétérogènes. [Internet] [Doctoral dissertation]. Université Toulouse III – Paul Sabatier; 2015. [cited 2019 Oct 14]. Available from: http://www.theses.fr/2015TOU30303.

Council of Science Editors:

Lopez F. Task-based multifrontal QR solver for heterogeneous architectures : Solveur multifrontal QR à base de tâches pour architectures hétérogènes. [Doctoral Dissertation]. Université Toulouse III – Paul Sabatier; 2015. Available from: http://www.theses.fr/2015TOU30303

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