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You searched for subject:(hardware scheduler). Showing records 1 – 4 of 4 total matches.

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1. Tjin A Djie, M.E. (author). MEP-MAS: A Message Passing Multiprocessor Array for Streaming Applications.

Degree: 2012, Delft University of Technology

This thesis presents the design and implementation of a Chip-Multiprocessor (CMP) targeted at streaming applications(e.g. MPEG, MP3). Streaming applications are applications which can be split… (more)

Subjects/Keywords: Multiprocessors; Streaming; Hardware scheduler

…between processors. • Design of a distributed hardware scheduler, which takes the producer… …4 Architecture 4.1 The Distributed Scheduler… …4.1.1 The Primary Scheduler . . . . . . . . . . . . . . . . . . . . . . . 4.1.2 The Secondary… …basic structure of the primary scheduler. . . . . . . . Data Flow Graph representation… …Dynamic scheduling requires scheduling logic in hardware, but has the advantage that run-time… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tjin A Djie, M. E. (. (2012). MEP-MAS: A Message Passing Multiprocessor Array for Streaming Applications. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:f5fa2307-fe28-4570-a679-b4ac64d007e6

Chicago Manual of Style (16th Edition):

Tjin A Djie, M E (author). “MEP-MAS: A Message Passing Multiprocessor Array for Streaming Applications.” 2012. Masters Thesis, Delft University of Technology. Accessed November 29, 2020. http://resolver.tudelft.nl/uuid:f5fa2307-fe28-4570-a679-b4ac64d007e6.

MLA Handbook (7th Edition):

Tjin A Djie, M E (author). “MEP-MAS: A Message Passing Multiprocessor Array for Streaming Applications.” 2012. Web. 29 Nov 2020.

Vancouver:

Tjin A Djie ME(. MEP-MAS: A Message Passing Multiprocessor Array for Streaming Applications. [Internet] [Masters thesis]. Delft University of Technology; 2012. [cited 2020 Nov 29]. Available from: http://resolver.tudelft.nl/uuid:f5fa2307-fe28-4570-a679-b4ac64d007e6.

Council of Science Editors:

Tjin A Djie ME(. MEP-MAS: A Message Passing Multiprocessor Array for Streaming Applications. [Masters Thesis]. Delft University of Technology; 2012. Available from: http://resolver.tudelft.nl/uuid:f5fa2307-fe28-4570-a679-b4ac64d007e6

2. 大崎, 哲弥. リアルタイムシステムにおけるハードウェアスケジュールに関する研究.

Degree: Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学

Supervisor:田中 清史

情報科学研究科

修士

Subjects/Keywords: リアルタイム,ハードウェアスケジューラ,組込み; Real-Time, hardware-scheduler, embedded system

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APA (6th Edition):

大崎, . (n.d.). リアルタイムシステムにおけるハードウェアスケジュールに関する研究. (Thesis). Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10119/1803

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

大崎, 哲弥. “リアルタイムシステムにおけるハードウェアスケジュールに関する研究.” Thesis, Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学. Accessed November 29, 2020. http://hdl.handle.net/10119/1803.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

大崎, 哲弥. “リアルタイムシステムにおけるハードウェアスケジュールに関する研究.” Web. 29 Nov 2020.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

大崎 . リアルタイムシステムにおけるハードウェアスケジュールに関する研究. [Internet] [Thesis]. Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学; [cited 2020 Nov 29]. Available from: http://hdl.handle.net/10119/1803.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

大崎 . リアルタイムシステムにおけるハードウェアスケジュールに関する研究. [Thesis]. Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学; Available from: http://hdl.handle.net/10119/1803

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.


Brigham Young University

3. Isaacson, Spencer W. Hardware Support for a Configurable Architecture for Real-Time Embedded Systems on a Programmable Chip.

Degree: MS, 2007, Brigham Young University

 Current FPGA technology has advanced to the point that useful embedded SoPCs can now be designed. The Real Time Processor (RTP) project at Brigham Young… (more)

Subjects/Keywords: FPGA; hardware RTOS; real-time; fast context switch; register bank; task; task-resource matrix; embedded; computer architecture; hardware scheduler; task switch; hardware assisted RTOS; Electrical and Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Isaacson, S. W. (2007). Hardware Support for a Configurable Architecture for Real-Time Embedded Systems on a Programmable Chip. (Masters Thesis). Brigham Young University. Retrieved from https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=1970&context=etd

Chicago Manual of Style (16th Edition):

Isaacson, Spencer W. “Hardware Support for a Configurable Architecture for Real-Time Embedded Systems on a Programmable Chip.” 2007. Masters Thesis, Brigham Young University. Accessed November 29, 2020. https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=1970&context=etd.

MLA Handbook (7th Edition):

Isaacson, Spencer W. “Hardware Support for a Configurable Architecture for Real-Time Embedded Systems on a Programmable Chip.” 2007. Web. 29 Nov 2020.

Vancouver:

Isaacson SW. Hardware Support for a Configurable Architecture for Real-Time Embedded Systems on a Programmable Chip. [Internet] [Masters thesis]. Brigham Young University; 2007. [cited 2020 Nov 29]. Available from: https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=1970&context=etd.

Council of Science Editors:

Isaacson SW. Hardware Support for a Configurable Architecture for Real-Time Embedded Systems on a Programmable Chip. [Masters Thesis]. Brigham Young University; 2007. Available from: https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=1970&context=etd

4. Mancuso, Renato. Next-generation safety-critical systems on multi-core platforms.

Degree: PhD, Computer Science, 2017, University of Illinois – Urbana-Champaign

 Multi-core platforms represent the answer of the industry to the increasing demand for computational capabilities. In fact, multi-core platforms can deliver large computational power together… (more)

Subjects/Keywords: Real-time systems; Multi-core systems; Commercial-off-the-shelf (COTS); Single-core equivalence; Single-core equivalent; Hardware resource management; Operating system (OS); Real-time operating system (RTOS); Worst case execution time (WCET); Scheduling; Schedulability analysis; Multi-core real-time operating system (RTOS); Profiling; Avionics; Safety-critical; Cyber-physical systems (CPS); Memguard; Colored lockdown; Palloc; Kernel verification; Scratchpad-centric operating system (OS); Scratchpad memories operating system (SPM-OS); Scratchpad scheduling; Direct memory access (DMA) scheduling; Flow-shop task; Flow-shop scheduling; Hardware scheduler; Field-programmable gate array (FPGA) scheduler; Real-time Linux; Automotive; Smart manufacturing; Real-time networking; Embedded systems; Multi-core avionics; Multi-core automotive; Self-driving cars; Multi-core safety-critical; Many-core; Reconfigurable computing; Internet of things; Real-time cloud computing; Provably safe cyber-physical systems (CPS); Multi-core scheduling; Performance isolation; Real-time resource management; Real-time cache; Real-time dynamic random access memory (DRAM); P4080; MPC5777M; Inter-core interference; Interference channels; CAST32; CAST32A; Federal Aviation Administration (FAA); Minimal multicore avionics certification guidance; Multi-core automotive open system architecture (AUTOSAR); DO-178C; DO-178B; Resource partitioning; Multi-core resource partitioning; Predictable execution model (PREM); Multi-core predictable execution model (PREM)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mancuso, R. (2017). Next-generation safety-critical systems on multi-core platforms. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/97399

Chicago Manual of Style (16th Edition):

Mancuso, Renato. “Next-generation safety-critical systems on multi-core platforms.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed November 29, 2020. http://hdl.handle.net/2142/97399.

MLA Handbook (7th Edition):

Mancuso, Renato. “Next-generation safety-critical systems on multi-core platforms.” 2017. Web. 29 Nov 2020.

Vancouver:

Mancuso R. Next-generation safety-critical systems on multi-core platforms. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2020 Nov 29]. Available from: http://hdl.handle.net/2142/97399.

Council of Science Editors:

Mancuso R. Next-generation safety-critical systems on multi-core platforms. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/97399

.