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You searched for subject:(hardware acceleration). Showing records 1 – 30 of 111 total matches.

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University of Arkansas

1. Ding, Hongyuan. Exploiting Hardware Abstraction for Parallel Programming Framework: Platform and Multitasking.

Degree: PhD, 2017, University of Arkansas

  With the help of the parallelism provided by the fine-grained architecture, hardware accelerators on Field Programmable Gate Arrays (FPGAs) can significantly improve the performance… (more)

Subjects/Keywords: FPGA; Hardware Abstraction; Hardware Acceleration; Hardware Multitasking; MPSoC; OpenCL; Hardware Systems

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APA (6th Edition):

Ding, H. (2017). Exploiting Hardware Abstraction for Parallel Programming Framework: Platform and Multitasking. (Doctoral Dissertation). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/1985

Chicago Manual of Style (16th Edition):

Ding, Hongyuan. “Exploiting Hardware Abstraction for Parallel Programming Framework: Platform and Multitasking.” 2017. Doctoral Dissertation, University of Arkansas. Accessed December 09, 2019. https://scholarworks.uark.edu/etd/1985.

MLA Handbook (7th Edition):

Ding, Hongyuan. “Exploiting Hardware Abstraction for Parallel Programming Framework: Platform and Multitasking.” 2017. Web. 09 Dec 2019.

Vancouver:

Ding H. Exploiting Hardware Abstraction for Parallel Programming Framework: Platform and Multitasking. [Internet] [Doctoral dissertation]. University of Arkansas; 2017. [cited 2019 Dec 09]. Available from: https://scholarworks.uark.edu/etd/1985.

Council of Science Editors:

Ding H. Exploiting Hardware Abstraction for Parallel Programming Framework: Platform and Multitasking. [Doctoral Dissertation]. University of Arkansas; 2017. Available from: https://scholarworks.uark.edu/etd/1985


University of Pretoria

2. Jacobson, Jared Neil. Assessing OpenGL for 2D rendering of geospatial data.

Degree: MSc, Geography, Geoinformatics and Meteorology, 2015, University of Pretoria

 The purpose of this study was to investigate the suitability of using the OpenGL and OpenCL graphics application programming interfaces (APIs), to increase the speed… (more)

Subjects/Keywords: UCTD; 2D; OpenGL; Rendering; GIS; Hardware Acceleration

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APA (6th Edition):

Jacobson, J. N. (2015). Assessing OpenGL for 2D rendering of geospatial data. (Masters Thesis). University of Pretoria. Retrieved from http://hdl.handle.net/2263/45917

Chicago Manual of Style (16th Edition):

Jacobson, Jared Neil. “Assessing OpenGL for 2D rendering of geospatial data.” 2015. Masters Thesis, University of Pretoria. Accessed December 09, 2019. http://hdl.handle.net/2263/45917.

MLA Handbook (7th Edition):

Jacobson, Jared Neil. “Assessing OpenGL for 2D rendering of geospatial data.” 2015. Web. 09 Dec 2019.

Vancouver:

Jacobson JN. Assessing OpenGL for 2D rendering of geospatial data. [Internet] [Masters thesis]. University of Pretoria; 2015. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/2263/45917.

Council of Science Editors:

Jacobson JN. Assessing OpenGL for 2D rendering of geospatial data. [Masters Thesis]. University of Pretoria; 2015. Available from: http://hdl.handle.net/2263/45917


McMaster University

3. Thong, Jason. FPGA Acceleration of Decision-Based Problems using Heterogeneous Computing.

Degree: PhD, 2014, McMaster University

The Boolean satisfiability (SAT) problem is central to many applications involving the verification and optimization of digital systems. These combinatorial problems are typically solved by… (more)

Subjects/Keywords: FPGA; heterogeneous computing; Boolean satisfiability; hardware acceleration

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APA (6th Edition):

Thong, J. (2014). FPGA Acceleration of Decision-Based Problems using Heterogeneous Computing. (Doctoral Dissertation). McMaster University. Retrieved from http://hdl.handle.net/11375/16419

Chicago Manual of Style (16th Edition):

Thong, Jason. “FPGA Acceleration of Decision-Based Problems using Heterogeneous Computing.” 2014. Doctoral Dissertation, McMaster University. Accessed December 09, 2019. http://hdl.handle.net/11375/16419.

MLA Handbook (7th Edition):

Thong, Jason. “FPGA Acceleration of Decision-Based Problems using Heterogeneous Computing.” 2014. Web. 09 Dec 2019.

Vancouver:

Thong J. FPGA Acceleration of Decision-Based Problems using Heterogeneous Computing. [Internet] [Doctoral dissertation]. McMaster University; 2014. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/11375/16419.

Council of Science Editors:

Thong J. FPGA Acceleration of Decision-Based Problems using Heterogeneous Computing. [Doctoral Dissertation]. McMaster University; 2014. Available from: http://hdl.handle.net/11375/16419


University of Windsor

4. Tang, Qing Yun. FPGA Based Acceleration of Matrix Decomposition and Clustering Algorithm Using High Level Synthesis.

Degree: MA, Electrical and Computer Engineering, 2016, University of Windsor

 FPGAs have shown great promise for accelerating computationally intensive algorithms. However, FPGA-based accelerator design is tedious and time consuming if we rely on traditional HDL… (more)

Subjects/Keywords: FPGA; Hardware Acceleration; High Level Synthesis; OpenCL

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APA (6th Edition):

Tang, Q. Y. (2016). FPGA Based Acceleration of Matrix Decomposition and Clustering Algorithm Using High Level Synthesis. (Masters Thesis). University of Windsor. Retrieved from https://scholar.uwindsor.ca/etd/5669

Chicago Manual of Style (16th Edition):

Tang, Qing Yun. “FPGA Based Acceleration of Matrix Decomposition and Clustering Algorithm Using High Level Synthesis.” 2016. Masters Thesis, University of Windsor. Accessed December 09, 2019. https://scholar.uwindsor.ca/etd/5669.

MLA Handbook (7th Edition):

Tang, Qing Yun. “FPGA Based Acceleration of Matrix Decomposition and Clustering Algorithm Using High Level Synthesis.” 2016. Web. 09 Dec 2019.

Vancouver:

Tang QY. FPGA Based Acceleration of Matrix Decomposition and Clustering Algorithm Using High Level Synthesis. [Internet] [Masters thesis]. University of Windsor; 2016. [cited 2019 Dec 09]. Available from: https://scholar.uwindsor.ca/etd/5669.

Council of Science Editors:

Tang QY. FPGA Based Acceleration of Matrix Decomposition and Clustering Algorithm Using High Level Synthesis. [Masters Thesis]. University of Windsor; 2016. Available from: https://scholar.uwindsor.ca/etd/5669


University of Guelph

5. Lacey, Griffin James. Deep Learning on FPGAs .

Degree: 2016, University of Guelph

 The recent successes of deep learning are largely attributed to the advancement of hardware acceleration technologies, which can accommodate the incredible growth of data sizes… (more)

Subjects/Keywords: Deep Learning; FPGA; Machine Learning; Hardware Acceleration

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APA (6th Edition):

Lacey, G. J. (2016). Deep Learning on FPGAs . (Thesis). University of Guelph. Retrieved from https://atrium.lib.uoguelph.ca/xmlui/handle/10214/9887

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lacey, Griffin James. “Deep Learning on FPGAs .” 2016. Thesis, University of Guelph. Accessed December 09, 2019. https://atrium.lib.uoguelph.ca/xmlui/handle/10214/9887.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lacey, Griffin James. “Deep Learning on FPGAs .” 2016. Web. 09 Dec 2019.

Vancouver:

Lacey GJ. Deep Learning on FPGAs . [Internet] [Thesis]. University of Guelph; 2016. [cited 2019 Dec 09]. Available from: https://atrium.lib.uoguelph.ca/xmlui/handle/10214/9887.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lacey GJ. Deep Learning on FPGAs . [Thesis]. University of Guelph; 2016. Available from: https://atrium.lib.uoguelph.ca/xmlui/handle/10214/9887

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Cornell University

6. Ilbeyi, Berkin. Co-Optimizing Hardware Design and Meta-Tracing Just-in-Time Compilation .

Degree: 2019, Cornell University

 Performance of computers has enjoyed consistent gains due to the availability of faster and cheaper transistors, more complex hardware designs, and better hardware design tools.… (more)

Subjects/Keywords: Computer engineering; Computer science; compiler; Hardware; Hardware Acceleration; Hardware Design; JIT; Meta-Tracing

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APA (6th Edition):

Ilbeyi, B. (2019). Co-Optimizing Hardware Design and Meta-Tracing Just-in-Time Compilation . (Thesis). Cornell University. Retrieved from http://hdl.handle.net/1813/67316

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ilbeyi, Berkin. “Co-Optimizing Hardware Design and Meta-Tracing Just-in-Time Compilation .” 2019. Thesis, Cornell University. Accessed December 09, 2019. http://hdl.handle.net/1813/67316.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ilbeyi, Berkin. “Co-Optimizing Hardware Design and Meta-Tracing Just-in-Time Compilation .” 2019. Web. 09 Dec 2019.

Vancouver:

Ilbeyi B. Co-Optimizing Hardware Design and Meta-Tracing Just-in-Time Compilation . [Internet] [Thesis]. Cornell University; 2019. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/1813/67316.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ilbeyi B. Co-Optimizing Hardware Design and Meta-Tracing Just-in-Time Compilation . [Thesis]. Cornell University; 2019. Available from: http://hdl.handle.net/1813/67316

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


The Ohio State University

7. XUE, Daqing. Volume Visualization Using Advanced Graphics Hardware Shaders.

Degree: PhD, Computer Science and Engineering, 2008, The Ohio State University

  Graphics hardware based volume visualization techniques have been the active research topic over the last decade. With the more powerful computation ability, the availability… (more)

Subjects/Keywords: Computer Science; volume visualization; graphics hardware; hardware acceleration; flow visualization; multi-shader rendering

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APA (6th Edition):

XUE, D. (2008). Volume Visualization Using Advanced Graphics Hardware Shaders. (Doctoral Dissertation). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1219382224

Chicago Manual of Style (16th Edition):

XUE, Daqing. “Volume Visualization Using Advanced Graphics Hardware Shaders.” 2008. Doctoral Dissertation, The Ohio State University. Accessed December 09, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=osu1219382224.

MLA Handbook (7th Edition):

XUE, Daqing. “Volume Visualization Using Advanced Graphics Hardware Shaders.” 2008. Web. 09 Dec 2019.

Vancouver:

XUE D. Volume Visualization Using Advanced Graphics Hardware Shaders. [Internet] [Doctoral dissertation]. The Ohio State University; 2008. [cited 2019 Dec 09]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1219382224.

Council of Science Editors:

XUE D. Volume Visualization Using Advanced Graphics Hardware Shaders. [Doctoral Dissertation]. The Ohio State University; 2008. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1219382224


Penn State University

8. Snyder, Joshua Scott. Optimization and Hardware Acceleration of Consensus-based Matching and Tracking.

Degree: MS, Computer Science and Engineering, 2015, Penn State University

 Image and video understanding has become an increasingly valuable capability for many emerging applications such as smart retail, intelligent surveillance, and autonomous robotic systems. The… (more)

Subjects/Keywords: hardware acceleration; object tracking; FPGA; CMT; hardware architecture; vision system; computer vision

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APA (6th Edition):

Snyder, J. S. (2015). Optimization and Hardware Acceleration of Consensus-based Matching and Tracking. (Masters Thesis). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/25036

Chicago Manual of Style (16th Edition):

Snyder, Joshua Scott. “Optimization and Hardware Acceleration of Consensus-based Matching and Tracking.” 2015. Masters Thesis, Penn State University. Accessed December 09, 2019. https://etda.libraries.psu.edu/catalog/25036.

MLA Handbook (7th Edition):

Snyder, Joshua Scott. “Optimization and Hardware Acceleration of Consensus-based Matching and Tracking.” 2015. Web. 09 Dec 2019.

Vancouver:

Snyder JS. Optimization and Hardware Acceleration of Consensus-based Matching and Tracking. [Internet] [Masters thesis]. Penn State University; 2015. [cited 2019 Dec 09]. Available from: https://etda.libraries.psu.edu/catalog/25036.

Council of Science Editors:

Snyder JS. Optimization and Hardware Acceleration of Consensus-based Matching and Tracking. [Masters Thesis]. Penn State University; 2015. Available from: https://etda.libraries.psu.edu/catalog/25036

9. Merchant, Murtaza. Testing and Validation of a Prototype Gpgpu Design for FPGAs.

Degree: MS, Electrical & Computer Engineering, 2013, University of Massachusetts

  Due to their suitability for highly parallel and pipelined computation, field programmable gate arrays (FPGAs) and general-purpose graphics processing units (GPGPUs) have emerged as… (more)

Subjects/Keywords: GPGPU; FPGA; hardware acceleration; CUDA compatible; scalable; flexible; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Merchant, M. (2013). Testing and Validation of a Prototype Gpgpu Design for FPGAs. (Masters Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/theses/1012

Chicago Manual of Style (16th Edition):

Merchant, Murtaza. “Testing and Validation of a Prototype Gpgpu Design for FPGAs.” 2013. Masters Thesis, University of Massachusetts. Accessed December 09, 2019. https://scholarworks.umass.edu/theses/1012.

MLA Handbook (7th Edition):

Merchant, Murtaza. “Testing and Validation of a Prototype Gpgpu Design for FPGAs.” 2013. Web. 09 Dec 2019.

Vancouver:

Merchant M. Testing and Validation of a Prototype Gpgpu Design for FPGAs. [Internet] [Masters thesis]. University of Massachusetts; 2013. [cited 2019 Dec 09]. Available from: https://scholarworks.umass.edu/theses/1012.

Council of Science Editors:

Merchant M. Testing and Validation of a Prototype Gpgpu Design for FPGAs. [Masters Thesis]. University of Massachusetts; 2013. Available from: https://scholarworks.umass.edu/theses/1012


Penn State University

10. DeBole, Michael Vincent. CONFIGURABLE ACCELERATORS FOR VIDEO ANALYTICS.

Degree: PhD, Computer Science and Engineering, 2011, Penn State University

 Video analytics is the science of analyzing image sequences and video with the aim to gain a cognitive understanding of a scene. The applications which… (more)

Subjects/Keywords: FPGA; Hardware Acceleration; Image Processing; 3D IC; FPGA Framework

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APA (6th Edition):

DeBole, M. V. (2011). CONFIGURABLE ACCELERATORS FOR VIDEO ANALYTICS. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/11829

Chicago Manual of Style (16th Edition):

DeBole, Michael Vincent. “CONFIGURABLE ACCELERATORS FOR VIDEO ANALYTICS.” 2011. Doctoral Dissertation, Penn State University. Accessed December 09, 2019. https://etda.libraries.psu.edu/catalog/11829.

MLA Handbook (7th Edition):

DeBole, Michael Vincent. “CONFIGURABLE ACCELERATORS FOR VIDEO ANALYTICS.” 2011. Web. 09 Dec 2019.

Vancouver:

DeBole MV. CONFIGURABLE ACCELERATORS FOR VIDEO ANALYTICS. [Internet] [Doctoral dissertation]. Penn State University; 2011. [cited 2019 Dec 09]. Available from: https://etda.libraries.psu.edu/catalog/11829.

Council of Science Editors:

DeBole MV. CONFIGURABLE ACCELERATORS FOR VIDEO ANALYTICS. [Doctoral Dissertation]. Penn State University; 2011. Available from: https://etda.libraries.psu.edu/catalog/11829


University of Debrecen

11. Gacsal, Patrik. Hardveres algoritmusgyorsítás FPGA segítségével .

Degree: DE – TEK – Informatikai Kar, 2012, University of Debrecen

 Az x86 architektúra hardveres gyorsításának elérhető megoldásai, egyedi gyorsítási lehetőségek tárgyalása FPGA segítségével. A dolgozat az x86 alapú számítógépek hardveres gyorsításának történelmét foglalja össze, valamint… (more)

Subjects/Keywords: hardware; acceleration; fpga; custom; ISA; extension; coprocessor; x86

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APA (6th Edition):

Gacsal, P. (2012). Hardveres algoritmusgyorsítás FPGA segítségével . (Thesis). University of Debrecen. Retrieved from http://hdl.handle.net/2437/128233

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gacsal, Patrik. “Hardveres algoritmusgyorsítás FPGA segítségével .” 2012. Thesis, University of Debrecen. Accessed December 09, 2019. http://hdl.handle.net/2437/128233.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gacsal, Patrik. “Hardveres algoritmusgyorsítás FPGA segítségével .” 2012. Web. 09 Dec 2019.

Vancouver:

Gacsal P. Hardveres algoritmusgyorsítás FPGA segítségével . [Internet] [Thesis]. University of Debrecen; 2012. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/2437/128233.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gacsal P. Hardveres algoritmusgyorsítás FPGA segítségével . [Thesis]. University of Debrecen; 2012. Available from: http://hdl.handle.net/2437/128233

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Linköping University

12. Holmér, Johan. Acceleration and Integration of Sound Decoding in FPGA.

Degree: Electrical Engineering, 2011, Linköping University

  The task has been to develop a network media renderer on an embedded linux system running on a Spartan 6 FPGA. One of the… (more)

Subjects/Keywords: Hardware acceleration; digital signal processing; embedded systems; sound encoding; Electronics; Elektronik

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APA (6th Edition):

Holmér, J. (2011). Acceleration and Integration of Sound Decoding in FPGA. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-70180

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Holmér, Johan. “Acceleration and Integration of Sound Decoding in FPGA.” 2011. Thesis, Linköping University. Accessed December 09, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-70180.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Holmér, Johan. “Acceleration and Integration of Sound Decoding in FPGA.” 2011. Web. 09 Dec 2019.

Vancouver:

Holmér J. Acceleration and Integration of Sound Decoding in FPGA. [Internet] [Thesis]. Linköping University; 2011. [cited 2019 Dec 09]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-70180.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Holmér J. Acceleration and Integration of Sound Decoding in FPGA. [Thesis]. Linköping University; 2011. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-70180

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Toronto

13. Boutros, Andrew Maher Mansour. Enhancing FPGA Architecture for Efficient Deep Learning Inference.

Degree: 2018, University of Toronto

Deep Learning (DL) has become best-in-class for numerous applications but at a high computational cost that necessitates high-performance energy-efficient acceleration. FPGAs offer an appealing DL… (more)

Subjects/Keywords: Convolutional Neural Networks; Deep Learning; FPGA Architecture; Hardware Acceleration; 0464

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APA (6th Edition):

Boutros, A. M. M. (2018). Enhancing FPGA Architecture for Efficient Deep Learning Inference. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/91435

Chicago Manual of Style (16th Edition):

Boutros, Andrew Maher Mansour. “Enhancing FPGA Architecture for Efficient Deep Learning Inference.” 2018. Masters Thesis, University of Toronto. Accessed December 09, 2019. http://hdl.handle.net/1807/91435.

MLA Handbook (7th Edition):

Boutros, Andrew Maher Mansour. “Enhancing FPGA Architecture for Efficient Deep Learning Inference.” 2018. Web. 09 Dec 2019.

Vancouver:

Boutros AMM. Enhancing FPGA Architecture for Efficient Deep Learning Inference. [Internet] [Masters thesis]. University of Toronto; 2018. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/1807/91435.

Council of Science Editors:

Boutros AMM. Enhancing FPGA Architecture for Efficient Deep Learning Inference. [Masters Thesis]. University of Toronto; 2018. Available from: http://hdl.handle.net/1807/91435


University of Windsor

14. Janik, Ian Spencer. High Level Synthesis and Evaluation of the Secure Hash Standard for FPGAs.

Degree: MA, Electrical and Computer Engineering, 2015, University of Windsor

  Secure hash algorithms (SHAs) are important components of cryptographic applications. SHA performance on central processing units (CPUs) is slow, therefore, acceleration must be done… (more)

Subjects/Keywords: FPGAs; Hardware Acceleration; High Level Synthesis; SHA1; SHA2; SHA3

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APA (6th Edition):

Janik, I. S. (2015). High Level Synthesis and Evaluation of the Secure Hash Standard for FPGAs. (Masters Thesis). University of Windsor. Retrieved from https://scholar.uwindsor.ca/etd/5470

Chicago Manual of Style (16th Edition):

Janik, Ian Spencer. “High Level Synthesis and Evaluation of the Secure Hash Standard for FPGAs.” 2015. Masters Thesis, University of Windsor. Accessed December 09, 2019. https://scholar.uwindsor.ca/etd/5470.

MLA Handbook (7th Edition):

Janik, Ian Spencer. “High Level Synthesis and Evaluation of the Secure Hash Standard for FPGAs.” 2015. Web. 09 Dec 2019.

Vancouver:

Janik IS. High Level Synthesis and Evaluation of the Secure Hash Standard for FPGAs. [Internet] [Masters thesis]. University of Windsor; 2015. [cited 2019 Dec 09]. Available from: https://scholar.uwindsor.ca/etd/5470.

Council of Science Editors:

Janik IS. High Level Synthesis and Evaluation of the Secure Hash Standard for FPGAs. [Masters Thesis]. University of Windsor; 2015. Available from: https://scholar.uwindsor.ca/etd/5470


University of Illinois – Urbana-Champaign

15. Kesler, David R. A hardware acceleration technique for gradient descent and conjugate gradient.

Degree: MS, 1200, 2011, University of Illinois – Urbana-Champaign

 Gradient descent, conjugate gradient, and other iterative algorithms are a powerful class of algorithms; however, they can take a long time for conver- gence. Baseline… (more)

Subjects/Keywords: Gradient Descent; Conjugate Gradient; Hardware Acceleration; Matrix Multiplication

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APA (6th Edition):

Kesler, D. R. (2011). A hardware acceleration technique for gradient descent and conjugate gradient. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/24241

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kesler, David R. “A hardware acceleration technique for gradient descent and conjugate gradient.” 2011. Thesis, University of Illinois – Urbana-Champaign. Accessed December 09, 2019. http://hdl.handle.net/2142/24241.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kesler, David R. “A hardware acceleration technique for gradient descent and conjugate gradient.” 2011. Web. 09 Dec 2019.

Vancouver:

Kesler DR. A hardware acceleration technique for gradient descent and conjugate gradient. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2011. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/2142/24241.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kesler DR. A hardware acceleration technique for gradient descent and conjugate gradient. [Thesis]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/24241

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

16. Okafor, Ikenna. Hardware Acceleration of Visual Object Search.

Degree: 2017, Penn State University

 Visual Object Search, the process of locating an object within an image, is a key task in many automated vision systems with applications ranging from… (more)

Subjects/Keywords: Computer Vision; Sliding Window; ROI; Hardware Acceleration; FPGA

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APA (6th Edition):

Okafor, I. (2017). Hardware Acceleration of Visual Object Search. (Thesis). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/14067izo5011

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Okafor, Ikenna. “Hardware Acceleration of Visual Object Search.” 2017. Thesis, Penn State University. Accessed December 09, 2019. https://etda.libraries.psu.edu/catalog/14067izo5011.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Okafor, Ikenna. “Hardware Acceleration of Visual Object Search.” 2017. Web. 09 Dec 2019.

Vancouver:

Okafor I. Hardware Acceleration of Visual Object Search. [Internet] [Thesis]. Penn State University; 2017. [cited 2019 Dec 09]. Available from: https://etda.libraries.psu.edu/catalog/14067izo5011.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Okafor I. Hardware Acceleration of Visual Object Search. [Thesis]. Penn State University; 2017. Available from: https://etda.libraries.psu.edu/catalog/14067izo5011

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of North Texas

17. Amarasinghe, Dhanyu Eshaka. Real-time Rendering of Burning Objects in Video Games.

Degree: 2013, University of North Texas

 In recent years there has been growing interest in limitless realism in computer graphics applications. Among those, my foremost concentration falls into the complex physical… (more)

Subjects/Keywords: Hardware acceleration; volume rendering; CUDA; free form deformation; polygonal modeling

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Amarasinghe, D. E. (2013). Real-time Rendering of Burning Objects in Video Games. (Thesis). University of North Texas. Retrieved from https://digital.library.unt.edu/ark:/67531/metadc500131/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Amarasinghe, Dhanyu Eshaka. “Real-time Rendering of Burning Objects in Video Games.” 2013. Thesis, University of North Texas. Accessed December 09, 2019. https://digital.library.unt.edu/ark:/67531/metadc500131/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Amarasinghe, Dhanyu Eshaka. “Real-time Rendering of Burning Objects in Video Games.” 2013. Web. 09 Dec 2019.

Vancouver:

Amarasinghe DE. Real-time Rendering of Burning Objects in Video Games. [Internet] [Thesis]. University of North Texas; 2013. [cited 2019 Dec 09]. Available from: https://digital.library.unt.edu/ark:/67531/metadc500131/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Amarasinghe DE. Real-time Rendering of Burning Objects in Video Games. [Thesis]. University of North Texas; 2013. Available from: https://digital.library.unt.edu/ark:/67531/metadc500131/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Boston University

18. Zhou, Boyou. A multi-layer approach to designing secure systems: from circuit to software.

Degree: PhD, Electrical & Computer Engineering, 2019, Boston University

 In the last few years, security has become one of the key challenges in computing systems. Failures in the secure operations of these systems have… (more)

Subjects/Keywords: Computer engineering; Cryptographic acceleration; Hardware Trojan detection; Malware detection; Security

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhou, B. (2019). A multi-layer approach to designing secure systems: from circuit to software. (Doctoral Dissertation). Boston University. Retrieved from http://hdl.handle.net/2144/36149

Chicago Manual of Style (16th Edition):

Zhou, Boyou. “A multi-layer approach to designing secure systems: from circuit to software.” 2019. Doctoral Dissertation, Boston University. Accessed December 09, 2019. http://hdl.handle.net/2144/36149.

MLA Handbook (7th Edition):

Zhou, Boyou. “A multi-layer approach to designing secure systems: from circuit to software.” 2019. Web. 09 Dec 2019.

Vancouver:

Zhou B. A multi-layer approach to designing secure systems: from circuit to software. [Internet] [Doctoral dissertation]. Boston University; 2019. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/2144/36149.

Council of Science Editors:

Zhou B. A multi-layer approach to designing secure systems: from circuit to software. [Doctoral Dissertation]. Boston University; 2019. Available from: http://hdl.handle.net/2144/36149


New Jersey Institute of Technology

19. Li, Gang. High-performance matrix multiplication on Intel and FGPA platforms.

Degree: MSin Computer Engineering - (M.S.), Electrical and Computer Engineering, 2012, New Jersey Institute of Technology

  Matrix multiplication is at the core of high-performance numerical computation. Software methods of accelerating matrix multiplication fall into two categories. One is based on… (more)

Subjects/Keywords: Matrix multiplication algorithms; Vector-based hardware acceleration; Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Li, G. (2012). High-performance matrix multiplication on Intel and FGPA platforms. (Thesis). New Jersey Institute of Technology. Retrieved from https://digitalcommons.njit.edu/theses/136

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Li, Gang. “High-performance matrix multiplication on Intel and FGPA platforms.” 2012. Thesis, New Jersey Institute of Technology. Accessed December 09, 2019. https://digitalcommons.njit.edu/theses/136.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Li, Gang. “High-performance matrix multiplication on Intel and FGPA platforms.” 2012. Web. 09 Dec 2019.

Vancouver:

Li G. High-performance matrix multiplication on Intel and FGPA platforms. [Internet] [Thesis]. New Jersey Institute of Technology; 2012. [cited 2019 Dec 09]. Available from: https://digitalcommons.njit.edu/theses/136.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li G. High-performance matrix multiplication on Intel and FGPA platforms. [Thesis]. New Jersey Institute of Technology; 2012. Available from: https://digitalcommons.njit.edu/theses/136

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

20. Hansson, Karl. Performance and Perceived Realism in Rasterized 3D Sound Propagation for Interactive Virtual Environments.

Degree: 2019, , Department of Software Engineering

Background. 3D sound propagation is important for immersion and realism in interactive and dynamic virtual environments. However, this is difficult to model in a… (more)

Subjects/Keywords: psychoacoustics; rasterization; hardware-acceleration; psykoakustik; rasterisering; hårdvaruacceleration; Media Engineering; Mediateknik

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hansson, K. (2019). Performance and Perceived Realism in Rasterized 3D Sound Propagation for Interactive Virtual Environments. (Thesis). , Department of Software Engineering. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:bth-18251

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hansson, Karl. “Performance and Perceived Realism in Rasterized 3D Sound Propagation for Interactive Virtual Environments.” 2019. Thesis, , Department of Software Engineering. Accessed December 09, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-18251.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hansson, Karl. “Performance and Perceived Realism in Rasterized 3D Sound Propagation for Interactive Virtual Environments.” 2019. Web. 09 Dec 2019.

Vancouver:

Hansson K. Performance and Perceived Realism in Rasterized 3D Sound Propagation for Interactive Virtual Environments. [Internet] [Thesis]. , Department of Software Engineering; 2019. [cited 2019 Dec 09]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:bth-18251.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hansson K. Performance and Perceived Realism in Rasterized 3D Sound Propagation for Interactive Virtual Environments. [Thesis]. , Department of Software Engineering; 2019. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:bth-18251

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Victoria

21. Kanan, Awos. Optimized hardware accelerators for data mining applications.

Degree: Department of Electrical and Computer Engineering, 2018, University of Victoria

 Data mining plays an important role in a variety of fields including bioinformatics, multimedia, business intelligence, marketing, and medical diagnosis. Analysis of today’s huge and… (more)

Subjects/Keywords: Data Mining; Parallel Algorithms; Hardware Acceleration; Systolic Arrays; Design Methodology

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APA (6th Edition):

Kanan, A. (2018). Optimized hardware accelerators for data mining applications. (Thesis). University of Victoria. Retrieved from https://dspace.library.uvic.ca//handle/1828/9079

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kanan, Awos. “Optimized hardware accelerators for data mining applications.” 2018. Thesis, University of Victoria. Accessed December 09, 2019. https://dspace.library.uvic.ca//handle/1828/9079.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kanan, Awos. “Optimized hardware accelerators for data mining applications.” 2018. Web. 09 Dec 2019.

Vancouver:

Kanan A. Optimized hardware accelerators for data mining applications. [Internet] [Thesis]. University of Victoria; 2018. [cited 2019 Dec 09]. Available from: https://dspace.library.uvic.ca//handle/1828/9079.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kanan A. Optimized hardware accelerators for data mining applications. [Thesis]. University of Victoria; 2018. Available from: https://dspace.library.uvic.ca//handle/1828/9079

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

22. Siddiqui, Fahad Manzoor. FPGA-based programmable embedded platform for image processing applications.

Degree: PhD, 2018, Queen's University Belfast

 A vast majority of electronic systems including medical, surveillance and critical infrastructure employs image processing to provide intelligent analysis. They use onboard pre-processing to reduce… (more)

Subjects/Keywords: FPGA; Dataflow; Multicore; Zynq; Parallel computing; Hardware acceleration; Image Processing; Programmable

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Siddiqui, F. M. (2018). FPGA-based programmable embedded platform for image processing applications. (Doctoral Dissertation). Queen's University Belfast. Retrieved from https://pure.qub.ac.uk/portal/en/theses/fpgabased-programmable-embedded-platform-for-image-processing-applications(a59d226f-253a-475b-b064-fd79359dcccb).html ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.766276

Chicago Manual of Style (16th Edition):

Siddiqui, Fahad Manzoor. “FPGA-based programmable embedded platform for image processing applications.” 2018. Doctoral Dissertation, Queen's University Belfast. Accessed December 09, 2019. https://pure.qub.ac.uk/portal/en/theses/fpgabased-programmable-embedded-platform-for-image-processing-applications(a59d226f-253a-475b-b064-fd79359dcccb).html ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.766276.

MLA Handbook (7th Edition):

Siddiqui, Fahad Manzoor. “FPGA-based programmable embedded platform for image processing applications.” 2018. Web. 09 Dec 2019.

Vancouver:

Siddiqui FM. FPGA-based programmable embedded platform for image processing applications. [Internet] [Doctoral dissertation]. Queen's University Belfast; 2018. [cited 2019 Dec 09]. Available from: https://pure.qub.ac.uk/portal/en/theses/fpgabased-programmable-embedded-platform-for-image-processing-applications(a59d226f-253a-475b-b064-fd79359dcccb).html ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.766276.

Council of Science Editors:

Siddiqui FM. FPGA-based programmable embedded platform for image processing applications. [Doctoral Dissertation]. Queen's University Belfast; 2018. Available from: https://pure.qub.ac.uk/portal/en/theses/fpgabased-programmable-embedded-platform-for-image-processing-applications(a59d226f-253a-475b-b064-fd79359dcccb).html ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.766276


Virginia Tech

23. Odom, Jacob Henry. Indexing Large Permutations in Hardware.

Degree: MS, Computer Engineering, 2019, Virginia Tech

 In computing, some applications need the ability to shuffle or rearrange items based on run time information during their normal operations. A similar task is… (more)

Subjects/Keywords: permutations; combinatorics; hardware acceleration; Fisher-Yates; Knuth-Shuffle

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APA (6th Edition):

Odom, J. H. (2019). Indexing Large Permutations in Hardware. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/89906

Chicago Manual of Style (16th Edition):

Odom, Jacob Henry. “Indexing Large Permutations in Hardware.” 2019. Masters Thesis, Virginia Tech. Accessed December 09, 2019. http://hdl.handle.net/10919/89906.

MLA Handbook (7th Edition):

Odom, Jacob Henry. “Indexing Large Permutations in Hardware.” 2019. Web. 09 Dec 2019.

Vancouver:

Odom JH. Indexing Large Permutations in Hardware. [Internet] [Masters thesis]. Virginia Tech; 2019. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/10919/89906.

Council of Science Editors:

Odom JH. Indexing Large Permutations in Hardware. [Masters Thesis]. Virginia Tech; 2019. Available from: http://hdl.handle.net/10919/89906


Brno University of Technology

24. Bareš, Jan. Návrh protokolu hardwarového akcelerátoru náročných výpočtů nad více jádry .

Degree: 2018, Brno University of Technology

 Práce se zabývá návrhem komunikačního protokolu, který má umožnit přenos dat mezi řídicím počítačem a výpočetními jádry, implementovanými na čipy FPGA. Účelem komunikace je urychlení… (more)

Subjects/Keywords: Hardwarová akcelerace; urychlovač; akcelerační systém; FPGA; návrh protokolu; komunikační protokol; Hardware acceleration; accelerator; acceleration system; FPGA; design of protocol; communication protocol

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bareš, J. (2018). Návrh protokolu hardwarového akcelerátoru náročných výpočtů nad více jádry . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/80760

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bareš, Jan. “Návrh protokolu hardwarového akcelerátoru náročných výpočtů nad více jádry .” 2018. Thesis, Brno University of Technology. Accessed December 09, 2019. http://hdl.handle.net/11012/80760.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bareš, Jan. “Návrh protokolu hardwarového akcelerátoru náročných výpočtů nad více jádry .” 2018. Web. 09 Dec 2019.

Vancouver:

Bareš J. Návrh protokolu hardwarového akcelerátoru náročných výpočtů nad více jádry . [Internet] [Thesis]. Brno University of Technology; 2018. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/11012/80760.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bareš J. Návrh protokolu hardwarového akcelerátoru náročných výpočtů nad více jádry . [Thesis]. Brno University of Technology; 2018. Available from: http://hdl.handle.net/11012/80760

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Chicago

25. Di Tucci, Lorenzo. Efficient High Performance FPGA-Based Applications Design via SDAccel.

Degree: 2016, University of Illinois – Chicago

 Custom hardware accelerators are widely used to improve the performance of software appli- cations in terms of execution times and to reduce energy consumption. However,… (more)

Subjects/Keywords: FPGA; SDAccel; EDA; CAD; Smith-Waterman; Protein Folding; Hardware Acceleration; Hardware Design Flow; High Level Synthesis; System Level Design; Hardware Architecture; Custom Hardware Accelerators

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APA (6th Edition):

Di Tucci, L. (2016). Efficient High Performance FPGA-Based Applications Design via SDAccel. (Thesis). University of Illinois – Chicago. Retrieved from http://hdl.handle.net/10027/21325

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Di Tucci, Lorenzo. “Efficient High Performance FPGA-Based Applications Design via SDAccel.” 2016. Thesis, University of Illinois – Chicago. Accessed December 09, 2019. http://hdl.handle.net/10027/21325.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Di Tucci, Lorenzo. “Efficient High Performance FPGA-Based Applications Design via SDAccel.” 2016. Web. 09 Dec 2019.

Vancouver:

Di Tucci L. Efficient High Performance FPGA-Based Applications Design via SDAccel. [Internet] [Thesis]. University of Illinois – Chicago; 2016. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/10027/21325.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Di Tucci L. Efficient High Performance FPGA-Based Applications Design via SDAccel. [Thesis]. University of Illinois – Chicago; 2016. Available from: http://hdl.handle.net/10027/21325

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

26. Novotňák, Jiří. Hardwarová akcelerace šifrování síťového provozu .

Degree: 2010, Brno University of Technology

 Cílem této práce je navrhnout a implementovat vyskorychlostní šifrátor síťového provozus propustností 10Gb/s v jednom směru. Implementační platformou je FPGA Xilinx Virtex5vlx155t umístěné na kartě… (more)

Subjects/Keywords: Hardware; akcelerace; šifrování; AES; FPGA; VHDL; IPSEC; ESP; Hardware; acceleration; encryption; AES; FPGA; VHDL; IPSEC; ESP

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Novotňák, J. (2010). Hardwarová akcelerace šifrování síťového provozu . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/54260

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Novotňák, Jiří. “Hardwarová akcelerace šifrování síťového provozu .” 2010. Thesis, Brno University of Technology. Accessed December 09, 2019. http://hdl.handle.net/11012/54260.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Novotňák, Jiří. “Hardwarová akcelerace šifrování síťového provozu .” 2010. Web. 09 Dec 2019.

Vancouver:

Novotňák J. Hardwarová akcelerace šifrování síťového provozu . [Internet] [Thesis]. Brno University of Technology; 2010. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/11012/54260.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Novotňák J. Hardwarová akcelerace šifrování síťového provozu . [Thesis]. Brno University of Technology; 2010. Available from: http://hdl.handle.net/11012/54260

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

27. Gulati, Kanupriya. Hardware Acceleration of Electronic Design Automation Algorithms.

Degree: 2010, Texas A&M University

 With the advances in very large scale integration (VLSI) technology, hardware is going parallel. Software, which was traditionally designed to execute on single core microprocessors,… (more)

Subjects/Keywords: Hardware Acceleration; Graphics Processing Units; FPGA; Custom IC; Boolean Satisfiability; Fault Simulation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gulati, K. (2010). Hardware Acceleration of Electronic Design Automation Algorithms. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-7471

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gulati, Kanupriya. “Hardware Acceleration of Electronic Design Automation Algorithms.” 2010. Thesis, Texas A&M University. Accessed December 09, 2019. http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-7471.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gulati, Kanupriya. “Hardware Acceleration of Electronic Design Automation Algorithms.” 2010. Web. 09 Dec 2019.

Vancouver:

Gulati K. Hardware Acceleration of Electronic Design Automation Algorithms. [Internet] [Thesis]. Texas A&M University; 2010. [cited 2019 Dec 09]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-7471.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gulati K. Hardware Acceleration of Electronic Design Automation Algorithms. [Thesis]. Texas A&M University; 2010. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2009-12-7471

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

28. Wu, Bo-sheng. Acceleration of Image Feature Extraction Algorithms.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 The description of local features of images has been successfully applied to many areas, including wide baseline matching, object recognition, texture recognition, image retrieval, robot… (more)

Subjects/Keywords: scale-invariant feature transform; Speeded-Up Robust Feature; hardware acceleration; image feature extraction; OpenCL; GPGPU

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu, B. (2014). Acceleration of Image Feature Extraction Algorithms. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0810114-020324

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Bo-sheng. “Acceleration of Image Feature Extraction Algorithms.” 2014. Thesis, NSYSU. Accessed December 09, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0810114-020324.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Bo-sheng. “Acceleration of Image Feature Extraction Algorithms.” 2014. Web. 09 Dec 2019.

Vancouver:

Wu B. Acceleration of Image Feature Extraction Algorithms. [Internet] [Thesis]. NSYSU; 2014. [cited 2019 Dec 09]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0810114-020324.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu B. Acceleration of Image Feature Extraction Algorithms. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0810114-020324

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

29. Chandrashekhar, Anusha. Acceleration of monocular depth extraction for images.

Degree: MS, Computer Science and Engineering, 2014, Penn State University

 This thesis evaluates and profiles a monocular depth estimation algorithm in which depth maps are generated from a single image using a non-parametric depth transfer… (more)

Subjects/Keywords: Monocular depth extraction; GPU; CUDA; Hardware acceleration; non-parametric depth; fast depth estimator; computer vision

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chandrashekhar, A. (2014). Acceleration of monocular depth extraction for images. (Masters Thesis). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/23442

Chicago Manual of Style (16th Edition):

Chandrashekhar, Anusha. “Acceleration of monocular depth extraction for images.” 2014. Masters Thesis, Penn State University. Accessed December 09, 2019. https://etda.libraries.psu.edu/catalog/23442.

MLA Handbook (7th Edition):

Chandrashekhar, Anusha. “Acceleration of monocular depth extraction for images.” 2014. Web. 09 Dec 2019.

Vancouver:

Chandrashekhar A. Acceleration of monocular depth extraction for images. [Internet] [Masters thesis]. Penn State University; 2014. [cited 2019 Dec 09]. Available from: https://etda.libraries.psu.edu/catalog/23442.

Council of Science Editors:

Chandrashekhar A. Acceleration of monocular depth extraction for images. [Masters Thesis]. Penn State University; 2014. Available from: https://etda.libraries.psu.edu/catalog/23442

30. Irick, Kevin Maurice. A Configurable Platform for Sensor and Image Processing.

Degree: PhD, Computer Science and Engineering, 2009, Penn State University

 Smart Environments are environments that exhibit ambient intelligence to those that interact with them. Smart Environments represent the next generation of pervasive computing enabled by… (more)

Subjects/Keywords: Image Processing; Hardware Acceleration; FPGA

…vi Chapter 5 Framework for Hardware Accelerator Integration… …51 Hardware Infrastructure… …25 Figure 3-3: Neural Network hardware architecture… …46 Figure 5-1: AlgoFLEX Hardware Infrastructure… …reconfigurable hardware devices that allow the functionality of a logic circuit to be defined and… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Irick, K. M. (2009). A Configurable Platform for Sensor and Image Processing. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/9989

Chicago Manual of Style (16th Edition):

Irick, Kevin Maurice. “A Configurable Platform for Sensor and Image Processing.” 2009. Doctoral Dissertation, Penn State University. Accessed December 09, 2019. https://etda.libraries.psu.edu/catalog/9989.

MLA Handbook (7th Edition):

Irick, Kevin Maurice. “A Configurable Platform for Sensor and Image Processing.” 2009. Web. 09 Dec 2019.

Vancouver:

Irick KM. A Configurable Platform for Sensor and Image Processing. [Internet] [Doctoral dissertation]. Penn State University; 2009. [cited 2019 Dec 09]. Available from: https://etda.libraries.psu.edu/catalog/9989.

Council of Science Editors:

Irick KM. A Configurable Platform for Sensor and Image Processing. [Doctoral Dissertation]. Penn State University; 2009. Available from: https://etda.libraries.psu.edu/catalog/9989

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