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You searched for subject:(gate oxide). Showing records 1 – 30 of 99 total matches.

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Rochester Institute of Technology

1. Fenger, Germain L. Development of plasma enhanced chemical vapor deposition (PECVD) gate dielectrics for TFT applications.

Degree: Microelectronic Engineering, 2010, Rochester Institute of Technology

 This study investigated a variety of electrically insulating materials for potential use as a gate dielectric in thin-film transistor applications. The materials that were investigated… (more)

Subjects/Keywords: Dielectric; Gate oxide; Low temperature; PECVD; TFT

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APA (6th Edition):

Fenger, G. L. (2010). Development of plasma enhanced chemical vapor deposition (PECVD) gate dielectrics for TFT applications. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/7433

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fenger, Germain L. “Development of plasma enhanced chemical vapor deposition (PECVD) gate dielectrics for TFT applications.” 2010. Thesis, Rochester Institute of Technology. Accessed August 09, 2020. https://scholarworks.rit.edu/theses/7433.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fenger, Germain L. “Development of plasma enhanced chemical vapor deposition (PECVD) gate dielectrics for TFT applications.” 2010. Web. 09 Aug 2020.

Vancouver:

Fenger GL. Development of plasma enhanced chemical vapor deposition (PECVD) gate dielectrics for TFT applications. [Internet] [Thesis]. Rochester Institute of Technology; 2010. [cited 2020 Aug 09]. Available from: https://scholarworks.rit.edu/theses/7433.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fenger GL. Development of plasma enhanced chemical vapor deposition (PECVD) gate dielectrics for TFT applications. [Thesis]. Rochester Institute of Technology; 2010. Available from: https://scholarworks.rit.edu/theses/7433

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Minnesota

2. McCarthy, Ivana. High-k Gate dielectric materials for CMOS.

Degree: 2010, University of Minnesota

University of Minnesota M.S. thesis. August 2010. Major:Electrical Engineering. Advisor: Stephen A. Campbell. 1 computer file (PDF); v, 32 pages. Ill. (some col.)

Abstract summary not available

Subjects/Keywords: MOSFETs; Switching speed; Physical gate oxide; Oxide; Moore’s Law; Electrical engineering

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APA (6th Edition):

McCarthy, I. (2010). High-k Gate dielectric materials for CMOS. (Masters Thesis). University of Minnesota. Retrieved from http://purl.umn.edu/102363

Chicago Manual of Style (16th Edition):

McCarthy, Ivana. “High-k Gate dielectric materials for CMOS.” 2010. Masters Thesis, University of Minnesota. Accessed August 09, 2020. http://purl.umn.edu/102363.

MLA Handbook (7th Edition):

McCarthy, Ivana. “High-k Gate dielectric materials for CMOS.” 2010. Web. 09 Aug 2020.

Vancouver:

McCarthy I. High-k Gate dielectric materials for CMOS. [Internet] [Masters thesis]. University of Minnesota; 2010. [cited 2020 Aug 09]. Available from: http://purl.umn.edu/102363.

Council of Science Editors:

McCarthy I. High-k Gate dielectric materials for CMOS. [Masters Thesis]. University of Minnesota; 2010. Available from: http://purl.umn.edu/102363


Delft University of Technology

3. Spring, Hélène (author). Electrostatic control of the anomalous Hall effect in SrRuO3.

Degree: 2019, Delft University of Technology

In this study, ultrathin films of the itinerant 4d ferromagnet SrRuO3 were epitaxially deposited on SrTiO3 and capped with a thin LaAlO3 layer. Top gates… (more)

Subjects/Keywords: anomalous Hall effect; complex oxide; top gate; tight-binding model

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APA (6th Edition):

Spring, H. (. (2019). Electrostatic control of the anomalous Hall effect in SrRuO3. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:bb30d5ee-c669-46f5-b3dd-be5c9e429484

Chicago Manual of Style (16th Edition):

Spring, Hélène (author). “Electrostatic control of the anomalous Hall effect in SrRuO3.” 2019. Masters Thesis, Delft University of Technology. Accessed August 09, 2020. http://resolver.tudelft.nl/uuid:bb30d5ee-c669-46f5-b3dd-be5c9e429484.

MLA Handbook (7th Edition):

Spring, Hélène (author). “Electrostatic control of the anomalous Hall effect in SrRuO3.” 2019. Web. 09 Aug 2020.

Vancouver:

Spring H(. Electrostatic control of the anomalous Hall effect in SrRuO3. [Internet] [Masters thesis]. Delft University of Technology; 2019. [cited 2020 Aug 09]. Available from: http://resolver.tudelft.nl/uuid:bb30d5ee-c669-46f5-b3dd-be5c9e429484.

Council of Science Editors:

Spring H(. Electrostatic control of the anomalous Hall effect in SrRuO3. [Masters Thesis]. Delft University of Technology; 2019. Available from: http://resolver.tudelft.nl/uuid:bb30d5ee-c669-46f5-b3dd-be5c9e429484


North Carolina State University

4. Wheeler, Virginia D. Structure and Properties of Epitaxial Dielectrics on GaN.

Degree: PhD, Materials Science and Engineering, 2010, North Carolina State University

 GaN is recognized as a possible material for metal oxide semiconductor field effect transistors (MOSFETs) used in high temperature, high power and high speed electronic… (more)

Subjects/Keywords: lanthanum oxide; scandium oxide; GaN; gate oxides; TEM; XRD; MOSFET; band offsets; XPS; power devices; epitaxial dielectrics; RHEED; crystalline oxide

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APA (6th Edition):

Wheeler, V. D. (2010). Structure and Properties of Epitaxial Dielectrics on GaN. (Doctoral Dissertation). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/6224

Chicago Manual of Style (16th Edition):

Wheeler, Virginia D. “Structure and Properties of Epitaxial Dielectrics on GaN.” 2010. Doctoral Dissertation, North Carolina State University. Accessed August 09, 2020. http://www.lib.ncsu.edu/resolver/1840.16/6224.

MLA Handbook (7th Edition):

Wheeler, Virginia D. “Structure and Properties of Epitaxial Dielectrics on GaN.” 2010. Web. 09 Aug 2020.

Vancouver:

Wheeler VD. Structure and Properties of Epitaxial Dielectrics on GaN. [Internet] [Doctoral dissertation]. North Carolina State University; 2010. [cited 2020 Aug 09]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/6224.

Council of Science Editors:

Wheeler VD. Structure and Properties of Epitaxial Dielectrics on GaN. [Doctoral Dissertation]. North Carolina State University; 2010. Available from: http://www.lib.ncsu.edu/resolver/1840.16/6224


University of Akron

5. Mulpuri, Vamsi. Failure Analysis and High Temperature Characterization of Silicon Carbide Power MOSFETs.

Degree: MSin Engineering, Electrical Engineering, 2017, University of Akron

 The reliability of power semiconductor switches is important when considering their vital role in power electronic converters for aerospace, railway, hybrid electric vehicle, and power… (more)

Subjects/Keywords: Engineering; Silicon Carbide, Threshold Voltage, On state Resistance, Gate leakage Current, Gate Oxide, Metallization, Bond wire

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APA (6th Edition):

Mulpuri, V. (2017). Failure Analysis and High Temperature Characterization of Silicon Carbide Power MOSFETs. (Masters Thesis). University of Akron. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=akron151076214366849

Chicago Manual of Style (16th Edition):

Mulpuri, Vamsi. “Failure Analysis and High Temperature Characterization of Silicon Carbide Power MOSFETs.” 2017. Masters Thesis, University of Akron. Accessed August 09, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=akron151076214366849.

MLA Handbook (7th Edition):

Mulpuri, Vamsi. “Failure Analysis and High Temperature Characterization of Silicon Carbide Power MOSFETs.” 2017. Web. 09 Aug 2020.

Vancouver:

Mulpuri V. Failure Analysis and High Temperature Characterization of Silicon Carbide Power MOSFETs. [Internet] [Masters thesis]. University of Akron; 2017. [cited 2020 Aug 09]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=akron151076214366849.

Council of Science Editors:

Mulpuri V. Failure Analysis and High Temperature Characterization of Silicon Carbide Power MOSFETs. [Masters Thesis]. University of Akron; 2017. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=akron151076214366849


University of California – Berkeley

6. Khan, Asif Islam. Negative Capacitance for Ultra-low Power Computing.

Degree: Electrical Engineering & Computer Sciences, 2015, University of California – Berkeley

 Owing to the fundamental physics of the Boltzmann distribution, the ever-increasing power dissipation in nanoscale transistors threatens an end to the almost-four-decade-old cadence of continued… (more)

Subjects/Keywords: Electrical engineering; Materials Science; ferroelectrics; gate oxide; MOSFET; Negative capacitance; subthreshold; ultra-low power

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APA (6th Edition):

Khan, A. I. (2015). Negative Capacitance for Ultra-low Power Computing. (Thesis). University of California – Berkeley. Retrieved from http://www.escholarship.org/uc/item/0283855m

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Khan, Asif Islam. “Negative Capacitance for Ultra-low Power Computing.” 2015. Thesis, University of California – Berkeley. Accessed August 09, 2020. http://www.escholarship.org/uc/item/0283855m.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Khan, Asif Islam. “Negative Capacitance for Ultra-low Power Computing.” 2015. Web. 09 Aug 2020.

Vancouver:

Khan AI. Negative Capacitance for Ultra-low Power Computing. [Internet] [Thesis]. University of California – Berkeley; 2015. [cited 2020 Aug 09]. Available from: http://www.escholarship.org/uc/item/0283855m.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Khan AI. Negative Capacitance for Ultra-low Power Computing. [Thesis]. University of California – Berkeley; 2015. Available from: http://www.escholarship.org/uc/item/0283855m

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


North Carolina State University

7. Lin, Yanxia. Advanced Gate Stacks for Strained Si Devices.

Degree: PhD, Electrical Engineering, 2005, North Carolina State University

 Due to the mobility enhancement provided by strained Si for both electrons and holes, as well as the scaling requirement and potential issues of polysilicon… (more)

Subjects/Keywords: Hafnium oxide; mobility; metal gate electrode

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APA (6th Edition):

Lin, Y. (2005). Advanced Gate Stacks for Strained Si Devices. (Doctoral Dissertation). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/3730

Chicago Manual of Style (16th Edition):

Lin, Yanxia. “Advanced Gate Stacks for Strained Si Devices.” 2005. Doctoral Dissertation, North Carolina State University. Accessed August 09, 2020. http://www.lib.ncsu.edu/resolver/1840.16/3730.

MLA Handbook (7th Edition):

Lin, Yanxia. “Advanced Gate Stacks for Strained Si Devices.” 2005. Web. 09 Aug 2020.

Vancouver:

Lin Y. Advanced Gate Stacks for Strained Si Devices. [Internet] [Doctoral dissertation]. North Carolina State University; 2005. [cited 2020 Aug 09]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/3730.

Council of Science Editors:

Lin Y. Advanced Gate Stacks for Strained Si Devices. [Doctoral Dissertation]. North Carolina State University; 2005. Available from: http://www.lib.ncsu.edu/resolver/1840.16/3730


Rochester Institute of Technology

8. Bohannon, Eric. Analog integrated circuit design in ultra-thin oxide CMOS technologies with significant direct tunneling-induced gate current.

Degree: PhD, Microsystems Engineering, 2011, Rochester Institute of Technology

 The ability to do mixed-signal IC design in a CMOS technology has been a driving force for manufacturing personal mobile electronic products such as cellular… (more)

Subjects/Keywords: Analog integrated circuits; Bandgap voltage reference; CMOS; Direct tunneling; Gate current; Ultra-thin oxide

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APA (6th Edition):

Bohannon, E. (2011). Analog integrated circuit design in ultra-thin oxide CMOS technologies with significant direct tunneling-induced gate current. (Doctoral Dissertation). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/12

Chicago Manual of Style (16th Edition):

Bohannon, Eric. “Analog integrated circuit design in ultra-thin oxide CMOS technologies with significant direct tunneling-induced gate current.” 2011. Doctoral Dissertation, Rochester Institute of Technology. Accessed August 09, 2020. https://scholarworks.rit.edu/theses/12.

MLA Handbook (7th Edition):

Bohannon, Eric. “Analog integrated circuit design in ultra-thin oxide CMOS technologies with significant direct tunneling-induced gate current.” 2011. Web. 09 Aug 2020.

Vancouver:

Bohannon E. Analog integrated circuit design in ultra-thin oxide CMOS technologies with significant direct tunneling-induced gate current. [Internet] [Doctoral dissertation]. Rochester Institute of Technology; 2011. [cited 2020 Aug 09]. Available from: https://scholarworks.rit.edu/theses/12.

Council of Science Editors:

Bohannon E. Analog integrated circuit design in ultra-thin oxide CMOS technologies with significant direct tunneling-induced gate current. [Doctoral Dissertation]. Rochester Institute of Technology; 2011. Available from: https://scholarworks.rit.edu/theses/12


NSYSU

9. CHEN, JIN-HUI. Large Signal Model Establishment for different gate length Mental-Oxide Semiconductor Field-Effect Transistor and its Characterization.

Degree: Master, Communications Engineering, 2013, NSYSU

 Due to the fast development of the microwave circuits, the circuit design relies on good and accurate model. The research focused on the nonlinear characteristics… (more)

Subjects/Keywords: Breakdown region; Metal-Oxide Semiconductor Field-Effect Transistor; Large signal model; Gate length; Nonlinear characteristics

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APA (6th Edition):

CHEN, J. (2013). Large Signal Model Establishment for different gate length Mental-Oxide Semiconductor Field-Effect Transistor and its Characterization. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0812113-091801

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

CHEN, JIN-HUI. “Large Signal Model Establishment for different gate length Mental-Oxide Semiconductor Field-Effect Transistor and its Characterization.” 2013. Thesis, NSYSU. Accessed August 09, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0812113-091801.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

CHEN, JIN-HUI. “Large Signal Model Establishment for different gate length Mental-Oxide Semiconductor Field-Effect Transistor and its Characterization.” 2013. Web. 09 Aug 2020.

Vancouver:

CHEN J. Large Signal Model Establishment for different gate length Mental-Oxide Semiconductor Field-Effect Transistor and its Characterization. [Internet] [Thesis]. NSYSU; 2013. [cited 2020 Aug 09]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0812113-091801.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

CHEN J. Large Signal Model Establishment for different gate length Mental-Oxide Semiconductor Field-Effect Transistor and its Characterization. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0812113-091801

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Delaware

10. Blake, Jolie. Characterization of nanostructured semiconductors by ultrafast luminescence imaging .

Degree: 2017, University of Delaware

 Single nanostructures are predicted to be the building blocks of next generation devices and have already been incorporated into prototypes for solar cells, biomedical devices… (more)

Subjects/Keywords: Pure sciences; Applied sciences; Kerr-gate; Microscopy; Nanowire; Spectroscopy; Ultrafast; Zinc oxide

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APA (6th Edition):

Blake, J. (2017). Characterization of nanostructured semiconductors by ultrafast luminescence imaging . (Doctoral Dissertation). University of Delaware. Retrieved from http://udspace.udel.edu/handle/19716/23107

Chicago Manual of Style (16th Edition):

Blake, Jolie. “Characterization of nanostructured semiconductors by ultrafast luminescence imaging .” 2017. Doctoral Dissertation, University of Delaware. Accessed August 09, 2020. http://udspace.udel.edu/handle/19716/23107.

MLA Handbook (7th Edition):

Blake, Jolie. “Characterization of nanostructured semiconductors by ultrafast luminescence imaging .” 2017. Web. 09 Aug 2020.

Vancouver:

Blake J. Characterization of nanostructured semiconductors by ultrafast luminescence imaging . [Internet] [Doctoral dissertation]. University of Delaware; 2017. [cited 2020 Aug 09]. Available from: http://udspace.udel.edu/handle/19716/23107.

Council of Science Editors:

Blake J. Characterization of nanostructured semiconductors by ultrafast luminescence imaging . [Doctoral Dissertation]. University of Delaware; 2017. Available from: http://udspace.udel.edu/handle/19716/23107


University of Illinois – Chicago

11. Colon, Albert. Design and Optimization of GaN-Based Power Semiconductor Transistors.

Degree: 2017, University of Illinois – Chicago

 Gallium Nitride, a wide bandgap semiconductor, is a robust material with applications in high-power transistors and power amplifiers. However, processing technology is still maturing and… (more)

Subjects/Keywords: AlGaN; Capacitors; Dielectrics; GaN; Gate Oxide; High-k; InAlN; Insulators; MISHFET; Ohmic Contact; Semiconductors; Transistors

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APA (6th Edition):

Colon, A. (2017). Design and Optimization of GaN-Based Power Semiconductor Transistors. (Thesis). University of Illinois – Chicago. Retrieved from http://hdl.handle.net/10027/21752

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Colon, Albert. “Design and Optimization of GaN-Based Power Semiconductor Transistors.” 2017. Thesis, University of Illinois – Chicago. Accessed August 09, 2020. http://hdl.handle.net/10027/21752.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Colon, Albert. “Design and Optimization of GaN-Based Power Semiconductor Transistors.” 2017. Web. 09 Aug 2020.

Vancouver:

Colon A. Design and Optimization of GaN-Based Power Semiconductor Transistors. [Internet] [Thesis]. University of Illinois – Chicago; 2017. [cited 2020 Aug 09]. Available from: http://hdl.handle.net/10027/21752.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Colon A. Design and Optimization of GaN-Based Power Semiconductor Transistors. [Thesis]. University of Illinois – Chicago; 2017. Available from: http://hdl.handle.net/10027/21752

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

12. Tsai, Chen-Chi. Study of Non-Classical CMOSs by Using Junctionless and Punch-Through Technology.

Degree: Master, Electrical Engineering, 2013, NSYSU

 In this thesis, we propose four types non-classical CMOS inverters which the load use junctionless and punch-through technology. These inverters all use traditional NMOS as… (more)

Subjects/Keywords: low power consumption; 3D fold up; junctionless PMOS; gate P+-I-P+ transistor; two embedded oxide punch-through transistor; gate P-P-P+ transistor

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APA (6th Edition):

Tsai, C. (2013). Study of Non-Classical CMOSs by Using Junctionless and Punch-Through Technology. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0705113-145004

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tsai, Chen-Chi. “Study of Non-Classical CMOSs by Using Junctionless and Punch-Through Technology.” 2013. Thesis, NSYSU. Accessed August 09, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0705113-145004.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tsai, Chen-Chi. “Study of Non-Classical CMOSs by Using Junctionless and Punch-Through Technology.” 2013. Web. 09 Aug 2020.

Vancouver:

Tsai C. Study of Non-Classical CMOSs by Using Junctionless and Punch-Through Technology. [Internet] [Thesis]. NSYSU; 2013. [cited 2020 Aug 09]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0705113-145004.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tsai C. Study of Non-Classical CMOSs by Using Junctionless and Punch-Through Technology. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0705113-145004

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Tech

13. Raszmann, Emma Barbara. Series-Connection of Silicon Carbide MOSFET Modules using Active Gate-Drivers with dv/dt Control.

Degree: MS, Electrical Engineering, 2019, Virginia Tech

 According to ABB, 40% of the world's power demand is supplied by electrical energy. Specifically, in 2018, the world's electrical demand has grown by 4%… (more)

Subjects/Keywords: series-connected devices; silicon carbide (SiC); metal-oxide-semiconductor field-effect transistor (MOSFET); gate-driver design; active gate control; active dv/dt control; medium-voltage; voltage balancing

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APA (6th Edition):

Raszmann, E. B. (2019). Series-Connection of Silicon Carbide MOSFET Modules using Active Gate-Drivers with dv/dt Control. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/95938

Chicago Manual of Style (16th Edition):

Raszmann, Emma Barbara. “Series-Connection of Silicon Carbide MOSFET Modules using Active Gate-Drivers with dv/dt Control.” 2019. Masters Thesis, Virginia Tech. Accessed August 09, 2020. http://hdl.handle.net/10919/95938.

MLA Handbook (7th Edition):

Raszmann, Emma Barbara. “Series-Connection of Silicon Carbide MOSFET Modules using Active Gate-Drivers with dv/dt Control.” 2019. Web. 09 Aug 2020.

Vancouver:

Raszmann EB. Series-Connection of Silicon Carbide MOSFET Modules using Active Gate-Drivers with dv/dt Control. [Internet] [Masters thesis]. Virginia Tech; 2019. [cited 2020 Aug 09]. Available from: http://hdl.handle.net/10919/95938.

Council of Science Editors:

Raszmann EB. Series-Connection of Silicon Carbide MOSFET Modules using Active Gate-Drivers with dv/dt Control. [Masters Thesis]. Virginia Tech; 2019. Available from: http://hdl.handle.net/10919/95938

14. CHANDRASEKAR VENKATARAMANI. EXPERIMENTAL STUDY OF HIGH GATE TO DRAIN LEAKAGE CURRENT IN 0.18μm CMOS TECHNOLOGY.

Degree: 2003, National University of Singapore

Subjects/Keywords: Salicide Bridging; gate to drain leakage; gate oxide defects; Leakage current

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APA (6th Edition):

VENKATARAMANI, C. (2003). EXPERIMENTAL STUDY OF HIGH GATE TO DRAIN LEAKAGE CURRENT IN 0.18μm CMOS TECHNOLOGY. (Thesis). National University of Singapore. Retrieved from https://scholarbank.nus.edu.sg/handle/10635/154027

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

VENKATARAMANI, CHANDRASEKAR. “EXPERIMENTAL STUDY OF HIGH GATE TO DRAIN LEAKAGE CURRENT IN 0.18μm CMOS TECHNOLOGY.” 2003. Thesis, National University of Singapore. Accessed August 09, 2020. https://scholarbank.nus.edu.sg/handle/10635/154027.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

VENKATARAMANI, CHANDRASEKAR. “EXPERIMENTAL STUDY OF HIGH GATE TO DRAIN LEAKAGE CURRENT IN 0.18μm CMOS TECHNOLOGY.” 2003. Web. 09 Aug 2020.

Vancouver:

VENKATARAMANI C. EXPERIMENTAL STUDY OF HIGH GATE TO DRAIN LEAKAGE CURRENT IN 0.18μm CMOS TECHNOLOGY. [Internet] [Thesis]. National University of Singapore; 2003. [cited 2020 Aug 09]. Available from: https://scholarbank.nus.edu.sg/handle/10635/154027.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

VENKATARAMANI C. EXPERIMENTAL STUDY OF HIGH GATE TO DRAIN LEAKAGE CURRENT IN 0.18μm CMOS TECHNOLOGY. [Thesis]. National University of Singapore; 2003. Available from: https://scholarbank.nus.edu.sg/handle/10635/154027

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

15. Lu, Jiang. Hafnium-doped tantalum oxide high-k gate dielectric films for future CMOS technology.

Degree: 2007, Texas A&M University

 A novel high-k gate dielectric material, i.e., hafnium-doped tantalum oxide (Hf-doped TaOx), has been studied for the application of the future generation metal-oxidesemiconductor field effect… (more)

Subjects/Keywords: high-k; gate dielectric; metal gate electrode; Tantalum Oxide; Hafnium Oxide; Doped Oxide; Sputtering Deposition

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lu, J. (2007). Hafnium-doped tantalum oxide high-k gate dielectric films for future CMOS technology. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/4714

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lu, Jiang. “Hafnium-doped tantalum oxide high-k gate dielectric films for future CMOS technology.” 2007. Thesis, Texas A&M University. Accessed August 09, 2020. http://hdl.handle.net/1969.1/4714.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lu, Jiang. “Hafnium-doped tantalum oxide high-k gate dielectric films for future CMOS technology.” 2007. Web. 09 Aug 2020.

Vancouver:

Lu J. Hafnium-doped tantalum oxide high-k gate dielectric films for future CMOS technology. [Internet] [Thesis]. Texas A&M University; 2007. [cited 2020 Aug 09]. Available from: http://hdl.handle.net/1969.1/4714.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lu J. Hafnium-doped tantalum oxide high-k gate dielectric films for future CMOS technology. [Thesis]. Texas A&M University; 2007. Available from: http://hdl.handle.net/1969.1/4714

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Kentucky

16. Han, Lei. IMPROVEMENT OF SILICON OXIDE QUALITY USING HEAT TREATMENT.

Degree: 2012, University of Kentucky

 In decades, the tremendous development of integrated circuits industry could be mostly attributed to SiO2, since its satisfactory properties as a gate dielectric candidate. The… (more)

Subjects/Keywords: Gate Leakage Current; Silicon Oxide; Leatral Heating Process; Silicon Structure Change; Wet Etching; Electrical and Computer Engineering

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APA (6th Edition):

Han, L. (2012). IMPROVEMENT OF SILICON OXIDE QUALITY USING HEAT TREATMENT. (Masters Thesis). University of Kentucky. Retrieved from http://uknowledge.uky.edu/ece_etds/5

Chicago Manual of Style (16th Edition):

Han, Lei. “IMPROVEMENT OF SILICON OXIDE QUALITY USING HEAT TREATMENT.” 2012. Masters Thesis, University of Kentucky. Accessed August 09, 2020. http://uknowledge.uky.edu/ece_etds/5.

MLA Handbook (7th Edition):

Han, Lei. “IMPROVEMENT OF SILICON OXIDE QUALITY USING HEAT TREATMENT.” 2012. Web. 09 Aug 2020.

Vancouver:

Han L. IMPROVEMENT OF SILICON OXIDE QUALITY USING HEAT TREATMENT. [Internet] [Masters thesis]. University of Kentucky; 2012. [cited 2020 Aug 09]. Available from: http://uknowledge.uky.edu/ece_etds/5.

Council of Science Editors:

Han L. IMPROVEMENT OF SILICON OXIDE QUALITY USING HEAT TREATMENT. [Masters Thesis]. University of Kentucky; 2012. Available from: http://uknowledge.uky.edu/ece_etds/5

17. Anu, Philip. Preparation and Characterization ofHigh-k Aluminum Oxide Thin Films by Atomic Layer Deposition for Gate Dielectric Applications.

Degree: Instrumentation, 2011, Cochin University of Science and Technology

Present work deals with the Preparation and characterization of high-k aluminum oxide thin films by atomic layer deposition for gate dielectric applications.The ever-increasing demand for… (more)

Subjects/Keywords: Thin Films; Atomic Layer Deposition; High-k Aluminum Oxide; Gate Dielectric Applications; Plasma Enhanced Atomic Layer Deposition

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APA (6th Edition):

Anu, P. (2011). Preparation and Characterization ofHigh-k Aluminum Oxide Thin Films by Atomic Layer Deposition for Gate Dielectric Applications. (Thesis). Cochin University of Science and Technology. Retrieved from http://dyuthi.cusat.ac.in/purl/3034

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Anu, Philip. “Preparation and Characterization ofHigh-k Aluminum Oxide Thin Films by Atomic Layer Deposition for Gate Dielectric Applications.” 2011. Thesis, Cochin University of Science and Technology. Accessed August 09, 2020. http://dyuthi.cusat.ac.in/purl/3034.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Anu, Philip. “Preparation and Characterization ofHigh-k Aluminum Oxide Thin Films by Atomic Layer Deposition for Gate Dielectric Applications.” 2011. Web. 09 Aug 2020.

Vancouver:

Anu P. Preparation and Characterization ofHigh-k Aluminum Oxide Thin Films by Atomic Layer Deposition for Gate Dielectric Applications. [Internet] [Thesis]. Cochin University of Science and Technology; 2011. [cited 2020 Aug 09]. Available from: http://dyuthi.cusat.ac.in/purl/3034.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Anu P. Preparation and Characterization ofHigh-k Aluminum Oxide Thin Films by Atomic Layer Deposition for Gate Dielectric Applications. [Thesis]. Cochin University of Science and Technology; 2011. Available from: http://dyuthi.cusat.ac.in/purl/3034

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

18. Jiang, Jiayu. Study of Thin Silicon Oxides and High-K Materials for Gate Dielectrics in Metal-Insulator-Si Structures.

Degree: PhD, Engineering Science and Mechanics, 2004, Penn State University

 The development of a gate stack system (dielectric, electrode, and their compatibility with plasma etching processes and the scaled complementary metal oxide semiconductor [CMOS] integrated… (more)

Subjects/Keywords: thin oxide; high k; gate dielectrics; characterization

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APA (6th Edition):

Jiang, J. (2004). Study of Thin Silicon Oxides and High-K Materials for Gate Dielectrics in Metal-Insulator-Si Structures. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/6342

Chicago Manual of Style (16th Edition):

Jiang, Jiayu. “Study of Thin Silicon Oxides and High-K Materials for Gate Dielectrics in Metal-Insulator-Si Structures.” 2004. Doctoral Dissertation, Penn State University. Accessed August 09, 2020. https://etda.libraries.psu.edu/catalog/6342.

MLA Handbook (7th Edition):

Jiang, Jiayu. “Study of Thin Silicon Oxides and High-K Materials for Gate Dielectrics in Metal-Insulator-Si Structures.” 2004. Web. 09 Aug 2020.

Vancouver:

Jiang J. Study of Thin Silicon Oxides and High-K Materials for Gate Dielectrics in Metal-Insulator-Si Structures. [Internet] [Doctoral dissertation]. Penn State University; 2004. [cited 2020 Aug 09]. Available from: https://etda.libraries.psu.edu/catalog/6342.

Council of Science Editors:

Jiang J. Study of Thin Silicon Oxides and High-K Materials for Gate Dielectrics in Metal-Insulator-Si Structures. [Doctoral Dissertation]. Penn State University; 2004. Available from: https://etda.libraries.psu.edu/catalog/6342


Penn State University

19. Sun, Kaige. Double-Gate, Tri-Layer, and Vertical ZnO TFTs and Circuits.

Degree: PhD, Electrical Engineering, 2015, Penn State University

 Zinc oxide thin film transistor (ZnO TFT) technology can be applied to the integrated circuits (ICs) of high-performance large-area electronics. In this dissertation, innovations in… (more)

Subjects/Keywords: double-gate TFT; tri-layer TFT; vertical TFT; zinc oxide; circuits; modeling; PEALD; digital and analog circuits; rectifier

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APA (6th Edition):

Sun, K. (2015). Double-Gate, Tri-Layer, and Vertical ZnO TFTs and Circuits. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/26520

Chicago Manual of Style (16th Edition):

Sun, Kaige. “Double-Gate, Tri-Layer, and Vertical ZnO TFTs and Circuits.” 2015. Doctoral Dissertation, Penn State University. Accessed August 09, 2020. https://etda.libraries.psu.edu/catalog/26520.

MLA Handbook (7th Edition):

Sun, Kaige. “Double-Gate, Tri-Layer, and Vertical ZnO TFTs and Circuits.” 2015. Web. 09 Aug 2020.

Vancouver:

Sun K. Double-Gate, Tri-Layer, and Vertical ZnO TFTs and Circuits. [Internet] [Doctoral dissertation]. Penn State University; 2015. [cited 2020 Aug 09]. Available from: https://etda.libraries.psu.edu/catalog/26520.

Council of Science Editors:

Sun K. Double-Gate, Tri-Layer, and Vertical ZnO TFTs and Circuits. [Doctoral Dissertation]. Penn State University; 2015. Available from: https://etda.libraries.psu.edu/catalog/26520

20. Souza, Cesar Augusto Alves de. Caracterização elétrica de oxinitretos de silício ultrafinos para porta PMOS obtidos por implantação de nitrogênio na estrutura Si-poli/SiO2/Si.

Degree: Mestrado, Microeletrônica, 2008, University of São Paulo

Neste trabalho foram fabricados e caracterizados eletricamente capacitores MOS com óxido de silício ultrafino (2,6 nm) com porta de silício policristalino (Si-poli) P+ e N+.… (more)

Subjects/Keywords: Capacitores MOS; Gate dielectrics; Implantação Iônica; MOS capacitor; Nitrogen; Nitrogênio; Óxidos de porta ultrafino; Silicon oxide

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APA (6th Edition):

Souza, C. A. A. d. (2008). Caracterização elétrica de oxinitretos de silício ultrafinos para porta PMOS obtidos por implantação de nitrogênio na estrutura Si-poli/SiO2/Si. (Masters Thesis). University of São Paulo. Retrieved from http://www.teses.usp.br/teses/disponiveis/3/3140/tde-14082008-083525/ ;

Chicago Manual of Style (16th Edition):

Souza, Cesar Augusto Alves de. “Caracterização elétrica de oxinitretos de silício ultrafinos para porta PMOS obtidos por implantação de nitrogênio na estrutura Si-poli/SiO2/Si.” 2008. Masters Thesis, University of São Paulo. Accessed August 09, 2020. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-14082008-083525/ ;.

MLA Handbook (7th Edition):

Souza, Cesar Augusto Alves de. “Caracterização elétrica de oxinitretos de silício ultrafinos para porta PMOS obtidos por implantação de nitrogênio na estrutura Si-poli/SiO2/Si.” 2008. Web. 09 Aug 2020.

Vancouver:

Souza CAAd. Caracterização elétrica de oxinitretos de silício ultrafinos para porta PMOS obtidos por implantação de nitrogênio na estrutura Si-poli/SiO2/Si. [Internet] [Masters thesis]. University of São Paulo; 2008. [cited 2020 Aug 09]. Available from: http://www.teses.usp.br/teses/disponiveis/3/3140/tde-14082008-083525/ ;.

Council of Science Editors:

Souza CAAd. Caracterização elétrica de oxinitretos de silício ultrafinos para porta PMOS obtidos por implantação de nitrogênio na estrutura Si-poli/SiO2/Si. [Masters Thesis]. University of São Paulo; 2008. Available from: http://www.teses.usp.br/teses/disponiveis/3/3140/tde-14082008-083525/ ;

21. Matsumoto, Takashi. Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits : バイアス温度不安定性とランダムテレグラフノイズがCMOS論理回路特性に及ぼす影響.

Degree: 博士(情報学), 2015, Kyoto University / 京都大学

新制・課程博士

甲第19137号

情博第583号

Subjects/Keywords: CMOS; NBTI; RTN; combinational circuit; gate oxide; reliability; noise

Page 1 Page 2 Page 3 Page 4

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APA (6th Edition):

Matsumoto, T. (2015). Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits : バイアス温度不安定性とランダムテレグラフノイズがCMOS論理回路特性に及ぼす影響. (Thesis). Kyoto University / 京都大学. Retrieved from http://hdl.handle.net/2433/199461 ; http://dx.doi.org/10.14989/doctor.k19137

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Matsumoto, Takashi. “Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits : バイアス温度不安定性とランダムテレグラフノイズがCMOS論理回路特性に及ぼす影響.” 2015. Thesis, Kyoto University / 京都大学. Accessed August 09, 2020. http://hdl.handle.net/2433/199461 ; http://dx.doi.org/10.14989/doctor.k19137.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Matsumoto, Takashi. “Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits : バイアス温度不安定性とランダムテレグラフノイズがCMOS論理回路特性に及ぼす影響.” 2015. Web. 09 Aug 2020.

Vancouver:

Matsumoto T. Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits : バイアス温度不安定性とランダムテレグラフノイズがCMOS論理回路特性に及ぼす影響. [Internet] [Thesis]. Kyoto University / 京都大学; 2015. [cited 2020 Aug 09]. Available from: http://hdl.handle.net/2433/199461 ; http://dx.doi.org/10.14989/doctor.k19137.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Matsumoto T. Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits : バイアス温度不安定性とランダムテレグラフノイズがCMOS論理回路特性に及ぼす影響. [Thesis]. Kyoto University / 京都大学; 2015. Available from: http://hdl.handle.net/2433/199461 ; http://dx.doi.org/10.14989/doctor.k19137

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

22. Tsai, Mei-Na. Electrical Properties of n-MOSFETs under Uniaxial Mechanical Strain.

Degree: PhD, Physics, 2012, NSYSU

 Metal-oxide-semiconductor field-effect transistors (MOSFETs) are major devices inintegrated circuit, extensively used in various electronic products. In order to improve the electrical characteristics, scaling channel width… (more)

Subjects/Keywords: mechanical strains; gate leakage.; external mechanical stress; CMOS; uniaxial stress; metal-oxide-semiconductor field-effect transistors (MOSFET); strained-silicon (Si)

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APA (6th Edition):

Tsai, M. (2012). Electrical Properties of n-MOSFETs under Uniaxial Mechanical Strain. (Doctoral Dissertation). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0118112-073858

Chicago Manual of Style (16th Edition):

Tsai, Mei-Na. “Electrical Properties of n-MOSFETs under Uniaxial Mechanical Strain.” 2012. Doctoral Dissertation, NSYSU. Accessed August 09, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0118112-073858.

MLA Handbook (7th Edition):

Tsai, Mei-Na. “Electrical Properties of n-MOSFETs under Uniaxial Mechanical Strain.” 2012. Web. 09 Aug 2020.

Vancouver:

Tsai M. Electrical Properties of n-MOSFETs under Uniaxial Mechanical Strain. [Internet] [Doctoral dissertation]. NSYSU; 2012. [cited 2020 Aug 09]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0118112-073858.

Council of Science Editors:

Tsai M. Electrical Properties of n-MOSFETs under Uniaxial Mechanical Strain. [Doctoral Dissertation]. NSYSU; 2012. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0118112-073858


Kyoto University / 京都大学

23. 松本, 高士. バイアス温度不安定性とランダムテレグラフノイズがCMOS論理回路特性に及ぼす影響 : Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits.

Degree: 博士(情報学), 2015, Kyoto University / 京都大学

新制・課程博士

甲第19137号

情博第583号

Subjects/Keywords: CMOS; NBTI; RTN; combinational circuit; gate oxide; reliability; noise

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

松本, . (2015). バイアス温度不安定性とランダムテレグラフノイズがCMOS論理回路特性に及ぼす影響 : Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits. (Thesis). Kyoto University / 京都大学. Retrieved from http://hdl.handle.net/2433/199558

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

松本, 高士. “バイアス温度不安定性とランダムテレグラフノイズがCMOS論理回路特性に及ぼす影響 : Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits.” 2015. Thesis, Kyoto University / 京都大学. Accessed August 09, 2020. http://hdl.handle.net/2433/199558.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

松本, 高士. “バイアス温度不安定性とランダムテレグラフノイズがCMOS論理回路特性に及ぼす影響 : Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits.” 2015. Web. 09 Aug 2020.

Vancouver:

松本 . バイアス温度不安定性とランダムテレグラフノイズがCMOS論理回路特性に及ぼす影響 : Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits. [Internet] [Thesis]. Kyoto University / 京都大学; 2015. [cited 2020 Aug 09]. Available from: http://hdl.handle.net/2433/199558.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

松本 . バイアス温度不安定性とランダムテレグラフノイズがCMOS論理回路特性に及ぼす影響 : Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits. [Thesis]. Kyoto University / 京都大学; 2015. Available from: http://hdl.handle.net/2433/199558

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Tokyo Institute of Technology / 東京工業大学

24. DOU, CHUN MENG. A study on interface traps and near interfacial bulk traps at the interfaces of dielectric/semiconductor and semiconductor heterojunction : A study on interface traps and near interfacial bulk traps at the interfaces of dielectric/semiconductor and semiconductor heterojunction; 誘電体/半導体と半導体ヘテロ接合界面における界面トラップおよび界面近傍のバルクトラップに関する研究.

Degree: 博士(工学), 2014, Tokyo Institute of Technology / 東京工業大学

 In order to avoid CMOS down-scaling limit due to the short-channel effect, multi-gate structure, such as fin-FETs or Tri-gate has been introduced. In addition, MOSFETs… (more)

Subjects/Keywords: Interface traps; oxide border traps; MOS; multi-gate structure; high-k/III-V; AlGaN/GaN HEMT

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APA (6th Edition):

DOU, C. M. (2014). A study on interface traps and near interfacial bulk traps at the interfaces of dielectric/semiconductor and semiconductor heterojunction : A study on interface traps and near interfacial bulk traps at the interfaces of dielectric/semiconductor and semiconductor heterojunction; 誘電体/半導体と半導体ヘテロ接合界面における界面トラップおよび界面近傍のバルクトラップに関する研究. (Thesis). Tokyo Institute of Technology / 東京工業大学. Retrieved from http://t2r2.star.titech.ac.jp/cgi-bin/publicationinfo.cgi?q_publication_content_number=CTT100667420

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

DOU, CHUN MENG. “A study on interface traps and near interfacial bulk traps at the interfaces of dielectric/semiconductor and semiconductor heterojunction : A study on interface traps and near interfacial bulk traps at the interfaces of dielectric/semiconductor and semiconductor heterojunction; 誘電体/半導体と半導体ヘテロ接合界面における界面トラップおよび界面近傍のバルクトラップに関する研究.” 2014. Thesis, Tokyo Institute of Technology / 東京工業大学. Accessed August 09, 2020. http://t2r2.star.titech.ac.jp/cgi-bin/publicationinfo.cgi?q_publication_content_number=CTT100667420.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

DOU, CHUN MENG. “A study on interface traps and near interfacial bulk traps at the interfaces of dielectric/semiconductor and semiconductor heterojunction : A study on interface traps and near interfacial bulk traps at the interfaces of dielectric/semiconductor and semiconductor heterojunction; 誘電体/半導体と半導体ヘテロ接合界面における界面トラップおよび界面近傍のバルクトラップに関する研究.” 2014. Web. 09 Aug 2020.

Vancouver:

DOU CM. A study on interface traps and near interfacial bulk traps at the interfaces of dielectric/semiconductor and semiconductor heterojunction : A study on interface traps and near interfacial bulk traps at the interfaces of dielectric/semiconductor and semiconductor heterojunction; 誘電体/半導体と半導体ヘテロ接合界面における界面トラップおよび界面近傍のバルクトラップに関する研究. [Internet] [Thesis]. Tokyo Institute of Technology / 東京工業大学; 2014. [cited 2020 Aug 09]. Available from: http://t2r2.star.titech.ac.jp/cgi-bin/publicationinfo.cgi?q_publication_content_number=CTT100667420.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

DOU CM. A study on interface traps and near interfacial bulk traps at the interfaces of dielectric/semiconductor and semiconductor heterojunction : A study on interface traps and near interfacial bulk traps at the interfaces of dielectric/semiconductor and semiconductor heterojunction; 誘電体/半導体と半導体ヘテロ接合界面における界面トラップおよび界面近傍のバルクトラップに関する研究. [Thesis]. Tokyo Institute of Technology / 東京工業大学; 2014. Available from: http://t2r2.star.titech.ac.jp/cgi-bin/publicationinfo.cgi?q_publication_content_number=CTT100667420

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Kyoto University

25. Matsumoto, Takashi. Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits .

Degree: 2015, Kyoto University

Subjects/Keywords: CMOS; NBTI; RTN; combinational circuit; gate oxide; reliability; noise

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Matsumoto, T. (2015). Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits . (Thesis). Kyoto University. Retrieved from http://hdl.handle.net/2433/199461

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Matsumoto, Takashi. “Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits .” 2015. Thesis, Kyoto University. Accessed August 09, 2020. http://hdl.handle.net/2433/199461.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Matsumoto, Takashi. “Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits .” 2015. Web. 09 Aug 2020.

Vancouver:

Matsumoto T. Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits . [Internet] [Thesis]. Kyoto University; 2015. [cited 2020 Aug 09]. Available from: http://hdl.handle.net/2433/199461.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Matsumoto T. Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits . [Thesis]. Kyoto University; 2015. Available from: http://hdl.handle.net/2433/199461

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

26. Mamy Randriamihaja, Yoann. Etude de la fiabilité des technologies CMOS avancées, depuis la création des défauts jusqu'à la dégradation des transistors : Responses of naturally regenerated beech (Fagus sylvatica L.) and sycamore (Acer pseudoplatanus L.) saplings to canopy opening : growth and functional adjustments.

Degree: Docteur es, Micro et Nano Electronique, 2012, Aix Marseille Université

L'étude de la fiabilité représente un enjeu majeur de la qualification des technologies de l'industrie de la microélectronique. Elle est traditionnellement étudiée en suivant la… (more)

Subjects/Keywords: Transistor MOS; Fiabilité; Porteurs chauds; Claquage d’oxyde; Modélisation; MOS transistor; Reliability; Hot Carrier; Gate-oxide breakdown; Modeling

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APA (6th Edition):

Mamy Randriamihaja, Y. (2012). Etude de la fiabilité des technologies CMOS avancées, depuis la création des défauts jusqu'à la dégradation des transistors : Responses of naturally regenerated beech (Fagus sylvatica L.) and sycamore (Acer pseudoplatanus L.) saplings to canopy opening : growth and functional adjustments. (Doctoral Dissertation). Aix Marseille Université. Retrieved from http://www.theses.fr/2012AIXM4781

Chicago Manual of Style (16th Edition):

Mamy Randriamihaja, Yoann. “Etude de la fiabilité des technologies CMOS avancées, depuis la création des défauts jusqu'à la dégradation des transistors : Responses of naturally regenerated beech (Fagus sylvatica L.) and sycamore (Acer pseudoplatanus L.) saplings to canopy opening : growth and functional adjustments.” 2012. Doctoral Dissertation, Aix Marseille Université. Accessed August 09, 2020. http://www.theses.fr/2012AIXM4781.

MLA Handbook (7th Edition):

Mamy Randriamihaja, Yoann. “Etude de la fiabilité des technologies CMOS avancées, depuis la création des défauts jusqu'à la dégradation des transistors : Responses of naturally regenerated beech (Fagus sylvatica L.) and sycamore (Acer pseudoplatanus L.) saplings to canopy opening : growth and functional adjustments.” 2012. Web. 09 Aug 2020.

Vancouver:

Mamy Randriamihaja Y. Etude de la fiabilité des technologies CMOS avancées, depuis la création des défauts jusqu'à la dégradation des transistors : Responses of naturally regenerated beech (Fagus sylvatica L.) and sycamore (Acer pseudoplatanus L.) saplings to canopy opening : growth and functional adjustments. [Internet] [Doctoral dissertation]. Aix Marseille Université 2012. [cited 2020 Aug 09]. Available from: http://www.theses.fr/2012AIXM4781.

Council of Science Editors:

Mamy Randriamihaja Y. Etude de la fiabilité des technologies CMOS avancées, depuis la création des défauts jusqu'à la dégradation des transistors : Responses of naturally regenerated beech (Fagus sylvatica L.) and sycamore (Acer pseudoplatanus L.) saplings to canopy opening : growth and functional adjustments. [Doctoral Dissertation]. Aix Marseille Université 2012. Available from: http://www.theses.fr/2012AIXM4781


University of Illinois – Chicago

27. Zhang, Nanzhu. Interface Phonon Modes of Heterostructures and Quantum Dots/Polymer Composite System.

Degree: 2014, University of Illinois – Chicago

 In the first part of the thesis, some basic knowledge related to my research is introduced, such as what is MOSFET, polymer and QDs. In… (more)

Subjects/Keywords: Dual-gate Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET); Wurtzite Quantum Heterostructures; Photodetector; Quantum Dots; Interface phonon modes

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APA (6th Edition):

Zhang, N. (2014). Interface Phonon Modes of Heterostructures and Quantum Dots/Polymer Composite System. (Thesis). University of Illinois – Chicago. Retrieved from http://hdl.handle.net/10027/18882

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zhang, Nanzhu. “Interface Phonon Modes of Heterostructures and Quantum Dots/Polymer Composite System.” 2014. Thesis, University of Illinois – Chicago. Accessed August 09, 2020. http://hdl.handle.net/10027/18882.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zhang, Nanzhu. “Interface Phonon Modes of Heterostructures and Quantum Dots/Polymer Composite System.” 2014. Web. 09 Aug 2020.

Vancouver:

Zhang N. Interface Phonon Modes of Heterostructures and Quantum Dots/Polymer Composite System. [Internet] [Thesis]. University of Illinois – Chicago; 2014. [cited 2020 Aug 09]. Available from: http://hdl.handle.net/10027/18882.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zhang N. Interface Phonon Modes of Heterostructures and Quantum Dots/Polymer Composite System. [Thesis]. University of Illinois – Chicago; 2014. Available from: http://hdl.handle.net/10027/18882

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

28. LIAO HONG. Characterization of hot carrier reliability in deep submicronmeter MOSFETs.

Degree: 2005, National University of Singapore

Subjects/Keywords: MOSFET; hot carrier effect; reliability; gate oxide; interface; degradation

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APA (6th Edition):

HONG, L. (2005). Characterization of hot carrier reliability in deep submicronmeter MOSFETs. (Thesis). National University of Singapore. Retrieved from http://scholarbank.nus.edu.sg/handle/10635/14920

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

HONG, LIAO. “Characterization of hot carrier reliability in deep submicronmeter MOSFETs.” 2005. Thesis, National University of Singapore. Accessed August 09, 2020. http://scholarbank.nus.edu.sg/handle/10635/14920.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

HONG, LIAO. “Characterization of hot carrier reliability in deep submicronmeter MOSFETs.” 2005. Web. 09 Aug 2020.

Vancouver:

HONG L. Characterization of hot carrier reliability in deep submicronmeter MOSFETs. [Internet] [Thesis]. National University of Singapore; 2005. [cited 2020 Aug 09]. Available from: http://scholarbank.nus.edu.sg/handle/10635/14920.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

HONG L. Characterization of hot carrier reliability in deep submicronmeter MOSFETs. [Thesis]. National University of Singapore; 2005. Available from: http://scholarbank.nus.edu.sg/handle/10635/14920

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

29. Akbal, Madjid. Effets d’antenne sur transistors FDSOI à film ultra mince issus de technologies 28nm et en deçà : Plasma charging in FDSOI ultra-thin body from 28nm technologies and below.

Degree: Docteur es, Nanoélectronique et nanotechnologie, 2016, Université Grenoble Alpes (ComUE)

Depuis ses débuts, l’industrie de la microélectronique s’est fixé comme objectif d’augmenter les performances et la densité des circuits, en suivant la loi de Moore.… (more)

Subjects/Keywords: Effets d’antenne; Procédé plasma; Transistor FDSOI; Dégradation de l’oxyde de grille; Antenna effect; Plasma process; FDSOI device; Gate oxide damage; 620

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Akbal, M. (2016). Effets d’antenne sur transistors FDSOI à film ultra mince issus de technologies 28nm et en deçà : Plasma charging in FDSOI ultra-thin body from 28nm technologies and below. (Doctoral Dissertation). Université Grenoble Alpes (ComUE). Retrieved from http://www.theses.fr/2016GREAT012

Chicago Manual of Style (16th Edition):

Akbal, Madjid. “Effets d’antenne sur transistors FDSOI à film ultra mince issus de technologies 28nm et en deçà : Plasma charging in FDSOI ultra-thin body from 28nm technologies and below.” 2016. Doctoral Dissertation, Université Grenoble Alpes (ComUE). Accessed August 09, 2020. http://www.theses.fr/2016GREAT012.

MLA Handbook (7th Edition):

Akbal, Madjid. “Effets d’antenne sur transistors FDSOI à film ultra mince issus de technologies 28nm et en deçà : Plasma charging in FDSOI ultra-thin body from 28nm technologies and below.” 2016. Web. 09 Aug 2020.

Vancouver:

Akbal M. Effets d’antenne sur transistors FDSOI à film ultra mince issus de technologies 28nm et en deçà : Plasma charging in FDSOI ultra-thin body from 28nm technologies and below. [Internet] [Doctoral dissertation]. Université Grenoble Alpes (ComUE); 2016. [cited 2020 Aug 09]. Available from: http://www.theses.fr/2016GREAT012.

Council of Science Editors:

Akbal M. Effets d’antenne sur transistors FDSOI à film ultra mince issus de technologies 28nm et en deçà : Plasma charging in FDSOI ultra-thin body from 28nm technologies and below. [Doctoral Dissertation]. Université Grenoble Alpes (ComUE); 2016. Available from: http://www.theses.fr/2016GREAT012


Texas Tech University

30. Mehta, Narendra Singh. Investigation of advanced gate dielectrics for future complementary metal-oxide semiconductor devices.

Degree: Electrical and Computer Engineering, 2002, Texas Tech University

Subjects/Keywords: Complementary; Dielectrics; Gate array circuits; Metal oxide semiconductors

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mehta, N. S. (2002). Investigation of advanced gate dielectrics for future complementary metal-oxide semiconductor devices. (Thesis). Texas Tech University. Retrieved from http://hdl.handle.net/2346/15731

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mehta, Narendra Singh. “Investigation of advanced gate dielectrics for future complementary metal-oxide semiconductor devices.” 2002. Thesis, Texas Tech University. Accessed August 09, 2020. http://hdl.handle.net/2346/15731.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mehta, Narendra Singh. “Investigation of advanced gate dielectrics for future complementary metal-oxide semiconductor devices.” 2002. Web. 09 Aug 2020.

Vancouver:

Mehta NS. Investigation of advanced gate dielectrics for future complementary metal-oxide semiconductor devices. [Internet] [Thesis]. Texas Tech University; 2002. [cited 2020 Aug 09]. Available from: http://hdl.handle.net/2346/15731.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mehta NS. Investigation of advanced gate dielectrics for future complementary metal-oxide semiconductor devices. [Thesis]. Texas Tech University; 2002. Available from: http://hdl.handle.net/2346/15731

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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