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You searched for subject:(flash ADC). Showing records 1 – 27 of 27 total matches.

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1. Crasso, Anthony. Background Calibration of a 6-Bit 1Gsps Split-Flash ADC.

Degree: MS, 2013, Worcester Polytechnic Institute

 In this MS thesis, a redundant flash analog-to-digital converter (ADC) using a ``Split-ADC' calibration structure and lookup-table-based correction is presented. ADC input capacitance is minimized… (more)

Subjects/Keywords: Calibration; Flash; ADC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Crasso, A. (2013). Background Calibration of a 6-Bit 1Gsps Split-Flash ADC. (Thesis). Worcester Polytechnic Institute. Retrieved from etd-011013-081923 ; https://digitalcommons.wpi.edu/etd-theses/54

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Crasso, Anthony. “Background Calibration of a 6-Bit 1Gsps Split-Flash ADC.” 2013. Thesis, Worcester Polytechnic Institute. Accessed August 14, 2020. etd-011013-081923 ; https://digitalcommons.wpi.edu/etd-theses/54.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Crasso, Anthony. “Background Calibration of a 6-Bit 1Gsps Split-Flash ADC.” 2013. Web. 14 Aug 2020.

Vancouver:

Crasso A. Background Calibration of a 6-Bit 1Gsps Split-Flash ADC. [Internet] [Thesis]. Worcester Polytechnic Institute; 2013. [cited 2020 Aug 14]. Available from: etd-011013-081923 ; https://digitalcommons.wpi.edu/etd-theses/54.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Crasso A. Background Calibration of a 6-Bit 1Gsps Split-Flash ADC. [Thesis]. Worcester Polytechnic Institute; 2013. Available from: etd-011013-081923 ; https://digitalcommons.wpi.edu/etd-theses/54

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Wright State University

2. Wang, Mingzhen. High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip.

Degree: PhD, Engineering PhD, 2007, Wright State University

 Wang, Mingzhen, Ph.D, Engineering Ph.D Program, Department of Electrical Engineering, Wright State University, 2007. High-Speed Low-Voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip With… (more)

Subjects/Keywords: tmp_output; ADC; flash ADC; CLK; CMOS; Outputs; comparator

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, M. (2007). High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip. (Doctoral Dissertation). Wright State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=wright1189815482

Chicago Manual of Style (16th Edition):

Wang, Mingzhen. “High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip.” 2007. Doctoral Dissertation, Wright State University. Accessed August 14, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=wright1189815482.

MLA Handbook (7th Edition):

Wang, Mingzhen. “High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip.” 2007. Web. 14 Aug 2020.

Vancouver:

Wang M. High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip. [Internet] [Doctoral dissertation]. Wright State University; 2007. [cited 2020 Aug 14]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1189815482.

Council of Science Editors:

Wang M. High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip. [Doctoral Dissertation]. Wright State University; 2007. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1189815482


University of California – Riverside

3. Tang, He. High Speed ADC Design Methodology.

Degree: Electrical Engineering, 2010, University of California – Riverside

 Analog-to-digital converter (ADC) is a very fundamental and key part to nearly all kinds of electronics. The applications cover a wide range requiring different resolution… (more)

Subjects/Keywords: Electrical Engineering; Design methodology; Flash ADC; High speed; Interpolation; Power dissipation

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APA (6th Edition):

Tang, H. (2010). High Speed ADC Design Methodology. (Thesis). University of California – Riverside. Retrieved from http://www.escholarship.org/uc/item/95k4k2d9

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tang, He. “High Speed ADC Design Methodology.” 2010. Thesis, University of California – Riverside. Accessed August 14, 2020. http://www.escholarship.org/uc/item/95k4k2d9.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tang, He. “High Speed ADC Design Methodology.” 2010. Web. 14 Aug 2020.

Vancouver:

Tang H. High Speed ADC Design Methodology. [Internet] [Thesis]. University of California – Riverside; 2010. [cited 2020 Aug 14]. Available from: http://www.escholarship.org/uc/item/95k4k2d9.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tang H. High Speed ADC Design Methodology. [Thesis]. University of California – Riverside; 2010. Available from: http://www.escholarship.org/uc/item/95k4k2d9

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

4. Park, Jun Hyuk. IMPROVED TIQ FLASH ADC TRANSISTOR SIZING ALGORITHMS TO REDUCE LINEARITY ERRORS.

Degree: 2017, Penn State University

 Integral nonlinearity and differential nonlinearity are the two main performance parameters for a high speed flash analog-to-digital converter, which determine the accuracy of the converter.… (more)

Subjects/Keywords: TIQ Flash ADC; TIQ Voltage Comparator; Nonlinearity; DNL; INL; Process Variation

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APA (6th Edition):

Park, J. H. (2017). IMPROVED TIQ FLASH ADC TRANSISTOR SIZING ALGORITHMS TO REDUCE LINEARITY ERRORS. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/14332jzp152

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Park, Jun Hyuk. “IMPROVED TIQ FLASH ADC TRANSISTOR SIZING ALGORITHMS TO REDUCE LINEARITY ERRORS.” 2017. Thesis, Penn State University. Accessed August 14, 2020. https://submit-etda.libraries.psu.edu/catalog/14332jzp152.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Park, Jun Hyuk. “IMPROVED TIQ FLASH ADC TRANSISTOR SIZING ALGORITHMS TO REDUCE LINEARITY ERRORS.” 2017. Web. 14 Aug 2020.

Vancouver:

Park JH. IMPROVED TIQ FLASH ADC TRANSISTOR SIZING ALGORITHMS TO REDUCE LINEARITY ERRORS. [Internet] [Thesis]. Penn State University; 2017. [cited 2020 Aug 14]. Available from: https://submit-etda.libraries.psu.edu/catalog/14332jzp152.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Park JH. IMPROVED TIQ FLASH ADC TRANSISTOR SIZING ALGORITHMS TO REDUCE LINEARITY ERRORS. [Thesis]. Penn State University; 2017. Available from: https://submit-etda.libraries.psu.edu/catalog/14332jzp152

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Harvard University

5. Mead, Curtis Charles. A Configurable Terasample-per-second Imaging System for Optical SETI.

Degree: PhD, Engineering and Applied Sciences, 2013, Harvard University

A new instrument for conducting astronomical searches for nanosecond-scale optical pulses has been designed, built, and is now operating at Oak Ridge Observatory in Harvard,… (more)

Subjects/Keywords: Astronomy; Electrical engineering; adc; extraterrestrial; flash; FPGA; optical; SETI

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APA (6th Edition):

Mead, C. C. (2013). A Configurable Terasample-per-second Imaging System for Optical SETI. (Doctoral Dissertation). Harvard University. Retrieved from http://nrs.harvard.edu/urn-3:HUL.InstRepos:11158246

Chicago Manual of Style (16th Edition):

Mead, Curtis Charles. “A Configurable Terasample-per-second Imaging System for Optical SETI.” 2013. Doctoral Dissertation, Harvard University. Accessed August 14, 2020. http://nrs.harvard.edu/urn-3:HUL.InstRepos:11158246.

MLA Handbook (7th Edition):

Mead, Curtis Charles. “A Configurable Terasample-per-second Imaging System for Optical SETI.” 2013. Web. 14 Aug 2020.

Vancouver:

Mead CC. A Configurable Terasample-per-second Imaging System for Optical SETI. [Internet] [Doctoral dissertation]. Harvard University; 2013. [cited 2020 Aug 14]. Available from: http://nrs.harvard.edu/urn-3:HUL.InstRepos:11158246.

Council of Science Editors:

Mead CC. A Configurable Terasample-per-second Imaging System for Optical SETI. [Doctoral Dissertation]. Harvard University; 2013. Available from: http://nrs.harvard.edu/urn-3:HUL.InstRepos:11158246

6. Ito, Tomohiko. 無線通信システム用A/D変換器の高性能化に関する研究.

Degree: 博士(工学), 2013, Hosei University / 法政大学

 To realize next-generation high-throughput wireless communication systems, it is essential to develop analog-to-digital converters (ADC) with high conversion speed, high resolution, low power, and low… (more)

Subjects/Keywords: ADC; A/D; Analog-to-Digital Converter; Pipeline; Flash; Wireless; Receiver

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APA (6th Edition):

Ito, T. (2013). 無線通信システム用A/D変換器の高性能化に関する研究. (Thesis). Hosei University / 法政大学. Retrieved from http://hdl.handle.net/10114/9760

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ito, Tomohiko. “無線通信システム用A/D変換器の高性能化に関する研究.” 2013. Thesis, Hosei University / 法政大学. Accessed August 14, 2020. http://hdl.handle.net/10114/9760.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ito, Tomohiko. “無線通信システム用A/D変換器の高性能化に関する研究.” 2013. Web. 14 Aug 2020.

Vancouver:

Ito T. 無線通信システム用A/D変換器の高性能化に関する研究. [Internet] [Thesis]. Hosei University / 法政大学; 2013. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/10114/9760.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ito T. 無線通信システム用A/D変換器の高性能化に関する研究. [Thesis]. Hosei University / 法政大学; 2013. Available from: http://hdl.handle.net/10114/9760

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

7. Majidi, Rabeeh. DIGITALLY ASSISTED TECHNIQUES FOR NYQUIST RATE ANALOG-to-DIGITAL CONVERTERS.

Degree: PhD, 2015, Worcester Polytechnic Institute

 With the advance of technology and rapid growth of digital systems, low power high speed analog-to-digital converters with great accuracy are in demand. To achieve… (more)

Subjects/Keywords: Analog to Digital Converter ADC SAR Flash Frequenc

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APA (6th Edition):

Majidi, R. (2015). DIGITALLY ASSISTED TECHNIQUES FOR NYQUIST RATE ANALOG-to-DIGITAL CONVERTERS. (Doctoral Dissertation). Worcester Polytechnic Institute. Retrieved from etd-050515-110405 ; https://digitalcommons.wpi.edu/etd-dissertations/275

Chicago Manual of Style (16th Edition):

Majidi, Rabeeh. “DIGITALLY ASSISTED TECHNIQUES FOR NYQUIST RATE ANALOG-to-DIGITAL CONVERTERS.” 2015. Doctoral Dissertation, Worcester Polytechnic Institute. Accessed August 14, 2020. etd-050515-110405 ; https://digitalcommons.wpi.edu/etd-dissertations/275.

MLA Handbook (7th Edition):

Majidi, Rabeeh. “DIGITALLY ASSISTED TECHNIQUES FOR NYQUIST RATE ANALOG-to-DIGITAL CONVERTERS.” 2015. Web. 14 Aug 2020.

Vancouver:

Majidi R. DIGITALLY ASSISTED TECHNIQUES FOR NYQUIST RATE ANALOG-to-DIGITAL CONVERTERS. [Internet] [Doctoral dissertation]. Worcester Polytechnic Institute; 2015. [cited 2020 Aug 14]. Available from: etd-050515-110405 ; https://digitalcommons.wpi.edu/etd-dissertations/275.

Council of Science Editors:

Majidi R. DIGITALLY ASSISTED TECHNIQUES FOR NYQUIST RATE ANALOG-to-DIGITAL CONVERTERS. [Doctoral Dissertation]. Worcester Polytechnic Institute; 2015. Available from: etd-050515-110405 ; https://digitalcommons.wpi.edu/etd-dissertations/275


Linköping University

8. Naqvi, Syed Hassan Raza. 1 GS/s, Low Power Flash, Analog to Digital Converter in 90nm CMOS Technology.

Degree: Electrical Engineering, 2007, Linköping University

  The analog to digital converters is the key components in modern electronic systems. As the digital signal processing industry grows the ADC design becomes… (more)

Subjects/Keywords: ADC; Data Converters; Flash ADC; Flash ADC in 90nm; Electrical engineering; Elektroteknik

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APA (6th Edition):

Naqvi, S. H. R. (2007). 1 GS/s, Low Power Flash, Analog to Digital Converter in 90nm CMOS Technology. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8382

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Naqvi, Syed Hassan Raza. “1 GS/s, Low Power Flash, Analog to Digital Converter in 90nm CMOS Technology.” 2007. Thesis, Linköping University. Accessed August 14, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8382.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Naqvi, Syed Hassan Raza. “1 GS/s, Low Power Flash, Analog to Digital Converter in 90nm CMOS Technology.” 2007. Web. 14 Aug 2020.

Vancouver:

Naqvi SHR. 1 GS/s, Low Power Flash, Analog to Digital Converter in 90nm CMOS Technology. [Internet] [Thesis]. Linköping University; 2007. [cited 2020 Aug 14]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8382.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Naqvi SHR. 1 GS/s, Low Power Flash, Analog to Digital Converter in 90nm CMOS Technology. [Thesis]. Linköping University; 2007. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8382

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

9. Abumurad, Abdulrahman. An Automated Framework for Flash ADC Design and Analysis.

Degree: 2020, Penn State University

 Threshold Inverter Quantizer (TIQ) Flash Analog to Digital Converters (ADCs) are good candidates for System-on-Chip applications because they can be designed using the digital CMOS… (more)

Subjects/Keywords: TIQ Comparators; Flash ADC; ADC Design Automation; Low-noise ADCs; Quality Flash ADCs; Circuit Layout Generation; Comparator Thresholds selection; Flash ADC and Process-Temperature-Voltage Variation; High-Precision Flash ADCs; Signal Switching Noise in Flash ADCs; Circuit Design Automation

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APA (6th Edition):

Abumurad, A. (2020). An Automated Framework for Flash ADC Design and Analysis. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/17761aka133

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Abumurad, Abdulrahman. “An Automated Framework for Flash ADC Design and Analysis.” 2020. Thesis, Penn State University. Accessed August 14, 2020. https://submit-etda.libraries.psu.edu/catalog/17761aka133.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Abumurad, Abdulrahman. “An Automated Framework for Flash ADC Design and Analysis.” 2020. Web. 14 Aug 2020.

Vancouver:

Abumurad A. An Automated Framework for Flash ADC Design and Analysis. [Internet] [Thesis]. Penn State University; 2020. [cited 2020 Aug 14]. Available from: https://submit-etda.libraries.psu.edu/catalog/17761aka133.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Abumurad A. An Automated Framework for Flash ADC Design and Analysis. [Thesis]. Penn State University; 2020. Available from: https://submit-etda.libraries.psu.edu/catalog/17761aka133

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Wright State University

10. Hiremath, Vinayashree. DESIGN OF ULTRA HIGH SPEED FLASH ADC, LOW POWER FOLDING AND INTERPOLATING ADC IN CMOS 90nm TECHNOLOGY.

Degree: MSEgr, Electrical Engineering, 2010, Wright State University

  In recent years, signal processing has gained ample significance making high speed and low voltage analog-to-digital converters (ADC) inevitable in numerous applications. Two such… (more)

Subjects/Keywords: Electrical Engineering; Analog to digital converter; Flash ADC; Fat tree encoder; Direct conversion encoder; Folding ADC; interpolation

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APA (6th Edition):

Hiremath, V. (2010). DESIGN OF ULTRA HIGH SPEED FLASH ADC, LOW POWER FOLDING AND INTERPOLATING ADC IN CMOS 90nm TECHNOLOGY. (Masters Thesis). Wright State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=wright1291391500

Chicago Manual of Style (16th Edition):

Hiremath, Vinayashree. “DESIGN OF ULTRA HIGH SPEED FLASH ADC, LOW POWER FOLDING AND INTERPOLATING ADC IN CMOS 90nm TECHNOLOGY.” 2010. Masters Thesis, Wright State University. Accessed August 14, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=wright1291391500.

MLA Handbook (7th Edition):

Hiremath, Vinayashree. “DESIGN OF ULTRA HIGH SPEED FLASH ADC, LOW POWER FOLDING AND INTERPOLATING ADC IN CMOS 90nm TECHNOLOGY.” 2010. Web. 14 Aug 2020.

Vancouver:

Hiremath V. DESIGN OF ULTRA HIGH SPEED FLASH ADC, LOW POWER FOLDING AND INTERPOLATING ADC IN CMOS 90nm TECHNOLOGY. [Internet] [Masters thesis]. Wright State University; 2010. [cited 2020 Aug 14]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1291391500.

Council of Science Editors:

Hiremath V. DESIGN OF ULTRA HIGH SPEED FLASH ADC, LOW POWER FOLDING AND INTERPOLATING ADC IN CMOS 90nm TECHNOLOGY. [Masters Thesis]. Wright State University; 2010. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1291391500


Université de Bordeaux I

11. Mariano, André Augusto. Mixed Simulations and Design of a Wideband Continuous-Time Bandpass Delta-Sigma Converter Dedicated to Software Dfined Radio Applications : Étude d'un émetteur numérique direct RF à base de synthétiseur numérique direct et de verrouillage par injection.

Degree: Docteur es, Electronique, 2008, Université de Bordeaux I

La chaîne de réception des téléphones mobiles de dernière génération utilisent au moins deux étages de transposition en fréquence avant d'effectuer la démodulation en quadrature.… (more)

Subjects/Keywords: Modulateur Sigma-Delta à temps continu; Convertisseur analogique-numérique; Modelisation comportementale; Convertisseur ultra-rapide; CAN Flash CMOS; High-Speed ADC; Continuous-time Delta-Sigma modulator; CMOS Flash ADC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mariano, A. A. (2008). Mixed Simulations and Design of a Wideband Continuous-Time Bandpass Delta-Sigma Converter Dedicated to Software Dfined Radio Applications : Étude d'un émetteur numérique direct RF à base de synthétiseur numérique direct et de verrouillage par injection. (Doctoral Dissertation). Université de Bordeaux I. Retrieved from http://www.theses.fr/2008BOR13644

Chicago Manual of Style (16th Edition):

Mariano, André Augusto. “Mixed Simulations and Design of a Wideband Continuous-Time Bandpass Delta-Sigma Converter Dedicated to Software Dfined Radio Applications : Étude d'un émetteur numérique direct RF à base de synthétiseur numérique direct et de verrouillage par injection.” 2008. Doctoral Dissertation, Université de Bordeaux I. Accessed August 14, 2020. http://www.theses.fr/2008BOR13644.

MLA Handbook (7th Edition):

Mariano, André Augusto. “Mixed Simulations and Design of a Wideband Continuous-Time Bandpass Delta-Sigma Converter Dedicated to Software Dfined Radio Applications : Étude d'un émetteur numérique direct RF à base de synthétiseur numérique direct et de verrouillage par injection.” 2008. Web. 14 Aug 2020.

Vancouver:

Mariano AA. Mixed Simulations and Design of a Wideband Continuous-Time Bandpass Delta-Sigma Converter Dedicated to Software Dfined Radio Applications : Étude d'un émetteur numérique direct RF à base de synthétiseur numérique direct et de verrouillage par injection. [Internet] [Doctoral dissertation]. Université de Bordeaux I; 2008. [cited 2020 Aug 14]. Available from: http://www.theses.fr/2008BOR13644.

Council of Science Editors:

Mariano AA. Mixed Simulations and Design of a Wideband Continuous-Time Bandpass Delta-Sigma Converter Dedicated to Software Dfined Radio Applications : Étude d'un émetteur numérique direct RF à base de synthétiseur numérique direct et de verrouillage par injection. [Doctoral Dissertation]. Université de Bordeaux I; 2008. Available from: http://www.theses.fr/2008BOR13644

12. Wagner, Wolfgang. Design and realisation of a new AMANDA data acquisition system with transient waveform recorders.

Degree: 2004, Universität Dortmund

 Die Doktorarbeit beschreibt die Entwicklung und den Aufbau eines Datennahmesystems für das AMANDA Neutrinoteleskop am geographischen Südpol. Das System basiert auf Flash ADCs (Transient Waveform… (more)

Subjects/Keywords: AMANDA; DAQ; Data Aquisition; Datenakquisition; Flash ADC; Neutrino; Transient Waveform Recorders; TWR; 530

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wagner, W. (2004). Design and realisation of a new AMANDA data acquisition system with transient waveform recorders. (Thesis). Universität Dortmund. Retrieved from http://hdl.handle.net/2003/20247

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wagner, Wolfgang. “Design and realisation of a new AMANDA data acquisition system with transient waveform recorders.” 2004. Thesis, Universität Dortmund. Accessed August 14, 2020. http://hdl.handle.net/2003/20247.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wagner, Wolfgang. “Design and realisation of a new AMANDA data acquisition system with transient waveform recorders.” 2004. Web. 14 Aug 2020.

Vancouver:

Wagner W. Design and realisation of a new AMANDA data acquisition system with transient waveform recorders. [Internet] [Thesis]. Universität Dortmund; 2004. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/2003/20247.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wagner W. Design and realisation of a new AMANDA data acquisition system with transient waveform recorders. [Thesis]. Universität Dortmund; 2004. Available from: http://hdl.handle.net/2003/20247

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

13. Torfs, Guy. A robust 2.4 GHz time-of-arrival based ranging system with sub-meter accuracy: feasibility study and realization of low power CMOS receiver.

Degree: 2012, Ghent University

 Draadloze sensornetwerken worden meer en meer aangewend om verschillende soorten informatie te verzamelen. De locatie, waar deze informatie verzameld is, is een belangerijke eigenschap en… (more)

Subjects/Keywords: Technology and Engineering; Antenna; Receiver; Flash ADC; RF; Ranging; Positioning; CMOS; LNA; Mixer; Sourcefollower; Filter

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APA (6th Edition):

Torfs, G. (2012). A robust 2.4 GHz time-of-arrival based ranging system with sub-meter accuracy: feasibility study and realization of low power CMOS receiver. (Thesis). Ghent University. Retrieved from http://hdl.handle.net/1854/LU-2955961

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Torfs, Guy. “A robust 2.4 GHz time-of-arrival based ranging system with sub-meter accuracy: feasibility study and realization of low power CMOS receiver.” 2012. Thesis, Ghent University. Accessed August 14, 2020. http://hdl.handle.net/1854/LU-2955961.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Torfs, Guy. “A robust 2.4 GHz time-of-arrival based ranging system with sub-meter accuracy: feasibility study and realization of low power CMOS receiver.” 2012. Web. 14 Aug 2020.

Vancouver:

Torfs G. A robust 2.4 GHz time-of-arrival based ranging system with sub-meter accuracy: feasibility study and realization of low power CMOS receiver. [Internet] [Thesis]. Ghent University; 2012. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/1854/LU-2955961.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Torfs G. A robust 2.4 GHz time-of-arrival based ranging system with sub-meter accuracy: feasibility study and realization of low power CMOS receiver. [Thesis]. Ghent University; 2012. Available from: http://hdl.handle.net/1854/LU-2955961

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of British Columbia

14. Sheikhaei, Samad. A 43mW single-channel 4GS/s 4-bit flash ADC IN 0.18um CMOS .

Degree: 2008, University of British Columbia

 The continued speed improvement of serial links and appearance of new communication technologies, such as ultra wideband (UWB), have introduced increasing demands on the speed… (more)

Subjects/Keywords: Analog-to-digital converter; Flash ADC

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APA (6th Edition):

Sheikhaei, S. (2008). A 43mW single-channel 4GS/s 4-bit flash ADC IN 0.18um CMOS . (Thesis). University of British Columbia. Retrieved from http://hdl.handle.net/2429/2746

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sheikhaei, Samad. “A 43mW single-channel 4GS/s 4-bit flash ADC IN 0.18um CMOS .” 2008. Thesis, University of British Columbia. Accessed August 14, 2020. http://hdl.handle.net/2429/2746.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sheikhaei, Samad. “A 43mW single-channel 4GS/s 4-bit flash ADC IN 0.18um CMOS .” 2008. Web. 14 Aug 2020.

Vancouver:

Sheikhaei S. A 43mW single-channel 4GS/s 4-bit flash ADC IN 0.18um CMOS . [Internet] [Thesis]. University of British Columbia; 2008. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/2429/2746.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sheikhaei S. A 43mW single-channel 4GS/s 4-bit flash ADC IN 0.18um CMOS . [Thesis]. University of British Columbia; 2008. Available from: http://hdl.handle.net/2429/2746

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

15. Harikumar, Prakash. A Study on the Design of Reconfigurable ADCs.

Degree: The Institute of Technology, 2011, Linköping UniversityLinköping University

  Analog-to-Digital Converters (ADCs) can be classified into two categories namely Nyquist-rate ADCs and OversampledADCs. Nyquist-rate ADCs can process very high bandwidths while Oversampling ADCs… (more)

Subjects/Keywords: ADC; Sigma-Delta; Delta-Sigma; MASH; Pipelined; Reconfigurable; MDAC; Loop filter; Switched-Capacitor; SNDR; Time-interleaved; Flash; Electrical engineering; Elektroteknik

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APA (6th Edition):

Harikumar, P. (2011). A Study on the Design of Reconfigurable ADCs. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-67867

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Harikumar, Prakash. “A Study on the Design of Reconfigurable ADCs.” 2011. Thesis, Linköping UniversityLinköping University. Accessed August 14, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-67867.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Harikumar, Prakash. “A Study on the Design of Reconfigurable ADCs.” 2011. Web. 14 Aug 2020.

Vancouver:

Harikumar P. A Study on the Design of Reconfigurable ADCs. [Internet] [Thesis]. Linköping UniversityLinköping University; 2011. [cited 2020 Aug 14]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-67867.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Harikumar P. A Study on the Design of Reconfigurable ADCs. [Thesis]. Linköping UniversityLinköping University; 2011. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-67867

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

16. Stefanou, Nikolaos. A 1Gsample/s 6-bit flash A/D converter with a combined chopping and averaging technique for reduced distortion in 0.18(mu)m CMOS.

Degree: MS, Vocational Education, 2005, Texas A&M University

 Hard disk drive applications require a high Spurious Free Dynamic Range (SFDR), 6-bit Analog-to-Digital Converter (ADC) at conversion rates of 1GHz and beyond. This work… (more)

Subjects/Keywords: Analog to Digital Converters; A/D; ADC; Flash; Averaging; Chopping; Dynamic Range; SFDR

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APA (6th Edition):

Stefanou, N. (2005). A 1Gsample/s 6-bit flash A/D converter with a combined chopping and averaging technique for reduced distortion in 0.18(mu)m CMOS. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/2469

Chicago Manual of Style (16th Edition):

Stefanou, Nikolaos. “A 1Gsample/s 6-bit flash A/D converter with a combined chopping and averaging technique for reduced distortion in 0.18(mu)m CMOS.” 2005. Masters Thesis, Texas A&M University. Accessed August 14, 2020. http://hdl.handle.net/1969.1/2469.

MLA Handbook (7th Edition):

Stefanou, Nikolaos. “A 1Gsample/s 6-bit flash A/D converter with a combined chopping and averaging technique for reduced distortion in 0.18(mu)m CMOS.” 2005. Web. 14 Aug 2020.

Vancouver:

Stefanou N. A 1Gsample/s 6-bit flash A/D converter with a combined chopping and averaging technique for reduced distortion in 0.18(mu)m CMOS. [Internet] [Masters thesis]. Texas A&M University; 2005. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/1969.1/2469.

Council of Science Editors:

Stefanou N. A 1Gsample/s 6-bit flash A/D converter with a combined chopping and averaging technique for reduced distortion in 0.18(mu)m CMOS. [Masters Thesis]. Texas A&M University; 2005. Available from: http://hdl.handle.net/1969.1/2469

17. LI TI. Design and implementation of a high speed and low power flash ADC with fully dynamic comparators.

Degree: 2010, National University of Singapore

Subjects/Keywords: low power; flash ADC; fully dynamic comparators; background calibration; high speed; offset voltage

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APA (6th Edition):

TI, L. (2010). Design and implementation of a high speed and low power flash ADC with fully dynamic comparators. (Thesis). National University of Singapore. Retrieved from http://scholarbank.nus.edu.sg/handle/10635/23792

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

TI, LI. “Design and implementation of a high speed and low power flash ADC with fully dynamic comparators.” 2010. Thesis, National University of Singapore. Accessed August 14, 2020. http://scholarbank.nus.edu.sg/handle/10635/23792.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

TI, LI. “Design and implementation of a high speed and low power flash ADC with fully dynamic comparators.” 2010. Web. 14 Aug 2020.

Vancouver:

TI L. Design and implementation of a high speed and low power flash ADC with fully dynamic comparators. [Internet] [Thesis]. National University of Singapore; 2010. [cited 2020 Aug 14]. Available from: http://scholarbank.nus.edu.sg/handle/10635/23792.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

TI L. Design and implementation of a high speed and low power flash ADC with fully dynamic comparators. [Thesis]. National University of Singapore; 2010. Available from: http://scholarbank.nus.edu.sg/handle/10635/23792

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

18. Payami, Sima. Design of an Operational Amplifier for High Performance Pipelined ADCs in 65nm CMOS.

Degree: Electronic Devices, 2012, Linköping University

  In this work, a fully differential Operational Amplifier (OpAmp) with high Gain-Bandwidth (GBW), high linearity and Signal-to-Noise ratio (SNR) has been designed in 65nm… (more)

Subjects/Keywords: Pipelined; ADC; OpAmp; Gain Boosting; CMFB; 2.5bps architecture; Flash; MDAC

…5 1.1.1 Flash ADC… …14 2.2 Flash Sub-ADC… …5 Figure 1-2: (a) 2-bit Flash ADC (b) Thermo-Code to Digital-Code… …16 Figure 2-6: (a) Sampling Phase in Flash Sub-ADC, (b) Comparing Phase… …in Flash Sub-ADC................................. 17 Figure 2-7: Thermometer to Binary… 

Page 1 Page 2 Page 3 Page 4 Page 5 Page 6 Page 7 Sample image

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APA (6th Edition):

Payami, S. (2012). Design of an Operational Amplifier for High Performance Pipelined ADCs in 65nm CMOS. (Thesis). Linköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-78930

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Payami, Sima. “Design of an Operational Amplifier for High Performance Pipelined ADCs in 65nm CMOS.” 2012. Thesis, Linköping University. Accessed August 14, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-78930.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Payami, Sima. “Design of an Operational Amplifier for High Performance Pipelined ADCs in 65nm CMOS.” 2012. Web. 14 Aug 2020.

Vancouver:

Payami S. Design of an Operational Amplifier for High Performance Pipelined ADCs in 65nm CMOS. [Internet] [Thesis]. Linköping University; 2012. [cited 2020 Aug 14]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-78930.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Payami S. Design of an Operational Amplifier for High Performance Pipelined ADCs in 65nm CMOS. [Thesis]. Linköping University; 2012. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-78930

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

19. Carter, Nathan R. A 12-b 50Msample/s Pipeline Analog to Digital Converter.

Degree: MS, 2000, Worcester Polytechnic Institute

 This thesis focuses on the performace of pipeline converters and their integration on mixed signal processes. With this in mind, a 12-b 50MHz pipeline ADC(more)

Subjects/Keywords: digital; converter; analog; flash; ADC; folding; Analog-to-digital converters

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APA (6th Edition):

Carter, N. R. (2000). A 12-b 50Msample/s Pipeline Analog to Digital Converter. (Thesis). Worcester Polytechnic Institute. Retrieved from etd-0505100-104750 ; https://digitalcommons.wpi.edu/etd-theses/749

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Carter, Nathan R. “A 12-b 50Msample/s Pipeline Analog to Digital Converter.” 2000. Thesis, Worcester Polytechnic Institute. Accessed August 14, 2020. etd-0505100-104750 ; https://digitalcommons.wpi.edu/etd-theses/749.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Carter, Nathan R. “A 12-b 50Msample/s Pipeline Analog to Digital Converter.” 2000. Web. 14 Aug 2020.

Vancouver:

Carter NR. A 12-b 50Msample/s Pipeline Analog to Digital Converter. [Internet] [Thesis]. Worcester Polytechnic Institute; 2000. [cited 2020 Aug 14]. Available from: etd-0505100-104750 ; https://digitalcommons.wpi.edu/etd-theses/749.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Carter NR. A 12-b 50Msample/s Pipeline Analog to Digital Converter. [Thesis]. Worcester Polytechnic Institute; 2000. Available from: etd-0505100-104750 ; https://digitalcommons.wpi.edu/etd-theses/749

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

20. Wagner, Wolfgang. Design and realisation of a new AMANDA data acquisition system with transient waveform recorders.

Degree: 2005, Technische Universität Dortmund

 Die Doktorarbeit beschreibt die Entwicklung und den Aufbau eines Datennahmesystems für das AMANDA Neutrinoteleskop am geographischen Südpol. Das System basiert auf Flash ADCs (Transient Waveform… (more)

Subjects/Keywords: AMANDA; Neutrino; DAQ; Datenakquisition; Data Aquisition; TWR; Transient Waveform Recorders; Flash ADC; 530

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APA (6th Edition):

Wagner, W. (2005). Design and realisation of a new AMANDA data acquisition system with transient waveform recorders. (Doctoral Dissertation). Technische Universität Dortmund. Retrieved from http://dx.doi.org/10.17877/DE290R-5299

Chicago Manual of Style (16th Edition):

Wagner, Wolfgang. “Design and realisation of a new AMANDA data acquisition system with transient waveform recorders.” 2005. Doctoral Dissertation, Technische Universität Dortmund. Accessed August 14, 2020. http://dx.doi.org/10.17877/DE290R-5299.

MLA Handbook (7th Edition):

Wagner, Wolfgang. “Design and realisation of a new AMANDA data acquisition system with transient waveform recorders.” 2005. Web. 14 Aug 2020.

Vancouver:

Wagner W. Design and realisation of a new AMANDA data acquisition system with transient waveform recorders. [Internet] [Doctoral dissertation]. Technische Universität Dortmund; 2005. [cited 2020 Aug 14]. Available from: http://dx.doi.org/10.17877/DE290R-5299.

Council of Science Editors:

Wagner W. Design and realisation of a new AMANDA data acquisition system with transient waveform recorders. [Doctoral Dissertation]. Technische Universität Dortmund; 2005. Available from: http://dx.doi.org/10.17877/DE290R-5299

21. GU JUN. High-speed flash adc design.

Degree: 2007, National University of Singapore

Subjects/Keywords: High-speed comparator design; high-speed ADC design; flash ADC design; bipolar IC design; SiGe HBT technology.

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APA (6th Edition):

JUN, G. (2007). High-speed flash adc design. (Thesis). National University of Singapore. Retrieved from http://scholarbank.nus.edu.sg/handle/10635/15689

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

JUN, GU. “High-speed flash adc design.” 2007. Thesis, National University of Singapore. Accessed August 14, 2020. http://scholarbank.nus.edu.sg/handle/10635/15689.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

JUN, GU. “High-speed flash adc design.” 2007. Web. 14 Aug 2020.

Vancouver:

JUN G. High-speed flash adc design. [Internet] [Thesis]. National University of Singapore; 2007. [cited 2020 Aug 14]. Available from: http://scholarbank.nus.edu.sg/handle/10635/15689.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

JUN G. High-speed flash adc design. [Thesis]. National University of Singapore; 2007. Available from: http://scholarbank.nus.edu.sg/handle/10635/15689

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

22. Nasrollahpour, Mehdi. Time-based, Low-power, Low-offset 5-bit 1 GS/s Flash ADC Design in 65nm CMOS Technology.

Degree: MS, Electrical Engineering, 2017, San Jose State University

  Low-power, medium resolution, high-speed analog-to-digital converters (ADCs) have always been important block which have abundant applications such as digital signal processors (DSP), imaging sensors,… (more)

Subjects/Keywords: Flash ADC; High-speed; Low-offset; Low-power; Offset cancellation; Time-based ADC

…Frequency Converter Based ADC 8 CHAPTER THREE. Flash ADC Background… …13 Encoder .. 15 Errors in FLASH ADC .. 16… …10 Fig. 3.1 Conventional Flash ADC architecture… …24 Fig. 4.5 Proposed comparator used in the Flash ADC… …32 Fig. 4.13 Overall proposed Flash ADC block diagram… 

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APA (6th Edition):

Nasrollahpour, M. (2017). Time-based, Low-power, Low-offset 5-bit 1 GS/s Flash ADC Design in 65nm CMOS Technology. (Masters Thesis). San Jose State University. Retrieved from https://doi.org/10.31979/etd.6wsv-p773 ; https://scholarworks.sjsu.edu/etd_theses/4853

Chicago Manual of Style (16th Edition):

Nasrollahpour, Mehdi. “Time-based, Low-power, Low-offset 5-bit 1 GS/s Flash ADC Design in 65nm CMOS Technology.” 2017. Masters Thesis, San Jose State University. Accessed August 14, 2020. https://doi.org/10.31979/etd.6wsv-p773 ; https://scholarworks.sjsu.edu/etd_theses/4853.

MLA Handbook (7th Edition):

Nasrollahpour, Mehdi. “Time-based, Low-power, Low-offset 5-bit 1 GS/s Flash ADC Design in 65nm CMOS Technology.” 2017. Web. 14 Aug 2020.

Vancouver:

Nasrollahpour M. Time-based, Low-power, Low-offset 5-bit 1 GS/s Flash ADC Design in 65nm CMOS Technology. [Internet] [Masters thesis]. San Jose State University; 2017. [cited 2020 Aug 14]. Available from: https://doi.org/10.31979/etd.6wsv-p773 ; https://scholarworks.sjsu.edu/etd_theses/4853.

Council of Science Editors:

Nasrollahpour M. Time-based, Low-power, Low-offset 5-bit 1 GS/s Flash ADC Design in 65nm CMOS Technology. [Masters Thesis]. San Jose State University; 2017. Available from: https://doi.org/10.31979/etd.6wsv-p773 ; https://scholarworks.sjsu.edu/etd_theses/4853

23. Alashmouny, Khaled M. Analog Front-End Circuits for Massive Parallel 3-D Neural Microsystems.

Degree: PhD, Electrical Engineering, 2013, University of Michigan

 Understanding dynamics of the brain has tremendously improved due to the progress in neural recording techniques over the past five decades. The number of simultaneously… (more)

Subjects/Keywords: Analog Front-end; Neural Recording Microsystems; Low-noise Amplifier; SAR ADC; FLASH ADC; Current-mode Circuits; Electrical Engineering; Engineering

…131 Figure 3.36. Architecture of the 6-bit current-mode FLASH ADC… …130 3.8 6-bit Current-Mode FLASH Analog-to-Digital Converter… …162 4.3.4 Asynchronous 6-Bit SAR ADC… …to16), and 16 preamplifiers that are multiplexed into one ADC. Data acquisition… …54 Figure 2.12. 16-channel time-division multiplexer controlled by SOC signal from the ADC… 

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APA (6th Edition):

Alashmouny, K. M. (2013). Analog Front-End Circuits for Massive Parallel 3-D Neural Microsystems. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/98070

Chicago Manual of Style (16th Edition):

Alashmouny, Khaled M. “Analog Front-End Circuits for Massive Parallel 3-D Neural Microsystems.” 2013. Doctoral Dissertation, University of Michigan. Accessed August 14, 2020. http://hdl.handle.net/2027.42/98070.

MLA Handbook (7th Edition):

Alashmouny, Khaled M. “Analog Front-End Circuits for Massive Parallel 3-D Neural Microsystems.” 2013. Web. 14 Aug 2020.

Vancouver:

Alashmouny KM. Analog Front-End Circuits for Massive Parallel 3-D Neural Microsystems. [Internet] [Doctoral dissertation]. University of Michigan; 2013. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/2027.42/98070.

Council of Science Editors:

Alashmouny KM. Analog Front-End Circuits for Massive Parallel 3-D Neural Microsystems. [Doctoral Dissertation]. University of Michigan; 2013. Available from: http://hdl.handle.net/2027.42/98070


Penn State University

24. Yoo, Jincheol. A TIQ Based CMOS Flash A/D Converter for System-on-Chip Applications.

Degree: 2008, Penn State University

 This thesis addresses a Threshold Inverter Quantization (TIQ) based CMOS flash analog-to-digital converter (ADC) for system-on-chip (SoC) applications. The TIQ technique, which uses two cascaded… (more)

Subjects/Keywords: Threshold Inverter Quantization (TIQ); Flash ADC; Analog-to-Digital Converter; System-on-Chip (SoC)

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APA (6th Edition):

Yoo, J. (2008). A TIQ Based CMOS Flash A/D Converter for System-on-Chip Applications. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/6040

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yoo, Jincheol. “A TIQ Based CMOS Flash A/D Converter for System-on-Chip Applications.” 2008. Thesis, Penn State University. Accessed August 14, 2020. https://submit-etda.libraries.psu.edu/catalog/6040.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yoo, Jincheol. “A TIQ Based CMOS Flash A/D Converter for System-on-Chip Applications.” 2008. Web. 14 Aug 2020.

Vancouver:

Yoo J. A TIQ Based CMOS Flash A/D Converter for System-on-Chip Applications. [Internet] [Thesis]. Penn State University; 2008. [cited 2020 Aug 14]. Available from: https://submit-etda.libraries.psu.edu/catalog/6040.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yoo J. A TIQ Based CMOS Flash A/D Converter for System-on-Chip Applications. [Thesis]. Penn State University; 2008. Available from: https://submit-etda.libraries.psu.edu/catalog/6040

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

25. Sundar, Arun. A 3-Bit Current Mode Quantizer for Continuous Time Delta Sigma Analog-to-Digital Converters.

Degree: MS, Electrical Engineering, 2012, Texas A&M University

 The summing amplifier and the quantizer form two of the most critical blocks in a continuous time delta sigma (CT ΔΣ) analog-to-digital converter (ADC). Most… (more)

Subjects/Keywords: Current-mode; Quantizer; Flash; Continuous Time; Delta Sigma; Analog-to-Digital Converter; Summing Amplifier; ADC

…18 Figure 12 Voltage-mode flash ADC… …20 Figure 13 Current-mode flash ADC [11]… …currentmode flash ADC is provided. The overall operation of the quantizer is also presented. Results… …chosen for the quantizer. Flash ADC [7] is a common quantizer architecture which… …name „flash‟. There are two types of flash ADCs found in use – the traditional flash ADC… 

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APA (6th Edition):

Sundar, A. (2012). A 3-Bit Current Mode Quantizer for Continuous Time Delta Sigma Analog-to-Digital Converters. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10515

Chicago Manual of Style (16th Edition):

Sundar, Arun. “A 3-Bit Current Mode Quantizer for Continuous Time Delta Sigma Analog-to-Digital Converters.” 2012. Masters Thesis, Texas A&M University. Accessed August 14, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10515.

MLA Handbook (7th Edition):

Sundar, Arun. “A 3-Bit Current Mode Quantizer for Continuous Time Delta Sigma Analog-to-Digital Converters.” 2012. Web. 14 Aug 2020.

Vancouver:

Sundar A. A 3-Bit Current Mode Quantizer for Continuous Time Delta Sigma Analog-to-Digital Converters. [Internet] [Masters thesis]. Texas A&M University; 2012. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10515.

Council of Science Editors:

Sundar A. A 3-Bit Current Mode Quantizer for Continuous Time Delta Sigma Analog-to-Digital Converters. [Masters Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10515


Brno University of Technology

26. Zeman, Pavel. Návrh a realizace pěti-úrovňového kvantovacího obvodu: Design and realisation of the five-levels quantizator.

Degree: 2019, Brno University of Technology

 The work deals with design and realisation of the five-levels high-speed quantizer using switched-current technique (SI). The main aim is to use an advantage of… (more)

Subjects/Keywords: Technika spínaných proudů (SI); základní stavební bloky obvodové techniky spínaných proudů; chyby obvodové techniky spínaných proudů; paralelní převodník A/D v technologii CMOS; parametry převodníků A/D; Switched-current technique (SI); basic building blocks of switched-current technique; errors of switched-current technique; high-speed CMOS flash A/D converter; parameters of ADC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zeman, P. (2019). Návrh a realizace pěti-úrovňového kvantovacího obvodu: Design and realisation of the five-levels quantizator. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/17058

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zeman, Pavel. “Návrh a realizace pěti-úrovňového kvantovacího obvodu: Design and realisation of the five-levels quantizator.” 2019. Thesis, Brno University of Technology. Accessed August 14, 2020. http://hdl.handle.net/11012/17058.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zeman, Pavel. “Návrh a realizace pěti-úrovňového kvantovacího obvodu: Design and realisation of the five-levels quantizator.” 2019. Web. 14 Aug 2020.

Vancouver:

Zeman P. Návrh a realizace pěti-úrovňového kvantovacího obvodu: Design and realisation of the five-levels quantizator. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2020 Aug 14]. Available from: http://hdl.handle.net/11012/17058.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zeman P. Návrh a realizace pěti-úrovňového kvantovacího obvodu: Design and realisation of the five-levels quantizator. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/17058

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

27. Baskaran, Balakumaar. High-Speed Hybrid Current mode Sigma-Delta Modulator.

Degree: The Institute of Technology, 2012, Linköping UniversityLinköping University

  The majority of signals, that need to be processed, are analog, which are continuous and can take an infinite number of values at any… (more)

Subjects/Keywords: Current mode Sigma Delta Modulator; Leslie-Singh Architecture; Switched Current Integrator; Folded Cascode Integrator; Current mode Flash ADC; High Speed Latched Comparator; Cascode Current Mirrors

…graphs and verilog a code. The analog blocks like switched current integrator, flash ADC and… …4.5.3 Current mode Flash ADC 72 4.5.4 Simulation Result 73 Conclusion 74 Mismatch… …Frequency domain analysis with spatial spectra 5.7 6 79 Current Mode Flash ADC Mismatch… …6.7.3 Simulation results 91 Conclusion 92 Current mode Flash ADC 94 7.1 Introduction… …flash ADC 96 7.3.1 Simulation Result – Single Ended ADC 98 6.8 7 xv 7.4 Differential… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Baskaran, B. (2012). High-Speed Hybrid Current mode Sigma-Delta Modulator. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-80060

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Baskaran, Balakumaar. “High-Speed Hybrid Current mode Sigma-Delta Modulator.” 2012. Thesis, Linköping UniversityLinköping University. Accessed August 14, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-80060.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Baskaran, Balakumaar. “High-Speed Hybrid Current mode Sigma-Delta Modulator.” 2012. Web. 14 Aug 2020.

Vancouver:

Baskaran B. High-Speed Hybrid Current mode Sigma-Delta Modulator. [Internet] [Thesis]. Linköping UniversityLinköping University; 2012. [cited 2020 Aug 14]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-80060.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Baskaran B. High-Speed Hybrid Current mode Sigma-Delta Modulator. [Thesis]. Linköping UniversityLinköping University; 2012. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-80060

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

.