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You searched for subject:(error tolerance). Showing records 1 – 30 of 79 total matches.

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University of Southern California

1. Zheng, Yi-Cong. Towards efficient fault-tolerant quantum computation.

Degree: PhD, Electrical Engineering, 2015, University of Southern California

 The threshold theorem indicates that if errors are all local and their rates are below a certain threshold, it is possible to implement large scale… (more)

Subjects/Keywords: quantum computer; quantum error correction; fault-tolerance

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zheng, Y. (2015). Towards efficient fault-tolerant quantum computation. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/627948/rec/7524

Chicago Manual of Style (16th Edition):

Zheng, Yi-Cong. “Towards efficient fault-tolerant quantum computation.” 2015. Doctoral Dissertation, University of Southern California. Accessed December 13, 2019. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/627948/rec/7524.

MLA Handbook (7th Edition):

Zheng, Yi-Cong. “Towards efficient fault-tolerant quantum computation.” 2015. Web. 13 Dec 2019.

Vancouver:

Zheng Y. Towards efficient fault-tolerant quantum computation. [Internet] [Doctoral dissertation]. University of Southern California; 2015. [cited 2019 Dec 13]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/627948/rec/7524.

Council of Science Editors:

Zheng Y. Towards efficient fault-tolerant quantum computation. [Doctoral Dissertation]. University of Southern California; 2015. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/627948/rec/7524


The Ohio State University

2. Liu, Jiaqi. Handling Soft and Hard Errors for Scientific Applications.

Degree: PhD, Computer Science and Engineering, 2017, The Ohio State University

 Due to the rapid decrease in Mean Time Between Failure (MTBF) in High Performance Computing, fault tolerance emerged as a critical topic to improve overall… (more)

Subjects/Keywords: Computer Engineering; Computer Science; hard error; soft error; scientific application; fault tolerance; resilience

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liu, J. (2017). Handling Soft and Hard Errors for Scientific Applications. (Doctoral Dissertation). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1483632126075067

Chicago Manual of Style (16th Edition):

Liu, Jiaqi. “Handling Soft and Hard Errors for Scientific Applications.” 2017. Doctoral Dissertation, The Ohio State University. Accessed December 13, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=osu1483632126075067.

MLA Handbook (7th Edition):

Liu, Jiaqi. “Handling Soft and Hard Errors for Scientific Applications.” 2017. Web. 13 Dec 2019.

Vancouver:

Liu J. Handling Soft and Hard Errors for Scientific Applications. [Internet] [Doctoral dissertation]. The Ohio State University; 2017. [cited 2019 Dec 13]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1483632126075067.

Council of Science Editors:

Liu J. Handling Soft and Hard Errors for Scientific Applications. [Doctoral Dissertation]. The Ohio State University; 2017. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1483632126075067


NSYSU

3. Chen, Chao-Ju. A No-Reference Error-Tolerability Test Methodology and Its Hardware Implementation for Image Processing Circuits.

Degree: Master, Electrical Engineering, 2018, NSYSU

 With the ever-changing nature of techmology, internet of things (IoT) has become one of key applications of electronic systems. For IoT applications, such as object… (more)

Subjects/Keywords: False-edge; error-tolerance; on-line error-tolerability testing; no-reference; image quality assessment

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, C. (2018). A No-Reference Error-Tolerability Test Methodology and Its Hardware Implementation for Image Processing Circuits. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731118-105341

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Chao-Ju. “A No-Reference Error-Tolerability Test Methodology and Its Hardware Implementation for Image Processing Circuits.” 2018. Thesis, NSYSU. Accessed December 13, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731118-105341.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Chao-Ju. “A No-Reference Error-Tolerability Test Methodology and Its Hardware Implementation for Image Processing Circuits.” 2018. Web. 13 Dec 2019.

Vancouver:

Chen C. A No-Reference Error-Tolerability Test Methodology and Its Hardware Implementation for Image Processing Circuits. [Internet] [Thesis]. NSYSU; 2018. [cited 2019 Dec 13]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731118-105341.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen C. A No-Reference Error-Tolerability Test Methodology and Its Hardware Implementation for Image Processing Circuits. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731118-105341

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

4. Zea, Nicolas. Optimal power/performance pipelining for error resilient processors.

Degree: MS, 1200, 2010, University of Illinois – Urbana-Champaign

 Timing speculation has been proposed as a technique for maximizing energy efficiency of processors with minimal loss in performance. A typical implementation of timing speculation… (more)

Subjects/Keywords: microarchitecture; error recovery; error resiliency; computer architecture; low power design; fault tolerance; pipelining; analytical model

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zea, N. (2010). Optimal power/performance pipelining for error resilient processors. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/16791

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zea, Nicolas. “Optimal power/performance pipelining for error resilient processors.” 2010. Thesis, University of Illinois – Urbana-Champaign. Accessed December 13, 2019. http://hdl.handle.net/2142/16791.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zea, Nicolas. “Optimal power/performance pipelining for error resilient processors.” 2010. Web. 13 Dec 2019.

Vancouver:

Zea N. Optimal power/performance pipelining for error resilient processors. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2010. [cited 2019 Dec 13]. Available from: http://hdl.handle.net/2142/16791.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zea N. Optimal power/performance pipelining for error resilient processors. [Thesis]. University of Illinois – Urbana-Champaign; 2010. Available from: http://hdl.handle.net/2142/16791

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

5. Singhal, Rohit. Data integrity for on-chip interconnects.

Degree: 2007, Texas A&M University

 With shrinking feature size and growing integration density in the Deep Sub- Micron (DSM) technologies, the global buses are fast becoming the "weakest-links" in VLSI… (more)

Subjects/Keywords: VLSI; Error Tolerance; Low Power

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Singhal, R. (2007). Data integrity for on-chip interconnects. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/5929

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Singhal, Rohit. “Data integrity for on-chip interconnects.” 2007. Thesis, Texas A&M University. Accessed December 13, 2019. http://hdl.handle.net/1969.1/5929.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Singhal, Rohit. “Data integrity for on-chip interconnects.” 2007. Web. 13 Dec 2019.

Vancouver:

Singhal R. Data integrity for on-chip interconnects. [Internet] [Thesis]. Texas A&M University; 2007. [cited 2019 Dec 13]. Available from: http://hdl.handle.net/1969.1/5929.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Singhal R. Data integrity for on-chip interconnects. [Thesis]. Texas A&M University; 2007. Available from: http://hdl.handle.net/1969.1/5929

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

6. Wu, Mei-Jung. An Efficient Method to Assess Audio Quality and Its Hardware Implementation.

Degree: Master, Electrical Engineering, 2017, NSYSU

 To facilitate storage and transmission, lossy compression is usually used for audio signals despite the possible quality degradation. On the other hand, scaling down of… (more)

Subjects/Keywords: audio processing circuits; audio acceptability evaluation; error-tolerance; PEAQ; erroneous audio

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu, M. (2017). An Efficient Method to Assess Audio Quality and Its Hardware Implementation. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801117-101956

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Mei-Jung. “An Efficient Method to Assess Audio Quality and Its Hardware Implementation.” 2017. Thesis, NSYSU. Accessed December 13, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801117-101956.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Mei-Jung. “An Efficient Method to Assess Audio Quality and Its Hardware Implementation.” 2017. Web. 13 Dec 2019.

Vancouver:

Wu M. An Efficient Method to Assess Audio Quality and Its Hardware Implementation. [Internet] [Thesis]. NSYSU; 2017. [cited 2019 Dec 13]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801117-101956.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu M. An Efficient Method to Assess Audio Quality and Its Hardware Implementation. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801117-101956

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

7. Cheng, Tai-ang. Error-Tolerability Test and Enhancement Methods for Images in Face Detection Applications.

Degree: Master, Electrical Engineering, 2017, NSYSU

 Face detection is mainly used to determinate wherther the face in the image can be detected or not. Accordingly the identity of the person can… (more)

Subjects/Keywords: error-tolerance; face detection; image repair; image processing; image qulity evaluation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cheng, T. (2017). Error-Tolerability Test and Enhancement Methods for Images in Face Detection Applications. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-180159

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Cheng, Tai-ang. “Error-Tolerability Test and Enhancement Methods for Images in Face Detection Applications.” 2017. Thesis, NSYSU. Accessed December 13, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-180159.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Cheng, Tai-ang. “Error-Tolerability Test and Enhancement Methods for Images in Face Detection Applications.” 2017. Web. 13 Dec 2019.

Vancouver:

Cheng T. Error-Tolerability Test and Enhancement Methods for Images in Face Detection Applications. [Internet] [Thesis]. NSYSU; 2017. [cited 2019 Dec 13]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-180159.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Cheng T. Error-Tolerability Test and Enhancement Methods for Images in Face Detection Applications. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-180159

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

8. Kao, Tien-Tsai. Error Tolerability Analysis and Error-Tolerant Design Investigation of A JPEG2000 Image Encoder.

Degree: Master, Electrical Engineering, 2013, NSYSU

 JPEG2000 is a new image compression standard formulated by Joint Photographic Experts Group in 2000. There are two modes for image compression in JPEG2000 standard:… (more)

Subjects/Keywords: quantization; acceptability of faults; error tolerance; yield; discrete wavelet transform; JPEG2000

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kao, T. (2013). Error Tolerability Analysis and Error-Tolerant Design Investigation of A JPEG2000 Image Encoder. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0805113-011126

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kao, Tien-Tsai. “Error Tolerability Analysis and Error-Tolerant Design Investigation of A JPEG2000 Image Encoder.” 2013. Thesis, NSYSU. Accessed December 13, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0805113-011126.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kao, Tien-Tsai. “Error Tolerability Analysis and Error-Tolerant Design Investigation of A JPEG2000 Image Encoder.” 2013. Web. 13 Dec 2019.

Vancouver:

Kao T. Error Tolerability Analysis and Error-Tolerant Design Investigation of A JPEG2000 Image Encoder. [Internet] [Thesis]. NSYSU; 2013. [cited 2019 Dec 13]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0805113-011126.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kao T. Error Tolerability Analysis and Error-Tolerant Design Investigation of A JPEG2000 Image Encoder. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0805113-011126

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

9. Kuan-Hsien, Li. Error-Tolerant Analysis and Design of Discrete Wavelet Transform and Quantization in JPEG2000 Codec.

Degree: Master, Electrical Engineering, 2014, NSYSU

 With the advance of integrated circuits, yield and reliability have become one of the critical and popular issues to be addressed. Error-tolerance is a novel… (more)

Subjects/Keywords: JPEG2000; yield; discrete wavelet transform; error-tolerance; quantization; reliability

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kuan-Hsien, L. (2014). Error-Tolerant Analysis and Design of Discrete Wavelet Transform and Quantization in JPEG2000 Codec. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801114-231430

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kuan-Hsien, Li. “Error-Tolerant Analysis and Design of Discrete Wavelet Transform and Quantization in JPEG2000 Codec.” 2014. Thesis, NSYSU. Accessed December 13, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801114-231430.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kuan-Hsien, Li. “Error-Tolerant Analysis and Design of Discrete Wavelet Transform and Quantization in JPEG2000 Codec.” 2014. Web. 13 Dec 2019.

Vancouver:

Kuan-Hsien L. Error-Tolerant Analysis and Design of Discrete Wavelet Transform and Quantization in JPEG2000 Codec. [Internet] [Thesis]. NSYSU; 2014. [cited 2019 Dec 13]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801114-231430.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kuan-Hsien L. Error-Tolerant Analysis and Design of Discrete Wavelet Transform and Quantization in JPEG2000 Codec. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801114-231430

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

10. Chih, Tsung-Liang. Design and Implementation of A Defect and Soft-Error Tolerable Cache.

Degree: Master, Electrical Engineering, 2015, NSYSU

 When the feature size of transistors becomes smaller, chips are more sensitive to process defects and variation, which may result in low yield and reliability.… (more)

Subjects/Keywords: cache; performance degradation tolerance; performance degrading faults; defect; soft-error

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chih, T. (2015). Design and Implementation of A Defect and Soft-Error Tolerable Cache. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-142034

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chih, Tsung-Liang. “Design and Implementation of A Defect and Soft-Error Tolerable Cache.” 2015. Thesis, NSYSU. Accessed December 13, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-142034.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chih, Tsung-Liang. “Design and Implementation of A Defect and Soft-Error Tolerable Cache.” 2015. Web. 13 Dec 2019.

Vancouver:

Chih T. Design and Implementation of A Defect and Soft-Error Tolerable Cache. [Internet] [Thesis]. NSYSU; 2015. [cited 2019 Dec 13]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-142034.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chih T. Design and Implementation of A Defect and Soft-Error Tolerable Cache. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-142034

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

11. Cheng, Kuan-Chih. A Low-Cost Dependability Evaluation and Grading Method and Its Hardware Implementation for Image Processing Circuits.

Degree: Master, Electrical Engineering, 2016, NSYSU

 Image processing circuits are expected to be widely used in IoT (Internet of Things) and automotive electronics. For these applications, dependability evaluation is critical. In… (more)

Subjects/Keywords: dependability; error-tolerance; quality evaluation; FSIMc; image processing circuits

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cheng, K. (2016). A Low-Cost Dependability Evaluation and Grading Method and Its Hardware Implementation for Image Processing Circuits. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627116-230604

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Cheng, Kuan-Chih. “A Low-Cost Dependability Evaluation and Grading Method and Its Hardware Implementation for Image Processing Circuits.” 2016. Thesis, NSYSU. Accessed December 13, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627116-230604.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Cheng, Kuan-Chih. “A Low-Cost Dependability Evaluation and Grading Method and Its Hardware Implementation for Image Processing Circuits.” 2016. Web. 13 Dec 2019.

Vancouver:

Cheng K. A Low-Cost Dependability Evaluation and Grading Method and Its Hardware Implementation for Image Processing Circuits. [Internet] [Thesis]. NSYSU; 2016. [cited 2019 Dec 13]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627116-230604.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Cheng K. A Low-Cost Dependability Evaluation and Grading Method and Its Hardware Implementation for Image Processing Circuits. [Thesis]. NSYSU; 2016. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0627116-230604

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Southern California

12. Shin, Doochul. Techniques for design and synthesis of approximate digital circuits for error-tolerant applications.

Degree: PhD, Computer Engineering, 2011, University of Southern California

 As VLSI technology node scales to nano-scale, dramatic improvements in most attributes of circuits, especially delay and yield, provided by scaling are beginning to decrease.… (more)

Subjects/Keywords: circuit design; error tolerance; logic synthesis; yield improvement

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shin, D. (2011). Techniques for design and synthesis of approximate digital circuits for error-tolerant applications. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/654132/rec/6363

Chicago Manual of Style (16th Edition):

Shin, Doochul. “Techniques for design and synthesis of approximate digital circuits for error-tolerant applications.” 2011. Doctoral Dissertation, University of Southern California. Accessed December 13, 2019. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/654132/rec/6363.

MLA Handbook (7th Edition):

Shin, Doochul. “Techniques for design and synthesis of approximate digital circuits for error-tolerant applications.” 2011. Web. 13 Dec 2019.

Vancouver:

Shin D. Techniques for design and synthesis of approximate digital circuits for error-tolerant applications. [Internet] [Doctoral dissertation]. University of Southern California; 2011. [cited 2019 Dec 13]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/654132/rec/6363.

Council of Science Editors:

Shin D. Techniques for design and synthesis of approximate digital circuits for error-tolerant applications. [Doctoral Dissertation]. University of Southern California; 2011. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/654132/rec/6363

13. Isaza-González, José. Aportaciones a la tolerancia a fallos en microprocesadores bajo efectos de la radiación .

Degree: 2018, University of Alicante

 El funcionamiento correcto de un sistema electrónico, aún bajo perturbaciones y fallos causados por la radiación, ha sido siempre un factor crucial en aplicaciones aeroespaciales,… (more)

Subjects/Keywords: Microprocessor reliability; Fault injection; Soft error; Radiation effects fault tolerance

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Isaza-González, J. (2018). Aportaciones a la tolerancia a fallos en microprocesadores bajo efectos de la radiación . (Thesis). University of Alicante. Retrieved from http://hdl.handle.net/10045/90359

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Isaza-González, José. “Aportaciones a la tolerancia a fallos en microprocesadores bajo efectos de la radiación .” 2018. Thesis, University of Alicante. Accessed December 13, 2019. http://hdl.handle.net/10045/90359.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Isaza-González, José. “Aportaciones a la tolerancia a fallos en microprocesadores bajo efectos de la radiación .” 2018. Web. 13 Dec 2019.

Vancouver:

Isaza-González J. Aportaciones a la tolerancia a fallos en microprocesadores bajo efectos de la radiación . [Internet] [Thesis]. University of Alicante; 2018. [cited 2019 Dec 13]. Available from: http://hdl.handle.net/10045/90359.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Isaza-González J. Aportaciones a la tolerancia a fallos en microprocesadores bajo efectos de la radiación . [Thesis]. University of Alicante; 2018. Available from: http://hdl.handle.net/10045/90359

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

14. Chen, Yu-Chun. Design and Implementation of A High-Performance Sorting-Free Two-Dimensional Median Filter.

Degree: Master, Electrical Engineering, 2018, NSYSU

 As the transistor feature size keeps scaling down, more and more transistors are integrated to a single chip. These factors increase the difficulty of the… (more)

Subjects/Keywords: sorting-free; error-tolerance; median filter; bit-level; image processing circuits

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, Y. (2018). Design and Implementation of A High-Performance Sorting-Free Two-Dimensional Median Filter. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625118-154854

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chen, Yu-Chun. “Design and Implementation of A High-Performance Sorting-Free Two-Dimensional Median Filter.” 2018. Thesis, NSYSU. Accessed December 13, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625118-154854.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chen, Yu-Chun. “Design and Implementation of A High-Performance Sorting-Free Two-Dimensional Median Filter.” 2018. Web. 13 Dec 2019.

Vancouver:

Chen Y. Design and Implementation of A High-Performance Sorting-Free Two-Dimensional Median Filter. [Internet] [Thesis]. NSYSU; 2018. [cited 2019 Dec 13]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625118-154854.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chen Y. Design and Implementation of A High-Performance Sorting-Free Two-Dimensional Median Filter. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0625118-154854

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Waterloo

15. Jochym-O'Connor, Tomas Raphael. Novel Methods in Quantum Error Correction.

Degree: 2016, University of Waterloo

 Quantum error correction is the backbone of fault-tolerant quantum computation, a necessary requirement for any large scale quantum computer. The fault-tolerance threshold theorem has long… (more)

Subjects/Keywords: Quantum computing; Quantum error correction; Quantum fault-tolerance

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jochym-O'Connor, T. R. (2016). Novel Methods in Quantum Error Correction. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/10676

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jochym-O'Connor, Tomas Raphael. “Novel Methods in Quantum Error Correction.” 2016. Thesis, University of Waterloo. Accessed December 13, 2019. http://hdl.handle.net/10012/10676.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jochym-O'Connor, Tomas Raphael. “Novel Methods in Quantum Error Correction.” 2016. Web. 13 Dec 2019.

Vancouver:

Jochym-O'Connor TR. Novel Methods in Quantum Error Correction. [Internet] [Thesis]. University of Waterloo; 2016. [cited 2019 Dec 13]. Available from: http://hdl.handle.net/10012/10676.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jochym-O'Connor TR. Novel Methods in Quantum Error Correction. [Thesis]. University of Waterloo; 2016. Available from: http://hdl.handle.net/10012/10676

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of New South Wales

16. Baldwin, Peter. A multimethod examination of vulnerability in hoarding.

Degree: Psychology, 2016, University of New South Wales

 A growing body of hoarding research suggests that specific psychological and physiological processes make an individual vulnerable to hoarding difficulties. Transdiagnostic vulnerabilities, such as anxiety… (more)

Subjects/Keywords: Anxiety Sensitivity; Hoarding; Intolerance of Uncertainty; Distress Tolerance; Error Related Negativity

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Baldwin, P. (2016). A multimethod examination of vulnerability in hoarding. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/56760 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:41376/SOURCE02?view=true

Chicago Manual of Style (16th Edition):

Baldwin, Peter. “A multimethod examination of vulnerability in hoarding.” 2016. Doctoral Dissertation, University of New South Wales. Accessed December 13, 2019. http://handle.unsw.edu.au/1959.4/56760 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:41376/SOURCE02?view=true.

MLA Handbook (7th Edition):

Baldwin, Peter. “A multimethod examination of vulnerability in hoarding.” 2016. Web. 13 Dec 2019.

Vancouver:

Baldwin P. A multimethod examination of vulnerability in hoarding. [Internet] [Doctoral dissertation]. University of New South Wales; 2016. [cited 2019 Dec 13]. Available from: http://handle.unsw.edu.au/1959.4/56760 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:41376/SOURCE02?view=true.

Council of Science Editors:

Baldwin P. A multimethod examination of vulnerability in hoarding. [Doctoral Dissertation]. University of New South Wales; 2016. Available from: http://handle.unsw.edu.au/1959.4/56760 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:41376/SOURCE02?view=true


University of Southern California

17. Pan, Zhaoliang. Error-rate and significance based error-rate (SBER) estimation via built-in self-test in support of error-tolerance.

Degree: PhD, Electrical Engineering, 2008, University of Southern California

 As CMOS scaling continues, feature size approaches molecular dimensions and the number of devices per chip reaches astronomical values. It becomes more and more difficult… (more)

Subjects/Keywords: error-tolerance; error-rate; error-significance; significance-based error-rate; estimation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pan, Z. (2008). Error-rate and significance based error-rate (SBER) estimation via built-in self-test in support of error-tolerance. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/117654/rec/2419

Chicago Manual of Style (16th Edition):

Pan, Zhaoliang. “Error-rate and significance based error-rate (SBER) estimation via built-in self-test in support of error-tolerance.” 2008. Doctoral Dissertation, University of Southern California. Accessed December 13, 2019. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/117654/rec/2419.

MLA Handbook (7th Edition):

Pan, Zhaoliang. “Error-rate and significance based error-rate (SBER) estimation via built-in self-test in support of error-tolerance.” 2008. Web. 13 Dec 2019.

Vancouver:

Pan Z. Error-rate and significance based error-rate (SBER) estimation via built-in self-test in support of error-tolerance. [Internet] [Doctoral dissertation]. University of Southern California; 2008. [cited 2019 Dec 13]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/117654/rec/2419.

Council of Science Editors:

Pan Z. Error-rate and significance based error-rate (SBER) estimation via built-in self-test in support of error-tolerance. [Doctoral Dissertation]. University of Southern California; 2008. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/117654/rec/2419


University of Southern California

18. Shahidi, Shideh M. Error-rate testing to improve yield for error tolerant applications.

Degree: PhD, Electrical Engineering (Computer Networks), 2008, University of Southern California

 VLSI scaling has entered an era where achieving desired yields is becoming increasingly challenging. The concept of error tolerance has been previously proposed with the… (more)

Subjects/Keywords: VLSI testing; error tolerance; test generation; error rate

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shahidi, S. M. (2008). Error-rate testing to improve yield for error tolerant applications. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/143342/rec/2420

Chicago Manual of Style (16th Edition):

Shahidi, Shideh M. “Error-rate testing to improve yield for error tolerant applications.” 2008. Doctoral Dissertation, University of Southern California. Accessed December 13, 2019. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/143342/rec/2420.

MLA Handbook (7th Edition):

Shahidi, Shideh M. “Error-rate testing to improve yield for error tolerant applications.” 2008. Web. 13 Dec 2019.

Vancouver:

Shahidi SM. Error-rate testing to improve yield for error tolerant applications. [Internet] [Doctoral dissertation]. University of Southern California; 2008. [cited 2019 Dec 13]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/143342/rec/2420.

Council of Science Editors:

Shahidi SM. Error-rate testing to improve yield for error tolerant applications. [Doctoral Dissertation]. University of Southern California; 2008. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/143342/rec/2420


NSYSU

19. Chan, Shang-En. An Efficient No-Reference Error-Tolerability Test Method for Videos.

Degree: Master, Electrical Engineering, 2017, NSYSU

 Since the IoT (Internet of Things) and home security is more and more common as technology progresses, the security that can be provided by surveillance… (more)

Subjects/Keywords: video processing circuits; video quality evaluation; no-reference quality assessment; erroneous video; error-tolerance

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chan, S. (2017). An Efficient No-Reference Error-Tolerability Test Method for Videos. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-180509

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chan, Shang-En. “An Efficient No-Reference Error-Tolerability Test Method for Videos.” 2017. Thesis, NSYSU. Accessed December 13, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-180509.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chan, Shang-En. “An Efficient No-Reference Error-Tolerability Test Method for Videos.” 2017. Web. 13 Dec 2019.

Vancouver:

Chan S. An Efficient No-Reference Error-Tolerability Test Method for Videos. [Internet] [Thesis]. NSYSU; 2017. [cited 2019 Dec 13]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-180509.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chan S. An Efficient No-Reference Error-Tolerability Test Method for Videos. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0811117-180509

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

20. KU, CHIA-CHI. A Yield and Reliability Improvement Methodology and Its Hardware Design for Image Processing Circuits Applications.

Degree: Master, Electrical Engineering, 2013, NSYSU

 With the shrinking of the feature size of transistors, chips become more sensible to manufacturing defects and/or external noises, which may cause low manufacturing yield.… (more)

Subjects/Keywords: yield improvement; VLSI testing; error-tolerance; built-in self-test; image enhancement

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

KU, C. (2013). A Yield and Reliability Improvement Methodology and Its Hardware Design for Image Processing Circuits Applications. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-181850

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

KU, CHIA-CHI. “A Yield and Reliability Improvement Methodology and Its Hardware Design for Image Processing Circuits Applications.” 2013. Thesis, NSYSU. Accessed December 13, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-181850.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

KU, CHIA-CHI. “A Yield and Reliability Improvement Methodology and Its Hardware Design for Image Processing Circuits Applications.” 2013. Web. 13 Dec 2019.

Vancouver:

KU C. A Yield and Reliability Improvement Methodology and Its Hardware Design for Image Processing Circuits Applications. [Internet] [Thesis]. NSYSU; 2013. [cited 2019 Dec 13]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-181850.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

KU C. A Yield and Reliability Improvement Methodology and Its Hardware Design for Image Processing Circuits Applications. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726113-181850

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Southern California

21. Chong, In Suk. Error tolerant multimedia compression system.

Degree: PhD, Electrical Engineering, 2009, University of Southern California

 All existing digital system design approaches strive to provide error-free values at system outputs, which is achieved by using testing techniques, as well as defect… (more)

Subjects/Keywords: error tolerance; high yield discrete cosine transform; low power motion estimation; multimedia compression

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chong, I. S. (2009). Error tolerant multimedia compression system. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/599334/rec/2418

Chicago Manual of Style (16th Edition):

Chong, In Suk. “Error tolerant multimedia compression system.” 2009. Doctoral Dissertation, University of Southern California. Accessed December 13, 2019. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/599334/rec/2418.

MLA Handbook (7th Edition):

Chong, In Suk. “Error tolerant multimedia compression system.” 2009. Web. 13 Dec 2019.

Vancouver:

Chong IS. Error tolerant multimedia compression system. [Internet] [Doctoral dissertation]. University of Southern California; 2009. [cited 2019 Dec 13]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/599334/rec/2418.

Council of Science Editors:

Chong IS. Error tolerant multimedia compression system. [Doctoral Dissertation]. University of Southern California; 2009. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/599334/rec/2418


Universidade do Rio Grande do Sul

22. Santos, Fernando Fernandes dos. Reliability evaluation and error mitigation in pedestrian detection algorithms for embedded GPUs.

Degree: 2017, Universidade do Rio Grande do Sul

Pedestrian detection reliability is a fundamental problem for autonomous or aided driving. Methods that use object detection algorithms such as Histogram of Oriented Gradients (HOG)… (more)

Subjects/Keywords: Sistemas embarcados; Fault tolerance; Soft error; Tolerancia : Falhas : Software; Pedestre; Pedestrian detection; Hardening

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Santos, F. F. d. (2017). Reliability evaluation and error mitigation in pedestrian detection algorithms for embedded GPUs. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/159210

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Santos, Fernando Fernandes dos. “Reliability evaluation and error mitigation in pedestrian detection algorithms for embedded GPUs.” 2017. Thesis, Universidade do Rio Grande do Sul. Accessed December 13, 2019. http://hdl.handle.net/10183/159210.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Santos, Fernando Fernandes dos. “Reliability evaluation and error mitigation in pedestrian detection algorithms for embedded GPUs.” 2017. Web. 13 Dec 2019.

Vancouver:

Santos FFd. Reliability evaluation and error mitigation in pedestrian detection algorithms for embedded GPUs. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2017. [cited 2019 Dec 13]. Available from: http://hdl.handle.net/10183/159210.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Santos FFd. Reliability evaluation and error mitigation in pedestrian detection algorithms for embedded GPUs. [Thesis]. Universidade do Rio Grande do Sul; 2017. Available from: http://hdl.handle.net/10183/159210

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

23. Hedefalk, Finn. Robustness of Spatial Databases: Using Network Analysis on GIS Data Models.

Degree: Technology and Built Environment, 2010, University of Gävle

  Demands on the quality and reliability of Volunteered Geographic Information have increased because of its rising popularity. Due to the less controlled data entry,… (more)

Subjects/Keywords: GIS; Database; UML; VGI; Power-law; Small-world; Error and attack tolerance; Network

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hedefalk, F. (2010). Robustness of Spatial Databases: Using Network Analysis on GIS Data Models. (Thesis). University of Gävle. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:hig:diva-6625

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hedefalk, Finn. “Robustness of Spatial Databases: Using Network Analysis on GIS Data Models.” 2010. Thesis, University of Gävle. Accessed December 13, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:hig:diva-6625.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hedefalk, Finn. “Robustness of Spatial Databases: Using Network Analysis on GIS Data Models.” 2010. Web. 13 Dec 2019.

Vancouver:

Hedefalk F. Robustness of Spatial Databases: Using Network Analysis on GIS Data Models. [Internet] [Thesis]. University of Gävle; 2010. [cited 2019 Dec 13]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hig:diva-6625.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hedefalk F. Robustness of Spatial Databases: Using Network Analysis on GIS Data Models. [Thesis]. University of Gävle; 2010. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:hig:diva-6625

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Iowa State University

24. Subramanian, Viswanathan. Timing speculation and adaptive reliable overclocking techniques for aggressive computer systems.

Degree: 2009, Iowa State University

 Computers have changed our lives beyond our own imagination in the past several decades. The continued and progressive advancements in VLSI technology and numerous micro-architectural… (more)

Subjects/Keywords: Fault tolerance; Microprocessors; Overclocking; Reliability; Soft error; Timing speculation; Electrical and Computer Engineering

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APA (6th Edition):

Subramanian, V. (2009). Timing speculation and adaptive reliable overclocking techniques for aggressive computer systems. (Thesis). Iowa State University. Retrieved from https://lib.dr.iastate.edu/etd/10967

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Subramanian, Viswanathan. “Timing speculation and adaptive reliable overclocking techniques for aggressive computer systems.” 2009. Thesis, Iowa State University. Accessed December 13, 2019. https://lib.dr.iastate.edu/etd/10967.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Subramanian, Viswanathan. “Timing speculation and adaptive reliable overclocking techniques for aggressive computer systems.” 2009. Web. 13 Dec 2019.

Vancouver:

Subramanian V. Timing speculation and adaptive reliable overclocking techniques for aggressive computer systems. [Internet] [Thesis]. Iowa State University; 2009. [cited 2019 Dec 13]. Available from: https://lib.dr.iastate.edu/etd/10967.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Subramanian V. Timing speculation and adaptive reliable overclocking techniques for aggressive computer systems. [Thesis]. Iowa State University; 2009. Available from: https://lib.dr.iastate.edu/etd/10967

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

25. Espinosa García, Jaime. New Fault Detection, Mitigation and Injection Strategies for Current and Forthcoming Challenges of HW Embedded Designs .

Degree: 2016, Universitat Politècnica de València

 [EN] Relevance of electronics towards safety of common devices has only been growing, as an ever growing stake of the functionality is assigned to them.… (more)

Subjects/Keywords: Fault tolerance; Fault injection; Error detection; Fault mitigation; Fault recovery; Fugacious faults; FALLES; CODESH

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APA (6th Edition):

Espinosa García, J. (2016). New Fault Detection, Mitigation and Injection Strategies for Current and Forthcoming Challenges of HW Embedded Designs . (Doctoral Dissertation). Universitat Politècnica de València. Retrieved from http://hdl.handle.net/10251/73146

Chicago Manual of Style (16th Edition):

Espinosa García, Jaime. “New Fault Detection, Mitigation and Injection Strategies for Current and Forthcoming Challenges of HW Embedded Designs .” 2016. Doctoral Dissertation, Universitat Politècnica de València. Accessed December 13, 2019. http://hdl.handle.net/10251/73146.

MLA Handbook (7th Edition):

Espinosa García, Jaime. “New Fault Detection, Mitigation and Injection Strategies for Current and Forthcoming Challenges of HW Embedded Designs .” 2016. Web. 13 Dec 2019.

Vancouver:

Espinosa García J. New Fault Detection, Mitigation and Injection Strategies for Current and Forthcoming Challenges of HW Embedded Designs . [Internet] [Doctoral dissertation]. Universitat Politècnica de València; 2016. [cited 2019 Dec 13]. Available from: http://hdl.handle.net/10251/73146.

Council of Science Editors:

Espinosa García J. New Fault Detection, Mitigation and Injection Strategies for Current and Forthcoming Challenges of HW Embedded Designs . [Doctoral Dissertation]. Universitat Politècnica de València; 2016. Available from: http://hdl.handle.net/10251/73146


University of Michigan

26. Newman, Michael. Applications of Locality and Asymmetry to Quantum Fault-Tolerance.

Degree: PhD, Mathematics, 2018, University of Michigan

 Quantum computing sounds like something out of a science-fiction novel. If we can exert control over unimaginably small systems, then we can harness their quantum… (more)

Subjects/Keywords: Quantum Computing; Quantum Error-Correcting Codes; Quantum Fault-Tolerance; Mathematics; Physics; Science

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Newman, M. (2018). Applications of Locality and Asymmetry to Quantum Fault-Tolerance. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/145948

Chicago Manual of Style (16th Edition):

Newman, Michael. “Applications of Locality and Asymmetry to Quantum Fault-Tolerance.” 2018. Doctoral Dissertation, University of Michigan. Accessed December 13, 2019. http://hdl.handle.net/2027.42/145948.

MLA Handbook (7th Edition):

Newman, Michael. “Applications of Locality and Asymmetry to Quantum Fault-Tolerance.” 2018. Web. 13 Dec 2019.

Vancouver:

Newman M. Applications of Locality and Asymmetry to Quantum Fault-Tolerance. [Internet] [Doctoral dissertation]. University of Michigan; 2018. [cited 2019 Dec 13]. Available from: http://hdl.handle.net/2027.42/145948.

Council of Science Editors:

Newman M. Applications of Locality and Asymmetry to Quantum Fault-Tolerance. [Doctoral Dissertation]. University of Michigan; 2018. Available from: http://hdl.handle.net/2027.42/145948


University of Arizona

27. Moussa, Mohamad. Beyond RAID 6  – Efficient Error Correcting Code for Dual-Disk Corruption .

Degree: 2018, University of Arizona

 An error correcting code is a technique of adding extra information to a message such that it can be recovered even when some of its… (more)

Subjects/Keywords: erasure codes; error correcting codes; fault tolerance; RAID 6; reed solomon code; silent data corruption

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Moussa, M. (2018). Beyond RAID 6  – Efficient Error Correcting Code for Dual-Disk Corruption . (Doctoral Dissertation). University of Arizona. Retrieved from http://hdl.handle.net/10150/631302

Chicago Manual of Style (16th Edition):

Moussa, Mohamad. “Beyond RAID 6  – Efficient Error Correcting Code for Dual-Disk Corruption .” 2018. Doctoral Dissertation, University of Arizona. Accessed December 13, 2019. http://hdl.handle.net/10150/631302.

MLA Handbook (7th Edition):

Moussa, Mohamad. “Beyond RAID 6  – Efficient Error Correcting Code for Dual-Disk Corruption .” 2018. Web. 13 Dec 2019.

Vancouver:

Moussa M. Beyond RAID 6  – Efficient Error Correcting Code for Dual-Disk Corruption . [Internet] [Doctoral dissertation]. University of Arizona; 2018. [cited 2019 Dec 13]. Available from: http://hdl.handle.net/10150/631302.

Council of Science Editors:

Moussa M. Beyond RAID 6  – Efficient Error Correcting Code for Dual-Disk Corruption . [Doctoral Dissertation]. University of Arizona; 2018. Available from: http://hdl.handle.net/10150/631302


Université de Sherbrooke

28. Iyer, Pavithran Sridharan. Une analyse critique de la correction d’erreurs quantique pour du bruit réaliste .

Degree: 2018, Université de Sherbrooke

 Contrôler des systèmes quantiques avec une précision arbitraire semble être un défi insurmontable en raison de l'influence de l'environnement se manifestant sous forme d'erreurs dans… (more)

Subjects/Keywords: Quantum error correction; Diamond distance; Coherent errors; Concatenated codes; Fault tolerance; Machine learning; Importance sampling; Surface codes; Quantum channels

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Iyer, P. S. (2018). Une analyse critique de la correction d’erreurs quantique pour du bruit réaliste . (Doctoral Dissertation). Université de Sherbrooke. Retrieved from http://hdl.handle.net/11143/14194

Chicago Manual of Style (16th Edition):

Iyer, Pavithran Sridharan. “Une analyse critique de la correction d’erreurs quantique pour du bruit réaliste .” 2018. Doctoral Dissertation, Université de Sherbrooke. Accessed December 13, 2019. http://hdl.handle.net/11143/14194.

MLA Handbook (7th Edition):

Iyer, Pavithran Sridharan. “Une analyse critique de la correction d’erreurs quantique pour du bruit réaliste .” 2018. Web. 13 Dec 2019.

Vancouver:

Iyer PS. Une analyse critique de la correction d’erreurs quantique pour du bruit réaliste . [Internet] [Doctoral dissertation]. Université de Sherbrooke; 2018. [cited 2019 Dec 13]. Available from: http://hdl.handle.net/11143/14194.

Council of Science Editors:

Iyer PS. Une analyse critique de la correction d’erreurs quantique pour du bruit réaliste . [Doctoral Dissertation]. Université de Sherbrooke; 2018. Available from: http://hdl.handle.net/11143/14194


Universidade do Rio Grande do Sul

29. Seclen, Jorge Lucio Tonfat. Frame-level redundancy scrubbing technique for SRAM-based FPGAs.

Degree: 2015, Universidade do Rio Grande do Sul

Reliability is an important design constraint for critical applications at ground-level and aerospace. SRAM-based FPGAs are attractive for critical applications due to their high performance… (more)

Subjects/Keywords: Microeletrônica; SRAM-based FPGA; Fpga; Soft error; Circuitos digitais; Memory scrubbing; Reliability; Single event upsets; Fault tolerance; Microelectronics

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Seclen, J. L. T. (2015). Frame-level redundancy scrubbing technique for SRAM-based FPGAs. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/143194

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Seclen, Jorge Lucio Tonfat. “Frame-level redundancy scrubbing technique for SRAM-based FPGAs.” 2015. Thesis, Universidade do Rio Grande do Sul. Accessed December 13, 2019. http://hdl.handle.net/10183/143194.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Seclen, Jorge Lucio Tonfat. “Frame-level redundancy scrubbing technique for SRAM-based FPGAs.” 2015. Web. 13 Dec 2019.

Vancouver:

Seclen JLT. Frame-level redundancy scrubbing technique for SRAM-based FPGAs. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2015. [cited 2019 Dec 13]. Available from: http://hdl.handle.net/10183/143194.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Seclen JLT. Frame-level redundancy scrubbing technique for SRAM-based FPGAs. [Thesis]. Universidade do Rio Grande do Sul; 2015. Available from: http://hdl.handle.net/10183/143194

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Saskatchewan

30. Wen, Rui. Functional Studies of the Arabidopsis thaliana Ubc13-Uev Complex.

Degree: 2010, University of Saskatchewan

 Ubiquitination is an important biochemical reaction found in all eukaryotic organisms and is involved in a wide range of cellular processes. Conventional ubiquitination requires the… (more)

Subjects/Keywords: error-free DNA damage tolerance; Arabidopsis thaliana; Ubquitin-conjugating enzyme 13; Lys63-linked ubiquitination; Ubiquitin-conjugating enzyme variant

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wen, R. (2010). Functional Studies of the Arabidopsis thaliana Ubc13-Uev Complex. (Thesis). University of Saskatchewan. Retrieved from http://hdl.handle.net/10388/etd-09202010-123855

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wen, Rui. “Functional Studies of the Arabidopsis thaliana Ubc13-Uev Complex.” 2010. Thesis, University of Saskatchewan. Accessed December 13, 2019. http://hdl.handle.net/10388/etd-09202010-123855.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wen, Rui. “Functional Studies of the Arabidopsis thaliana Ubc13-Uev Complex.” 2010. Web. 13 Dec 2019.

Vancouver:

Wen R. Functional Studies of the Arabidopsis thaliana Ubc13-Uev Complex. [Internet] [Thesis]. University of Saskatchewan; 2010. [cited 2019 Dec 13]. Available from: http://hdl.handle.net/10388/etd-09202010-123855.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wen R. Functional Studies of the Arabidopsis thaliana Ubc13-Uev Complex. [Thesis]. University of Saskatchewan; 2010. Available from: http://hdl.handle.net/10388/etd-09202010-123855

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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