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Université de Grenoble

1. Soussou, Assawer. Modeling and characterization of electrical effects of Ge integration in Metal/High-k/SiGe MOS structures : Modélisation et caractérisation des effets électriques de l’intégration du Ge dans les structures Métal/High-k/SiGe.

Degree: Docteur es, Nanoélectronique et nanotechnologie, 2014, Université de Grenoble

L'introduction du SiGe dans les pMOS (Bulk et FDSOI) exige un bon contrôle de la tension de seuil (VT). Ceci nécessite une extraction précise des paramètres électriques ainsi qu'une compréhension des effets électriques du Ge dans de tels dispositifs. Dans cette thèse, nous avons d'abord proposé des méthodes pour une identification précise des paramètres électriques du « gate stack »: VT, la tension de bande plate (VFB) et l'épaisseur équivalente d'oxyde (EOT). Ces méthodes ont été validées avec des simulations Poisson-Schrödinger (PS) et appliquées avec succès aux mesures. Dans un second temps, nous avons étudié les effets électriques du Ge sur les paramètres du « gate stack » des pMOS. La comparaison des caractérisations électriques (C-V) avec les simulations PS a montré un décalage supplémentaire du travail de sortie effectif qui croit avec le Ge. Des caractérisations STEM, EELS et SIMS ont prouvé que ce décalage est due à la présence de dipôles à l'interface SiGe/oxyde.

Maintaining good threshold voltage (VT) centering is a paramount challenge for CMOS technology. The SiGe introduction in bulk and FDSOI pFETs requires VT control for such devices. To this end, we have to extract accurately electrical parameters and to understand Ge integration effects in SiGe based pFETs. In this thesis, first, we have proposed extraction methods to determine VT, flat band voltage (VFB) and equivalent oxide thickness (EOT) parameters in bulk and FDSOI transistors. The extraction methods have been validated via Poisson-Schrodinger (PS) simulations and successfully applied to measurements. Second, we have highlighted and explained electric effects of Ge on pMOS gate stack parameters. Electrical characterizations compared with PS simulations have evidenced an additional effective work function increase, induced by Ge, related to interfacial dipoles. STEM, EELS and SIMS characterizations have demonstrated that dipoles are located at SiGe/IL interface.

Advisors/Committee Members: Ghibaudo, Gérard (thesis director), Rideau, Denis (thesis director), Leroux, Charles (thesis director).

Subjects/Keywords: Modélisation; Caractérisation; SiGe; Extraction des paramètres électriques; Travail de sortie effectif; Charges et dipôles; Modeling; Caracterization; SiGe; Electrical parameters extraction; Effective gate work function; Oxide charges and dipoles; 620

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Soussou, A. (2014). Modeling and characterization of electrical effects of Ge integration in Metal/High-k/SiGe MOS structures : Modélisation et caractérisation des effets électriques de l’intégration du Ge dans les structures Métal/High-k/SiGe. (Doctoral Dissertation). Université de Grenoble. Retrieved from http://www.theses.fr/2014GRENT018

Chicago Manual of Style (16th Edition):

Soussou, Assawer. “Modeling and characterization of electrical effects of Ge integration in Metal/High-k/SiGe MOS structures : Modélisation et caractérisation des effets électriques de l’intégration du Ge dans les structures Métal/High-k/SiGe.” 2014. Doctoral Dissertation, Université de Grenoble. Accessed August 05, 2020. http://www.theses.fr/2014GRENT018.

MLA Handbook (7th Edition):

Soussou, Assawer. “Modeling and characterization of electrical effects of Ge integration in Metal/High-k/SiGe MOS structures : Modélisation et caractérisation des effets électriques de l’intégration du Ge dans les structures Métal/High-k/SiGe.” 2014. Web. 05 Aug 2020.

Vancouver:

Soussou A. Modeling and characterization of electrical effects of Ge integration in Metal/High-k/SiGe MOS structures : Modélisation et caractérisation des effets électriques de l’intégration du Ge dans les structures Métal/High-k/SiGe. [Internet] [Doctoral dissertation]. Université de Grenoble; 2014. [cited 2020 Aug 05]. Available from: http://www.theses.fr/2014GRENT018.

Council of Science Editors:

Soussou A. Modeling and characterization of electrical effects of Ge integration in Metal/High-k/SiGe MOS structures : Modélisation et caractérisation des effets électriques de l’intégration du Ge dans les structures Métal/High-k/SiGe. [Doctoral Dissertation]. Université de Grenoble; 2014. Available from: http://www.theses.fr/2014GRENT018


North Carolina State University

2. Jur, Jesse Stephen. Lanthanide-based Oxides and Silicates for High-K Gate Dielectric Applications.

Degree: PhD, Materials Science and Engineering, 2007, North Carolina State University

The ability to improve performance of the high-end metal oxide semiconductor field effect transistor (MOSFET) is highly reliant on the dimensional scaling of such a device. In scaling, a decrease in dielectric thickness results in high leakage current between the electrode and the substrate by way of direct tunneling through the gate dielectric. Observation of a high leakage current when the standard gate dielectric, SiO2, is decreased below a thickness of 1.5 nm requires engineering of a replacement dielectric that is much more scalable. This high- dielectric allows for a physically thicker oxide, reducing leakage current. Integration of select lanthanide-based oxides and silicates, in particular lanthanum oxide and silicate, into MOS gate stack devices is examined. The quality of the high-K dielectrics is monitored electrically to determine properties such as equivalent oxide thickness, leakage current density and defect densities. In addition, analytical characterization of the dielectric and the gate stack is provided to examine the materialistic significance to the change of the electrical properties of the devices. It is shown that optimization of low-temperature processing can result in MOS devices with an equivalent oxide thickness (EOT) as low 5 Å and a leakage current density of 5.0 A⁄cm2. High-temperature processing, consistent with a MOSFET source-drain activation anneal, yields MOS devices with an EOT as low as 1.1 nm after optimization of the TaN/W electrode properties. The decrease in the device effective work function (phi_M,eff) observed in these samples is examined in detail. First, as a La2O3 capping layer on HfSiO(N), the shift yields ideal-phi_M,eff values for nMOSFET deices (4.0 eV) that were previously inaccessible. Other lanthanide oxides (Dy, Ho and Yb) used as capping layers show similar effects. It is also shown that tuning of phi_M,eff can be realized by controlling the extent of lanthanide-silicate formation. This research, conducted in conjunction with SEMATECH and the SRC, represents a significant technological advancement in realizing 45 and sub-45 nm MOSFET device nodes. Advisors/Committee Members: Angus Kingon, Committee Chair (advisor), Gregory Parsons, Committee Member (advisor), Jon-Paul Maria, Committee Member (advisor), Mark Johnson, Committee Member (advisor).

Subjects/Keywords: dc magnetron sputtering; physical vapor deposition; tungsten oxide; tungsten; W; tantalum nitride; TaN; lanthanum; lanthanum oxide; La; La2O3; La2SiO5; lanthanum silicate; La2Si2O7; Ho; holmium; holmium oxide; cation diffusion; back-side SIMS; secondary ion mass spectroscopy; SIMS; XRD; x-ray diffraction; molecular beam deposition; PMA; XPS; x-ray photoemission spectroscopy; post metallization anneal; RCA; chemical oxide; metal oxide semiconductor field effect transistor; MBE; silica; SiO2; interfacial layer; gate dielectric; dielectric; silicate; oxide; high-kappa; EOT; equivalent oxide thickness; high-k; band diagram; valance band offset; conduction band offset; band gap energy; effective work function; work function; voltage shift; threshold voltage; flat band voltage; leakage current; capacitance; mobility; electronic materials; scaling; Moore?s Law; MIS; MOS; MOSFET; high resolution transmission electron microscopy; HRTEM; RTA; rapid thermal anneal; PVD; tantalum; Ta; gate electrode; metal electrode; hafnium silicate; hafnium oxide; hafnium; ytterbium; ytterbium oxide; Yb; dysprosium oxide; dysprosium; Dy; E-beam evaporation; thermal evaporation; forming gas anneal; ozone; ammonia anneal; FGA

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Jur, J. S. (2007). Lanthanide-based Oxides and Silicates for High-K Gate Dielectric Applications. (Doctoral Dissertation). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/5447

Chicago Manual of Style (16th Edition):

Jur, Jesse Stephen. “Lanthanide-based Oxides and Silicates for High-K Gate Dielectric Applications.” 2007. Doctoral Dissertation, North Carolina State University. Accessed August 05, 2020. http://www.lib.ncsu.edu/resolver/1840.16/5447.

MLA Handbook (7th Edition):

Jur, Jesse Stephen. “Lanthanide-based Oxides and Silicates for High-K Gate Dielectric Applications.” 2007. Web. 05 Aug 2020.

Vancouver:

Jur JS. Lanthanide-based Oxides and Silicates for High-K Gate Dielectric Applications. [Internet] [Doctoral dissertation]. North Carolina State University; 2007. [cited 2020 Aug 05]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/5447.

Council of Science Editors:

Jur JS. Lanthanide-based Oxides and Silicates for High-K Gate Dielectric Applications. [Doctoral Dissertation]. North Carolina State University; 2007. Available from: http://www.lib.ncsu.edu/resolver/1840.16/5447

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