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You searched for subject:(dynamic scaling). Showing records 1 – 30 of 105 total matches.

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University of New South Wales

1. Tariq, Umair. Energy-Aware Task Scheduling with Conditional Precedence Constraints on MPSoCs.

Degree: Computer Science & Engineering, 2018, University of New South Wales

 In order to extract maximum performance out of MPSoCs (Multiprocessor System on- Chips), efficientscheduling is crucial. In embedded systems, one of the major design goals… (more)

Subjects/Keywords: Mapping; Power Optimization; Dynamic Voltage Scaling; Scheduling

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APA (6th Edition):

Tariq, U. (2018). Energy-Aware Task Scheduling with Conditional Precedence Constraints on MPSoCs. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/60342 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51870/SOURCE02?view=true

Chicago Manual of Style (16th Edition):

Tariq, Umair. “Energy-Aware Task Scheduling with Conditional Precedence Constraints on MPSoCs.” 2018. Doctoral Dissertation, University of New South Wales. Accessed August 10, 2020. http://handle.unsw.edu.au/1959.4/60342 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51870/SOURCE02?view=true.

MLA Handbook (7th Edition):

Tariq, Umair. “Energy-Aware Task Scheduling with Conditional Precedence Constraints on MPSoCs.” 2018. Web. 10 Aug 2020.

Vancouver:

Tariq U. Energy-Aware Task Scheduling with Conditional Precedence Constraints on MPSoCs. [Internet] [Doctoral dissertation]. University of New South Wales; 2018. [cited 2020 Aug 10]. Available from: http://handle.unsw.edu.au/1959.4/60342 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51870/SOURCE02?view=true.

Council of Science Editors:

Tariq U. Energy-Aware Task Scheduling with Conditional Precedence Constraints on MPSoCs. [Doctoral Dissertation]. University of New South Wales; 2018. Available from: http://handle.unsw.edu.au/1959.4/60342 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51870/SOURCE02?view=true


Delft University of Technology

2. Jeyachandra, Evelyn Rashmi (author). A System-Level Aging and Mitigation Assessment Simulation Framework.

Degree: 2017, Delft University of Technology

As technology scaling enters the nanometer regime, device aging effects cause quality and reliability issues in CMOS Integrated Circuits (ICs), which in turn shorten its… (more)

Subjects/Keywords: System-level aging; IC lifetime; NBTI; CHC; Dynamic voltage scaling; Dynamic frequency scaling; Adaptive Body Bias

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APA (6th Edition):

Jeyachandra, E. R. (. (2017). A System-Level Aging and Mitigation Assessment Simulation Framework. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:9c942c1b-58be-42f0-accf-0bbe0947b208

Chicago Manual of Style (16th Edition):

Jeyachandra, Evelyn Rashmi (author). “A System-Level Aging and Mitigation Assessment Simulation Framework.” 2017. Masters Thesis, Delft University of Technology. Accessed August 10, 2020. http://resolver.tudelft.nl/uuid:9c942c1b-58be-42f0-accf-0bbe0947b208.

MLA Handbook (7th Edition):

Jeyachandra, Evelyn Rashmi (author). “A System-Level Aging and Mitigation Assessment Simulation Framework.” 2017. Web. 10 Aug 2020.

Vancouver:

Jeyachandra ER(. A System-Level Aging and Mitigation Assessment Simulation Framework. [Internet] [Masters thesis]. Delft University of Technology; 2017. [cited 2020 Aug 10]. Available from: http://resolver.tudelft.nl/uuid:9c942c1b-58be-42f0-accf-0bbe0947b208.

Council of Science Editors:

Jeyachandra ER(. A System-Level Aging and Mitigation Assessment Simulation Framework. [Masters Thesis]. Delft University of Technology; 2017. Available from: http://resolver.tudelft.nl/uuid:9c942c1b-58be-42f0-accf-0bbe0947b208


George Mason University

3. Devadas, Vinay. System-Level Energy Management for Real-Time Systems .

Degree: 2011, George Mason University

 Energy management has recently become one of the key dimensions in the design of real-time embedded systems. While early studies focused separately on individual energy… (more)

Subjects/Keywords: Real-Time Systems; Dynamic Voltage Scaling; Power Management; Dynamic Power Management; Embedded Systems; Online Algorithms

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APA (6th Edition):

Devadas, V. (2011). System-Level Energy Management for Real-Time Systems . (Thesis). George Mason University. Retrieved from http://hdl.handle.net/1920/6590

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Devadas, Vinay. “System-Level Energy Management for Real-Time Systems .” 2011. Thesis, George Mason University. Accessed August 10, 2020. http://hdl.handle.net/1920/6590.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Devadas, Vinay. “System-Level Energy Management for Real-Time Systems .” 2011. Web. 10 Aug 2020.

Vancouver:

Devadas V. System-Level Energy Management for Real-Time Systems . [Internet] [Thesis]. George Mason University; 2011. [cited 2020 Aug 10]. Available from: http://hdl.handle.net/1920/6590.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Devadas V. System-Level Energy Management for Real-Time Systems . [Thesis]. George Mason University; 2011. Available from: http://hdl.handle.net/1920/6590

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Anna University

4. Seshasayanan R. Implementation of novel low power VLIW DSP architecture;.

Degree: Implementation of novel low power VLIW DSP architecture, 2014, Anna University

Technology has seen the development of processor industry right newlinefrom micro to the latest Nano technology With Speed and performance newlinebeing important criteria not much… (more)

Subjects/Keywords: Application specific instruction set processor; Clock skew problem; Dynamic voltage scaling

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APA (6th Edition):

R, S. (2014). Implementation of novel low power VLIW DSP architecture;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/27991

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

R, Seshasayanan. “Implementation of novel low power VLIW DSP architecture;.” 2014. Thesis, Anna University. Accessed August 10, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/27991.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

R, Seshasayanan. “Implementation of novel low power VLIW DSP architecture;.” 2014. Web. 10 Aug 2020.

Vancouver:

R S. Implementation of novel low power VLIW DSP architecture;. [Internet] [Thesis]. Anna University; 2014. [cited 2020 Aug 10]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/27991.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

R S. Implementation of novel low power VLIW DSP architecture;. [Thesis]. Anna University; 2014. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/27991

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

5. Esquit Hernandez, Carlos A. IMPACT OF DYNAMIC VOLTAGE SCALING (DVS) ON CIRCUIT OPTIMIZATION.

Degree: 2010, Texas A&M University

 Circuit designers perform optimization procedures targeting speed and power during the design of a circuit. Gate sizing can be applied to optimize for speed, while… (more)

Subjects/Keywords: VLSI; DVS; dynamic voltage scaling; circuit optimization; logical effort; dual-vt

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APA (6th Edition):

Esquit Hernandez, C. A. (2010). IMPACT OF DYNAMIC VOLTAGE SCALING (DVS) ON CIRCUIT OPTIMIZATION. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2009-05-324

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Esquit Hernandez, Carlos A. “IMPACT OF DYNAMIC VOLTAGE SCALING (DVS) ON CIRCUIT OPTIMIZATION.” 2010. Thesis, Texas A&M University. Accessed August 10, 2020. http://hdl.handle.net/1969.1/ETD-TAMU-2009-05-324.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Esquit Hernandez, Carlos A. “IMPACT OF DYNAMIC VOLTAGE SCALING (DVS) ON CIRCUIT OPTIMIZATION.” 2010. Web. 10 Aug 2020.

Vancouver:

Esquit Hernandez CA. IMPACT OF DYNAMIC VOLTAGE SCALING (DVS) ON CIRCUIT OPTIMIZATION. [Internet] [Thesis]. Texas A&M University; 2010. [cited 2020 Aug 10]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2009-05-324.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Esquit Hernandez CA. IMPACT OF DYNAMIC VOLTAGE SCALING (DVS) ON CIRCUIT OPTIMIZATION. [Thesis]. Texas A&M University; 2010. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2009-05-324

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

6. Chilambuchelvan A. Certain investigations on the Performance analysis of dynamic Voltage scaling algorithms for low Power embedded operating systems;.

Degree: Certain investigations on the Performance analysis of dynamic Voltage scaling algorithms for low Power embedded operating systems, 2014, Anna University

Energy efficiency is an important property of mobile and pervasive newlinecomputing devices Dynamic voltage scaling DVS is an energy saving newlinetechnique which is achieved by… (more)

Subjects/Keywords: Dynamic voltage scaling; Information and Communication engineering; Power embedded operating systems

Page 1

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

A, C. (2014). Certain investigations on the Performance analysis of dynamic Voltage scaling algorithms for low Power embedded operating systems;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/26824

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

A, Chilambuchelvan. “Certain investigations on the Performance analysis of dynamic Voltage scaling algorithms for low Power embedded operating systems;.” 2014. Thesis, Anna University. Accessed August 10, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/26824.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

A, Chilambuchelvan. “Certain investigations on the Performance analysis of dynamic Voltage scaling algorithms for low Power embedded operating systems;.” 2014. Web. 10 Aug 2020.

Vancouver:

A C. Certain investigations on the Performance analysis of dynamic Voltage scaling algorithms for low Power embedded operating systems;. [Internet] [Thesis]. Anna University; 2014. [cited 2020 Aug 10]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/26824.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

A C. Certain investigations on the Performance analysis of dynamic Voltage scaling algorithms for low Power embedded operating systems;. [Thesis]. Anna University; 2014. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/26824

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

7. Jheng, Hao-Yi. An Adaptive Proportional-Integral Controller for Power Management of 3D Graphics System-On-Chip.

Degree: Master, Computer Science and Engineering, 2009, NSYSU

 In the past few years, due to the rapid advance in technology and the aid of 3D graphics applications the world of 3D graphics is… (more)

Subjects/Keywords: proportional control; dynamic voltage scaling; Power management; 3D graphics; Integral control

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APA (6th Edition):

Jheng, H. (2009). An Adaptive Proportional-Integral Controller for Power Management of 3D Graphics System-On-Chip. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731109-121154

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Jheng, Hao-Yi. “An Adaptive Proportional-Integral Controller for Power Management of 3D Graphics System-On-Chip.” 2009. Thesis, NSYSU. Accessed August 10, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731109-121154.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Jheng, Hao-Yi. “An Adaptive Proportional-Integral Controller for Power Management of 3D Graphics System-On-Chip.” 2009. Web. 10 Aug 2020.

Vancouver:

Jheng H. An Adaptive Proportional-Integral Controller for Power Management of 3D Graphics System-On-Chip. [Internet] [Thesis]. NSYSU; 2009. [cited 2020 Aug 10]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731109-121154.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Jheng H. An Adaptive Proportional-Integral Controller for Power Management of 3D Graphics System-On-Chip. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0731109-121154

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Tech

8. Chou, Yen-Liang. Relaxation phenomena during non-equilibrium growth.

Degree: PhD, Physics, 2011, Virginia Tech

 The surface width, a global quantity that depends on time, is used to characterize the temporal evolution of growing surfaces. One of the most successful… (more)

Subjects/Keywords: response function; correlation function; surface growth processes; dynamic scaling; kinetic roughening

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APA (6th Edition):

Chou, Y. (2011). Relaxation phenomena during non-equilibrium growth. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/28574

Chicago Manual of Style (16th Edition):

Chou, Yen-Liang. “Relaxation phenomena during non-equilibrium growth.” 2011. Doctoral Dissertation, Virginia Tech. Accessed August 10, 2020. http://hdl.handle.net/10919/28574.

MLA Handbook (7th Edition):

Chou, Yen-Liang. “Relaxation phenomena during non-equilibrium growth.” 2011. Web. 10 Aug 2020.

Vancouver:

Chou Y. Relaxation phenomena during non-equilibrium growth. [Internet] [Doctoral dissertation]. Virginia Tech; 2011. [cited 2020 Aug 10]. Available from: http://hdl.handle.net/10919/28574.

Council of Science Editors:

Chou Y. Relaxation phenomena during non-equilibrium growth. [Doctoral Dissertation]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/28574


Virginia Tech

9. Saha, Sonal. An Experimental Evaluation of Real-Time DVFS Scheduling Algorithms.

Degree: MS, Electrical and Computer Engineering, 2011, Virginia Tech

Dynamic voltage and frequency scaling (DVFS) is an extensively studied energy manage- ment technique, which aims to reduce the energy consumption of computing platforms by… (more)

Subjects/Keywords: Dynamic Voltage and Frequency Scaling; Real-Time Linux

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APA (6th Edition):

Saha, S. (2011). An Experimental Evaluation of Real-Time DVFS Scheduling Algorithms. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/35035

Chicago Manual of Style (16th Edition):

Saha, Sonal. “An Experimental Evaluation of Real-Time DVFS Scheduling Algorithms.” 2011. Masters Thesis, Virginia Tech. Accessed August 10, 2020. http://hdl.handle.net/10919/35035.

MLA Handbook (7th Edition):

Saha, Sonal. “An Experimental Evaluation of Real-Time DVFS Scheduling Algorithms.” 2011. Web. 10 Aug 2020.

Vancouver:

Saha S. An Experimental Evaluation of Real-Time DVFS Scheduling Algorithms. [Internet] [Masters thesis]. Virginia Tech; 2011. [cited 2020 Aug 10]. Available from: http://hdl.handle.net/10919/35035.

Council of Science Editors:

Saha S. An Experimental Evaluation of Real-Time DVFS Scheduling Algorithms. [Masters Thesis]. Virginia Tech; 2011. Available from: http://hdl.handle.net/10919/35035


University of New South Wales

10. Le Sueur, Etienne. An analysis of the effectiveness of energy management on modern computer processors.

Degree: Computer Science & Engineering, 2011, University of New South Wales

 Managing energy consumption has become a critical issue for computer system designers. End-users are forced to charge battery-powered devices on a daily basis because battery… (more)

Subjects/Keywords: Dynamic voltage frequency scaling; Operating system; Power energy management

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APA (6th Edition):

Le Sueur, E. (2011). An analysis of the effectiveness of energy management on modern computer processors. (Masters Thesis). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/50882 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:9776/SOURCE02?view=true

Chicago Manual of Style (16th Edition):

Le Sueur, Etienne. “An analysis of the effectiveness of energy management on modern computer processors.” 2011. Masters Thesis, University of New South Wales. Accessed August 10, 2020. http://handle.unsw.edu.au/1959.4/50882 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:9776/SOURCE02?view=true.

MLA Handbook (7th Edition):

Le Sueur, Etienne. “An analysis of the effectiveness of energy management on modern computer processors.” 2011. Web. 10 Aug 2020.

Vancouver:

Le Sueur E. An analysis of the effectiveness of energy management on modern computer processors. [Internet] [Masters thesis]. University of New South Wales; 2011. [cited 2020 Aug 10]. Available from: http://handle.unsw.edu.au/1959.4/50882 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:9776/SOURCE02?view=true.

Council of Science Editors:

Le Sueur E. An analysis of the effectiveness of energy management on modern computer processors. [Masters Thesis]. University of New South Wales; 2011. Available from: http://handle.unsw.edu.au/1959.4/50882 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:9776/SOURCE02?view=true


University of New South Wales

11. Snowdon, David. Operating system directed power management.

Degree: Computer Science & Engineering, 2010, University of New South Wales

 Energy is a critical resource in all types of computing systems from servers, where energy costs dominate data centre expenses and carbon footprints, to embedded… (more)

Subjects/Keywords: Operating Systems; Power Management; Dynamic Voltage Scaling; Energy; Efficiency; Modelling

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APA (6th Edition):

Snowdon, D. (2010). Operating system directed power management. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/44747 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:8046/SOURCE02?view=true

Chicago Manual of Style (16th Edition):

Snowdon, David. “Operating system directed power management.” 2010. Doctoral Dissertation, University of New South Wales. Accessed August 10, 2020. http://handle.unsw.edu.au/1959.4/44747 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:8046/SOURCE02?view=true.

MLA Handbook (7th Edition):

Snowdon, David. “Operating system directed power management.” 2010. Web. 10 Aug 2020.

Vancouver:

Snowdon D. Operating system directed power management. [Internet] [Doctoral dissertation]. University of New South Wales; 2010. [cited 2020 Aug 10]. Available from: http://handle.unsw.edu.au/1959.4/44747 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:8046/SOURCE02?view=true.

Council of Science Editors:

Snowdon D. Operating system directed power management. [Doctoral Dissertation]. University of New South Wales; 2010. Available from: http://handle.unsw.edu.au/1959.4/44747 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:8046/SOURCE02?view=true


University of Toronto

12. Zhao, Shuze. Moving Beyond Worst-Case Power Design in Datacenters - Distributed UPS and Dynamic Voltage Scaling for FPGAs.

Degree: PhD, 2018, University of Toronto

 Millions of datacenters are operating all over the world, consuming up to 3% of the global electricity power and leaving a significant carbon footprint. Due… (more)

Subjects/Keywords: datacenter; distributed UPS; dynamic voltage scaling (DVS); FPGA; 0544

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APA (6th Edition):

Zhao, S. (2018). Moving Beyond Worst-Case Power Design in Datacenters - Distributed UPS and Dynamic Voltage Scaling for FPGAs. (Doctoral Dissertation). University of Toronto. Retrieved from http://hdl.handle.net/1807/89899

Chicago Manual of Style (16th Edition):

Zhao, Shuze. “Moving Beyond Worst-Case Power Design in Datacenters - Distributed UPS and Dynamic Voltage Scaling for FPGAs.” 2018. Doctoral Dissertation, University of Toronto. Accessed August 10, 2020. http://hdl.handle.net/1807/89899.

MLA Handbook (7th Edition):

Zhao, Shuze. “Moving Beyond Worst-Case Power Design in Datacenters - Distributed UPS and Dynamic Voltage Scaling for FPGAs.” 2018. Web. 10 Aug 2020.

Vancouver:

Zhao S. Moving Beyond Worst-Case Power Design in Datacenters - Distributed UPS and Dynamic Voltage Scaling for FPGAs. [Internet] [Doctoral dissertation]. University of Toronto; 2018. [cited 2020 Aug 10]. Available from: http://hdl.handle.net/1807/89899.

Council of Science Editors:

Zhao S. Moving Beyond Worst-Case Power Design in Datacenters - Distributed UPS and Dynamic Voltage Scaling for FPGAs. [Doctoral Dissertation]. University of Toronto; 2018. Available from: http://hdl.handle.net/1807/89899


University of Ontario Institute of Technology

13. Mi, Yi. Comparative assessment of small modular reactor Passive Safety System design via integration of dynamic methods of analyses.

Degree: 2019, University of Ontario Institute of Technology

 Integral Pressurized Water Reactor (iPWR) type SMR designs were studied featuring Passive Safety Systems (PSS) in all cases. As many as 11 current SMR designs… (more)

Subjects/Keywords: iPWR; PSS; Evaluation metrics; Scaling analysis; Dynamic PRA

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APA (6th Edition):

Mi, Y. (2019). Comparative assessment of small modular reactor Passive Safety System design via integration of dynamic methods of analyses. (Thesis). University of Ontario Institute of Technology. Retrieved from http://hdl.handle.net/10155/1135

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mi, Yi. “Comparative assessment of small modular reactor Passive Safety System design via integration of dynamic methods of analyses.” 2019. Thesis, University of Ontario Institute of Technology. Accessed August 10, 2020. http://hdl.handle.net/10155/1135.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mi, Yi. “Comparative assessment of small modular reactor Passive Safety System design via integration of dynamic methods of analyses.” 2019. Web. 10 Aug 2020.

Vancouver:

Mi Y. Comparative assessment of small modular reactor Passive Safety System design via integration of dynamic methods of analyses. [Internet] [Thesis]. University of Ontario Institute of Technology; 2019. [cited 2020 Aug 10]. Available from: http://hdl.handle.net/10155/1135.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mi Y. Comparative assessment of small modular reactor Passive Safety System design via integration of dynamic methods of analyses. [Thesis]. University of Ontario Institute of Technology; 2019. Available from: http://hdl.handle.net/10155/1135

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

14. Li, Bo. Modeling and Runtime Systems for Coordinated Power-Performance Management.

Degree: PhD, Computer Science and Applications, 2019, Virginia Tech

 System efficiency on high-performance computing (HPC) systems is the key to achieving the goal of power budget for exascale supercomputers. Techniques for adjusting the performance… (more)

Subjects/Keywords: Parallel Performance Modeling; Dynamic Voltage and Frequency Scaling; Dynamic Memory Throttling; Dynamic Concurrency Throttling; Shared-Memory Systems

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APA (6th Edition):

Li, B. (2019). Modeling and Runtime Systems for Coordinated Power-Performance Management. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/87064

Chicago Manual of Style (16th Edition):

Li, Bo. “Modeling and Runtime Systems for Coordinated Power-Performance Management.” 2019. Doctoral Dissertation, Virginia Tech. Accessed August 10, 2020. http://hdl.handle.net/10919/87064.

MLA Handbook (7th Edition):

Li, Bo. “Modeling and Runtime Systems for Coordinated Power-Performance Management.” 2019. Web. 10 Aug 2020.

Vancouver:

Li B. Modeling and Runtime Systems for Coordinated Power-Performance Management. [Internet] [Doctoral dissertation]. Virginia Tech; 2019. [cited 2020 Aug 10]. Available from: http://hdl.handle.net/10919/87064.

Council of Science Editors:

Li B. Modeling and Runtime Systems for Coordinated Power-Performance Management. [Doctoral Dissertation]. Virginia Tech; 2019. Available from: http://hdl.handle.net/10919/87064


University of Waterloo

15. Ghaznavi, Milad. Scalable and Reliable Middlebox Deployment.

Degree: 2020, University of Waterloo

 Middleboxes are pervasive in modern computer networks providing functionalities beyond mere packet forwarding. Load balancers, intrusion detection systems, and network address translators are typical examples… (more)

Subjects/Keywords: Middlebox; Network Function; Service Function Chain; Service Chain; Fault Tolerance; Scalability; Replication; Dynamic Scaling; Elastic Scaling; Distributed Deployment

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ghaznavi, M. (2020). Scalable and Reliable Middlebox Deployment. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/15947

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ghaznavi, Milad. “Scalable and Reliable Middlebox Deployment.” 2020. Thesis, University of Waterloo. Accessed August 10, 2020. http://hdl.handle.net/10012/15947.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ghaznavi, Milad. “Scalable and Reliable Middlebox Deployment.” 2020. Web. 10 Aug 2020.

Vancouver:

Ghaznavi M. Scalable and Reliable Middlebox Deployment. [Internet] [Thesis]. University of Waterloo; 2020. [cited 2020 Aug 10]. Available from: http://hdl.handle.net/10012/15947.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ghaznavi M. Scalable and Reliable Middlebox Deployment. [Thesis]. University of Waterloo; 2020. Available from: http://hdl.handle.net/10012/15947

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

16. Park, Junyoung. Self-tuning dynamic voltage scaling techniques for processor design.

Degree: PhD, Electrical and Computer Engineering, 2013, University of Texas – Austin

 The Dynamic Voltage Scaling (DVS) technique has proven to be ideal in regard to balancing performance and energy consumption of a processor since it allows… (more)

Subjects/Keywords: Dynamic voltage scaling; Dynamic voltage scaled processor; Adaptive voltage scaling; Adaptive voltage scaled processor; Critical path monitor; Critical path replica; Path slope; Critical paths; Energy delay product

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Park, J. (2013). Self-tuning dynamic voltage scaling techniques for processor design. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/22989

Chicago Manual of Style (16th Edition):

Park, Junyoung. “Self-tuning dynamic voltage scaling techniques for processor design.” 2013. Doctoral Dissertation, University of Texas – Austin. Accessed August 10, 2020. http://hdl.handle.net/2152/22989.

MLA Handbook (7th Edition):

Park, Junyoung. “Self-tuning dynamic voltage scaling techniques for processor design.” 2013. Web. 10 Aug 2020.

Vancouver:

Park J. Self-tuning dynamic voltage scaling techniques for processor design. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2013. [cited 2020 Aug 10]. Available from: http://hdl.handle.net/2152/22989.

Council of Science Editors:

Park J. Self-tuning dynamic voltage scaling techniques for processor design. [Doctoral Dissertation]. University of Texas – Austin; 2013. Available from: http://hdl.handle.net/2152/22989


Penn State University

17. Erwin, Brian M. Temperature Dependence of the Length Scale for Cooperative Motion in Glass-Forming Liquids.

Degree: PhD, Materials Science and Engineering, 2005, Penn State University

 When considered in the framework of a dynamic scaling model, the length scale of cooperative motion of all glass-forming liquids appears to have a universal… (more)

Subjects/Keywords: glass; dynamic scaling; indane; critical temperature

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APA (6th Edition):

Erwin, B. M. (2005). Temperature Dependence of the Length Scale for Cooperative Motion in Glass-Forming Liquids. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/6786

Chicago Manual of Style (16th Edition):

Erwin, Brian M. “Temperature Dependence of the Length Scale for Cooperative Motion in Glass-Forming Liquids.” 2005. Doctoral Dissertation, Penn State University. Accessed August 10, 2020. https://etda.libraries.psu.edu/catalog/6786.

MLA Handbook (7th Edition):

Erwin, Brian M. “Temperature Dependence of the Length Scale for Cooperative Motion in Glass-Forming Liquids.” 2005. Web. 10 Aug 2020.

Vancouver:

Erwin BM. Temperature Dependence of the Length Scale for Cooperative Motion in Glass-Forming Liquids. [Internet] [Doctoral dissertation]. Penn State University; 2005. [cited 2020 Aug 10]. Available from: https://etda.libraries.psu.edu/catalog/6786.

Council of Science Editors:

Erwin BM. Temperature Dependence of the Length Scale for Cooperative Motion in Glass-Forming Liquids. [Doctoral Dissertation]. Penn State University; 2005. Available from: https://etda.libraries.psu.edu/catalog/6786


North Carolina State University

18. Pan, Feng. Exploring Energy-Time Tradeoff in High Performance Computing.

Degree: MS, Computer Science, 2005, North Carolina State University

 Recently, energy has become an important issue in high-performance computing. For example, low power/energy supercomputers, such as Green Destiny, have been built; the idea is… (more)

Subjects/Keywords: Dynamic Voltage Scaling; Power-Aware Computing

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APA (6th Edition):

Pan, F. (2005). Exploring Energy-Time Tradeoff in High Performance Computing. (Thesis). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/1742

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pan, Feng. “Exploring Energy-Time Tradeoff in High Performance Computing.” 2005. Thesis, North Carolina State University. Accessed August 10, 2020. http://www.lib.ncsu.edu/resolver/1840.16/1742.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pan, Feng. “Exploring Energy-Time Tradeoff in High Performance Computing.” 2005. Web. 10 Aug 2020.

Vancouver:

Pan F. Exploring Energy-Time Tradeoff in High Performance Computing. [Internet] [Thesis]. North Carolina State University; 2005. [cited 2020 Aug 10]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/1742.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pan F. Exploring Energy-Time Tradeoff in High Performance Computing. [Thesis]. North Carolina State University; 2005. Available from: http://www.lib.ncsu.edu/resolver/1840.16/1742

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

19. Yeh, Jia-huei. An Adaptive Fuzzy Proportional-Integral Predictor for Power Management of 3D Graphics System-On-Chip.

Degree: Master, Computer Science and Engineering, 2010, NSYSU

 As time goes by rapid development of 3D graphics technique and 3C portable product output, 3D graphics have been widely applied to handheld devices, such… (more)

Subjects/Keywords: Power Management; Dynamic Voltage Frequency Scaling(DVFS); Proportional- Integral Controller; Fuzzy Controller

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APA (6th Edition):

Yeh, J. (2010). An Adaptive Fuzzy Proportional-Integral Predictor for Power Management of 3D Graphics System-On-Chip. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0802110-133640

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yeh, Jia-huei. “An Adaptive Fuzzy Proportional-Integral Predictor for Power Management of 3D Graphics System-On-Chip.” 2010. Thesis, NSYSU. Accessed August 10, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0802110-133640.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yeh, Jia-huei. “An Adaptive Fuzzy Proportional-Integral Predictor for Power Management of 3D Graphics System-On-Chip.” 2010. Web. 10 Aug 2020.

Vancouver:

Yeh J. An Adaptive Fuzzy Proportional-Integral Predictor for Power Management of 3D Graphics System-On-Chip. [Internet] [Thesis]. NSYSU; 2010. [cited 2020 Aug 10]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0802110-133640.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yeh J. An Adaptive Fuzzy Proportional-Integral Predictor for Power Management of 3D Graphics System-On-Chip. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0802110-133640

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Virginia Tech

20. Park, Hyunhang. Spin Systems far from Equilibrium: Aging and Dynamic Phase Transition.

Degree: PhD, Physics, 2013, Virginia Tech

 Among the many non-equilibrium processes encountered in nature we deal with two different but related aspects. One is the non-equilibrium relaxation process that is at… (more)

Subjects/Keywords: Aging Phenomena; Disordered Ferromagnets; Dynamical Scaling; Dynamic Phase Transition; Surface Critical Phenomena; Surface Phase Diagram

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Park, H. (2013). Spin Systems far from Equilibrium: Aging and Dynamic Phase Transition. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/19323

Chicago Manual of Style (16th Edition):

Park, Hyunhang. “Spin Systems far from Equilibrium: Aging and Dynamic Phase Transition.” 2013. Doctoral Dissertation, Virginia Tech. Accessed August 10, 2020. http://hdl.handle.net/10919/19323.

MLA Handbook (7th Edition):

Park, Hyunhang. “Spin Systems far from Equilibrium: Aging and Dynamic Phase Transition.” 2013. Web. 10 Aug 2020.

Vancouver:

Park H. Spin Systems far from Equilibrium: Aging and Dynamic Phase Transition. [Internet] [Doctoral dissertation]. Virginia Tech; 2013. [cited 2020 Aug 10]. Available from: http://hdl.handle.net/10919/19323.

Council of Science Editors:

Park H. Spin Systems far from Equilibrium: Aging and Dynamic Phase Transition. [Doctoral Dissertation]. Virginia Tech; 2013. Available from: http://hdl.handle.net/10919/19323


Florida International University

21. Shivashanker, Mohan. The Development of Hardware Multi-core Test-bed on Field Programmable Gate Array.

Degree: Electrical Engineering, 2011, Florida International University

  The goal of this project is to develop a flexible multi-core hardware test-bed on field programmable gate array (FPGA) that can be used to… (more)

Subjects/Keywords: Hardware multi-core; dynamic frequency scaling; test-bed; field programmable gate array

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APA (6th Edition):

Shivashanker, M. (2011). The Development of Hardware Multi-core Test-bed on Field Programmable Gate Array. (Thesis). Florida International University. Retrieved from https://digitalcommons.fiu.edu/etd/395 ; 10.25148/etd.FI11050902 ; FI11050902

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shivashanker, Mohan. “The Development of Hardware Multi-core Test-bed on Field Programmable Gate Array.” 2011. Thesis, Florida International University. Accessed August 10, 2020. https://digitalcommons.fiu.edu/etd/395 ; 10.25148/etd.FI11050902 ; FI11050902.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shivashanker, Mohan. “The Development of Hardware Multi-core Test-bed on Field Programmable Gate Array.” 2011. Web. 10 Aug 2020.

Vancouver:

Shivashanker M. The Development of Hardware Multi-core Test-bed on Field Programmable Gate Array. [Internet] [Thesis]. Florida International University; 2011. [cited 2020 Aug 10]. Available from: https://digitalcommons.fiu.edu/etd/395 ; 10.25148/etd.FI11050902 ; FI11050902.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shivashanker M. The Development of Hardware Multi-core Test-bed on Field Programmable Gate Array. [Thesis]. Florida International University; 2011. Available from: https://digitalcommons.fiu.edu/etd/395 ; 10.25148/etd.FI11050902 ; FI11050902

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of South Florida

22. Wang, Yue. Performance and Power Optimization of GPU Architectures for General-purpose Computing.

Degree: 2014, University of South Florida

 Power-performance efficiency has become a central focus that is challenging in heterogeneous processing platforms as the power constraints have to be established without hindering the… (more)

Subjects/Keywords: Cache; Dynamic Frequency Scaling; Linear Programming; PID Controller; Workload Balancing; Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wang, Y. (2014). Performance and Power Optimization of GPU Architectures for General-purpose Computing. (Thesis). University of South Florida. Retrieved from https://scholarcommons.usf.edu/etd/5325

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Yue. “Performance and Power Optimization of GPU Architectures for General-purpose Computing.” 2014. Thesis, University of South Florida. Accessed August 10, 2020. https://scholarcommons.usf.edu/etd/5325.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Yue. “Performance and Power Optimization of GPU Architectures for General-purpose Computing.” 2014. Web. 10 Aug 2020.

Vancouver:

Wang Y. Performance and Power Optimization of GPU Architectures for General-purpose Computing. [Internet] [Thesis]. University of South Florida; 2014. [cited 2020 Aug 10]. Available from: https://scholarcommons.usf.edu/etd/5325.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang Y. Performance and Power Optimization of GPU Architectures for General-purpose Computing. [Thesis]. University of South Florida; 2014. Available from: https://scholarcommons.usf.edu/etd/5325

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Wright State University

23. Lee, Yu-Heng George. DYNAMIC KERNEL FUNCTION FOR HIGH-SPEED REAL-TIME FAST FOURIER TRANSFORM PROCESSORS.

Degree: PhD, Engineering PhD, 2009, Wright State University

  The fast Fourier transform (FFT) plays a critical role in many modern applications, such as acoustics, optics, telecommunications, wireless sensor networks, location sensing, patient… (more)

Subjects/Keywords: Electrical Engineering; Dynamic kernel function; fast Fourier transform; dynamic range; FPGA; variable truncation scheme; data scaling

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lee, Y. G. (2009). DYNAMIC KERNEL FUNCTION FOR HIGH-SPEED REAL-TIME FAST FOURIER TRANSFORM PROCESSORS. (Doctoral Dissertation). Wright State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=wright1260821902

Chicago Manual of Style (16th Edition):

Lee, Yu-Heng George. “DYNAMIC KERNEL FUNCTION FOR HIGH-SPEED REAL-TIME FAST FOURIER TRANSFORM PROCESSORS.” 2009. Doctoral Dissertation, Wright State University. Accessed August 10, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=wright1260821902.

MLA Handbook (7th Edition):

Lee, Yu-Heng George. “DYNAMIC KERNEL FUNCTION FOR HIGH-SPEED REAL-TIME FAST FOURIER TRANSFORM PROCESSORS.” 2009. Web. 10 Aug 2020.

Vancouver:

Lee YG. DYNAMIC KERNEL FUNCTION FOR HIGH-SPEED REAL-TIME FAST FOURIER TRANSFORM PROCESSORS. [Internet] [Doctoral dissertation]. Wright State University; 2009. [cited 2020 Aug 10]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1260821902.

Council of Science Editors:

Lee YG. DYNAMIC KERNEL FUNCTION FOR HIGH-SPEED REAL-TIME FAST FOURIER TRANSFORM PROCESSORS. [Doctoral Dissertation]. Wright State University; 2009. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=wright1260821902


University of Kentucky

24. Datta, Srabosti. POWER REDUCTION BY DYNAMICALLY VARYING SAMPLING RATE.

Degree: 2006, University of Kentucky

 In modern digital audio applications, a continuous audio signal stream is sampled at a fixed sampling rate, which is always greater than twice the highest… (more)

Subjects/Keywords: Digital signal processors; Audio applications; Dynamic voltage scaling; frequency scaling; sampling rate

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Datta, S. (2006). POWER REDUCTION BY DYNAMICALLY VARYING SAMPLING RATE. (Masters Thesis). University of Kentucky. Retrieved from http://uknowledge.uky.edu/gradschool_theses/275

Chicago Manual of Style (16th Edition):

Datta, Srabosti. “POWER REDUCTION BY DYNAMICALLY VARYING SAMPLING RATE.” 2006. Masters Thesis, University of Kentucky. Accessed August 10, 2020. http://uknowledge.uky.edu/gradschool_theses/275.

MLA Handbook (7th Edition):

Datta, Srabosti. “POWER REDUCTION BY DYNAMICALLY VARYING SAMPLING RATE.” 2006. Web. 10 Aug 2020.

Vancouver:

Datta S. POWER REDUCTION BY DYNAMICALLY VARYING SAMPLING RATE. [Internet] [Masters thesis]. University of Kentucky; 2006. [cited 2020 Aug 10]. Available from: http://uknowledge.uky.edu/gradschool_theses/275.

Council of Science Editors:

Datta S. POWER REDUCTION BY DYNAMICALLY VARYING SAMPLING RATE. [Masters Thesis]. University of Kentucky; 2006. Available from: http://uknowledge.uky.edu/gradschool_theses/275


North Carolina State University

25. Seth, Kiran Ravi. Frequency-aware Static Timing Analysis for Power-aware Embedded Architectures.

Degree: MS, Computer Engineering, 2004, North Carolina State University

 Power is a valuable resource in embedded systems as the lifetime of many such systems is constrained by their battery capacity. Recent advances in processor… (more)

Subjects/Keywords: real-time scheduling; frequency scaling; real-time systems; dynamic voltage scaling

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Seth, K. R. (2004). Frequency-aware Static Timing Analysis for Power-aware Embedded Architectures. (Thesis). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/824

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Seth, Kiran Ravi. “Frequency-aware Static Timing Analysis for Power-aware Embedded Architectures.” 2004. Thesis, North Carolina State University. Accessed August 10, 2020. http://www.lib.ncsu.edu/resolver/1840.16/824.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Seth, Kiran Ravi. “Frequency-aware Static Timing Analysis for Power-aware Embedded Architectures.” 2004. Web. 10 Aug 2020.

Vancouver:

Seth KR. Frequency-aware Static Timing Analysis for Power-aware Embedded Architectures. [Internet] [Thesis]. North Carolina State University; 2004. [cited 2020 Aug 10]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/824.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Seth KR. Frequency-aware Static Timing Analysis for Power-aware Embedded Architectures. [Thesis]. North Carolina State University; 2004. Available from: http://www.lib.ncsu.edu/resolver/1840.16/824

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

26. Rathnala, Prasanthi. Power efficient and power attacks resistant system design and analysis using aggressive scaling with timing speculation.

Degree: PhD, 2017, University of Derby

 Growing usage of smart and portable electronic devices demands embedded system designers to provide solutions with better performance and reduced power consumption. Due to the… (more)

Subjects/Keywords: 004.67; Differential power analysis; Dynamic voltage and frequency scaling; Internet of things; S-Box; Low power performance improvement; Time-Borrowing; Timing Error; Aggressive Scaling; Process voltage and temperature

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Rathnala, P. (2017). Power efficient and power attacks resistant system design and analysis using aggressive scaling with timing speculation. (Doctoral Dissertation). University of Derby. Retrieved from http://hdl.handle.net/10545/621716

Chicago Manual of Style (16th Edition):

Rathnala, Prasanthi. “Power efficient and power attacks resistant system design and analysis using aggressive scaling with timing speculation.” 2017. Doctoral Dissertation, University of Derby. Accessed August 10, 2020. http://hdl.handle.net/10545/621716.

MLA Handbook (7th Edition):

Rathnala, Prasanthi. “Power efficient and power attacks resistant system design and analysis using aggressive scaling with timing speculation.” 2017. Web. 10 Aug 2020.

Vancouver:

Rathnala P. Power efficient and power attacks resistant system design and analysis using aggressive scaling with timing speculation. [Internet] [Doctoral dissertation]. University of Derby; 2017. [cited 2020 Aug 10]. Available from: http://hdl.handle.net/10545/621716.

Council of Science Editors:

Rathnala P. Power efficient and power attacks resistant system design and analysis using aggressive scaling with timing speculation. [Doctoral Dissertation]. University of Derby; 2017. Available from: http://hdl.handle.net/10545/621716


University of Illinois – Urbana-Champaign

27. Tu, Jane. Continuous voltage-frequency scaling (CVFS).

Degree: MS, 1200, 2012, University of Illinois – Urbana-Champaign

 Voltage reduction is an effective technique for minimizing energy consumption but suffers from delay penalty. Conventional methodologies require rigorous voltage regulation and workload scheduling to… (more)

Subjects/Keywords: Minimum Energy Operation Point (MEOP); Dynamic Voltage Scaling (DVS); Compute Voltage Regulator Module (VRM); Continuous Voltage-Frequency Scaling (CVFS); Critical Path Replica (CPR)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tu, J. (2012). Continuous voltage-frequency scaling (CVFS). (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/34459

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tu, Jane. “Continuous voltage-frequency scaling (CVFS).” 2012. Thesis, University of Illinois – Urbana-Champaign. Accessed August 10, 2020. http://hdl.handle.net/2142/34459.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tu, Jane. “Continuous voltage-frequency scaling (CVFS).” 2012. Web. 10 Aug 2020.

Vancouver:

Tu J. Continuous voltage-frequency scaling (CVFS). [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2012. [cited 2020 Aug 10]. Available from: http://hdl.handle.net/2142/34459.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tu J. Continuous voltage-frequency scaling (CVFS). [Thesis]. University of Illinois – Urbana-Champaign; 2012. Available from: http://hdl.handle.net/2142/34459

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Georgia

28. Tangirala, Sairam. Computational study of polymer films using a Monte Carlo model of vapor deposition polymerization.

Degree: PhD, Physics, 2011, University of Georgia

 Polymer films are a subject of both technological importance and fundamental scientific interest. Very often polymer films are created under far-from-equilibrium conditions. Polymer film growth… (more)

Subjects/Keywords: Vapor deposition polymerization; Polymer films; Monte Carlo model; Stochastic processes; Growth models; Dynamic scaling analysis; Universality classes

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tangirala, S. (2011). Computational study of polymer films using a Monte Carlo model of vapor deposition polymerization. (Doctoral Dissertation). University of Georgia. Retrieved from http://purl.galileo.usg.edu/uga_etd/tangirala_sairam_201105_phd

Chicago Manual of Style (16th Edition):

Tangirala, Sairam. “Computational study of polymer films using a Monte Carlo model of vapor deposition polymerization.” 2011. Doctoral Dissertation, University of Georgia. Accessed August 10, 2020. http://purl.galileo.usg.edu/uga_etd/tangirala_sairam_201105_phd.

MLA Handbook (7th Edition):

Tangirala, Sairam. “Computational study of polymer films using a Monte Carlo model of vapor deposition polymerization.” 2011. Web. 10 Aug 2020.

Vancouver:

Tangirala S. Computational study of polymer films using a Monte Carlo model of vapor deposition polymerization. [Internet] [Doctoral dissertation]. University of Georgia; 2011. [cited 2020 Aug 10]. Available from: http://purl.galileo.usg.edu/uga_etd/tangirala_sairam_201105_phd.

Council of Science Editors:

Tangirala S. Computational study of polymer films using a Monte Carlo model of vapor deposition polymerization. [Doctoral Dissertation]. University of Georgia; 2011. Available from: http://purl.galileo.usg.edu/uga_etd/tangirala_sairam_201105_phd


UCLA

29. Conos, Nathaniel Alcala. Energy Minimization under Uncertainty using Coordinated Multi-phase Synthesis Techniques.

Degree: Computer Science, 2014, UCLA

 Energy minimization is one of the premiere design objectives in modern inte-grated circuits (ICs). Currently, there is a pressing need to reduce energy con-sumption in… (more)

Subjects/Keywords: Computer science; Computer engineering; Dynamic Voltage Scaling; Energy Minimization; Gate Sizing; Integrated Circuit Synthesis; Power Gating; Threshold Voltage Selection

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Conos, N. A. (2014). Energy Minimization under Uncertainty using Coordinated Multi-phase Synthesis Techniques. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/0m13d0wq

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Conos, Nathaniel Alcala. “Energy Minimization under Uncertainty using Coordinated Multi-phase Synthesis Techniques.” 2014. Thesis, UCLA. Accessed August 10, 2020. http://www.escholarship.org/uc/item/0m13d0wq.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Conos, Nathaniel Alcala. “Energy Minimization under Uncertainty using Coordinated Multi-phase Synthesis Techniques.” 2014. Web. 10 Aug 2020.

Vancouver:

Conos NA. Energy Minimization under Uncertainty using Coordinated Multi-phase Synthesis Techniques. [Internet] [Thesis]. UCLA; 2014. [cited 2020 Aug 10]. Available from: http://www.escholarship.org/uc/item/0m13d0wq.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Conos NA. Energy Minimization under Uncertainty using Coordinated Multi-phase Synthesis Techniques. [Thesis]. UCLA; 2014. Available from: http://www.escholarship.org/uc/item/0m13d0wq

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


RMIT University

30. Pradhan, R. Priority based energy efficient access networks.

Degree: 2013, RMIT University

 Information and Communication Technologies (ICT) enjoys a reputation as a green technology by reducing the cost of information and service delivery and promoting such activities… (more)

Subjects/Keywords: Fields of Research; Energy Efficient Ethernet; Dynamic Power Scaling; IEEE 802.3 az; Priority Queuing; Exponential Smoothing; Buffer based Power Management

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pradhan, R. (2013). Priority based energy efficient access networks. (Thesis). RMIT University. Retrieved from http://researchbank.rmit.edu.au/view/rmit:160492

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Pradhan, R. “Priority based energy efficient access networks.” 2013. Thesis, RMIT University. Accessed August 10, 2020. http://researchbank.rmit.edu.au/view/rmit:160492.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Pradhan, R. “Priority based energy efficient access networks.” 2013. Web. 10 Aug 2020.

Vancouver:

Pradhan R. Priority based energy efficient access networks. [Internet] [Thesis]. RMIT University; 2013. [cited 2020 Aug 10]. Available from: http://researchbank.rmit.edu.au/view/rmit:160492.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Pradhan R. Priority based energy efficient access networks. [Thesis]. RMIT University; 2013. Available from: http://researchbank.rmit.edu.au/view/rmit:160492

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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