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You searched for subject:(dynamic offset voltage cancellation). Showing records 1 – 30 of 16363 total matches.

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NSYSU

1. Huang, Hao-Chun. A Highly Sensitive Portable Microsystem for Rapid Marijuana Detection and A Peak Detector with Offset Cancellation.

Degree: Master, Electrical Engineering, 2018, NSYSU

 As early as in the 1960s, drugs abuse has long been a serious problem in the world.The most popular one is marijuana, where 160 million… (more)

Subjects/Keywords: peak detector; portable medical device; flexural plate wave microsonic sensor; resonant frequency shift; dynamic offset voltage cancellation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Huang, H. (2018). A Highly Sensitive Portable Microsystem for Rapid Marijuana Detection and A Peak Detector with Offset Cancellation. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0629118-213302

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Huang, Hao-Chun. “A Highly Sensitive Portable Microsystem for Rapid Marijuana Detection and A Peak Detector with Offset Cancellation.” 2018. Thesis, NSYSU. Accessed August 13, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0629118-213302.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Huang, Hao-Chun. “A Highly Sensitive Portable Microsystem for Rapid Marijuana Detection and A Peak Detector with Offset Cancellation.” 2018. Web. 13 Aug 2020.

Vancouver:

Huang H. A Highly Sensitive Portable Microsystem for Rapid Marijuana Detection and A Peak Detector with Offset Cancellation. [Internet] [Thesis]. NSYSU; 2018. [cited 2020 Aug 13]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0629118-213302.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Huang H. A Highly Sensitive Portable Microsystem for Rapid Marijuana Detection and A Peak Detector with Offset Cancellation. [Thesis]. NSYSU; 2018. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0629118-213302

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


The Ohio State University

2. Fragasse, Roman Augustus. A High-Speed Self-Timed SRAM with Offset Cancellation inthe IBM .13µm BiCMOS (8HP) Process.

Degree: MS, Electrical and Computer Engineering, 2018, The Ohio State University

 This thesis presents work on the design of a 10 Kb, 500 MHz, self-timed, static random-access memory (SRAM) in the IBM8HP 0.13µm BiCMOS process. A… (more)

Subjects/Keywords: Electrical Engineering; SRAM, High-Speed, IBM8HP, Input-Referred, Offset, Cancellation

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APA (6th Edition):

Fragasse, R. A. (2018). A High-Speed Self-Timed SRAM with Offset Cancellation inthe IBM .13µm BiCMOS (8HP) Process. (Masters Thesis). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1543570399314152

Chicago Manual of Style (16th Edition):

Fragasse, Roman Augustus. “A High-Speed Self-Timed SRAM with Offset Cancellation inthe IBM .13µm BiCMOS (8HP) Process.” 2018. Masters Thesis, The Ohio State University. Accessed August 13, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=osu1543570399314152.

MLA Handbook (7th Edition):

Fragasse, Roman Augustus. “A High-Speed Self-Timed SRAM with Offset Cancellation inthe IBM .13µm BiCMOS (8HP) Process.” 2018. Web. 13 Aug 2020.

Vancouver:

Fragasse RA. A High-Speed Self-Timed SRAM with Offset Cancellation inthe IBM .13µm BiCMOS (8HP) Process. [Internet] [Masters thesis]. The Ohio State University; 2018. [cited 2020 Aug 13]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1543570399314152.

Council of Science Editors:

Fragasse RA. A High-Speed Self-Timed SRAM with Offset Cancellation inthe IBM .13µm BiCMOS (8HP) Process. [Masters Thesis]. The Ohio State University; 2018. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1543570399314152

3. LI TI. Design and implementation of a high speed and low power flash ADC with fully dynamic comparators.

Degree: 2010, National University of Singapore

Subjects/Keywords: low power; flash ADC; fully dynamic comparators; background calibration; high speed; offset voltage

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APA (6th Edition):

TI, L. (2010). Design and implementation of a high speed and low power flash ADC with fully dynamic comparators. (Thesis). National University of Singapore. Retrieved from http://scholarbank.nus.edu.sg/handle/10635/23792

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

TI, LI. “Design and implementation of a high speed and low power flash ADC with fully dynamic comparators.” 2010. Thesis, National University of Singapore. Accessed August 13, 2020. http://scholarbank.nus.edu.sg/handle/10635/23792.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

TI, LI. “Design and implementation of a high speed and low power flash ADC with fully dynamic comparators.” 2010. Web. 13 Aug 2020.

Vancouver:

TI L. Design and implementation of a high speed and low power flash ADC with fully dynamic comparators. [Internet] [Thesis]. National University of Singapore; 2010. [cited 2020 Aug 13]. Available from: http://scholarbank.nus.edu.sg/handle/10635/23792.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

TI L. Design and implementation of a high speed and low power flash ADC with fully dynamic comparators. [Thesis]. National University of Singapore; 2010. Available from: http://scholarbank.nus.edu.sg/handle/10635/23792

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Waterloo

4. Shah, Jaspal Singh. Low-Power Soft-Error-Robust Embedded SRAM.

Degree: 2013, University of Waterloo

 Soft errors are radiation-induced ionization events (induced by energetic particles like alpha particles, cosmic neutron, etc.) that cause transient errors in integrated circuits. The circuit… (more)

Subjects/Keywords: VLSI; Embedded SRAM; Cache; Soft Error; Offset cancellation; Sense amplifier; Low Power

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APA (6th Edition):

Shah, J. S. (2013). Low-Power Soft-Error-Robust Embedded SRAM. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/7186

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shah, Jaspal Singh. “Low-Power Soft-Error-Robust Embedded SRAM.” 2013. Thesis, University of Waterloo. Accessed August 13, 2020. http://hdl.handle.net/10012/7186.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shah, Jaspal Singh. “Low-Power Soft-Error-Robust Embedded SRAM.” 2013. Web. 13 Aug 2020.

Vancouver:

Shah JS. Low-Power Soft-Error-Robust Embedded SRAM. [Internet] [Thesis]. University of Waterloo; 2013. [cited 2020 Aug 13]. Available from: http://hdl.handle.net/10012/7186.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shah JS. Low-Power Soft-Error-Robust Embedded SRAM. [Thesis]. University of Waterloo; 2013. Available from: http://hdl.handle.net/10012/7186

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

5. Πετούσης, Βλάσιος. Η ελάττωση της τάσης offset σε αισθητήρες ρεύματος βασισμένους στο φαινόμενο Hall.

Degree: 2011, University of Thessaly (UTH); Πανεπιστήμιο Θεσσαλίας

The research in this dissertation aims at finding a truly offset less silicon Hall plate. Only the magnetic field sensitive Hall effect is on interest… (more)

Subjects/Keywords: Τάση offset; Αισθητήρες ρεύματος Hall; Φαινόμενο Hall; Μέθοδοι μείωσης τάσης offset; Ανιχνευτές; Ηλεκτρονικά κυκλώματα; Offset voltage; Current hall effect sensors; Hall effect; Offset reduction methods

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APA (6th Edition):

Πετούσης, . . (2011). Η ελάττωση της τάσης offset σε αισθητήρες ρεύματος βασισμένους στο φαινόμενο Hall. (Thesis). University of Thessaly (UTH); Πανεπιστήμιο Θεσσαλίας. Retrieved from http://hdl.handle.net/10442/hedi/24648

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Πετούσης, Βλάσιος. “Η ελάττωση της τάσης offset σε αισθητήρες ρεύματος βασισμένους στο φαινόμενο Hall.” 2011. Thesis, University of Thessaly (UTH); Πανεπιστήμιο Θεσσαλίας. Accessed August 13, 2020. http://hdl.handle.net/10442/hedi/24648.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Πετούσης, Βλάσιος. “Η ελάττωση της τάσης offset σε αισθητήρες ρεύματος βασισμένους στο φαινόμενο Hall.” 2011. Web. 13 Aug 2020.

Vancouver:

Πετούσης . Η ελάττωση της τάσης offset σε αισθητήρες ρεύματος βασισμένους στο φαινόμενο Hall. [Internet] [Thesis]. University of Thessaly (UTH); Πανεπιστήμιο Θεσσαλίας; 2011. [cited 2020 Aug 13]. Available from: http://hdl.handle.net/10442/hedi/24648.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Πετούσης . Η ελάττωση της τάσης offset σε αισθητήρες ρεύματος βασισμένους στο φαινόμενο Hall. [Thesis]. University of Thessaly (UTH); Πανεπιστήμιο Θεσσαλίας; 2011. Available from: http://hdl.handle.net/10442/hedi/24648

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

6. Li, Pei-Hsun. An Improved ICI Self-Cancellation Scheme for Distributed MISO-OFDM Systems.

Degree: Master, Communications Engineering, 2011, NSYSU

 One of the challenges of distributed cooperative orthogonal frequency division multiplexing systems is that the multiple carrier frequency offsets (CFOs) simultaneously present at the receiver.… (more)

Subjects/Keywords: self-cancellation; maximum ratio combining (MRC); intercarrier interference (ICI); cooperative orthogonal frequency division multiplexing (OFDM); Carrier frequency offset (CFO)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Li, P. (2011). An Improved ICI Self-Cancellation Scheme for Distributed MISO-OFDM Systems. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0824111-124156

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Li, Pei-Hsun. “An Improved ICI Self-Cancellation Scheme for Distributed MISO-OFDM Systems.” 2011. Thesis, NSYSU. Accessed August 13, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0824111-124156.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Li, Pei-Hsun. “An Improved ICI Self-Cancellation Scheme for Distributed MISO-OFDM Systems.” 2011. Web. 13 Aug 2020.

Vancouver:

Li P. An Improved ICI Self-Cancellation Scheme for Distributed MISO-OFDM Systems. [Internet] [Thesis]. NSYSU; 2011. [cited 2020 Aug 13]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0824111-124156.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li P. An Improved ICI Self-Cancellation Scheme for Distributed MISO-OFDM Systems. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0824111-124156

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

7. Bábek, Tomáš. Automatizace měření Zenerových referencí: Meaurement process automatization of Zener reference.

Degree: 2019, Brno University of Technology

 This thesis deals with metrology specialized to DC voltage. In the begining of thesis is explanation of technical terms from metrology, summarization of units from… (more)

Subjects/Keywords: Metrologie; etalon; stejnosměrné napětí; reference; JVS; ZRS; skener; offset.; Metrology; standard; DC voltage; reference; JVS; ZRS; scanner; offset.

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APA (6th Edition):

Bábek, T. (2019). Automatizace měření Zenerových referencí: Meaurement process automatization of Zener reference. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/2000

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bábek, Tomáš. “Automatizace měření Zenerových referencí: Meaurement process automatization of Zener reference.” 2019. Thesis, Brno University of Technology. Accessed August 13, 2020. http://hdl.handle.net/11012/2000.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bábek, Tomáš. “Automatizace měření Zenerových referencí: Meaurement process automatization of Zener reference.” 2019. Web. 13 Aug 2020.

Vancouver:

Bábek T. Automatizace měření Zenerových referencí: Meaurement process automatization of Zener reference. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2020 Aug 13]. Available from: http://hdl.handle.net/11012/2000.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bábek T. Automatizace měření Zenerových referencí: Meaurement process automatization of Zener reference. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/2000

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Missouri – Columbia

8. Ghavrish, Artem. Prioritization of hospital orders considering cancellation probabilities.

Degree: 2012, University of Missouri – Columbia

 In a hospital laboratory premature cancellations of the test orders are driving up the laboratory running cost as they result in wasted resources and time.… (more)

Subjects/Keywords: order prioritization; cancellation probability; hospital laboratory; dynamic programming model

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APA (6th Edition):

Ghavrish, A. (2012). Prioritization of hospital orders considering cancellation probabilities. (Thesis). University of Missouri – Columbia. Retrieved from http://hdl.handle.net/10355/15948

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ghavrish, Artem. “Prioritization of hospital orders considering cancellation probabilities.” 2012. Thesis, University of Missouri – Columbia. Accessed August 13, 2020. http://hdl.handle.net/10355/15948.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ghavrish, Artem. “Prioritization of hospital orders considering cancellation probabilities.” 2012. Web. 13 Aug 2020.

Vancouver:

Ghavrish A. Prioritization of hospital orders considering cancellation probabilities. [Internet] [Thesis]. University of Missouri – Columbia; 2012. [cited 2020 Aug 13]. Available from: http://hdl.handle.net/10355/15948.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ghavrish A. Prioritization of hospital orders considering cancellation probabilities. [Thesis]. University of Missouri – Columbia; 2012. Available from: http://hdl.handle.net/10355/15948

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

9. Srinivasan, Venkatesh. Programmable Analog Techniques For Precision Analog Circuits, Low-Power Signal Processing and On-Chip Learning.

Degree: PhD, Electrical and Computer Engineering, 2006, Georgia Tech

 In this work, programmable analog techniques using floating-gate transistors have been developed to design precision analog circuits, low-power signal processing primitives and adaptive systems that… (more)

Subjects/Keywords: Programmable multipliers; Adaptive filters; Voltage references; Offset cancellation; Floating-gate transistors; Synapse; Neural networks (Computer science); Signal processing; Adaptive signal processing; Electronic analog computers Circuits; Gate array circuits

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APA (6th Edition):

Srinivasan, V. (2006). Programmable Analog Techniques For Precision Analog Circuits, Low-Power Signal Processing and On-Chip Learning. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/11588

Chicago Manual of Style (16th Edition):

Srinivasan, Venkatesh. “Programmable Analog Techniques For Precision Analog Circuits, Low-Power Signal Processing and On-Chip Learning.” 2006. Doctoral Dissertation, Georgia Tech. Accessed August 13, 2020. http://hdl.handle.net/1853/11588.

MLA Handbook (7th Edition):

Srinivasan, Venkatesh. “Programmable Analog Techniques For Precision Analog Circuits, Low-Power Signal Processing and On-Chip Learning.” 2006. Web. 13 Aug 2020.

Vancouver:

Srinivasan V. Programmable Analog Techniques For Precision Analog Circuits, Low-Power Signal Processing and On-Chip Learning. [Internet] [Doctoral dissertation]. Georgia Tech; 2006. [cited 2020 Aug 13]. Available from: http://hdl.handle.net/1853/11588.

Council of Science Editors:

Srinivasan V. Programmable Analog Techniques For Precision Analog Circuits, Low-Power Signal Processing and On-Chip Learning. [Doctoral Dissertation]. Georgia Tech; 2006. Available from: http://hdl.handle.net/1853/11588

10. Zhang, R. (author). A 1-Mega Pixels HDR and UV Sensitive Image Sensor With Interleaved 14-bit 64Ms/s SAR ADC.

Degree: 2015, Delft University of Technology

This thesis presents a 1-Mega pixels high-dynamic range and UV sensitive image sensor in 0.18 µm technology with 14-bit interleaved 64Ms/s SAR ADC. It can… (more)

Subjects/Keywords: UV sensitive; interleaved SAR ADC; comparator; offset calibration; high dynamic range

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APA (6th Edition):

Zhang, R. (. (2015). A 1-Mega Pixels HDR and UV Sensitive Image Sensor With Interleaved 14-bit 64Ms/s SAR ADC. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:26cd1922-1ecc-4f7e-b8bc-46c5c00f8846

Chicago Manual of Style (16th Edition):

Zhang, R (author). “A 1-Mega Pixels HDR and UV Sensitive Image Sensor With Interleaved 14-bit 64Ms/s SAR ADC.” 2015. Masters Thesis, Delft University of Technology. Accessed August 13, 2020. http://resolver.tudelft.nl/uuid:26cd1922-1ecc-4f7e-b8bc-46c5c00f8846.

MLA Handbook (7th Edition):

Zhang, R (author). “A 1-Mega Pixels HDR and UV Sensitive Image Sensor With Interleaved 14-bit 64Ms/s SAR ADC.” 2015. Web. 13 Aug 2020.

Vancouver:

Zhang R(. A 1-Mega Pixels HDR and UV Sensitive Image Sensor With Interleaved 14-bit 64Ms/s SAR ADC. [Internet] [Masters thesis]. Delft University of Technology; 2015. [cited 2020 Aug 13]. Available from: http://resolver.tudelft.nl/uuid:26cd1922-1ecc-4f7e-b8bc-46c5c00f8846.

Council of Science Editors:

Zhang R(. A 1-Mega Pixels HDR and UV Sensitive Image Sensor With Interleaved 14-bit 64Ms/s SAR ADC. [Masters Thesis]. Delft University of Technology; 2015. Available from: http://resolver.tudelft.nl/uuid:26cd1922-1ecc-4f7e-b8bc-46c5c00f8846


California State University – Sacramento

11. Martin, Nicholas Thomas. Fault diagnosis and comparator redesign for an 8-bit 20ms/s calibrated pipelined analog-to-digital converter in 0.5um CMOS.

Degree: MS, Electrical and Electronic Engineering, 2011, California State University – Sacramento

 This project is a fault diagnosis and redesign effort for an 8-bit 20-MS/s pipelined analog-to-digital converter designed and fabricated in a 0.5??m CMOS process technology.… (more)

Subjects/Keywords: Swing minimizing circuit; Dynamic offset test bench; Preamplifier

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APA (6th Edition):

Martin, N. T. (2011). Fault diagnosis and comparator redesign for an 8-bit 20ms/s calibrated pipelined analog-to-digital converter in 0.5um CMOS. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.9/1346

Chicago Manual of Style (16th Edition):

Martin, Nicholas Thomas. “Fault diagnosis and comparator redesign for an 8-bit 20ms/s calibrated pipelined analog-to-digital converter in 0.5um CMOS.” 2011. Masters Thesis, California State University – Sacramento. Accessed August 13, 2020. http://hdl.handle.net/10211.9/1346.

MLA Handbook (7th Edition):

Martin, Nicholas Thomas. “Fault diagnosis and comparator redesign for an 8-bit 20ms/s calibrated pipelined analog-to-digital converter in 0.5um CMOS.” 2011. Web. 13 Aug 2020.

Vancouver:

Martin NT. Fault diagnosis and comparator redesign for an 8-bit 20ms/s calibrated pipelined analog-to-digital converter in 0.5um CMOS. [Internet] [Masters thesis]. California State University – Sacramento; 2011. [cited 2020 Aug 13]. Available from: http://hdl.handle.net/10211.9/1346.

Council of Science Editors:

Martin NT. Fault diagnosis and comparator redesign for an 8-bit 20ms/s calibrated pipelined analog-to-digital converter in 0.5um CMOS. [Masters Thesis]. California State University – Sacramento; 2011. Available from: http://hdl.handle.net/10211.9/1346


University of Akron

12. Naini, Srikar Reddy. PING-PONG AUTO-ZERO AMPLIFIER WITH RAIL-TO-RAIL OUTPUT BUFFER.

Degree: MS, Electrical Engineering, 2018, University of Akron

 This work presents a ping-pong auto-zero amplifier for precision sensor applications. The transistor level circuit design of the amplifier building blocks including the transconductance stage… (more)

Subjects/Keywords: Electrical Engineering; Auto-zero, Ping-Pong Auto-zero amplifier, DC Offset voltage, Noise

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APA (6th Edition):

Naini, S. R. (2018). PING-PONG AUTO-ZERO AMPLIFIER WITH RAIL-TO-RAIL OUTPUT BUFFER. (Masters Thesis). University of Akron. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=akron1537224512595497

Chicago Manual of Style (16th Edition):

Naini, Srikar Reddy. “PING-PONG AUTO-ZERO AMPLIFIER WITH RAIL-TO-RAIL OUTPUT BUFFER.” 2018. Masters Thesis, University of Akron. Accessed August 13, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=akron1537224512595497.

MLA Handbook (7th Edition):

Naini, Srikar Reddy. “PING-PONG AUTO-ZERO AMPLIFIER WITH RAIL-TO-RAIL OUTPUT BUFFER.” 2018. Web. 13 Aug 2020.

Vancouver:

Naini SR. PING-PONG AUTO-ZERO AMPLIFIER WITH RAIL-TO-RAIL OUTPUT BUFFER. [Internet] [Masters thesis]. University of Akron; 2018. [cited 2020 Aug 13]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=akron1537224512595497.

Council of Science Editors:

Naini SR. PING-PONG AUTO-ZERO AMPLIFIER WITH RAIL-TO-RAIL OUTPUT BUFFER. [Masters Thesis]. University of Akron; 2018. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=akron1537224512595497


California State University – Sacramento

13. Pham, Hao Qui. Intergration of a dynamic offset testbench to measure comparator offsets in 0.18um CMOS.

Degree: MS, Electrical and Electronic Engineering, 2020, California State University – Sacramento

 High-speed latching comparators are important building blocks in analog and mixed-signal integrated circuits (ICs) such as analog-to-digital converters. A key performance parameter of these comparators… (more)

Subjects/Keywords: Input referred offset voltage of comparator; Top-level DOTB design and simulations; Fully-differential DOTB

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APA (6th Edition):

Pham, H. Q. (2020). Intergration of a dynamic offset testbench to measure comparator offsets in 0.18um CMOS. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.3/216894

Chicago Manual of Style (16th Edition):

Pham, Hao Qui. “Intergration of a dynamic offset testbench to measure comparator offsets in 0.18um CMOS.” 2020. Masters Thesis, California State University – Sacramento. Accessed August 13, 2020. http://hdl.handle.net/10211.3/216894.

MLA Handbook (7th Edition):

Pham, Hao Qui. “Intergration of a dynamic offset testbench to measure comparator offsets in 0.18um CMOS.” 2020. Web. 13 Aug 2020.

Vancouver:

Pham HQ. Intergration of a dynamic offset testbench to measure comparator offsets in 0.18um CMOS. [Internet] [Masters thesis]. California State University – Sacramento; 2020. [cited 2020 Aug 13]. Available from: http://hdl.handle.net/10211.3/216894.

Council of Science Editors:

Pham HQ. Intergration of a dynamic offset testbench to measure comparator offsets in 0.18um CMOS. [Masters Thesis]. California State University – Sacramento; 2020. Available from: http://hdl.handle.net/10211.3/216894


Anna University

14. Abdul rahman S. Mitigation of voltage sag and swell using direct converters;.

Degree: Mitigation of voltage sag and swell using direct converters, 2015, Anna University

The power quality gets degraded due to the disturbances, occurring in the transmission as well as in the distribution sides Flexible AC Transmission System devices… (more)

Subjects/Keywords: Custom Power System; Dynamic voltage restorers

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APA (6th Edition):

S, A. r. (2015). Mitigation of voltage sag and swell using direct converters;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/33162

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

S, Abdul rahman. “Mitigation of voltage sag and swell using direct converters;.” 2015. Thesis, Anna University. Accessed August 13, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/33162.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

S, Abdul rahman. “Mitigation of voltage sag and swell using direct converters;.” 2015. Web. 13 Aug 2020.

Vancouver:

S Ar. Mitigation of voltage sag and swell using direct converters;. [Internet] [Thesis]. Anna University; 2015. [cited 2020 Aug 13]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/33162.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

S Ar. Mitigation of voltage sag and swell using direct converters;. [Thesis]. Anna University; 2015. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/33162

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Oregon State University

15. Patwary, Md. Ataur R. Low-power dynamic CMOS circuits in high-performance memory arrays.

Degree: PhD, Electrical and Computer Engineering, 2009, Oregon State University

Dynamic CMOS circuits are commonly used in high-performance memory arrays to implement wide-NOR logic functions for their read and search operations. This is because dynamic(more)

Subjects/Keywords: Dynamic circuits; Low voltage integrated circuits

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APA (6th Edition):

Patwary, M. A. R. (2009). Low-power dynamic CMOS circuits in high-performance memory arrays. (Doctoral Dissertation). Oregon State University. Retrieved from http://hdl.handle.net/1957/10906

Chicago Manual of Style (16th Edition):

Patwary, Md Ataur R. “Low-power dynamic CMOS circuits in high-performance memory arrays.” 2009. Doctoral Dissertation, Oregon State University. Accessed August 13, 2020. http://hdl.handle.net/1957/10906.

MLA Handbook (7th Edition):

Patwary, Md Ataur R. “Low-power dynamic CMOS circuits in high-performance memory arrays.” 2009. Web. 13 Aug 2020.

Vancouver:

Patwary MAR. Low-power dynamic CMOS circuits in high-performance memory arrays. [Internet] [Doctoral dissertation]. Oregon State University; 2009. [cited 2020 Aug 13]. Available from: http://hdl.handle.net/1957/10906.

Council of Science Editors:

Patwary MAR. Low-power dynamic CMOS circuits in high-performance memory arrays. [Doctoral Dissertation]. Oregon State University; 2009. Available from: http://hdl.handle.net/1957/10906


University of New South Wales

16. Tariq, Umair. Energy-Aware Task Scheduling with Conditional Precedence Constraints on MPSoCs.

Degree: Computer Science & Engineering, 2018, University of New South Wales

 In order to extract maximum performance out of MPSoCs (Multiprocessor System on- Chips), efficientscheduling is crucial. In embedded systems, one of the major design goals… (more)

Subjects/Keywords: Mapping; Power Optimization; Dynamic Voltage Scaling; Scheduling

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APA (6th Edition):

Tariq, U. (2018). Energy-Aware Task Scheduling with Conditional Precedence Constraints on MPSoCs. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/60342 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51870/SOURCE02?view=true

Chicago Manual of Style (16th Edition):

Tariq, Umair. “Energy-Aware Task Scheduling with Conditional Precedence Constraints on MPSoCs.” 2018. Doctoral Dissertation, University of New South Wales. Accessed August 13, 2020. http://handle.unsw.edu.au/1959.4/60342 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51870/SOURCE02?view=true.

MLA Handbook (7th Edition):

Tariq, Umair. “Energy-Aware Task Scheduling with Conditional Precedence Constraints on MPSoCs.” 2018. Web. 13 Aug 2020.

Vancouver:

Tariq U. Energy-Aware Task Scheduling with Conditional Precedence Constraints on MPSoCs. [Internet] [Doctoral dissertation]. University of New South Wales; 2018. [cited 2020 Aug 13]. Available from: http://handle.unsw.edu.au/1959.4/60342 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51870/SOURCE02?view=true.

Council of Science Editors:

Tariq U. Energy-Aware Task Scheduling with Conditional Precedence Constraints on MPSoCs. [Doctoral Dissertation]. University of New South Wales; 2018. Available from: http://handle.unsw.edu.au/1959.4/60342 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51870/SOURCE02?view=true


University of KwaZulu-Natal

17. Ogunboyo, Patrick Taiwo. Power quality enhancement in secondary electric power distr[i]bution networks using dynamic voltage restorer.

Degree: 2018, University of KwaZulu-Natal

 This research study investigates and proposes an effective and efficient method for improving voltage profile and mitigating unbalance voltage, voltage variation disturbances in rural and… (more)

Subjects/Keywords: Voltage profile.; Power quality.; Electric power.; Distribution networks.; Dynamic voltage restorer.

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APA (6th Edition):

Ogunboyo, P. T. (2018). Power quality enhancement in secondary electric power distr[i]bution networks using dynamic voltage restorer. (Thesis). University of KwaZulu-Natal. Retrieved from https://researchspace.ukzn.ac.za/handle/10413/17104

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ogunboyo, Patrick Taiwo. “Power quality enhancement in secondary electric power distr[i]bution networks using dynamic voltage restorer.” 2018. Thesis, University of KwaZulu-Natal. Accessed August 13, 2020. https://researchspace.ukzn.ac.za/handle/10413/17104.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ogunboyo, Patrick Taiwo. “Power quality enhancement in secondary electric power distr[i]bution networks using dynamic voltage restorer.” 2018. Web. 13 Aug 2020.

Vancouver:

Ogunboyo PT. Power quality enhancement in secondary electric power distr[i]bution networks using dynamic voltage restorer. [Internet] [Thesis]. University of KwaZulu-Natal; 2018. [cited 2020 Aug 13]. Available from: https://researchspace.ukzn.ac.za/handle/10413/17104.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ogunboyo PT. Power quality enhancement in secondary electric power distr[i]bution networks using dynamic voltage restorer. [Thesis]. University of KwaZulu-Natal; 2018. Available from: https://researchspace.ukzn.ac.za/handle/10413/17104

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Anna University

18. Usha Rani P. Power quality improvement using dynamic voltage restorer and interline power flow controller.

Degree: Electrical and Electronics, 2011, Anna University

This work deals with power quality improvement using Dynamic Voltage Restorer (DVR) and Interline Power Flow Controller (IPFC) systems. The Dynamic Voltage Restorer as a… (more)

Subjects/Keywords: Dynamic Voltage Restorer; Dynamic voltage restorer; Interline Power Flow Controllerx; Interline Power Flow Controller; MATLAB

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APA (6th Edition):

P, U. R. (2011). Power quality improvement using dynamic voltage restorer and interline power flow controller. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/9826

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

P, Usha Rani. “Power quality improvement using dynamic voltage restorer and interline power flow controller.” 2011. Thesis, Anna University. Accessed August 13, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/9826.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

P, Usha Rani. “Power quality improvement using dynamic voltage restorer and interline power flow controller.” 2011. Web. 13 Aug 2020.

Vancouver:

P UR. Power quality improvement using dynamic voltage restorer and interline power flow controller. [Internet] [Thesis]. Anna University; 2011. [cited 2020 Aug 13]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/9826.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

P UR. Power quality improvement using dynamic voltage restorer and interline power flow controller. [Thesis]. Anna University; 2011. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/9826

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

19. Saxena, Sanchit. Exploration of Cancellation Strategies for Parallel Simulation on Multi-Core Beowulf Clusters.

Degree: MS, Engineering and Applied Science: Computer Engineering, 2012, University of Cincinnati

  A time warp synchronized distributed simulation organizes a discrete event simulation into concurrently executing Logical Processes (LPs) that use a rollback recover mechanism whenever… (more)

Subjects/Keywords: Computer Engineering; PDES; Cancellation Strategies; Anti-Messages; Aggressive Cancellation; Dynamic Cancellation; Lazy Cancellation

…of an LP [22]. This algorithm is called dynamic cancellation. The work of this… …WARPED. Chapter 8 details the implementation details of dynamic cancellation algorithm for… …Threaded WARPED. It also presents the basic operation of dynamic cancellation. Chapter 9 analyzes… …dynamic cancellation algorithm as future work. 3 Chapter 2 Background The concepts of… …use of lazy and anti-message queues used by lazy/dynamic cancellation techniques… 

Page 1 Page 2 Page 3 Page 4 Page 5 Page 6 Page 7

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APA (6th Edition):

Saxena, S. (2012). Exploration of Cancellation Strategies for Parallel Simulation on Multi-Core Beowulf Clusters. (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1352403477

Chicago Manual of Style (16th Edition):

Saxena, Sanchit. “Exploration of Cancellation Strategies for Parallel Simulation on Multi-Core Beowulf Clusters.” 2012. Masters Thesis, University of Cincinnati. Accessed August 13, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1352403477.

MLA Handbook (7th Edition):

Saxena, Sanchit. “Exploration of Cancellation Strategies for Parallel Simulation on Multi-Core Beowulf Clusters.” 2012. Web. 13 Aug 2020.

Vancouver:

Saxena S. Exploration of Cancellation Strategies for Parallel Simulation on Multi-Core Beowulf Clusters. [Internet] [Masters thesis]. University of Cincinnati; 2012. [cited 2020 Aug 13]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1352403477.

Council of Science Editors:

Saxena S. Exploration of Cancellation Strategies for Parallel Simulation on Multi-Core Beowulf Clusters. [Masters Thesis]. University of Cincinnati; 2012. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1352403477


NSYSU

20. Ye, Hua-Cheng. Performance Analysis of Novel MC-CDMA Uplink with Multiple Carrier Frequency Offsets.

Degree: Master, Communications Engineering, 2015, NSYSU

 Multi-carrier code division multiple access (MC-CDMA) systems experience serious multiple access interference (MAI) in uplink transmission because the orthogonality among codes is destroyed by the… (more)

Subjects/Keywords: multi carrier-code division multiple access (MC-CDMA); carrier frequency offset (CFO); successive interference cancellation (SIC); multiple access interference (MAI); Gaussian integer perfect sequence (GIPS)

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APA (6th Edition):

Ye, H. (2015). Performance Analysis of Novel MC-CDMA Uplink with Multiple Carrier Frequency Offsets. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-104105

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ye, Hua-Cheng. “Performance Analysis of Novel MC-CDMA Uplink with Multiple Carrier Frequency Offsets.” 2015. Thesis, NSYSU. Accessed August 13, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-104105.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ye, Hua-Cheng. “Performance Analysis of Novel MC-CDMA Uplink with Multiple Carrier Frequency Offsets.” 2015. Web. 13 Aug 2020.

Vancouver:

Ye H. Performance Analysis of Novel MC-CDMA Uplink with Multiple Carrier Frequency Offsets. [Internet] [Thesis]. NSYSU; 2015. [cited 2020 Aug 13]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-104105.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ye H. Performance Analysis of Novel MC-CDMA Uplink with Multiple Carrier Frequency Offsets. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0808115-104105

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

21. Tanu, Tanu. High sensitivity nanotechnology gas sensing device.

Degree: 2016, IUPUI

Indiana University-Purdue University Indianapolis (IUPUI)

The nanotechnology materials have been used for high sensitivity sensing devices due to their ability to alter their properties in… (more)

Subjects/Keywords: gas sensor; nanoparticles; IoT; Graphene; offset cancellation; embedded

Dynamic o↵set cancellation circuit . . . . . . . . . . . . . . . . . . . . 41 5.8 Non… …8.4 Dynamics of charge carriers when negative voltage is applied . . . . . . 64 8.5… …Dynamics of charge carriers when positive voltage is applied . . . . . . 65 8.6 The FET… …di↵erent CO2 concentrations . . . 73 8.14 Dynamic characteristics of sensor in resistive… …the sensing unit is received by an o↵set cancellation amplifying system using a system on… 

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APA (6th Edition):

Tanu, T. (2016). High sensitivity nanotechnology gas sensing device. (Thesis). IUPUI. Retrieved from http://hdl.handle.net/1805/11831

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tanu, Tanu. “High sensitivity nanotechnology gas sensing device.” 2016. Thesis, IUPUI. Accessed August 13, 2020. http://hdl.handle.net/1805/11831.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tanu, Tanu. “High sensitivity nanotechnology gas sensing device.” 2016. Web. 13 Aug 2020.

Vancouver:

Tanu T. High sensitivity nanotechnology gas sensing device. [Internet] [Thesis]. IUPUI; 2016. [cited 2020 Aug 13]. Available from: http://hdl.handle.net/1805/11831.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tanu T. High sensitivity nanotechnology gas sensing device. [Thesis]. IUPUI; 2016. Available from: http://hdl.handle.net/1805/11831

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

22. Nasrollahpour, Mehdi. Time-based, Low-power, Low-offset 5-bit 1 GS/s Flash ADC Design in 65nm CMOS Technology.

Degree: MS, Electrical Engineering, 2017, San Jose State University

  Low-power, medium resolution, high-speed analog-to-digital converters (ADCs) have always been important block which have abundant applications such as digital signal processors (DSP), imaging sensors,… (more)

Subjects/Keywords: Flash ADC; High-speed; Low-offset; Low-power; Offset cancellation; Time-based ADC

…Input offset cancellation The offset voltage of latched comparators can be omitted with the… …11 Fig. 3.2 Output series offset cancellation… …14 Fig. 3.3 Input offset cancellation… …14 Fig. 3.4 Auto-zeroing technique offset cancellation… …low power consumption, while also employing an offset cancellation technique in order to… 

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APA (6th Edition):

Nasrollahpour, M. (2017). Time-based, Low-power, Low-offset 5-bit 1 GS/s Flash ADC Design in 65nm CMOS Technology. (Masters Thesis). San Jose State University. Retrieved from https://doi.org/10.31979/etd.6wsv-p773 ; https://scholarworks.sjsu.edu/etd_theses/4853

Chicago Manual of Style (16th Edition):

Nasrollahpour, Mehdi. “Time-based, Low-power, Low-offset 5-bit 1 GS/s Flash ADC Design in 65nm CMOS Technology.” 2017. Masters Thesis, San Jose State University. Accessed August 13, 2020. https://doi.org/10.31979/etd.6wsv-p773 ; https://scholarworks.sjsu.edu/etd_theses/4853.

MLA Handbook (7th Edition):

Nasrollahpour, Mehdi. “Time-based, Low-power, Low-offset 5-bit 1 GS/s Flash ADC Design in 65nm CMOS Technology.” 2017. Web. 13 Aug 2020.

Vancouver:

Nasrollahpour M. Time-based, Low-power, Low-offset 5-bit 1 GS/s Flash ADC Design in 65nm CMOS Technology. [Internet] [Masters thesis]. San Jose State University; 2017. [cited 2020 Aug 13]. Available from: https://doi.org/10.31979/etd.6wsv-p773 ; https://scholarworks.sjsu.edu/etd_theses/4853.

Council of Science Editors:

Nasrollahpour M. Time-based, Low-power, Low-offset 5-bit 1 GS/s Flash ADC Design in 65nm CMOS Technology. [Masters Thesis]. San Jose State University; 2017. Available from: https://doi.org/10.31979/etd.6wsv-p773 ; https://scholarworks.sjsu.edu/etd_theses/4853


University of Illinois – Urbana-Champaign

23. Kim, Katherine A. Voltage-Offset Resistive Control for Photovoltaics.

Degree: MS, 1200, 2012, University of Illinois – Urbana-Champaign

 This thesis introduces voltage-offset resistive control (VRC) for photovoltaic (PV) applications that exhibits low sensitivity to solar irradiance changes. Although there are numerous control schemes… (more)

Subjects/Keywords: voltage-offset resistive control; photovoltaics; power electronics; dc-dc converter control; maximum power point tracking; irradiance sensitivity; direct current (dc)

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APA (6th Edition):

Kim, K. A. (2012). Voltage-Offset Resistive Control for Photovoltaics. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/29691

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kim, Katherine A. “Voltage-Offset Resistive Control for Photovoltaics.” 2012. Thesis, University of Illinois – Urbana-Champaign. Accessed August 13, 2020. http://hdl.handle.net/2142/29691.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kim, Katherine A. “Voltage-Offset Resistive Control for Photovoltaics.” 2012. Web. 13 Aug 2020.

Vancouver:

Kim KA. Voltage-Offset Resistive Control for Photovoltaics. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2012. [cited 2020 Aug 13]. Available from: http://hdl.handle.net/2142/29691.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kim KA. Voltage-Offset Resistive Control for Photovoltaics. [Thesis]. University of Illinois – Urbana-Champaign; 2012. Available from: http://hdl.handle.net/2142/29691

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

24. Zhou, Yong. A New High Power Density Modular Multilevel DC-DC Converter with Localized Voltage Balancing Control for Arbitrary Number of Levels.

Degree: MS, Electrical Engineering, 2016, Texas A&M University

 A new modular multilevel DC-DC converter (MMC) with high power density and simplified localized voltage balancing control is proposed. Converter building block and controller module… (more)

Subjects/Keywords: Modular Multilevel Converter (MMC); DC-DC; high power density; localized control; voltage balancing; converter building block; controller module; integrated H- bridge; mutual coupled inductor; current cancellation; voltage ripple reduction

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APA (6th Edition):

Zhou, Y. (2016). A New High Power Density Modular Multilevel DC-DC Converter with Localized Voltage Balancing Control for Arbitrary Number of Levels. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/156913

Chicago Manual of Style (16th Edition):

Zhou, Yong. “A New High Power Density Modular Multilevel DC-DC Converter with Localized Voltage Balancing Control for Arbitrary Number of Levels.” 2016. Masters Thesis, Texas A&M University. Accessed August 13, 2020. http://hdl.handle.net/1969.1/156913.

MLA Handbook (7th Edition):

Zhou, Yong. “A New High Power Density Modular Multilevel DC-DC Converter with Localized Voltage Balancing Control for Arbitrary Number of Levels.” 2016. Web. 13 Aug 2020.

Vancouver:

Zhou Y. A New High Power Density Modular Multilevel DC-DC Converter with Localized Voltage Balancing Control for Arbitrary Number of Levels. [Internet] [Masters thesis]. Texas A&M University; 2016. [cited 2020 Aug 13]. Available from: http://hdl.handle.net/1969.1/156913.

Council of Science Editors:

Zhou Y. A New High Power Density Modular Multilevel DC-DC Converter with Localized Voltage Balancing Control for Arbitrary Number of Levels. [Masters Thesis]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/156913

25. Park, Junyoung. Self-tuning dynamic voltage scaling techniques for processor design.

Degree: PhD, Electrical and Computer Engineering, 2013, University of Texas – Austin

 The Dynamic Voltage Scaling (DVS) technique has proven to be ideal in regard to balancing performance and energy consumption of a processor since it allows… (more)

Subjects/Keywords: Dynamic voltage scaling; Dynamic voltage scaled processor; Adaptive voltage scaling; Adaptive voltage scaled processor; Critical path monitor; Critical path replica; Path slope; Critical paths; Energy delay product

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APA (6th Edition):

Park, J. (2013). Self-tuning dynamic voltage scaling techniques for processor design. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/22989

Chicago Manual of Style (16th Edition):

Park, Junyoung. “Self-tuning dynamic voltage scaling techniques for processor design.” 2013. Doctoral Dissertation, University of Texas – Austin. Accessed August 13, 2020. http://hdl.handle.net/2152/22989.

MLA Handbook (7th Edition):

Park, Junyoung. “Self-tuning dynamic voltage scaling techniques for processor design.” 2013. Web. 13 Aug 2020.

Vancouver:

Park J. Self-tuning dynamic voltage scaling techniques for processor design. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2013. [cited 2020 Aug 13]. Available from: http://hdl.handle.net/2152/22989.

Council of Science Editors:

Park J. Self-tuning dynamic voltage scaling techniques for processor design. [Doctoral Dissertation]. University of Texas – Austin; 2013. Available from: http://hdl.handle.net/2152/22989


University of New Orleans

26. Beeravolu, Nagendrakumar. Predicting Voltage Abnormality Using Power System Dynamics.

Degree: PhD, Electrical Engineering, 2013, University of New Orleans

  The purpose of this dissertation is to analyze dynamic behavior of a stressed power system and to correlate the dynamic responses to a near… (more)

Subjects/Keywords: Pattern recognition; Power system dynamic response; Blackouts; Voltage stability; Voltage collapse; Power and Energy

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APA (6th Edition):

Beeravolu, N. (2013). Predicting Voltage Abnormality Using Power System Dynamics. (Doctoral Dissertation). University of New Orleans. Retrieved from https://scholarworks.uno.edu/td/1722

Chicago Manual of Style (16th Edition):

Beeravolu, Nagendrakumar. “Predicting Voltage Abnormality Using Power System Dynamics.” 2013. Doctoral Dissertation, University of New Orleans. Accessed August 13, 2020. https://scholarworks.uno.edu/td/1722.

MLA Handbook (7th Edition):

Beeravolu, Nagendrakumar. “Predicting Voltage Abnormality Using Power System Dynamics.” 2013. Web. 13 Aug 2020.

Vancouver:

Beeravolu N. Predicting Voltage Abnormality Using Power System Dynamics. [Internet] [Doctoral dissertation]. University of New Orleans; 2013. [cited 2020 Aug 13]. Available from: https://scholarworks.uno.edu/td/1722.

Council of Science Editors:

Beeravolu N. Predicting Voltage Abnormality Using Power System Dynamics. [Doctoral Dissertation]. University of New Orleans; 2013. Available from: https://scholarworks.uno.edu/td/1722

27. Khazane, Nitish Kumar. Design of a comparator and an integrator for a dynamic offset testbench in 0.18??m CMOS.

Degree: MS, Electrical and Electronic Engineering, 2019, California State University – Sacramento

 This report describes the operation, design, and simulation of a comparator and an integrator for a Dynamic Offset Test Bench (DOTB) in 0.18??m CMOS. The… (more)

Subjects/Keywords: DOTB; Comparator; Integrator; Input-Referred Offset; Dynamic Offset Testbench; CMOS

…comparator. This shift is referred to as the input-referred offset voltage, or V​OS , of the… …and time consuming. To address these problems, a Dynamic Offset Test Bench (DOTB)… …offset voltage, V​OS​. As a result there is a practical need to analyze these offsets during… …the Dynamic Offset Testbench (DOTB) can be used to determine the input-referred… …offset voltage of a latching comparator, as shown in Figure 1 [7]. In this conceptual… 

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APA (6th Edition):

Khazane, N. K. (2019). Design of a comparator and an integrator for a dynamic offset testbench in 0.18??m CMOS. (Masters Thesis). California State University – Sacramento. Retrieved from http://hdl.handle.net/10211.3/207783

Chicago Manual of Style (16th Edition):

Khazane, Nitish Kumar. “Design of a comparator and an integrator for a dynamic offset testbench in 0.18??m CMOS.” 2019. Masters Thesis, California State University – Sacramento. Accessed August 13, 2020. http://hdl.handle.net/10211.3/207783.

MLA Handbook (7th Edition):

Khazane, Nitish Kumar. “Design of a comparator and an integrator for a dynamic offset testbench in 0.18??m CMOS.” 2019. Web. 13 Aug 2020.

Vancouver:

Khazane NK. Design of a comparator and an integrator for a dynamic offset testbench in 0.18??m CMOS. [Internet] [Masters thesis]. California State University – Sacramento; 2019. [cited 2020 Aug 13]. Available from: http://hdl.handle.net/10211.3/207783.

Council of Science Editors:

Khazane NK. Design of a comparator and an integrator for a dynamic offset testbench in 0.18??m CMOS. [Masters Thesis]. California State University – Sacramento; 2019. Available from: http://hdl.handle.net/10211.3/207783


NSYSU

28. Lin, Chih-peng. A Study on Wind Turbine Low Voltage Ride Through Capability Enhancement by STATCOM and DVR.

Degree: Master, Electrical Engineering, 2010, NSYSU

 When more induction generator based wind farms are integrated into the power system, the system voltage dips and stability problems may arise due to the… (more)

Subjects/Keywords: Static Synchronous Compensator; Wind Farm; Low Voltage Ride-Through Capability; Induction Wind Generator; Dynamic Voltage Restorer; Voltage Tolerance Curve

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APA (6th Edition):

Lin, C. (2010). A Study on Wind Turbine Low Voltage Ride Through Capability Enhancement by STATCOM and DVR. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0205110-173448

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lin, Chih-peng. “A Study on Wind Turbine Low Voltage Ride Through Capability Enhancement by STATCOM and DVR.” 2010. Thesis, NSYSU. Accessed August 13, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0205110-173448.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lin, Chih-peng. “A Study on Wind Turbine Low Voltage Ride Through Capability Enhancement by STATCOM and DVR.” 2010. Web. 13 Aug 2020.

Vancouver:

Lin C. A Study on Wind Turbine Low Voltage Ride Through Capability Enhancement by STATCOM and DVR. [Internet] [Thesis]. NSYSU; 2010. [cited 2020 Aug 13]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0205110-173448.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lin C. A Study on Wind Turbine Low Voltage Ride Through Capability Enhancement by STATCOM and DVR. [Thesis]. NSYSU; 2010. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0205110-173448

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

29. Lee, Cyuan-min. Series Voltage Regulator Based On Dual Mode Full Bridge Inverter.

Degree: Master, Electrical Engineering, 2017, NSYSU

 The feeder voltage fluctuation range is too large in the power system, and it may affect the user's electrical equipment performance and using life. Therefore,… (more)

Subjects/Keywords: Feeder voltage variation; Buck converter; Dynamic voltage restorer; AC/AC Inverter; Buck-Boost converter; Series voltage regulator

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Lee, C. (2017). Series Voltage Regulator Based On Dual Mode Full Bridge Inverter. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0202115-192721

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Lee, Cyuan-min. “Series Voltage Regulator Based On Dual Mode Full Bridge Inverter.” 2017. Thesis, NSYSU. Accessed August 13, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0202115-192721.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Lee, Cyuan-min. “Series Voltage Regulator Based On Dual Mode Full Bridge Inverter.” 2017. Web. 13 Aug 2020.

Vancouver:

Lee C. Series Voltage Regulator Based On Dual Mode Full Bridge Inverter. [Internet] [Thesis]. NSYSU; 2017. [cited 2020 Aug 13]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0202115-192721.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Lee C. Series Voltage Regulator Based On Dual Mode Full Bridge Inverter. [Thesis]. NSYSU; 2017. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0202115-192721

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of New South Wales

30. Hossain, Md. Jahangir. Dynamic Voltage Stability Augmentation in Interconnected Power Systems with Renewable Energy.

Degree: Engineering & Information Technology, 2010, University of New South Wales

 The first contribution of this dissertation is the case studies for capturing the development of different types of dynamic voltage instability, in both the short-… (more)

Subjects/Keywords: Dynamic Transfer Capability Enhancement; Power System Voltage Stability; Voltage Stability with Dynamic Loads; Renewable energy sources; Interconnected Power Systems

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APA (6th Edition):

Hossain, M. J. (2010). Dynamic Voltage Stability Augmentation in Interconnected Power Systems with Renewable Energy. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/50251 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:9129/SOURCE01?view=true

Chicago Manual of Style (16th Edition):

Hossain, Md Jahangir. “Dynamic Voltage Stability Augmentation in Interconnected Power Systems with Renewable Energy.” 2010. Doctoral Dissertation, University of New South Wales. Accessed August 13, 2020. http://handle.unsw.edu.au/1959.4/50251 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:9129/SOURCE01?view=true.

MLA Handbook (7th Edition):

Hossain, Md Jahangir. “Dynamic Voltage Stability Augmentation in Interconnected Power Systems with Renewable Energy.” 2010. Web. 13 Aug 2020.

Vancouver:

Hossain MJ. Dynamic Voltage Stability Augmentation in Interconnected Power Systems with Renewable Energy. [Internet] [Doctoral dissertation]. University of New South Wales; 2010. [cited 2020 Aug 13]. Available from: http://handle.unsw.edu.au/1959.4/50251 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:9129/SOURCE01?view=true.

Council of Science Editors:

Hossain MJ. Dynamic Voltage Stability Augmentation in Interconnected Power Systems with Renewable Energy. [Doctoral Dissertation]. University of New South Wales; 2010. Available from: http://handle.unsw.edu.au/1959.4/50251 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:9129/SOURCE01?view=true

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