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Univerzitet u Beogradu

1. Stojilović, Mirjana, 1983-. A Method for designing domain-specific reconfigurable arrays.

Degree: Elektrotehnički fakultet, 2016, Univerzitet u Beogradu

Tehničke nauke – elektrotehnika - Elektronika / Technical sciences, Electrical engineering - Electronics

Namenski računarski sistemi se najčesće projektuju tako da mogu da podrže izvršavanje većeg broja željenih aplikacija. Za postizanje što veće efikasnosti, preporučuje se korišćenje specijalizovanih procesora Application Specific Instruction Set Processors–ASIPs, na kojima se izvršavanje programskih instrukcija obavlja u za to projektovanim i nezavisnimhardverskim blokovima (akceleratorima). Glavni razlog za postojanje nezavisnih akceleratora jeste postizanjemaksimalnog ubrzanja izvršavanja instrukcija. Me ¯ dutim, ovakav pristup podrazumeva da je za svaki od blokova potrebno projektovati integrisano (ASIC) kolo, čime se bitno povećava ukupna površina procesora. Metod za smanjenje ukupne površine jeste primena DatapathMerging tehnike na dijagrame toka podataka ulaznih aplikacija. Kao rezultat, dobija se jedan programabilni hardverski akcelerator, sa mogućnosću izvršavanja svih željenih instrukcija. Međutim, ovo ima negativne posledice na efikasnost sistema. često se zanemaruje činjenica da, usled veoma ograničene fleksibilnosti ASIC hardverskih akceleratora, specijalizovani procesori imaju i drugih nedostataka. Naime, u slučaju izmena, ili prosto nadogradnje, specifikacije procesora u završnimfazama projektovanja, neizbežna su velika kašnjenja i dodatni troškovi promene dizajna. U ovoj tezi je pokazano da zahtevi za fleksibilnošću i efikasnošću ne moraju biti međusobno isključivi. Demonstrirano je je da je moguce uneti ograničeni nivo fleksibilnosti hardvera tokom dizajn procesa, tako da dobijeni hardverski akcelerator može da izvršava ne samo aplikacije definisane na samom početku projektovanja, već i druge aplikacije, pod uslovom da one pripadaju istom domenu. Drugim rečima, u tezi je prezentovana metoda projektovanja fleksibilnih namenskih hardverskih akceleratora. Eksperimentalnom evaluacijom pokazano je da su tako dobijeni akceleratori u većini slučajeva samo do 2 x veće površine ili 2 x većeg kašnjenja od akceleratora dobijenih primenom DatapathMerging metode, koja pritom ne pruža ni malo dodatne fleksibilnosti.

Advisors/Committee Members: Saranovac, Lazar, 1961-.

Subjects/Keywords: CGRA; datapath; domain-specific customization; flexibility; FPGA routing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Stojilović, Mirjana, 1. (2016). A Method for designing domain-specific reconfigurable arrays. (Thesis). Univerzitet u Beogradu. Retrieved from https://fedorabg.bg.ac.rs/fedora/get/o:13568/bdef:Content/get

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Stojilović, Mirjana, 1983-. “A Method for designing domain-specific reconfigurable arrays.” 2016. Thesis, Univerzitet u Beogradu. Accessed August 14, 2020. https://fedorabg.bg.ac.rs/fedora/get/o:13568/bdef:Content/get.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Stojilović, Mirjana, 1983-. “A Method for designing domain-specific reconfigurable arrays.” 2016. Web. 14 Aug 2020.

Vancouver:

Stojilović, Mirjana 1. A Method for designing domain-specific reconfigurable arrays. [Internet] [Thesis]. Univerzitet u Beogradu; 2016. [cited 2020 Aug 14]. Available from: https://fedorabg.bg.ac.rs/fedora/get/o:13568/bdef:Content/get.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Stojilović, Mirjana 1. A Method for designing domain-specific reconfigurable arrays. [Thesis]. Univerzitet u Beogradu; 2016. Available from: https://fedorabg.bg.ac.rs/fedora/get/o:13568/bdef:Content/get

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

2. Liu, Chunyue. Architecture Support for Customizable Domain-Specific Computing.

Degree: Computer Science, 2012, UCLA

This dissertation investigates the power-efficient high-performance architecture support for customizable domain-specific computing at both memory and communication levels in a customizable heterogeneous platform (CHP).In domain-specific computing, the memory access pattern can be obtained through offline analysis. With this knowledge, the cores and the accelerators in the CHP can use on-chip scratchpad memory (SPM) and buffers to directly manage the data replacement in order to save off-chip memory bandwidth. We propose efficient schemes to hybrid the SPM and primary caches, and to also hybrid buffers and the shared last-level cache (LLC). In the hybrid primary cache, due to its low associativity, the problem of balancing the cache set utilization when the SPM is allocated in the cache is critical. We propose an adaptive hybrid cache (AH-Cache) to dynamically remap SPM blocks from high-demand cache sets to low-demand cache sets. In the hybrid LLC (typically designed as a nonuniform cache architecture, NUCA), the problem of resource contention and fragmentation becomes crucial. We propose a buffer-in-NUCA (BiN) scheme to assign shared buffer spaces to accelerators that can best utilize the additional buffer space, and use flexible paged buffer allocation to limit the impact of buffer fragmentation.In domain-specific computing, the communication pattern can be also obtained through offline analysis. With this knowledge, the topology and routing scheme in the CHP communication subsystem can be customized to dynamically adapt to the known communication pattern. For the topology customization, we propose application-specific shortcuts and multicast realized by radio frequency interconnects (RF-I) overlaid network-on-chip (NoC). At runtime, we can flexibly allocate RF-I bandwidth to adapt the NoC topology to the known communication requirement of an application. For the routing customization, we propose an power-efficient application-specific cycle elimination and splitting (ACES) routing scheme to avoid restricting the critical routes of an application while achieving deadlock-free for irregular NoCs.To further demonstrate the feasibility and effectiveness of these techniques, we develop a FPGA prototype of the proposed CHP with shared accelerators and buffers. The buffer sharing is achieved through a cost-efficient partial-crossbar to reduce the sharing overhead on timing and area.

Subjects/Keywords: Computer science; Accelerators; Customization; Domain-Specific Computing; Heterogeneous Platform; Hybrid Cache; Network-on-Chip

…1 1.1 Customizable Domain-Specific Computing… …1 1.2 Architecture Support for Customizable Domain-Specific Computing................. 3… …Figure 7-1. Interactions of phases for customizable domain-specific computing ... 140 xii… …specific customization as the next disruptive technology [1]. This can be attributed to… …enable power-efficient performance tuned to the specific needs of an application domain; 2)… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liu, C. (2012). Architecture Support for Customizable Domain-Specific Computing. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/32s189v6

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Chunyue. “Architecture Support for Customizable Domain-Specific Computing.” 2012. Thesis, UCLA. Accessed August 14, 2020. http://www.escholarship.org/uc/item/32s189v6.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Chunyue. “Architecture Support for Customizable Domain-Specific Computing.” 2012. Web. 14 Aug 2020.

Vancouver:

Liu C. Architecture Support for Customizable Domain-Specific Computing. [Internet] [Thesis]. UCLA; 2012. [cited 2020 Aug 14]. Available from: http://www.escholarship.org/uc/item/32s189v6.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu C. Architecture Support for Customizable Domain-Specific Computing. [Thesis]. UCLA; 2012. Available from: http://www.escholarship.org/uc/item/32s189v6

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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