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You searched for subject:(digital circuit). Showing records 1 – 30 of 182 total matches.

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University of Windsor

1. Zhan, Suoyue. Reliability Analysis and Optimization Models for Large Scale Combinational Circuits.

Degree: MA, Electrical and Computer Engineering, 2018, University of Windsor

 With increasingly high density, today’s integrated circuit chips become sensitive to minor effects such as temperature and environmental noises, which may lead to unreliable operation.… (more)

Subjects/Keywords: Combinational Circuit; Digital; Reliability

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APA (6th Edition):

Zhan, S. (2018). Reliability Analysis and Optimization Models for Large Scale Combinational Circuits. (Masters Thesis). University of Windsor. Retrieved from https://scholar.uwindsor.ca/etd/7591

Chicago Manual of Style (16th Edition):

Zhan, Suoyue. “Reliability Analysis and Optimization Models for Large Scale Combinational Circuits.” 2018. Masters Thesis, University of Windsor. Accessed September 28, 2020. https://scholar.uwindsor.ca/etd/7591.

MLA Handbook (7th Edition):

Zhan, Suoyue. “Reliability Analysis and Optimization Models for Large Scale Combinational Circuits.” 2018. Web. 28 Sep 2020.

Vancouver:

Zhan S. Reliability Analysis and Optimization Models for Large Scale Combinational Circuits. [Internet] [Masters thesis]. University of Windsor; 2018. [cited 2020 Sep 28]. Available from: https://scholar.uwindsor.ca/etd/7591.

Council of Science Editors:

Zhan S. Reliability Analysis and Optimization Models for Large Scale Combinational Circuits. [Masters Thesis]. University of Windsor; 2018. Available from: https://scholar.uwindsor.ca/etd/7591


Carnegie Mellon University

2. Niewenhuis, Benjamin T. A Logic Test Chip for Optimal Test and Diagnosis.

Degree: 2018, Carnegie Mellon University

 The benefits of the continued progress in integrated circuit manufacturing have been numerous, most notably in the explosion of computing power in devices ranging from… (more)

Subjects/Keywords: digital circuit diagnosis; digital circuit test; test chip design; yield learning

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APA (6th Edition):

Niewenhuis, B. T. (2018). A Logic Test Chip for Optimal Test and Diagnosis. (Thesis). Carnegie Mellon University. Retrieved from http://repository.cmu.edu/dissertations/1176

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Niewenhuis, Benjamin T. “A Logic Test Chip for Optimal Test and Diagnosis.” 2018. Thesis, Carnegie Mellon University. Accessed September 28, 2020. http://repository.cmu.edu/dissertations/1176.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Niewenhuis, Benjamin T. “A Logic Test Chip for Optimal Test and Diagnosis.” 2018. Web. 28 Sep 2020.

Vancouver:

Niewenhuis BT. A Logic Test Chip for Optimal Test and Diagnosis. [Internet] [Thesis]. Carnegie Mellon University; 2018. [cited 2020 Sep 28]. Available from: http://repository.cmu.edu/dissertations/1176.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Niewenhuis BT. A Logic Test Chip for Optimal Test and Diagnosis. [Thesis]. Carnegie Mellon University; 2018. Available from: http://repository.cmu.edu/dissertations/1176

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Anna University

3. Kathirvelu M. Certain Investigation On Optimized Area And Power Delay Product In Digital Circuit Applications;.

Degree: communication engineering, 2013, Anna University

Owing to explosive growth of laptops portable personal newlinecommunication systems and the evolution of the shrinking technology the newlineresearch effort in lowpower electronics has become… (more)

Subjects/Keywords: Digital Circuit; digital signal processing; Optimized Area; Power Delay Product; transistors

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APA (6th Edition):

M, K. (2013). Certain Investigation On Optimized Area And Power Delay Product In Digital Circuit Applications;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/24055

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

M, Kathirvelu. “Certain Investigation On Optimized Area And Power Delay Product In Digital Circuit Applications;.” 2013. Thesis, Anna University. Accessed September 28, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/24055.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

M, Kathirvelu. “Certain Investigation On Optimized Area And Power Delay Product In Digital Circuit Applications;.” 2013. Web. 28 Sep 2020.

Vancouver:

M K. Certain Investigation On Optimized Area And Power Delay Product In Digital Circuit Applications;. [Internet] [Thesis]. Anna University; 2013. [cited 2020 Sep 28]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/24055.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

M K. Certain Investigation On Optimized Area And Power Delay Product In Digital Circuit Applications;. [Thesis]. Anna University; 2013. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/24055

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Université Montpellier II

4. Tran, Duc Anh. Architecture hybride tolérante aux fautes pour l'amélioration de la robustesse des circuits et systèmes intégrés numériques. : A Hybrid Fault-Tolerant Architecture for Robustness Improvement of Digital Integrated Circuits and Systems.

Degree: Docteur es, SYAM - Systèmes Automatiques et Microélectroniques, 2012, Université Montpellier II

L'évolution de la technologie CMOS consiste à la miniaturisation continue de la taille des transistors. Cela permet la réalisation de circuits et systèmes intégrés de… (more)

Subjects/Keywords: Tolérance aux fautes; Circuit numérique; Logique combinatoire; Fault tolerance; Digital circuit; Combinational logic

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APA (6th Edition):

Tran, D. A. (2012). Architecture hybride tolérante aux fautes pour l'amélioration de la robustesse des circuits et systèmes intégrés numériques. : A Hybrid Fault-Tolerant Architecture for Robustness Improvement of Digital Integrated Circuits and Systems. (Doctoral Dissertation). Université Montpellier II. Retrieved from http://www.theses.fr/2012MON20132

Chicago Manual of Style (16th Edition):

Tran, Duc Anh. “Architecture hybride tolérante aux fautes pour l'amélioration de la robustesse des circuits et systèmes intégrés numériques. : A Hybrid Fault-Tolerant Architecture for Robustness Improvement of Digital Integrated Circuits and Systems.” 2012. Doctoral Dissertation, Université Montpellier II. Accessed September 28, 2020. http://www.theses.fr/2012MON20132.

MLA Handbook (7th Edition):

Tran, Duc Anh. “Architecture hybride tolérante aux fautes pour l'amélioration de la robustesse des circuits et systèmes intégrés numériques. : A Hybrid Fault-Tolerant Architecture for Robustness Improvement of Digital Integrated Circuits and Systems.” 2012. Web. 28 Sep 2020.

Vancouver:

Tran DA. Architecture hybride tolérante aux fautes pour l'amélioration de la robustesse des circuits et systèmes intégrés numériques. : A Hybrid Fault-Tolerant Architecture for Robustness Improvement of Digital Integrated Circuits and Systems. [Internet] [Doctoral dissertation]. Université Montpellier II; 2012. [cited 2020 Sep 28]. Available from: http://www.theses.fr/2012MON20132.

Council of Science Editors:

Tran DA. Architecture hybride tolérante aux fautes pour l'amélioration de la robustesse des circuits et systèmes intégrés numériques. : A Hybrid Fault-Tolerant Architecture for Robustness Improvement of Digital Integrated Circuits and Systems. [Doctoral Dissertation]. Université Montpellier II; 2012. Available from: http://www.theses.fr/2012MON20132


Wayne State University

5. Konampurath George, Aby. Design Of Dna Strand Displacement Based Circuits.

Degree: PhD, Electrical and Computer Engineering, 2018, Wayne State University

  DNA is the basic building block of any living organism. DNA is considered a popular candidate for future biological devices and circuits for solving… (more)

Subjects/Keywords: Biological Circuit; Digital Design; DNA Circuit Design; Fuzzy Inference Engine; Nano Circuit Design; Nanoscience and Nanotechnology

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APA (6th Edition):

Konampurath George, A. (2018). Design Of Dna Strand Displacement Based Circuits. (Doctoral Dissertation). Wayne State University. Retrieved from https://digitalcommons.wayne.edu/oa_dissertations/1937

Chicago Manual of Style (16th Edition):

Konampurath George, Aby. “Design Of Dna Strand Displacement Based Circuits.” 2018. Doctoral Dissertation, Wayne State University. Accessed September 28, 2020. https://digitalcommons.wayne.edu/oa_dissertations/1937.

MLA Handbook (7th Edition):

Konampurath George, Aby. “Design Of Dna Strand Displacement Based Circuits.” 2018. Web. 28 Sep 2020.

Vancouver:

Konampurath George A. Design Of Dna Strand Displacement Based Circuits. [Internet] [Doctoral dissertation]. Wayne State University; 2018. [cited 2020 Sep 28]. Available from: https://digitalcommons.wayne.edu/oa_dissertations/1937.

Council of Science Editors:

Konampurath George A. Design Of Dna Strand Displacement Based Circuits. [Doctoral Dissertation]. Wayne State University; 2018. Available from: https://digitalcommons.wayne.edu/oa_dissertations/1937


Stellenbosch University

6. Muller, Louis C. RSFQ digital circuit design automation and optimisation.

Degree: PhD, Electrical and Electronic Engineering, 2015, Stellenbosch University

 ENGLISH ABSTRACT: In order to facilitate the creation of complex and robust RSFQ digital logic circuits an extensive library of electronic design automation (EDA) tools… (more)

Subjects/Keywords: RSFQ digital circuit design  – Automation; Rapid Single Flux Quantum (RSFQ); RSFQ digital circuit design  – Optimisation; UCTD

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APA (6th Edition):

Muller, L. C. (2015). RSFQ digital circuit design automation and optimisation. (Doctoral Dissertation). Stellenbosch University. Retrieved from http://hdl.handle.net/10019.1/96808

Chicago Manual of Style (16th Edition):

Muller, Louis C. “RSFQ digital circuit design automation and optimisation.” 2015. Doctoral Dissertation, Stellenbosch University. Accessed September 28, 2020. http://hdl.handle.net/10019.1/96808.

MLA Handbook (7th Edition):

Muller, Louis C. “RSFQ digital circuit design automation and optimisation.” 2015. Web. 28 Sep 2020.

Vancouver:

Muller LC. RSFQ digital circuit design automation and optimisation. [Internet] [Doctoral dissertation]. Stellenbosch University; 2015. [cited 2020 Sep 28]. Available from: http://hdl.handle.net/10019.1/96808.

Council of Science Editors:

Muller LC. RSFQ digital circuit design automation and optimisation. [Doctoral Dissertation]. Stellenbosch University; 2015. Available from: http://hdl.handle.net/10019.1/96808


University of Arkansas

7. Kuhns, Nathan William. Power Efficient High Temperature Asynchronous Microcontroller Design.

Degree: PhD, 2017, University of Arkansas

  There is an increasing demand for dependable and efficient digital circuitry capable of operating in high temperature environments. Extreme temperatures have adverse effects on… (more)

Subjects/Keywords: Applied sciences; Asynchronous circuit; Digital circuit; High temperature; Microcontroller; Null convention logic; Silicon carbide; Computer and Systems Architecture; Digital Circuits

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APA (6th Edition):

Kuhns, N. W. (2017). Power Efficient High Temperature Asynchronous Microcontroller Design. (Doctoral Dissertation). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/1911

Chicago Manual of Style (16th Edition):

Kuhns, Nathan William. “Power Efficient High Temperature Asynchronous Microcontroller Design.” 2017. Doctoral Dissertation, University of Arkansas. Accessed September 28, 2020. https://scholarworks.uark.edu/etd/1911.

MLA Handbook (7th Edition):

Kuhns, Nathan William. “Power Efficient High Temperature Asynchronous Microcontroller Design.” 2017. Web. 28 Sep 2020.

Vancouver:

Kuhns NW. Power Efficient High Temperature Asynchronous Microcontroller Design. [Internet] [Doctoral dissertation]. University of Arkansas; 2017. [cited 2020 Sep 28]. Available from: https://scholarworks.uark.edu/etd/1911.

Council of Science Editors:

Kuhns NW. Power Efficient High Temperature Asynchronous Microcontroller Design. [Doctoral Dissertation]. University of Arkansas; 2017. Available from: https://scholarworks.uark.edu/etd/1911


Universidade do Rio Grande do Sul

8. Bortolon, Felipe Todeschini. Static noise margin analysis for CMOS logic cells in near-threshold.

Degree: 2018, Universidade do Rio Grande do Sul

The advancement of semiconductor technology enabled the fabrication of devices with faster switching activity and chips with higher integration density. However, these advances are facing… (more)

Subjects/Keywords: Microeletrônica; Digital circuit; Circuitos digitais; SNM; Noise tolerance; Digital cell design; Subthreshold

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APA (6th Edition):

Bortolon, F. T. (2018). Static noise margin analysis for CMOS logic cells in near-threshold. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/178664

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bortolon, Felipe Todeschini. “Static noise margin analysis for CMOS logic cells in near-threshold.” 2018. Thesis, Universidade do Rio Grande do Sul. Accessed September 28, 2020. http://hdl.handle.net/10183/178664.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bortolon, Felipe Todeschini. “Static noise margin analysis for CMOS logic cells in near-threshold.” 2018. Web. 28 Sep 2020.

Vancouver:

Bortolon FT. Static noise margin analysis for CMOS logic cells in near-threshold. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2018. [cited 2020 Sep 28]. Available from: http://hdl.handle.net/10183/178664.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bortolon FT. Static noise margin analysis for CMOS logic cells in near-threshold. [Thesis]. Universidade do Rio Grande do Sul; 2018. Available from: http://hdl.handle.net/10183/178664

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


UCLA

9. Yuan, Fang-Li. Energy-Efficient VLSI Architectures for Next-Generation Software-Defined and Cognitive Radios.

Degree: Electrical Engineering, 2014, UCLA

 Dedicated radio hardware is no longer promising as it was in the past. Today, the support of diverse standards dictates more flexible solutions. Software-defined radio… (more)

Subjects/Keywords: Electrical engineering; Digital Circuit Designs; Digital Signal Processing; Processor Designs; Wireless Communications

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APA (6th Edition):

Yuan, F. (2014). Energy-Efficient VLSI Architectures for Next-Generation Software-Defined and Cognitive Radios. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/5vw9x3p9

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Yuan, Fang-Li. “Energy-Efficient VLSI Architectures for Next-Generation Software-Defined and Cognitive Radios.” 2014. Thesis, UCLA. Accessed September 28, 2020. http://www.escholarship.org/uc/item/5vw9x3p9.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Yuan, Fang-Li. “Energy-Efficient VLSI Architectures for Next-Generation Software-Defined and Cognitive Radios.” 2014. Web. 28 Sep 2020.

Vancouver:

Yuan F. Energy-Efficient VLSI Architectures for Next-Generation Software-Defined and Cognitive Radios. [Internet] [Thesis]. UCLA; 2014. [cited 2020 Sep 28]. Available from: http://www.escholarship.org/uc/item/5vw9x3p9.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Yuan F. Energy-Efficient VLSI Architectures for Next-Generation Software-Defined and Cognitive Radios. [Thesis]. UCLA; 2014. Available from: http://www.escholarship.org/uc/item/5vw9x3p9

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Arkansas

10. Mize, Nicholas Renoudet. Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic.

Degree: MSCmpE, 2019, University of Arkansas

  As the demand for an energy-efficient alternative to traditional synchronous circuit design grows, hardware designers must reconsider the traditional clock tree. By doing away… (more)

Subjects/Keywords: Asynchronous; Circuit; Digital; MTNCL; Synthesis; VHDL; Digital Circuits; VLSI and Circuits, Embedded and Hardware Systems

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APA (6th Edition):

Mize, N. R. (2019). Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic. (Masters Thesis). University of Arkansas. Retrieved from https://scholarworks.uark.edu/etd/3168

Chicago Manual of Style (16th Edition):

Mize, Nicholas Renoudet. “Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic.” 2019. Masters Thesis, University of Arkansas. Accessed September 28, 2020. https://scholarworks.uark.edu/etd/3168.

MLA Handbook (7th Edition):

Mize, Nicholas Renoudet. “Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic.” 2019. Web. 28 Sep 2020.

Vancouver:

Mize NR. Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic. [Internet] [Masters thesis]. University of Arkansas; 2019. [cited 2020 Sep 28]. Available from: https://scholarworks.uark.edu/etd/3168.

Council of Science Editors:

Mize NR. Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic. [Masters Thesis]. University of Arkansas; 2019. Available from: https://scholarworks.uark.edu/etd/3168


Anna University

11. Mahendran N. Fuzzy controller based space vector pulse width modulation scheme for direct ac conversion system;.

Degree: 2013, Anna University

In power electronic applications direct AC/AC conversion plays an important role. This direct AC/AC conversion provides inherent attractive characteristics. There is no need of DC… (more)

Subjects/Keywords: Digital Logic Combination Circuit; fuzzy controller; modulation scheme; space vector pulse

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APA (6th Edition):

N, M. (2013). Fuzzy controller based space vector pulse width modulation scheme for direct ac conversion system;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/10150

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

N, Mahendran. “Fuzzy controller based space vector pulse width modulation scheme for direct ac conversion system;.” 2013. Thesis, Anna University. Accessed September 28, 2020. http://shodhganga.inflibnet.ac.in/handle/10603/10150.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

N, Mahendran. “Fuzzy controller based space vector pulse width modulation scheme for direct ac conversion system;.” 2013. Web. 28 Sep 2020.

Vancouver:

N M. Fuzzy controller based space vector pulse width modulation scheme for direct ac conversion system;. [Internet] [Thesis]. Anna University; 2013. [cited 2020 Sep 28]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/10150.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

N M. Fuzzy controller based space vector pulse width modulation scheme for direct ac conversion system;. [Thesis]. Anna University; 2013. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/10150

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

12. Lynch, John Daniel. Stochastic fault simulation of triple-modular redundant asynchronous pipeline circuits.

Degree: PhD, 2009, Oregon Health Sciences University

Subjects/Keywords: Asynchronous; Fault-tolerant; Digital circuit

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APA (6th Edition):

Lynch, J. D. (2009). Stochastic fault simulation of triple-modular redundant asynchronous pipeline circuits. (Doctoral Dissertation). Oregon Health Sciences University. Retrieved from doi:10.6083/M4J964B9 ; http://digitalcommons.ohsu.edu/etd/344

Chicago Manual of Style (16th Edition):

Lynch, John Daniel. “Stochastic fault simulation of triple-modular redundant asynchronous pipeline circuits.” 2009. Doctoral Dissertation, Oregon Health Sciences University. Accessed September 28, 2020. doi:10.6083/M4J964B9 ; http://digitalcommons.ohsu.edu/etd/344.

MLA Handbook (7th Edition):

Lynch, John Daniel. “Stochastic fault simulation of triple-modular redundant asynchronous pipeline circuits.” 2009. Web. 28 Sep 2020.

Vancouver:

Lynch JD. Stochastic fault simulation of triple-modular redundant asynchronous pipeline circuits. [Internet] [Doctoral dissertation]. Oregon Health Sciences University; 2009. [cited 2020 Sep 28]. Available from: doi:10.6083/M4J964B9 ; http://digitalcommons.ohsu.edu/etd/344.

Council of Science Editors:

Lynch JD. Stochastic fault simulation of triple-modular redundant asynchronous pipeline circuits. [Doctoral Dissertation]. Oregon Health Sciences University; 2009. Available from: doi:10.6083/M4J964B9 ; http://digitalcommons.ohsu.edu/etd/344


Northeastern University

13. Cho, Geunho. Modeling undeposited CNTs for high performance design and the evaluation of reliable CNTFET circuits.

Degree: PhD, Department of Electrical and Computer Engineering, 2012, Northeastern University

 The Carbon NanoTube Field Effect Transistor (CNTFET) is one of the most promising emerging technologies to extend and complement silicon MOSFET; this is due to… (more)

Subjects/Keywords: Carbon NanoTube Field Effect Transistorcircuits; integrated circuit; Computer Engineering; Digital Circuits

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APA (6th Edition):

Cho, G. (2012). Modeling undeposited CNTs for high performance design and the evaluation of reliable CNTFET circuits. (Doctoral Dissertation). Northeastern University. Retrieved from http://hdl.handle.net/2047/d20002840

Chicago Manual of Style (16th Edition):

Cho, Geunho. “Modeling undeposited CNTs for high performance design and the evaluation of reliable CNTFET circuits.” 2012. Doctoral Dissertation, Northeastern University. Accessed September 28, 2020. http://hdl.handle.net/2047/d20002840.

MLA Handbook (7th Edition):

Cho, Geunho. “Modeling undeposited CNTs for high performance design and the evaluation of reliable CNTFET circuits.” 2012. Web. 28 Sep 2020.

Vancouver:

Cho G. Modeling undeposited CNTs for high performance design and the evaluation of reliable CNTFET circuits. [Internet] [Doctoral dissertation]. Northeastern University; 2012. [cited 2020 Sep 28]. Available from: http://hdl.handle.net/2047/d20002840.

Council of Science Editors:

Cho G. Modeling undeposited CNTs for high performance design and the evaluation of reliable CNTFET circuits. [Doctoral Dissertation]. Northeastern University; 2012. Available from: http://hdl.handle.net/2047/d20002840


University of Toronto

14. Onaissi, Sari. Circuit Performance Verification and Optimization in the Presence of Variability.

Degree: 2011, University of Toronto

The continued scaling of digital integrated circuits has led to an increasingly larger impact of process, supply voltage, and temperature (PVT) variations. The effect of… (more)

Subjects/Keywords: Digital Circuit Performance, Process Variations, Computer-Aided Design; 0544

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APA (6th Edition):

Onaissi, S. (2011). Circuit Performance Verification and Optimization in the Presence of Variability. (Doctoral Dissertation). University of Toronto. Retrieved from http://hdl.handle.net/1807/31886

Chicago Manual of Style (16th Edition):

Onaissi, Sari. “Circuit Performance Verification and Optimization in the Presence of Variability.” 2011. Doctoral Dissertation, University of Toronto. Accessed September 28, 2020. http://hdl.handle.net/1807/31886.

MLA Handbook (7th Edition):

Onaissi, Sari. “Circuit Performance Verification and Optimization in the Presence of Variability.” 2011. Web. 28 Sep 2020.

Vancouver:

Onaissi S. Circuit Performance Verification and Optimization in the Presence of Variability. [Internet] [Doctoral dissertation]. University of Toronto; 2011. [cited 2020 Sep 28]. Available from: http://hdl.handle.net/1807/31886.

Council of Science Editors:

Onaissi S. Circuit Performance Verification and Optimization in the Presence of Variability. [Doctoral Dissertation]. University of Toronto; 2011. Available from: http://hdl.handle.net/1807/31886


University of Minnesota

15. Everson, Luke. Energy Efficient Computing with Time-Based Digital Circuits.

Degree: PhD, Electrical Engineering, 2019, University of Minnesota

 Advancements in semiconductor technology have given the world economical, abundant, and reliable computing resources which have enabled countless breakthroughs in science, medicine, and agriculture which… (more)

Subjects/Keywords: circuit design; digital circuits; graph computing; machine learning; time-domain; vlsi

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APA (6th Edition):

Everson, L. (2019). Energy Efficient Computing with Time-Based Digital Circuits. (Doctoral Dissertation). University of Minnesota. Retrieved from http://hdl.handle.net/11299/206288

Chicago Manual of Style (16th Edition):

Everson, Luke. “Energy Efficient Computing with Time-Based Digital Circuits.” 2019. Doctoral Dissertation, University of Minnesota. Accessed September 28, 2020. http://hdl.handle.net/11299/206288.

MLA Handbook (7th Edition):

Everson, Luke. “Energy Efficient Computing with Time-Based Digital Circuits.” 2019. Web. 28 Sep 2020.

Vancouver:

Everson L. Energy Efficient Computing with Time-Based Digital Circuits. [Internet] [Doctoral dissertation]. University of Minnesota; 2019. [cited 2020 Sep 28]. Available from: http://hdl.handle.net/11299/206288.

Council of Science Editors:

Everson L. Energy Efficient Computing with Time-Based Digital Circuits. [Doctoral Dissertation]. University of Minnesota; 2019. Available from: http://hdl.handle.net/11299/206288


Utah State University

16. Sakib, Nazmus. Hardware Accelerator for Star Centroiding.

Degree: MS, Electrical and Computer Engineering, 2020, Utah State University

  Since the dawn of civilization mankind has gazed upon the night sky and looked for directions. In this modern age, the stars have proved… (more)

Subjects/Keywords: star centroid; digital circuit; parallel processing; Electrical and Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sakib, N. (2020). Hardware Accelerator for Star Centroiding. (Masters Thesis). Utah State University. Retrieved from https://digitalcommons.usu.edu/etd/7748

Chicago Manual of Style (16th Edition):

Sakib, Nazmus. “Hardware Accelerator for Star Centroiding.” 2020. Masters Thesis, Utah State University. Accessed September 28, 2020. https://digitalcommons.usu.edu/etd/7748.

MLA Handbook (7th Edition):

Sakib, Nazmus. “Hardware Accelerator for Star Centroiding.” 2020. Web. 28 Sep 2020.

Vancouver:

Sakib N. Hardware Accelerator for Star Centroiding. [Internet] [Masters thesis]. Utah State University; 2020. [cited 2020 Sep 28]. Available from: https://digitalcommons.usu.edu/etd/7748.

Council of Science Editors:

Sakib N. Hardware Accelerator for Star Centroiding. [Masters Thesis]. Utah State University; 2020. Available from: https://digitalcommons.usu.edu/etd/7748


Louisiana State University

17. Marasco, Anthony Thomas. Bendit_I/O: A System for Extending Mediated and Networked Performance Techniques to Circuit-Bent Devices.

Degree: PhD, Composition, 2020, Louisiana State University

Circuit bending—the act of modifying a consumer device's internal circuitry in search of new, previously-unintended responses—provides artists with a chance to subvert expectations for… (more)

Subjects/Keywords: circuit-bending; composition; technology; digital art; computer music; hardware

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Marasco, A. T. (2020). Bendit_I/O: A System for Extending Mediated and Networked Performance Techniques to Circuit-Bent Devices. (Doctoral Dissertation). Louisiana State University. Retrieved from https://digitalcommons.lsu.edu/gradschool_dissertations/5343

Chicago Manual of Style (16th Edition):

Marasco, Anthony Thomas. “Bendit_I/O: A System for Extending Mediated and Networked Performance Techniques to Circuit-Bent Devices.” 2020. Doctoral Dissertation, Louisiana State University. Accessed September 28, 2020. https://digitalcommons.lsu.edu/gradschool_dissertations/5343.

MLA Handbook (7th Edition):

Marasco, Anthony Thomas. “Bendit_I/O: A System for Extending Mediated and Networked Performance Techniques to Circuit-Bent Devices.” 2020. Web. 28 Sep 2020.

Vancouver:

Marasco AT. Bendit_I/O: A System for Extending Mediated and Networked Performance Techniques to Circuit-Bent Devices. [Internet] [Doctoral dissertation]. Louisiana State University; 2020. [cited 2020 Sep 28]. Available from: https://digitalcommons.lsu.edu/gradschool_dissertations/5343.

Council of Science Editors:

Marasco AT. Bendit_I/O: A System for Extending Mediated and Networked Performance Techniques to Circuit-Bent Devices. [Doctoral Dissertation]. Louisiana State University; 2020. Available from: https://digitalcommons.lsu.edu/gradschool_dissertations/5343


King Abdullah University of Science and Technology

18. zou, xuecui. Micro-electro-mechanical Resonator-Based Digital and Interface Elements for Low Power Circuits.

Degree: 2019, King Abdullah University of Science and Technology

 The interest in implementing energy-efficient digital circuits using micro and nanoelectromechanical resonator technology has increased significantly over the last decade given their lower energy consumption… (more)

Subjects/Keywords: MEMs Resonators; Analog-to-Digital; Counter; Low power circuit

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

zou, x. (2019). Micro-electro-mechanical Resonator-Based Digital and Interface Elements for Low Power Circuits. (Thesis). King Abdullah University of Science and Technology. Retrieved from http://hdl.handle.net/10754/660269

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

zou, xuecui. “Micro-electro-mechanical Resonator-Based Digital and Interface Elements for Low Power Circuits.” 2019. Thesis, King Abdullah University of Science and Technology. Accessed September 28, 2020. http://hdl.handle.net/10754/660269.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

zou, xuecui. “Micro-electro-mechanical Resonator-Based Digital and Interface Elements for Low Power Circuits.” 2019. Web. 28 Sep 2020.

Vancouver:

zou x. Micro-electro-mechanical Resonator-Based Digital and Interface Elements for Low Power Circuits. [Internet] [Thesis]. King Abdullah University of Science and Technology; 2019. [cited 2020 Sep 28]. Available from: http://hdl.handle.net/10754/660269.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

zou x. Micro-electro-mechanical Resonator-Based Digital and Interface Elements for Low Power Circuits. [Thesis]. King Abdullah University of Science and Technology; 2019. Available from: http://hdl.handle.net/10754/660269

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade Federal de Santa Maria

19. Débora Aita Gasparetto. ARTE DIGITAL E CIRCUITO EXPOSITIVO: UM CURTO EM TORNO DO FILE.

Degree: 2012, Universidade Federal de Santa Maria

O objetivo desta pesquisa é discutir o circuito expositivo da arte digital na contemporaneidade, verificando como se articula a arte digital, quais são suas particularidades… (more)

Subjects/Keywords: arte contemporânea; mídias digitais; ARTES; digital media; arte digital; circuito expositivo; contemporary art; digital art; expositive circuit

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gasparetto, D. A. (2012). ARTE DIGITAL E CIRCUITO EXPOSITIVO: UM CURTO EM TORNO DO FILE. (Thesis). Universidade Federal de Santa Maria. Retrieved from http://coralx.ufsm.br/tede/tde_busca/arquivo.php?codArquivo=4856

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Gasparetto, Débora Aita. “ARTE DIGITAL E CIRCUITO EXPOSITIVO: UM CURTO EM TORNO DO FILE.” 2012. Thesis, Universidade Federal de Santa Maria. Accessed September 28, 2020. http://coralx.ufsm.br/tede/tde_busca/arquivo.php?codArquivo=4856.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Gasparetto, Débora Aita. “ARTE DIGITAL E CIRCUITO EXPOSITIVO: UM CURTO EM TORNO DO FILE.” 2012. Web. 28 Sep 2020.

Vancouver:

Gasparetto DA. ARTE DIGITAL E CIRCUITO EXPOSITIVO: UM CURTO EM TORNO DO FILE. [Internet] [Thesis]. Universidade Federal de Santa Maria; 2012. [cited 2020 Sep 28]. Available from: http://coralx.ufsm.br/tede/tde_busca/arquivo.php?codArquivo=4856.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Gasparetto DA. ARTE DIGITAL E CIRCUITO EXPOSITIVO: UM CURTO EM TORNO DO FILE. [Thesis]. Universidade Federal de Santa Maria; 2012. Available from: http://coralx.ufsm.br/tede/tde_busca/arquivo.php?codArquivo=4856

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

20. Bavaresco, Simone. On-silicon testbench for validation of soft logic cell libraries.

Degree: 2008, Universidade do Rio Grande do Sul

Projeto baseado em células-padrão é a abordagem mais aplicada no mercado de ASIC atualmente. Essa abordagem de projeto consiste no reuso de bibliotecas de células… (more)

Subjects/Keywords: Integrated circuit; Microeletrônica; ASIC; Testes : Circuitos integrados; Digital design; Standard cell; Library-free technology mapping; Soft library; Test circuit

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Bavaresco, S. (2008). On-silicon testbench for validation of soft logic cell libraries. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/14907

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bavaresco, Simone. “On-silicon testbench for validation of soft logic cell libraries.” 2008. Thesis, Universidade do Rio Grande do Sul. Accessed September 28, 2020. http://hdl.handle.net/10183/14907.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bavaresco, Simone. “On-silicon testbench for validation of soft logic cell libraries.” 2008. Web. 28 Sep 2020.

Vancouver:

Bavaresco S. On-silicon testbench for validation of soft logic cell libraries. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2008. [cited 2020 Sep 28]. Available from: http://hdl.handle.net/10183/14907.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bavaresco S. On-silicon testbench for validation of soft logic cell libraries. [Thesis]. Universidade do Rio Grande do Sul; 2008. Available from: http://hdl.handle.net/10183/14907

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

21. Chairat, Soundous. Réseau de service asynchrone pour contrôle distribué dans un circuit numérique ou mixte : Asynchronous network service for distributed control in a digital or mixed-signal circuit.

Degree: Docteur es, Nano electronique et nano technologies, 2017, Université Grenoble Alpes (ComUE)

Les réseaux de capteurs sans fils (WSN) ont connu un succès important ces dernières années, en particulier grâce à l’émergence de l’Internet des Objets (IoT),… (more)

Subjects/Keywords: Réseau de service asynchrone; Contrôle distribué; Circuit numérique ou mixte; Network service; Distributed control; Digital or mixed circuit; 620

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chairat, S. (2017). Réseau de service asynchrone pour contrôle distribué dans un circuit numérique ou mixte : Asynchronous network service for distributed control in a digital or mixed-signal circuit. (Doctoral Dissertation). Université Grenoble Alpes (ComUE). Retrieved from http://www.theses.fr/2017GREAT058

Chicago Manual of Style (16th Edition):

Chairat, Soundous. “Réseau de service asynchrone pour contrôle distribué dans un circuit numérique ou mixte : Asynchronous network service for distributed control in a digital or mixed-signal circuit.” 2017. Doctoral Dissertation, Université Grenoble Alpes (ComUE). Accessed September 28, 2020. http://www.theses.fr/2017GREAT058.

MLA Handbook (7th Edition):

Chairat, Soundous. “Réseau de service asynchrone pour contrôle distribué dans un circuit numérique ou mixte : Asynchronous network service for distributed control in a digital or mixed-signal circuit.” 2017. Web. 28 Sep 2020.

Vancouver:

Chairat S. Réseau de service asynchrone pour contrôle distribué dans un circuit numérique ou mixte : Asynchronous network service for distributed control in a digital or mixed-signal circuit. [Internet] [Doctoral dissertation]. Université Grenoble Alpes (ComUE); 2017. [cited 2020 Sep 28]. Available from: http://www.theses.fr/2017GREAT058.

Council of Science Editors:

Chairat S. Réseau de service asynchrone pour contrôle distribué dans un circuit numérique ou mixte : Asynchronous network service for distributed control in a digital or mixed-signal circuit. [Doctoral Dissertation]. Université Grenoble Alpes (ComUE); 2017. Available from: http://www.theses.fr/2017GREAT058


Texas A&M University

22. Mukherjee, Parijat. Detection and Diagnosis of Out-of-Specification Failures in Mixed-Signal Circuits.

Degree: PhD, Computer Engineering, 2014, Texas A&M University

 Verifying whether a circuit meets its intended specifications, as well as diagnosing the circuits that do not, is indispensable at every stage of integrated circuit(more)

Subjects/Keywords: Model checking; Integrated circuit testing; Integrated circuit yield; Yield estimation; Circuit optimization; Statistical analysis; Sampling methods; Monte carlo methods; Machine learning; Analog circuits; Mixed analog digital integrated circuits

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mukherjee, P. (2014). Detection and Diagnosis of Out-of-Specification Failures in Mixed-Signal Circuits. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/154004

Chicago Manual of Style (16th Edition):

Mukherjee, Parijat. “Detection and Diagnosis of Out-of-Specification Failures in Mixed-Signal Circuits.” 2014. Doctoral Dissertation, Texas A&M University. Accessed September 28, 2020. http://hdl.handle.net/1969.1/154004.

MLA Handbook (7th Edition):

Mukherjee, Parijat. “Detection and Diagnosis of Out-of-Specification Failures in Mixed-Signal Circuits.” 2014. Web. 28 Sep 2020.

Vancouver:

Mukherjee P. Detection and Diagnosis of Out-of-Specification Failures in Mixed-Signal Circuits. [Internet] [Doctoral dissertation]. Texas A&M University; 2014. [cited 2020 Sep 28]. Available from: http://hdl.handle.net/1969.1/154004.

Council of Science Editors:

Mukherjee P. Detection and Diagnosis of Out-of-Specification Failures in Mixed-Signal Circuits. [Doctoral Dissertation]. Texas A&M University; 2014. Available from: http://hdl.handle.net/1969.1/154004


Indian Institute of Science

23. Harish, B P. Process Variability-Aware Performance Modeling In 65 nm CMOS.

Degree: PhD, Faculty of Engineering, 2011, Indian Institute of Science

 With the continued and successful scaling of CMOS, process, voltage, and temperature (PVT), variations are increasing with each technology generation. The process variability impacts all… (more)

Subjects/Keywords: Complementary Metal Oxide Semiconductors; Semiconductors; NAND Gate; Gate Delay Models; CMOS Digital Circuits; Circuit Design; Circuit Delay Performance; Circuit Delay Distribution; CMOS Designs; 65nm CMOS; Electronic Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Harish, B. P. (2011). Process Variability-Aware Performance Modeling In 65 nm CMOS. (Doctoral Dissertation). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/1080

Chicago Manual of Style (16th Edition):

Harish, B P. “Process Variability-Aware Performance Modeling In 65 nm CMOS.” 2011. Doctoral Dissertation, Indian Institute of Science. Accessed September 28, 2020. http://etd.iisc.ac.in/handle/2005/1080.

MLA Handbook (7th Edition):

Harish, B P. “Process Variability-Aware Performance Modeling In 65 nm CMOS.” 2011. Web. 28 Sep 2020.

Vancouver:

Harish BP. Process Variability-Aware Performance Modeling In 65 nm CMOS. [Internet] [Doctoral dissertation]. Indian Institute of Science; 2011. [cited 2020 Sep 28]. Available from: http://etd.iisc.ac.in/handle/2005/1080.

Council of Science Editors:

Harish BP. Process Variability-Aware Performance Modeling In 65 nm CMOS. [Doctoral Dissertation]. Indian Institute of Science; 2011. Available from: http://etd.iisc.ac.in/handle/2005/1080


University of Utah

24. You, Junbok. Design and optimization of asynchronous network-on-chip.

Degree: PhD, Electrical & Computer Engineering, 2011, University of Utah

 The bandwidth requirement for each link on a network-on-chip (NoC) may differ based on topology and traffic properties of the IP cores. Available bandwidth on… (more)

Subjects/Keywords: Asynchronous circuit design; Digital VLSI design; Interconnect system; Network-on-chip; System-on-chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

You, J. (2011). Design and optimization of asynchronous network-on-chip. (Doctoral Dissertation). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/564/rec/633

Chicago Manual of Style (16th Edition):

You, Junbok. “Design and optimization of asynchronous network-on-chip.” 2011. Doctoral Dissertation, University of Utah. Accessed September 28, 2020. http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/564/rec/633.

MLA Handbook (7th Edition):

You, Junbok. “Design and optimization of asynchronous network-on-chip.” 2011. Web. 28 Sep 2020.

Vancouver:

You J. Design and optimization of asynchronous network-on-chip. [Internet] [Doctoral dissertation]. University of Utah; 2011. [cited 2020 Sep 28]. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/564/rec/633.

Council of Science Editors:

You J. Design and optimization of asynchronous network-on-chip. [Doctoral Dissertation]. University of Utah; 2011. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/564/rec/633


Universidade do Rio Grande do Sul

25. Neutzling, Augusto. Thereshold logic technology mapping for emerging nanotechnologies.

Degree: 2017, Universidade do Rio Grande do Sul

Threshold logic is a powerful alternative paradigm for realizing Boolean functions in digital circuit design. A threshold logic function (TLF) can be roughly defined as… (more)

Subjects/Keywords: Logic synthesis; Microeletrônica; Circuitos digitais; Digital circuit; Technology mapping; Threshold logic; Majority logic; Nanotechnologies

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Neutzling, A. (2017). Thereshold logic technology mapping for emerging nanotechnologies. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/180356

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Neutzling, Augusto. “Thereshold logic technology mapping for emerging nanotechnologies.” 2017. Thesis, Universidade do Rio Grande do Sul. Accessed September 28, 2020. http://hdl.handle.net/10183/180356.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Neutzling, Augusto. “Thereshold logic technology mapping for emerging nanotechnologies.” 2017. Web. 28 Sep 2020.

Vancouver:

Neutzling A. Thereshold logic technology mapping for emerging nanotechnologies. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2017. [cited 2020 Sep 28]. Available from: http://hdl.handle.net/10183/180356.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Neutzling A. Thereshold logic technology mapping for emerging nanotechnologies. [Thesis]. Universidade do Rio Grande do Sul; 2017. Available from: http://hdl.handle.net/10183/180356

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Penn State University

26. Kim, Moon Seok. DIGITAL/MIXED-SIGNAL CIRCUIT DESIGNS WITH STEEP SLOPE III-V TUNNEL TRANSISTORS.

Degree: 2016, Penn State University

 The scaling of silicon complementary metal-oxide-semiconductor (CMOS) has long been the driving force in the improvement of device performance, increase of transistor density, and circuit-energy… (more)

Subjects/Keywords: Steep Slope Transistor; Heterojunction Tunnel FETs; TFETs; HTFETs; Digital/Mixed-Signal Circuit Designs; Energy Efficiency

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APA (6th Edition):

Kim, M. S. (2016). DIGITAL/MIXED-SIGNAL CIRCUIT DESIGNS WITH STEEP SLOPE III-V TUNNEL TRANSISTORS. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/13048mqk5211

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kim, Moon Seok. “DIGITAL/MIXED-SIGNAL CIRCUIT DESIGNS WITH STEEP SLOPE III-V TUNNEL TRANSISTORS.” 2016. Thesis, Penn State University. Accessed September 28, 2020. https://submit-etda.libraries.psu.edu/catalog/13048mqk5211.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kim, Moon Seok. “DIGITAL/MIXED-SIGNAL CIRCUIT DESIGNS WITH STEEP SLOPE III-V TUNNEL TRANSISTORS.” 2016. Web. 28 Sep 2020.

Vancouver:

Kim MS. DIGITAL/MIXED-SIGNAL CIRCUIT DESIGNS WITH STEEP SLOPE III-V TUNNEL TRANSISTORS. [Internet] [Thesis]. Penn State University; 2016. [cited 2020 Sep 28]. Available from: https://submit-etda.libraries.psu.edu/catalog/13048mqk5211.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kim MS. DIGITAL/MIXED-SIGNAL CIRCUIT DESIGNS WITH STEEP SLOPE III-V TUNNEL TRANSISTORS. [Thesis]. Penn State University; 2016. Available from: https://submit-etda.libraries.psu.edu/catalog/13048mqk5211

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Addis Ababa University

27. Demisew, Teferi. Modeling Carbon Nanotube Field Effect Transistor for Analog and Digital Circuit Design with VHDL-AMS .

Degree: 2011, Addis Ababa University

 The objective of this thesis is to study the basic electronic properties of carbon nanotubes (CNTs here after) and to model the I-V characteristics of… (more)

Subjects/Keywords: Modeling Carbon Nanotube; Field Effect Transistor; Analog and Digital Circuit Design with VHDL-AMS

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Demisew, T. (2011). Modeling Carbon Nanotube Field Effect Transistor for Analog and Digital Circuit Design with VHDL-AMS . (Thesis). Addis Ababa University. Retrieved from http://etd.aau.edu.et/dspace/handle/123456789/5068

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Demisew, Teferi. “Modeling Carbon Nanotube Field Effect Transistor for Analog and Digital Circuit Design with VHDL-AMS .” 2011. Thesis, Addis Ababa University. Accessed September 28, 2020. http://etd.aau.edu.et/dspace/handle/123456789/5068.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Demisew, Teferi. “Modeling Carbon Nanotube Field Effect Transistor for Analog and Digital Circuit Design with VHDL-AMS .” 2011. Web. 28 Sep 2020.

Vancouver:

Demisew T. Modeling Carbon Nanotube Field Effect Transistor for Analog and Digital Circuit Design with VHDL-AMS . [Internet] [Thesis]. Addis Ababa University; 2011. [cited 2020 Sep 28]. Available from: http://etd.aau.edu.et/dspace/handle/123456789/5068.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Demisew T. Modeling Carbon Nanotube Field Effect Transistor for Analog and Digital Circuit Design with VHDL-AMS . [Thesis]. Addis Ababa University; 2011. Available from: http://etd.aau.edu.et/dspace/handle/123456789/5068

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Universidade do Rio Grande do Sul

28. Butzen, Paulo Francisco. Aging aware design techniques and CMOS gate degradation estimative.

Degree: 2012, Universidade do Rio Grande do Sul

O advento da utilização de circuitos integrados pela sociedade se deu por dois motivos. O primeiro consiste na miniaturização das dimensões dos dispositivos integrados. Essa… (more)

Subjects/Keywords: Digital integrated circuit design; Microeletrônica; Cmos; Logic gates; CMOS technology; Aging effects; Modeling; Reliability

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Butzen, P. F. (2012). Aging aware design techniques and CMOS gate degradation estimative. (Thesis). Universidade do Rio Grande do Sul. Retrieved from http://hdl.handle.net/10183/61868

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Butzen, Paulo Francisco. “Aging aware design techniques and CMOS gate degradation estimative.” 2012. Thesis, Universidade do Rio Grande do Sul. Accessed September 28, 2020. http://hdl.handle.net/10183/61868.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Butzen, Paulo Francisco. “Aging aware design techniques and CMOS gate degradation estimative.” 2012. Web. 28 Sep 2020.

Vancouver:

Butzen PF. Aging aware design techniques and CMOS gate degradation estimative. [Internet] [Thesis]. Universidade do Rio Grande do Sul; 2012. [cited 2020 Sep 28]. Available from: http://hdl.handle.net/10183/61868.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Butzen PF. Aging aware design techniques and CMOS gate degradation estimative. [Thesis]. Universidade do Rio Grande do Sul; 2012. Available from: http://hdl.handle.net/10183/61868

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

29. Ou, Shih-hao. Design of CMOS voltage-to-time converter for CM/DM analog-to-digital conversion.

Degree: Master, Electrical Engineering, 2013, NSYSU

 With advances in integrated circuit (IC) processing technology, medical devices are becoming miniature, with low power consumption. Therefore, wearable and implantable applications become feasible, and… (more)

Subjects/Keywords: Common-mode; Differential-mode; Analog-to-digital converter; Voltage-to-time converter; Integrated circuit

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ou, S. (2013). Design of CMOS voltage-to-time converter for CM/DM analog-to-digital conversion. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0826113-161753

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ou, Shih-hao. “Design of CMOS voltage-to-time converter for CM/DM analog-to-digital conversion.” 2013. Thesis, NSYSU. Accessed September 28, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0826113-161753.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ou, Shih-hao. “Design of CMOS voltage-to-time converter for CM/DM analog-to-digital conversion.” 2013. Web. 28 Sep 2020.

Vancouver:

Ou S. Design of CMOS voltage-to-time converter for CM/DM analog-to-digital conversion. [Internet] [Thesis]. NSYSU; 2013. [cited 2020 Sep 28]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0826113-161753.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ou S. Design of CMOS voltage-to-time converter for CM/DM analog-to-digital conversion. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0826113-161753

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

30. Nien, Chen-ming. Implementation of Front-end Compression for a Wireless BAN Sensor Node.

Degree: Master, Electrical Engineering, 2013, NSYSU

 With the aging of the world population, the importance of long-term medical monitoring has increased along with the need for home care services for the… (more)

Subjects/Keywords: Body area network (BAN); Curvature compression; Huffman coding; Microcontroller coding; FPGA digital circuit design

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Nien, C. (2013). Implementation of Front-end Compression for a Wireless BAN Sensor Node. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0827113-191922

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Nien, Chen-ming. “Implementation of Front-end Compression for a Wireless BAN Sensor Node.” 2013. Thesis, NSYSU. Accessed September 28, 2020. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0827113-191922.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Nien, Chen-ming. “Implementation of Front-end Compression for a Wireless BAN Sensor Node.” 2013. Web. 28 Sep 2020.

Vancouver:

Nien C. Implementation of Front-end Compression for a Wireless BAN Sensor Node. [Internet] [Thesis]. NSYSU; 2013. [cited 2020 Sep 28]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0827113-191922.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Nien C. Implementation of Front-end Compression for a Wireless BAN Sensor Node. [Thesis]. NSYSU; 2013. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0827113-191922

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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