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You searched for subject:(deadlock). Showing records 1 – 30 of 68 total matches.

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Universidade Nova

1. Parreira, Daniel Luis Landeiroto. Data-centric concurrency control on the java programming language.

Degree: 2013, Universidade Nova

Dissertação para obtenção do Grau de Mestre em Engenharia Informática

The multi-core paradigm has propelled shared-memory concurrent programming to an important role in software development.… (more)

Subjects/Keywords: Data-centric; Concurrency control; Deadlock-freedom; Atomicity

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Parreira, D. L. L. (2013). Data-centric concurrency control on the java programming language. (Thesis). Universidade Nova. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/10814

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Parreira, Daniel Luis Landeiroto. “Data-centric concurrency control on the java programming language.” 2013. Thesis, Universidade Nova. Accessed September 19, 2019. http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/10814.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Parreira, Daniel Luis Landeiroto. “Data-centric concurrency control on the java programming language.” 2013. Web. 19 Sep 2019.

Vancouver:

Parreira DLL. Data-centric concurrency control on the java programming language. [Internet] [Thesis]. Universidade Nova; 2013. [cited 2019 Sep 19]. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/10814.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Parreira DLL. Data-centric concurrency control on the java programming language. [Thesis]. Universidade Nova; 2013. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/10814

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

2. LÔBO, Rafael Brandão. Deadlocks as runtime exceptions .

Degree: 2015, Universidade Federal de Pernambuco

 Deadlocks are a common type of concurrency bug. When a deadlock occurs, it is difficult to clearly determine whether there is an actual deadlock or… (more)

Subjects/Keywords: Deadlock; Concorrência; Tratamento de Exceção; Estudos Empíricos; Deadlock; Concurrency; Exception Handling; Empirical Studies

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

LÔBO, R. B. (2015). Deadlocks as runtime exceptions . (Masters Thesis). Universidade Federal de Pernambuco. Retrieved from https://repositorio.ufpe.br/handle/123456789/17332

Chicago Manual of Style (16th Edition):

LÔBO, Rafael Brandão. “Deadlocks as runtime exceptions .” 2015. Masters Thesis, Universidade Federal de Pernambuco. Accessed September 19, 2019. https://repositorio.ufpe.br/handle/123456789/17332.

MLA Handbook (7th Edition):

LÔBO, Rafael Brandão. “Deadlocks as runtime exceptions .” 2015. Web. 19 Sep 2019.

Vancouver:

LÔBO RB. Deadlocks as runtime exceptions . [Internet] [Masters thesis]. Universidade Federal de Pernambuco; 2015. [cited 2019 Sep 19]. Available from: https://repositorio.ufpe.br/handle/123456789/17332.

Council of Science Editors:

LÔBO RB. Deadlocks as runtime exceptions . [Masters Thesis]. Universidade Federal de Pernambuco; 2015. Available from: https://repositorio.ufpe.br/handle/123456789/17332


Rice University

3. Stephens, Brent. Handling Congestion and Routing Failures in Data Center Networking.

Degree: PhD, Engineering, 2015, Rice University

 Today's data center networks are made of highly reliable components. Nonetheless, given the current scale of data center networks and the bursty traffic patterns of… (more)

Subjects/Keywords: DCN; Data Center; Local Fast Failover; DCB; Lossless Ethernet; Plinko; DF-EDST; TCP-Bolt; Deadlock; Deadlock-free Routing; DFR

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Stephens, B. (2015). Handling Congestion and Routing Failures in Data Center Networking. (Doctoral Dissertation). Rice University. Retrieved from http://hdl.handle.net/1911/88166

Chicago Manual of Style (16th Edition):

Stephens, Brent. “Handling Congestion and Routing Failures in Data Center Networking.” 2015. Doctoral Dissertation, Rice University. Accessed September 19, 2019. http://hdl.handle.net/1911/88166.

MLA Handbook (7th Edition):

Stephens, Brent. “Handling Congestion and Routing Failures in Data Center Networking.” 2015. Web. 19 Sep 2019.

Vancouver:

Stephens B. Handling Congestion and Routing Failures in Data Center Networking. [Internet] [Doctoral dissertation]. Rice University; 2015. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/1911/88166.

Council of Science Editors:

Stephens B. Handling Congestion and Routing Failures in Data Center Networking. [Doctoral Dissertation]. Rice University; 2015. Available from: http://hdl.handle.net/1911/88166


Universidade do Rio Grande do Norte

4. Pereira, Dalay Israel de Almeida. An extension of a tool for the formal support for component-based development .

Degree: 2017, Universidade do Rio Grande do Norte

 Using the component-based development approach, the system complexity is reduced and its maintenance is facilitated, bringing more reliability and reuse of components. However, the composition… (more)

Subjects/Keywords: Sistemas baseados em componentes; CSP; Automação; SMT; Deadlock; Ferramenta; Extensão

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pereira, D. I. d. A. (2017). An extension of a tool for the formal support for component-based development . (Masters Thesis). Universidade do Rio Grande do Norte. Retrieved from http://repositorio.ufrn.br/handle/123456789/24200

Chicago Manual of Style (16th Edition):

Pereira, Dalay Israel de Almeida. “An extension of a tool for the formal support for component-based development .” 2017. Masters Thesis, Universidade do Rio Grande do Norte. Accessed September 19, 2019. http://repositorio.ufrn.br/handle/123456789/24200.

MLA Handbook (7th Edition):

Pereira, Dalay Israel de Almeida. “An extension of a tool for the formal support for component-based development .” 2017. Web. 19 Sep 2019.

Vancouver:

Pereira DIdA. An extension of a tool for the formal support for component-based development . [Internet] [Masters thesis]. Universidade do Rio Grande do Norte; 2017. [cited 2019 Sep 19]. Available from: http://repositorio.ufrn.br/handle/123456789/24200.

Council of Science Editors:

Pereira DIdA. An extension of a tool for the formal support for component-based development . [Masters Thesis]. Universidade do Rio Grande do Norte; 2017. Available from: http://repositorio.ufrn.br/handle/123456789/24200


University of Ontario Institute of Technology

5. Kelk, David. CORE: a framework for the automatic repair of concurrency bugs.

Degree: 2015, University of Ontario Institute of Technology

 Desktop computers now contain 2, 4 or even 8 processors. To benefit from them programs must be written to work in parallel. If writing good… (more)

Subjects/Keywords: Genetic algorithm; Concurrency; Automatic repair; Deadlock; Data race

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kelk, D. (2015). CORE: a framework for the automatic repair of concurrency bugs. (Thesis). University of Ontario Institute of Technology. Retrieved from http://hdl.handle.net/10155/505

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kelk, David. “CORE: a framework for the automatic repair of concurrency bugs.” 2015. Thesis, University of Ontario Institute of Technology. Accessed September 19, 2019. http://hdl.handle.net/10155/505.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kelk, David. “CORE: a framework for the automatic repair of concurrency bugs.” 2015. Web. 19 Sep 2019.

Vancouver:

Kelk D. CORE: a framework for the automatic repair of concurrency bugs. [Internet] [Thesis]. University of Ontario Institute of Technology; 2015. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/10155/505.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kelk D. CORE: a framework for the automatic repair of concurrency bugs. [Thesis]. University of Ontario Institute of Technology; 2015. Available from: http://hdl.handle.net/10155/505

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Anna University

6. Srinivasan.S. Efficient design and evaluation of distributed deadlock detection and resolution in generalized model;.

Degree: 2013, Anna University

Deadlock is one of the canonical problems in distributed systems. It arises naturally in distributed systems such as distributed databases, distributed operating systems and store… (more)

Subjects/Keywords: Deadlock; generalized model; centralized algorithms; distributed algorithms; JAVA

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Srinivasan.S. (2013). Efficient design and evaluation of distributed deadlock detection and resolution in generalized model;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/13650

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Srinivasan.S. “Efficient design and evaluation of distributed deadlock detection and resolution in generalized model;.” 2013. Thesis, Anna University. Accessed September 19, 2019. http://shodhganga.inflibnet.ac.in/handle/10603/13650.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Srinivasan.S. “Efficient design and evaluation of distributed deadlock detection and resolution in generalized model;.” 2013. Web. 19 Sep 2019.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete

Vancouver:

Srinivasan.S. Efficient design and evaluation of distributed deadlock detection and resolution in generalized model;. [Internet] [Thesis]. Anna University; 2013. [cited 2019 Sep 19]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/13650.

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Srinivasan.S. Efficient design and evaluation of distributed deadlock detection and resolution in generalized model;. [Thesis]. Anna University; 2013. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/13650

Note: this citation may be lacking information needed for this citation format:
Author name may be incomplete
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

7. Zheng, Yi-Xue. Fault-Tolerant Deadlock-Free Custom NoC Topology Synthesis for Three-Dimensional Integrated Circuits.

Degree: Master, Computer Science and Engineering, 2011, NSYSU

 This thesis proposes a synthesis methodology which is capable of fault-tolerance and deadlock-free for constructing a custom NoC topology in 3D ICs. In this thesis,… (more)

Subjects/Keywords: 3D ICs; deadlock-free; topology; fault tolerant; Network-on-Chip

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zheng, Y. (2011). Fault-Tolerant Deadlock-Free Custom NoC Topology Synthesis for Three-Dimensional Integrated Circuits. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801111-164321

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zheng, Yi-Xue. “Fault-Tolerant Deadlock-Free Custom NoC Topology Synthesis for Three-Dimensional Integrated Circuits.” 2011. Thesis, NSYSU. Accessed September 19, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801111-164321.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zheng, Yi-Xue. “Fault-Tolerant Deadlock-Free Custom NoC Topology Synthesis for Three-Dimensional Integrated Circuits.” 2011. Web. 19 Sep 2019.

Vancouver:

Zheng Y. Fault-Tolerant Deadlock-Free Custom NoC Topology Synthesis for Three-Dimensional Integrated Circuits. [Internet] [Thesis]. NSYSU; 2011. [cited 2019 Sep 19]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801111-164321.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zheng Y. Fault-Tolerant Deadlock-Free Custom NoC Topology Synthesis for Three-Dimensional Integrated Circuits. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0801111-164321

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

8. W.M.M., Tharindu Weerakoon. Artificial Potential Field and Feature Extraction Method for Mobile Robot Path Planning in Structured Environments : 人工ポテンシャル場と特徴抽出法に基づく屋内環境における移動ロボットの経路計画.

Degree: 博士(工学), 2017, Kyushu Institute of Technology / 九州工業大学

 Mobile robots are widely used in many applications in industrial fields as well as in academic and research fields. The robot path planning problem is… (more)

Subjects/Keywords: Artificial potential field; Local minima; Deadlock; Path planning; Segmentation; Feature extraction

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

W.M.M., T. W. (2017). Artificial Potential Field and Feature Extraction Method for Mobile Robot Path Planning in Structured Environments : 人工ポテンシャル場と特徴抽出法に基づく屋内環境における移動ロボットの経路計画. (Thesis). Kyushu Institute of Technology / 九州工業大学. Retrieved from http://hdl.handle.net/10228/5713

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

W.M.M., Tharindu Weerakoon. “Artificial Potential Field and Feature Extraction Method for Mobile Robot Path Planning in Structured Environments : 人工ポテンシャル場と特徴抽出法に基づく屋内環境における移動ロボットの経路計画.” 2017. Thesis, Kyushu Institute of Technology / 九州工業大学. Accessed September 19, 2019. http://hdl.handle.net/10228/5713.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

W.M.M., Tharindu Weerakoon. “Artificial Potential Field and Feature Extraction Method for Mobile Robot Path Planning in Structured Environments : 人工ポテンシャル場と特徴抽出法に基づく屋内環境における移動ロボットの経路計画.” 2017. Web. 19 Sep 2019.

Vancouver:

W.M.M. TW. Artificial Potential Field and Feature Extraction Method for Mobile Robot Path Planning in Structured Environments : 人工ポテンシャル場と特徴抽出法に基づく屋内環境における移動ロボットの経路計画. [Internet] [Thesis]. Kyushu Institute of Technology / 九州工業大学; 2017. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/10228/5713.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

W.M.M. TW. Artificial Potential Field and Feature Extraction Method for Mobile Robot Path Planning in Structured Environments : 人工ポテンシャル場と特徴抽出法に基づく屋内環境における移動ロボットの経路計画. [Thesis]. Kyushu Institute of Technology / 九州工業大学; 2017. Available from: http://hdl.handle.net/10228/5713

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Southern California

9. Chen, Lizhong. Design of low-power and resource-efficient on-chip networks.

Degree: PhD, Computer Engineering, 2014, University of Southern California

 Many‐core processors will continue to proliferate in the next decade across the entire computing landscape. While on‐chip networks provide a potentially scalable interconnection solution for… (more)

Subjects/Keywords: network‐on‐chip; power; energy; power‐gating; deadlock; flow control

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chen, L. (2014). Design of low-power and resource-efficient on-chip networks. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/429487/rec/1867

Chicago Manual of Style (16th Edition):

Chen, Lizhong. “Design of low-power and resource-efficient on-chip networks.” 2014. Doctoral Dissertation, University of Southern California. Accessed September 19, 2019. http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/429487/rec/1867.

MLA Handbook (7th Edition):

Chen, Lizhong. “Design of low-power and resource-efficient on-chip networks.” 2014. Web. 19 Sep 2019.

Vancouver:

Chen L. Design of low-power and resource-efficient on-chip networks. [Internet] [Doctoral dissertation]. University of Southern California; 2014. [cited 2019 Sep 19]. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/429487/rec/1867.

Council of Science Editors:

Chen L. Design of low-power and resource-efficient on-chip networks. [Doctoral Dissertation]. University of Southern California; 2014. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll3/id/429487/rec/1867

10. Ezpeleta Mateo, Joaquín. Análisis, prevención y evitación de bloqueos en sistemas secuenciales de asignación de recursos.

Degree: 2011, Universidad de Zaragoza

 El propósito de este trabajo es generalizar y extender los resultados existentes en el análisis, prevención y evitación de bloqueos en sistemas de asignación de… (more)

Subjects/Keywords: bloqueos; cerrojos; redes de Petri; deadlock; siphons; petri nets

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APA (6th Edition):

Ezpeleta Mateo, J. (2011). Análisis, prevención y evitación de bloqueos en sistemas secuenciales de asignación de recursos. (Thesis). Universidad de Zaragoza. Retrieved from http://zaguan.unizar.es/record/4315

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ezpeleta Mateo, Joaquín. “Análisis, prevención y evitación de bloqueos en sistemas secuenciales de asignación de recursos.” 2011. Thesis, Universidad de Zaragoza. Accessed September 19, 2019. http://zaguan.unizar.es/record/4315.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ezpeleta Mateo, Joaquín. “Análisis, prevención y evitación de bloqueos en sistemas secuenciales de asignación de recursos.” 2011. Web. 19 Sep 2019.

Vancouver:

Ezpeleta Mateo J. Análisis, prevención y evitación de bloqueos en sistemas secuenciales de asignación de recursos. [Internet] [Thesis]. Universidad de Zaragoza; 2011. [cited 2019 Sep 19]. Available from: http://zaguan.unizar.es/record/4315.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ezpeleta Mateo J. Análisis, prevención y evitación de bloqueos en sistemas secuenciales de asignación de recursos. [Thesis]. Universidad de Zaragoza; 2011. Available from: http://zaguan.unizar.es/record/4315

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

11. Sorrentino, Francesco. Algorithmic techniques for predictive testing of concurrent programs and distributed systems.

Degree: PhD, 0112, 2014, University of Illinois – Urbana-Champaign

 The rise of multicore hardware platforms has lead to a new era of computing. In order to take full advantage of the power of multicore… (more)

Subjects/Keywords: Testing; Concurrency; Cloud; Diagnosis; Bugs; Data-Race; Deadlock; Null-Pointer; Atomicity

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sorrentino, F. (2014). Algorithmic techniques for predictive testing of concurrent programs and distributed systems. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/49713

Chicago Manual of Style (16th Edition):

Sorrentino, Francesco. “Algorithmic techniques for predictive testing of concurrent programs and distributed systems.” 2014. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed September 19, 2019. http://hdl.handle.net/2142/49713.

MLA Handbook (7th Edition):

Sorrentino, Francesco. “Algorithmic techniques for predictive testing of concurrent programs and distributed systems.” 2014. Web. 19 Sep 2019.

Vancouver:

Sorrentino F. Algorithmic techniques for predictive testing of concurrent programs and distributed systems. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2014. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/2142/49713.

Council of Science Editors:

Sorrentino F. Algorithmic techniques for predictive testing of concurrent programs and distributed systems. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2014. Available from: http://hdl.handle.net/2142/49713


Universidad de Cantabria

12. Fuentes Sáez, Pablo. Interconexiones balanceadas y eficientes para supercomputadores Exascale.

Degree: Departamento de Electrónica y Computadores, 2017, Universidad de Cantabria

 Increasing computational needs demand Exascale machines; one of the approaches to develop such machines is to increase the number of nodes, what places a stronger… (more)

Subjects/Keywords: Evitación de deadlock; Evaluación de rendimiento; Contención; Red de interconexión; Throughput fairness; Graph500; Dragonfly; Exascale; Deadlock avoidance; Performance evaluation; Contention; Interconnection network; Arquitectura y Tecnología de Computadores; 004; 621.3

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APA (6th Edition):

Fuentes Sáez, P. (2017). Interconexiones balanceadas y eficientes para supercomputadores Exascale. (Thesis). Universidad de Cantabria. Retrieved from http://hdl.handle.net/10803/440520

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Fuentes Sáez, Pablo. “Interconexiones balanceadas y eficientes para supercomputadores Exascale.” 2017. Thesis, Universidad de Cantabria. Accessed September 19, 2019. http://hdl.handle.net/10803/440520.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Fuentes Sáez, Pablo. “Interconexiones balanceadas y eficientes para supercomputadores Exascale.” 2017. Web. 19 Sep 2019.

Vancouver:

Fuentes Sáez P. Interconexiones balanceadas y eficientes para supercomputadores Exascale. [Internet] [Thesis]. Universidad de Cantabria; 2017. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/10803/440520.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Fuentes Sáez P. Interconexiones balanceadas y eficientes para supercomputadores Exascale. [Thesis]. Universidad de Cantabria; 2017. Available from: http://hdl.handle.net/10803/440520

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

13. Shaukat, Noman. B-RPM: An Efficient One-to-Many Communication Framework for On-Chip Networks.

Degree: 2012, Texas A&M University

 The prevalence of multicore architectures has accentuated the need for scalable on-chip communication media. Various parallel applications and programming paradigms use a mix of unicast… (more)

Subjects/Keywords: Multicast; On-Chip Networks; B-RPM; Dynamically Sized Virtual Networks; Virtual Networks; Deadlock

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shaukat, N. (2012). B-RPM: An Efficient One-to-Many Communication Framework for On-Chip Networks. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11731

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shaukat, Noman. “B-RPM: An Efficient One-to-Many Communication Framework for On-Chip Networks.” 2012. Thesis, Texas A&M University. Accessed September 19, 2019. http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11731.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shaukat, Noman. “B-RPM: An Efficient One-to-Many Communication Framework for On-Chip Networks.” 2012. Web. 19 Sep 2019.

Vancouver:

Shaukat N. B-RPM: An Efficient One-to-Many Communication Framework for On-Chip Networks. [Internet] [Thesis]. Texas A&M University; 2012. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11731.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shaukat N. B-RPM: An Efficient One-to-Many Communication Framework for On-Chip Networks. [Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11731

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

14. Li, Ran. Performance optimization of complex resource allocation systems.

Degree: PhD, Industrial and Systems Engineering, 2016, Georgia Tech

 The typical control objective for a sequential resource allocation system (RAS) is the optimization of some (time-based) performance index, while ensuring the logical/behavioral correctness of… (more)

Subjects/Keywords: Resource allocation systems; Deadlock avoidance; Petri nets; Markov decision processes; Stochastic approximation; Disaggregation

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Li, R. (2016). Performance optimization of complex resource allocation systems. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/56273

Chicago Manual of Style (16th Edition):

Li, Ran. “Performance optimization of complex resource allocation systems.” 2016. Doctoral Dissertation, Georgia Tech. Accessed September 19, 2019. http://hdl.handle.net/1853/56273.

MLA Handbook (7th Edition):

Li, Ran. “Performance optimization of complex resource allocation systems.” 2016. Web. 19 Sep 2019.

Vancouver:

Li R. Performance optimization of complex resource allocation systems. [Internet] [Doctoral dissertation]. Georgia Tech; 2016. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/1853/56273.

Council of Science Editors:

Li R. Performance optimization of complex resource allocation systems. [Doctoral Dissertation]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/56273


Penn State University

15. Sidhu, Amiteshwar Singh. SEARCH-BASED MAXIMALLY PERMISSIVE DEADLOCK AVOIDANCE IN FLEXIBLE MANUFACTURING CELLS.

Degree: MS, Industrial Engineering, 2009, Penn State University

 A search based maximally permissive method for deadlock avoidance was developed in this research. The method developed is maximally permissive in that no safe part… (more)

Subjects/Keywords: Problem Reduction; Look Ahead Search; Search Algorithms; Flexible Manufacturing Systems; Deadlock Avoidance; Circuit Detection

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sidhu, A. S. (2009). SEARCH-BASED MAXIMALLY PERMISSIVE DEADLOCK AVOIDANCE IN FLEXIBLE MANUFACTURING CELLS. (Masters Thesis). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/10124

Chicago Manual of Style (16th Edition):

Sidhu, Amiteshwar Singh. “SEARCH-BASED MAXIMALLY PERMISSIVE DEADLOCK AVOIDANCE IN FLEXIBLE MANUFACTURING CELLS.” 2009. Masters Thesis, Penn State University. Accessed September 19, 2019. https://etda.libraries.psu.edu/catalog/10124.

MLA Handbook (7th Edition):

Sidhu, Amiteshwar Singh. “SEARCH-BASED MAXIMALLY PERMISSIVE DEADLOCK AVOIDANCE IN FLEXIBLE MANUFACTURING CELLS.” 2009. Web. 19 Sep 2019.

Vancouver:

Sidhu AS. SEARCH-BASED MAXIMALLY PERMISSIVE DEADLOCK AVOIDANCE IN FLEXIBLE MANUFACTURING CELLS. [Internet] [Masters thesis]. Penn State University; 2009. [cited 2019 Sep 19]. Available from: https://etda.libraries.psu.edu/catalog/10124.

Council of Science Editors:

Sidhu AS. SEARCH-BASED MAXIMALLY PERMISSIVE DEADLOCK AVOIDANCE IN FLEXIBLE MANUFACTURING CELLS. [Masters Thesis]. Penn State University; 2009. Available from: https://etda.libraries.psu.edu/catalog/10124


UCLA

16. Eslamimehr, Mohammad Mahdi. Directed Testing of Event-Driven and Parallel Programs.

Degree: Computer Science, 2014, UCLA

 Detecting computational states of a program, where safety requirements have been violated, is the main task of a software tester. We focus on three critical… (more)

Subjects/Keywords: Computer science; Concurrent Programs; Data Race; Deadlock; Directed Testing; Event-Driven Software; Stack Size

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Eslamimehr, M. M. (2014). Directed Testing of Event-Driven and Parallel Programs. (Thesis). UCLA. Retrieved from http://www.escholarship.org/uc/item/7bb4k79b

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Eslamimehr, Mohammad Mahdi. “Directed Testing of Event-Driven and Parallel Programs.” 2014. Thesis, UCLA. Accessed September 19, 2019. http://www.escholarship.org/uc/item/7bb4k79b.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Eslamimehr, Mohammad Mahdi. “Directed Testing of Event-Driven and Parallel Programs.” 2014. Web. 19 Sep 2019.

Vancouver:

Eslamimehr MM. Directed Testing of Event-Driven and Parallel Programs. [Internet] [Thesis]. UCLA; 2014. [cited 2019 Sep 19]. Available from: http://www.escholarship.org/uc/item/7bb4k79b.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Eslamimehr MM. Directed Testing of Event-Driven and Parallel Programs. [Thesis]. UCLA; 2014. Available from: http://www.escholarship.org/uc/item/7bb4k79b

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

17. Li, Peng. The Synchronized Filtering Dataflow.

Degree: PhD, Computer Science & Engineering, 2014, Washington University in St. Louis

  In the past decade, the world has seen the rise of big data, which calls for a paradigm shift in data processing. Streaming processing,… (more)

Subjects/Keywords: Dataflow; Deadlock Avoidance; Filtering; Engineering

…101 Figure 7.3 A deadlock example. w filters 46 of 64 consumed data tokens, and no other… …synchronized, applications can deadlock due to empty and full channel buffers. To avoid deadlocks and… …particular, deadlock avoidance. 1.3 Problem Statement In streaming computing, some nodes… …process unbounded streams, which means 10 deadlock given bounded memory5 . Our goal is to… …artificial deadlock” to distinguish from deadlocks caused by all empty channels [49, 43]… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Li, P. (2014). The Synchronized Filtering Dataflow. (Doctoral Dissertation). Washington University in St. Louis. Retrieved from https://openscholarship.wustl.edu/eng_etds/61

Chicago Manual of Style (16th Edition):

Li, Peng. “The Synchronized Filtering Dataflow.” 2014. Doctoral Dissertation, Washington University in St. Louis. Accessed September 19, 2019. https://openscholarship.wustl.edu/eng_etds/61.

MLA Handbook (7th Edition):

Li, Peng. “The Synchronized Filtering Dataflow.” 2014. Web. 19 Sep 2019.

Vancouver:

Li P. The Synchronized Filtering Dataflow. [Internet] [Doctoral dissertation]. Washington University in St. Louis; 2014. [cited 2019 Sep 19]. Available from: https://openscholarship.wustl.edu/eng_etds/61.

Council of Science Editors:

Li P. The Synchronized Filtering Dataflow. [Doctoral Dissertation]. Washington University in St. Louis; 2014. Available from: https://openscholarship.wustl.edu/eng_etds/61


University of Manchester

18. Zhang, Guangda. FAULT TOLERANT TECHNIQUES FOR ASYNCHRONOUS NETWORKS ON CHIP.

Degree: 2016, University of Manchester

 Advancing semiconductor technology is boosting the core count on a single chip to achieve continuously increasing performance, posing a growing demand for scalable, efficient and… (more)

Subjects/Keywords: Network-on-Chip; asynchronous; QDI; fault tolerance; deadlock; permanent fault; transient fault; GALS

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhang, G. (2016). FAULT TOLERANT TECHNIQUES FOR ASYNCHRONOUS NETWORKS ON CHIP. (Doctoral Dissertation). University of Manchester. Retrieved from http://www.manchester.ac.uk/escholar/uk-ac-man-scw:301183

Chicago Manual of Style (16th Edition):

Zhang, Guangda. “FAULT TOLERANT TECHNIQUES FOR ASYNCHRONOUS NETWORKS ON CHIP.” 2016. Doctoral Dissertation, University of Manchester. Accessed September 19, 2019. http://www.manchester.ac.uk/escholar/uk-ac-man-scw:301183.

MLA Handbook (7th Edition):

Zhang, Guangda. “FAULT TOLERANT TECHNIQUES FOR ASYNCHRONOUS NETWORKS ON CHIP.” 2016. Web. 19 Sep 2019.

Vancouver:

Zhang G. FAULT TOLERANT TECHNIQUES FOR ASYNCHRONOUS NETWORKS ON CHIP. [Internet] [Doctoral dissertation]. University of Manchester; 2016. [cited 2019 Sep 19]. Available from: http://www.manchester.ac.uk/escholar/uk-ac-man-scw:301183.

Council of Science Editors:

Zhang G. FAULT TOLERANT TECHNIQUES FOR ASYNCHRONOUS NETWORKS ON CHIP. [Doctoral Dissertation]. University of Manchester; 2016. Available from: http://www.manchester.ac.uk/escholar/uk-ac-man-scw:301183


Virginia Tech

19. Pyla, Hari Krishna. Safe Concurrent Programming and Execution.

Degree: PhD, Computer Science, 2013, Virginia Tech

 The increasing prevalence of multi and many core processors has brought the issues of concurrency and parallelism to the forefront of everyday computing. Even for… (more)

Subjects/Keywords: Concurrent Programming; Concurrency Bugs; Program Analysis; Runtime Systems; Deadlock Detection and Recovery; Speculative Parall

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pyla, H. K. (2013). Safe Concurrent Programming and Execution. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/19276

Chicago Manual of Style (16th Edition):

Pyla, Hari Krishna. “Safe Concurrent Programming and Execution.” 2013. Doctoral Dissertation, Virginia Tech. Accessed September 19, 2019. http://hdl.handle.net/10919/19276.

MLA Handbook (7th Edition):

Pyla, Hari Krishna. “Safe Concurrent Programming and Execution.” 2013. Web. 19 Sep 2019.

Vancouver:

Pyla HK. Safe Concurrent Programming and Execution. [Internet] [Doctoral dissertation]. Virginia Tech; 2013. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/10919/19276.

Council of Science Editors:

Pyla HK. Safe Concurrent Programming and Execution. [Doctoral Dissertation]. Virginia Tech; 2013. Available from: http://hdl.handle.net/10919/19276


University of Manchester

20. Zhang, Guangda. Fault tolerant techniques for asynchronous networks on chip.

Degree: PhD, 2016, University of Manchester

 Advancing semiconductor technology is boosting the core count on a single chip to achieve continuously increasing performance, posing a growing demand for scalable, efficient and… (more)

Subjects/Keywords: 621.3815; Network-on-Chip; asynchronous; QDI; fault tolerance; deadlock; permanent fault; transient fault; GALS

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhang, G. (2016). Fault tolerant techniques for asynchronous networks on chip. (Doctoral Dissertation). University of Manchester. Retrieved from https://www.research.manchester.ac.uk/portal/en/theses/fault-tolerant-techniques-for-asynchronous-networks-on-chip(ce820f3a-461a-4e48-b1a3-d98fa6497a68).html ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.694275

Chicago Manual of Style (16th Edition):

Zhang, Guangda. “Fault tolerant techniques for asynchronous networks on chip.” 2016. Doctoral Dissertation, University of Manchester. Accessed September 19, 2019. https://www.research.manchester.ac.uk/portal/en/theses/fault-tolerant-techniques-for-asynchronous-networks-on-chip(ce820f3a-461a-4e48-b1a3-d98fa6497a68).html ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.694275.

MLA Handbook (7th Edition):

Zhang, Guangda. “Fault tolerant techniques for asynchronous networks on chip.” 2016. Web. 19 Sep 2019.

Vancouver:

Zhang G. Fault tolerant techniques for asynchronous networks on chip. [Internet] [Doctoral dissertation]. University of Manchester; 2016. [cited 2019 Sep 19]. Available from: https://www.research.manchester.ac.uk/portal/en/theses/fault-tolerant-techniques-for-asynchronous-networks-on-chip(ce820f3a-461a-4e48-b1a3-d98fa6497a68).html ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.694275.

Council of Science Editors:

Zhang G. Fault tolerant techniques for asynchronous networks on chip. [Doctoral Dissertation]. University of Manchester; 2016. Available from: https://www.research.manchester.ac.uk/portal/en/theses/fault-tolerant-techniques-for-asynchronous-networks-on-chip(ce820f3a-461a-4e48-b1a3-d98fa6497a68).html ; http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.694275

21. Mastandrea, Vicenzo. Analyse de synchronisation dans les objets actifs basée sur les types comportementaux : Analysis of synchronisation patterns in active objects based on behavioural types.

Degree: Docteur es, Informatique, 2017, Côte d'Azur

Le concept d'objet actif est un modèle de calcul puissant utilisé pour définir des systèmes distribués et concurrents. Dans ce travail, nous étudions un modèle… (more)

Subjects/Keywords: Analyse de synchronisation; Objets actifs; Types comportementaux; Deadlock; Synchronisations; Active objects; Behavioural types

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mastandrea, V. (2017). Analyse de synchronisation dans les objets actifs basée sur les types comportementaux : Analysis of synchronisation patterns in active objects based on behavioural types. (Doctoral Dissertation). Côte d'Azur. Retrieved from http://www.theses.fr/2017AZUR4113

Chicago Manual of Style (16th Edition):

Mastandrea, Vicenzo. “Analyse de synchronisation dans les objets actifs basée sur les types comportementaux : Analysis of synchronisation patterns in active objects based on behavioural types.” 2017. Doctoral Dissertation, Côte d'Azur. Accessed September 19, 2019. http://www.theses.fr/2017AZUR4113.

MLA Handbook (7th Edition):

Mastandrea, Vicenzo. “Analyse de synchronisation dans les objets actifs basée sur les types comportementaux : Analysis of synchronisation patterns in active objects based on behavioural types.” 2017. Web. 19 Sep 2019.

Vancouver:

Mastandrea V. Analyse de synchronisation dans les objets actifs basée sur les types comportementaux : Analysis of synchronisation patterns in active objects based on behavioural types. [Internet] [Doctoral dissertation]. Côte d'Azur; 2017. [cited 2019 Sep 19]. Available from: http://www.theses.fr/2017AZUR4113.

Council of Science Editors:

Mastandrea V. Analyse de synchronisation dans les objets actifs basée sur les types comportementaux : Analysis of synchronisation patterns in active objects based on behavioural types. [Doctoral Dissertation]. Côte d'Azur; 2017. Available from: http://www.theses.fr/2017AZUR4113


University of Texas – Austin

22. Santa Maria, Daniel Ruiz. Identifying post-silicon bugs and their root causes through a hardware introspection engine.

Degree: MSin Engineering, Electrical and Computer Engineering, 2017, University of Texas – Austin

 The goal of this project is to design, build, and evaluate new hardware mechanisms to debug post-silicon bugs in Systems-on-Chip (SoCs). Specifically, we aim to… (more)

Subjects/Keywords: Design-for-debug; Anomaly detection; System deadlock; Post-silicon bugs; Hardware introspection engine

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Santa Maria, D. R. (2017). Identifying post-silicon bugs and their root causes through a hardware introspection engine. (Masters Thesis). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/63952

Chicago Manual of Style (16th Edition):

Santa Maria, Daniel Ruiz. “Identifying post-silicon bugs and their root causes through a hardware introspection engine.” 2017. Masters Thesis, University of Texas – Austin. Accessed September 19, 2019. http://hdl.handle.net/2152/63952.

MLA Handbook (7th Edition):

Santa Maria, Daniel Ruiz. “Identifying post-silicon bugs and their root causes through a hardware introspection engine.” 2017. Web. 19 Sep 2019.

Vancouver:

Santa Maria DR. Identifying post-silicon bugs and their root causes through a hardware introspection engine. [Internet] [Masters thesis]. University of Texas – Austin; 2017. [cited 2019 Sep 19]. Available from: http://hdl.handle.net/2152/63952.

Council of Science Editors:

Santa Maria DR. Identifying post-silicon bugs and their root causes through a hardware introspection engine. [Masters Thesis]. University of Texas – Austin; 2017. Available from: http://hdl.handle.net/2152/63952

23. Liu, Ding. On intrinsically live structure and deadlock control of generalized Petri nets modeling flexible manufacturing systems : Sur le contrôle de blocage dans les systèmes flexibles de production à base de réseaux de Petri généralisés.

Degree: Docteur es, Informatique, 2015, Paris, CNAM

Nos travaux portent sur l'analyse des systèmes de production automatisée à l'aide de réseaux de Petri. Le problème posé est de savoir si un système… (more)

Subjects/Keywords: Réseaux de Petri; Interblocage; Siphons; Systèmes de fabrication automatisés; Structures; Petri net; Deadlock; Siphon; Automated manufacturing systems; Structure; 004

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Liu, D. (2015). On intrinsically live structure and deadlock control of generalized Petri nets modeling flexible manufacturing systems : Sur le contrôle de blocage dans les systèmes flexibles de production à base de réseaux de Petri généralisés. (Doctoral Dissertation). Paris, CNAM. Retrieved from http://www.theses.fr/2015CNAM1004

Chicago Manual of Style (16th Edition):

Liu, Ding. “On intrinsically live structure and deadlock control of generalized Petri nets modeling flexible manufacturing systems : Sur le contrôle de blocage dans les systèmes flexibles de production à base de réseaux de Petri généralisés.” 2015. Doctoral Dissertation, Paris, CNAM. Accessed September 19, 2019. http://www.theses.fr/2015CNAM1004.

MLA Handbook (7th Edition):

Liu, Ding. “On intrinsically live structure and deadlock control of generalized Petri nets modeling flexible manufacturing systems : Sur le contrôle de blocage dans les systèmes flexibles de production à base de réseaux de Petri généralisés.” 2015. Web. 19 Sep 2019.

Vancouver:

Liu D. On intrinsically live structure and deadlock control of generalized Petri nets modeling flexible manufacturing systems : Sur le contrôle de blocage dans les systèmes flexibles de production à base de réseaux de Petri généralisés. [Internet] [Doctoral dissertation]. Paris, CNAM; 2015. [cited 2019 Sep 19]. Available from: http://www.theses.fr/2015CNAM1004.

Council of Science Editors:

Liu D. On intrinsically live structure and deadlock control of generalized Petri nets modeling flexible manufacturing systems : Sur le contrôle de blocage dans les systèmes flexibles de production à base de réseaux de Petri généralisés. [Doctoral Dissertation]. Paris, CNAM; 2015. Available from: http://www.theses.fr/2015CNAM1004


Technical University of Lisbon

24. Antunes, Eduardo Augusto Pereira. A questão de Olivença:um caso de politica externa portuguesa.

Degree: 2013, Technical University of Lisbon

Dissertação de Mestrado em Relações Internacionais

A reconquista de Olivença pelos portugueses, no século XII, fez parte de um vasto plano militar e político com… (more)

Subjects/Keywords: Convenções; Tratados; Guerras (das laranjas); Usurpação; Retorno e Impasse; Conventions; Treaties; War ( of oranges ); Usurpation and deadlock

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APA (6th Edition):

Antunes, E. A. P. (2013). A questão de Olivença:um caso de politica externa portuguesa. (Thesis). Technical University of Lisbon. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:www.repository.utl.pt:10400.5/5885

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Antunes, Eduardo Augusto Pereira. “A questão de Olivença:um caso de politica externa portuguesa.” 2013. Thesis, Technical University of Lisbon. Accessed September 19, 2019. http://www.rcaap.pt/detail.jsp?id=oai:www.repository.utl.pt:10400.5/5885.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Antunes, Eduardo Augusto Pereira. “A questão de Olivença:um caso de politica externa portuguesa.” 2013. Web. 19 Sep 2019.

Vancouver:

Antunes EAP. A questão de Olivença:um caso de politica externa portuguesa. [Internet] [Thesis]. Technical University of Lisbon; 2013. [cited 2019 Sep 19]. Available from: http://www.rcaap.pt/detail.jsp?id=oai:www.repository.utl.pt:10400.5/5885.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Antunes EAP. A questão de Olivença:um caso de politica externa portuguesa. [Thesis]. Technical University of Lisbon; 2013. Available from: http://www.rcaap.pt/detail.jsp?id=oai:www.repository.utl.pt:10400.5/5885

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

25. ANTONINO, Pedro Ribeiro Gonçalves. A refinement based strategy for locally verifying networks of CSP processes .

Degree: 2014, Universidade Federal de Pernambuco

 Com o aumento da complexidade dos sistemas computacionais, houve também um aumento da dificuldade na tarefa de verificação de sistemas. Para lidar com essa complexidade,… (more)

Subjects/Keywords: Ausência de deadlocks; CSP; FDR; Análise local; Verificação de modelos; Deadlock freedom; Local analysis; Model checking

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APA (6th Edition):

ANTONINO, P. R. G. (2014). A refinement based strategy for locally verifying networks of CSP processes . (Thesis). Universidade Federal de Pernambuco. Retrieved from http://repositorio.ufpe.br/handle/123456789/11966

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

ANTONINO, Pedro Ribeiro Gonçalves. “A refinement based strategy for locally verifying networks of CSP processes .” 2014. Thesis, Universidade Federal de Pernambuco. Accessed September 19, 2019. http://repositorio.ufpe.br/handle/123456789/11966.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

ANTONINO, Pedro Ribeiro Gonçalves. “A refinement based strategy for locally verifying networks of CSP processes .” 2014. Web. 19 Sep 2019.

Vancouver:

ANTONINO PRG. A refinement based strategy for locally verifying networks of CSP processes . [Internet] [Thesis]. Universidade Federal de Pernambuco; 2014. [cited 2019 Sep 19]. Available from: http://repositorio.ufpe.br/handle/123456789/11966.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

ANTONINO PRG. A refinement based strategy for locally verifying networks of CSP processes . [Thesis]. Universidade Federal de Pernambuco; 2014. Available from: http://repositorio.ufpe.br/handle/123456789/11966

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Ohio University

26. Landrum, Chad Michael. A recursive algorithm to prevent deadlock in flexible manufacturing systems.

Degree: MS, Industrial and Manufacturing Systems Engineering (Engineering), 2000, Ohio University

A recursive algorithm to prevent deadlock in flexible manufacturing systems Advisors/Committee Members: Lipset, Robert (Advisor).

Subjects/Keywords: Engineering, Industrial; recursive algorithm; deadlock; flexible manufacturing systems

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APA (6th Edition):

Landrum, C. M. (2000). A recursive algorithm to prevent deadlock in flexible manufacturing systems. (Masters Thesis). Ohio University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1172265184

Chicago Manual of Style (16th Edition):

Landrum, Chad Michael. “A recursive algorithm to prevent deadlock in flexible manufacturing systems.” 2000. Masters Thesis, Ohio University. Accessed September 19, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1172265184.

MLA Handbook (7th Edition):

Landrum, Chad Michael. “A recursive algorithm to prevent deadlock in flexible manufacturing systems.” 2000. Web. 19 Sep 2019.

Vancouver:

Landrum CM. A recursive algorithm to prevent deadlock in flexible manufacturing systems. [Internet] [Masters thesis]. Ohio University; 2000. [cited 2019 Sep 19]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1172265184.

Council of Science Editors:

Landrum CM. A recursive algorithm to prevent deadlock in flexible manufacturing systems. [Masters Thesis]. Ohio University; 2000. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1172265184


Ohio University

27. Deering, Paul E. Necessary and sufficient conditions for deadlock in a manufacturing system.

Degree: PhD, Electrical Engineering & Computer Science (Engineering and Technology), 2000, Ohio University

  In manufacturing systems there has been major advances made in the design, scheduling, operation and performance. However, in resource sharing systems deadlock still occurs.… (more)

Subjects/Keywords: Engineering, Industrial; Necessary conditions; sufficient conditions; deadlock; manufacturing system

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APA (6th Edition):

Deering, P. E. (2000). Necessary and sufficient conditions for deadlock in a manufacturing system. (Doctoral Dissertation). Ohio University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1179169384

Chicago Manual of Style (16th Edition):

Deering, Paul E. “Necessary and sufficient conditions for deadlock in a manufacturing system.” 2000. Doctoral Dissertation, Ohio University. Accessed September 19, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1179169384.

MLA Handbook (7th Edition):

Deering, Paul E. “Necessary and sufficient conditions for deadlock in a manufacturing system.” 2000. Web. 19 Sep 2019.

Vancouver:

Deering PE. Necessary and sufficient conditions for deadlock in a manufacturing system. [Internet] [Doctoral dissertation]. Ohio University; 2000. [cited 2019 Sep 19]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1179169384.

Council of Science Editors:

Deering PE. Necessary and sufficient conditions for deadlock in a manufacturing system. [Doctoral Dissertation]. Ohio University; 2000. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1179169384


Ohio University

28. Zhang, Wenle. Scalable deadlock avoidance algorithms for flexible manufacturing systems.

Degree: PhD, Electrical Engineering & Computer Science (Engineering and Technology), 2000, Ohio University

  Existing deadlock prevention and avoidance methods for flexible manufacturing systems have either restricted the class of systems they apply to, or are conservative so… (more)

Subjects/Keywords: Scalable algorithms; deadlock avoidance algorithms; flexible manufacturing systems

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhang, W. (2000). Scalable deadlock avoidance algorithms for flexible manufacturing systems. (Doctoral Dissertation). Ohio University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1179862449

Chicago Manual of Style (16th Edition):

Zhang, Wenle. “Scalable deadlock avoidance algorithms for flexible manufacturing systems.” 2000. Doctoral Dissertation, Ohio University. Accessed September 19, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1179862449.

MLA Handbook (7th Edition):

Zhang, Wenle. “Scalable deadlock avoidance algorithms for flexible manufacturing systems.” 2000. Web. 19 Sep 2019.

Vancouver:

Zhang W. Scalable deadlock avoidance algorithms for flexible manufacturing systems. [Internet] [Doctoral dissertation]. Ohio University; 2000. [cited 2019 Sep 19]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1179862449.

Council of Science Editors:

Zhang W. Scalable deadlock avoidance algorithms for flexible manufacturing systems. [Doctoral Dissertation]. Ohio University; 2000. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1179862449

29. Perronnet, Florent. Régulation coopérative des intersections : protocoles et politiques : Cooperative Intersection Management : Protocols and policies.

Degree: Docteur es, Automatique, 2015, Belfort-Montbéliard

Dans ce travail, nous exploitons le potentiel offert par les véhicules autonomes coopératifs, pour fluidifier le trafic dans une intersection isolée puis dans un réseau… (more)

Subjects/Keywords: Régulation d'intersections; V2X; Véhicule autonome; Interblocage; Optimisation combinatoire; Intersection management; V2X; Autonomous vehicle; Deadlock; Combinatorial optimization

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Perronnet, F. (2015). Régulation coopérative des intersections : protocoles et politiques : Cooperative Intersection Management : Protocols and policies. (Doctoral Dissertation). Belfort-Montbéliard. Retrieved from http://www.theses.fr/2015BELF0259

Chicago Manual of Style (16th Edition):

Perronnet, Florent. “Régulation coopérative des intersections : protocoles et politiques : Cooperative Intersection Management : Protocols and policies.” 2015. Doctoral Dissertation, Belfort-Montbéliard. Accessed September 19, 2019. http://www.theses.fr/2015BELF0259.

MLA Handbook (7th Edition):

Perronnet, Florent. “Régulation coopérative des intersections : protocoles et politiques : Cooperative Intersection Management : Protocols and policies.” 2015. Web. 19 Sep 2019.

Vancouver:

Perronnet F. Régulation coopérative des intersections : protocoles et politiques : Cooperative Intersection Management : Protocols and policies. [Internet] [Doctoral dissertation]. Belfort-Montbéliard; 2015. [cited 2019 Sep 19]. Available from: http://www.theses.fr/2015BELF0259.

Council of Science Editors:

Perronnet F. Régulation coopérative des intersections : protocoles et politiques : Cooperative Intersection Management : Protocols and policies. [Doctoral Dissertation]. Belfort-Montbéliard; 2015. Available from: http://www.theses.fr/2015BELF0259


Delft University of Technology

30. Huijs, M.G. Building Castles in the (Dutch) Air: Understanding the Policy Deadlock of Amsterdam Airport Schiphol 1989 - 2009.

Degree: 2011, Delft University of Technology

 Ever since the 1950s, the Dutch national government has struggled intensely with the trade-off between the economic significance and environmental impact of Amsterdam Airport Schiphol,… (more)

Subjects/Keywords: Policy Deadlock; Foucault; Effective History; Schiphol; Power

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Huijs, M. G. (2011). Building Castles in the (Dutch) Air: Understanding the Policy Deadlock of Amsterdam Airport Schiphol 1989 - 2009. (Doctoral Dissertation). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:854e4d88-a03f-4941-8b63-792d065f557f ; urn:NBN:nl:ui:24-uuid:854e4d88-a03f-4941-8b63-792d065f557f ; urn:NBN:nl:ui:24-uuid:854e4d88-a03f-4941-8b63-792d065f557f ; http://resolver.tudelft.nl/uuid:854e4d88-a03f-4941-8b63-792d065f557f

Chicago Manual of Style (16th Edition):

Huijs, M G. “Building Castles in the (Dutch) Air: Understanding the Policy Deadlock of Amsterdam Airport Schiphol 1989 - 2009.” 2011. Doctoral Dissertation, Delft University of Technology. Accessed September 19, 2019. http://resolver.tudelft.nl/uuid:854e4d88-a03f-4941-8b63-792d065f557f ; urn:NBN:nl:ui:24-uuid:854e4d88-a03f-4941-8b63-792d065f557f ; urn:NBN:nl:ui:24-uuid:854e4d88-a03f-4941-8b63-792d065f557f ; http://resolver.tudelft.nl/uuid:854e4d88-a03f-4941-8b63-792d065f557f.

MLA Handbook (7th Edition):

Huijs, M G. “Building Castles in the (Dutch) Air: Understanding the Policy Deadlock of Amsterdam Airport Schiphol 1989 - 2009.” 2011. Web. 19 Sep 2019.

Vancouver:

Huijs MG. Building Castles in the (Dutch) Air: Understanding the Policy Deadlock of Amsterdam Airport Schiphol 1989 - 2009. [Internet] [Doctoral dissertation]. Delft University of Technology; 2011. [cited 2019 Sep 19]. Available from: http://resolver.tudelft.nl/uuid:854e4d88-a03f-4941-8b63-792d065f557f ; urn:NBN:nl:ui:24-uuid:854e4d88-a03f-4941-8b63-792d065f557f ; urn:NBN:nl:ui:24-uuid:854e4d88-a03f-4941-8b63-792d065f557f ; http://resolver.tudelft.nl/uuid:854e4d88-a03f-4941-8b63-792d065f557f.

Council of Science Editors:

Huijs MG. Building Castles in the (Dutch) Air: Understanding the Policy Deadlock of Amsterdam Airport Schiphol 1989 - 2009. [Doctoral Dissertation]. Delft University of Technology; 2011. Available from: http://resolver.tudelft.nl/uuid:854e4d88-a03f-4941-8b63-792d065f557f ; urn:NBN:nl:ui:24-uuid:854e4d88-a03f-4941-8b63-792d065f557f ; urn:NBN:nl:ui:24-uuid:854e4d88-a03f-4941-8b63-792d065f557f ; http://resolver.tudelft.nl/uuid:854e4d88-a03f-4941-8b63-792d065f557f

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