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You searched for subject:(datapath). Showing records 1 – 23 of 23 total matches.

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Brno University of Technology

1. Spišiak, Matej. Monitorování provozu VoIP pomocí technologie OnePK: Monitoring VoIP Traffic Using OnePK Technology.

Degree: 2019, Brno University of Technology

 This bachelor's thesis deals with new proprietary technology from Cisco systems called OnePK(one platform kit). The focus is on determining its possibilities of use considering… (more)

Subjects/Keywords: OnePK; SDK; API; SDN; VoIP; SIP; RTP; DataPath; statistika; Cisco; OnePK; SDK; API; SDN; VoIP; SIP; RTP; DataPath; statistics; Cisco

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Spišiak, M. (2019). Monitorování provozu VoIP pomocí technologie OnePK: Monitoring VoIP Traffic Using OnePK Technology. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/56482

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Spišiak, Matej. “Monitorování provozu VoIP pomocí technologie OnePK: Monitoring VoIP Traffic Using OnePK Technology.” 2019. Thesis, Brno University of Technology. Accessed April 19, 2021. http://hdl.handle.net/11012/56482.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Spišiak, Matej. “Monitorování provozu VoIP pomocí technologie OnePK: Monitoring VoIP Traffic Using OnePK Technology.” 2019. Web. 19 Apr 2021.

Vancouver:

Spišiak M. Monitorování provozu VoIP pomocí technologie OnePK: Monitoring VoIP Traffic Using OnePK Technology. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Apr 19]. Available from: http://hdl.handle.net/11012/56482.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Spišiak M. Monitorování provozu VoIP pomocí technologie OnePK: Monitoring VoIP Traffic Using OnePK Technology. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/56482

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

2. Hazlett, Christiaan D. A MIPS datapath simulator for enhancing visual learning of computer architecture.

Degree: MS, Computer Science, 2020, University of Illinois – Urbana-Champaign

 In this thesis, I introduce the Datapath Simulator—a tool for visually teaching the fundamentals of hardware architecture. Built over the 2019-2020 academic year, the Simulator… (more)

Subjects/Keywords: MIPS; datapath; datapath simulator; hardware architecture; education

…updating MIPS datapath—complete with bus, component, register, and memory values. DrMIPS… …to modify the datapath. Nova’s work is similar to earlier work done in 2008 by Cambridge… …to trace data values along the datapath and visually simulate the processor’s execution… …they do not allow users to modify the datapath at all. The Datapath Simulator encourages… …students’ learning by allowing them to build the MIPS Datapath in addition to simply simulating… 

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APA (6th Edition):

Hazlett, C. D. (2020). A MIPS datapath simulator for enhancing visual learning of computer architecture. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/108064

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hazlett, Christiaan D. “A MIPS datapath simulator for enhancing visual learning of computer architecture.” 2020. Thesis, University of Illinois – Urbana-Champaign. Accessed April 19, 2021. http://hdl.handle.net/2142/108064.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hazlett, Christiaan D. “A MIPS datapath simulator for enhancing visual learning of computer architecture.” 2020. Web. 19 Apr 2021.

Vancouver:

Hazlett CD. A MIPS datapath simulator for enhancing visual learning of computer architecture. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2020. [cited 2021 Apr 19]. Available from: http://hdl.handle.net/2142/108064.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hazlett CD. A MIPS datapath simulator for enhancing visual learning of computer architecture. [Thesis]. University of Illinois – Urbana-Champaign; 2020. Available from: http://hdl.handle.net/2142/108064

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Univerzitet u Beogradu

3. Stojilović, Mirjana, 1983-. A Method for designing domain-specific reconfigurable arrays.

Degree: Elektrotehnički fakultet, 2016, Univerzitet u Beogradu

Tehničke nauke – elektrotehnika - Elektronika / Technical sciences, Electrical engineering - Electronics

Namenski računarski sistemi se najčesće projektuju tako da mogu da podrže izvršavanje… (more)

Subjects/Keywords: CGRA; datapath; domain-specific customization; flexibility; FPGA routing

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APA (6th Edition):

Stojilović, Mirjana, 1. (2016). A Method for designing domain-specific reconfigurable arrays. (Thesis). Univerzitet u Beogradu. Retrieved from https://fedorabg.bg.ac.rs/fedora/get/o:13568/bdef:Content/get

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Stojilović, Mirjana, 1983-. “A Method for designing domain-specific reconfigurable arrays.” 2016. Thesis, Univerzitet u Beogradu. Accessed April 19, 2021. https://fedorabg.bg.ac.rs/fedora/get/o:13568/bdef:Content/get.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Stojilović, Mirjana, 1983-. “A Method for designing domain-specific reconfigurable arrays.” 2016. Web. 19 Apr 2021.

Vancouver:

Stojilović, Mirjana 1. A Method for designing domain-specific reconfigurable arrays. [Internet] [Thesis]. Univerzitet u Beogradu; 2016. [cited 2021 Apr 19]. Available from: https://fedorabg.bg.ac.rs/fedora/get/o:13568/bdef:Content/get.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Stojilović, Mirjana 1. A Method for designing domain-specific reconfigurable arrays. [Thesis]. Univerzitet u Beogradu; 2016. Available from: https://fedorabg.bg.ac.rs/fedora/get/o:13568/bdef:Content/get

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rochester Institute of Technology

4. VanBuren, Brian. Graphical microcode simulator with a reconfigurable datapath.

Degree: Computer Engineering, 2006, Rochester Institute of Technology

 Microcode is a symbolic way to simplify control design that allows changing, testing and updating the control unit of processors. By changing the microcode, the… (more)

Subjects/Keywords: Control unit; Datapath; Graphical; Microcode; Processors; Simulator

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APA (6th Edition):

VanBuren, B. (2006). Graphical microcode simulator with a reconfigurable datapath. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/5505

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

VanBuren, Brian. “Graphical microcode simulator with a reconfigurable datapath.” 2006. Thesis, Rochester Institute of Technology. Accessed April 19, 2021. https://scholarworks.rit.edu/theses/5505.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

VanBuren, Brian. “Graphical microcode simulator with a reconfigurable datapath.” 2006. Web. 19 Apr 2021.

Vancouver:

VanBuren B. Graphical microcode simulator with a reconfigurable datapath. [Internet] [Thesis]. Rochester Institute of Technology; 2006. [cited 2021 Apr 19]. Available from: https://scholarworks.rit.edu/theses/5505.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

VanBuren B. Graphical microcode simulator with a reconfigurable datapath. [Thesis]. Rochester Institute of Technology; 2006. Available from: https://scholarworks.rit.edu/theses/5505

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

5. Κρητικάκου, Αγγελική. Low cost low energy embedded processors for on-line biotechnology monitoring applications.

Degree: 2009, University of Patras

On-line monitoring is an important challenge in future biotechnology applications, for instance in the domain of precision livestock farming, there is need for low-cost intelligent… (more)

Subjects/Keywords: Low energy; Embedded processors; Low cost; Biotechnology applications; Datapath; ASIP; 004.6; Χαμηλή κατανάλωση ενέργειας; Ενσωματωμένοι επεξεργαστές; Χαμηλό κόστος; Βιοτεχνολογικές εφαρμογές

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APA (6th Edition):

Κρητικάκου, . (2009). Low cost low energy embedded processors for on-line biotechnology monitoring applications. (Masters Thesis). University of Patras. Retrieved from http://nemertes.lis.upatras.gr/jspui/handle/10889/1731

Chicago Manual of Style (16th Edition):

Κρητικάκου, Αγγελική. “Low cost low energy embedded processors for on-line biotechnology monitoring applications.” 2009. Masters Thesis, University of Patras. Accessed April 19, 2021. http://nemertes.lis.upatras.gr/jspui/handle/10889/1731.

MLA Handbook (7th Edition):

Κρητικάκου, Αγγελική. “Low cost low energy embedded processors for on-line biotechnology monitoring applications.” 2009. Web. 19 Apr 2021.

Vancouver:

Κρητικάκου . Low cost low energy embedded processors for on-line biotechnology monitoring applications. [Internet] [Masters thesis]. University of Patras; 2009. [cited 2021 Apr 19]. Available from: http://nemertes.lis.upatras.gr/jspui/handle/10889/1731.

Council of Science Editors:

Κρητικάκου . Low cost low energy embedded processors for on-line biotechnology monitoring applications. [Masters Thesis]. University of Patras; 2009. Available from: http://nemertes.lis.upatras.gr/jspui/handle/10889/1731


Virginia Tech

6. Agarwal, Deepak. An 8 GHz Ultra Wideband Transceiver Testbed.

Degree: MS, Electrical and Computer Engineering, 2005, Virginia Tech

 Software defined radios have the potential of changing the fundamental usage model of wireless communications devices, but the capabilities of these transceivers are often limited… (more)

Subjects/Keywords: high-speed datapath; software radio; FPGA; ultra-wideband

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APA (6th Edition):

Agarwal, D. (2005). An 8 GHz Ultra Wideband Transceiver Testbed. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/35605

Chicago Manual of Style (16th Edition):

Agarwal, Deepak. “An 8 GHz Ultra Wideband Transceiver Testbed.” 2005. Masters Thesis, Virginia Tech. Accessed April 19, 2021. http://hdl.handle.net/10919/35605.

MLA Handbook (7th Edition):

Agarwal, Deepak. “An 8 GHz Ultra Wideband Transceiver Testbed.” 2005. Web. 19 Apr 2021.

Vancouver:

Agarwal D. An 8 GHz Ultra Wideband Transceiver Testbed. [Internet] [Masters thesis]. Virginia Tech; 2005. [cited 2021 Apr 19]. Available from: http://hdl.handle.net/10919/35605.

Council of Science Editors:

Agarwal D. An 8 GHz Ultra Wideband Transceiver Testbed. [Masters Thesis]. Virginia Tech; 2005. Available from: http://hdl.handle.net/10919/35605

7. Roudel, Nicolas. SEEPROC : un modèle de processeur à chemin de données reconfigurable pour le traitement d'images embarqué : SEEPROC : a reconfigurable data path processor model for embedded image processing.

Degree: Docteur es, Vision pour la Robotique, 2012, Université Blaise-Pascale, Clermont-Ferrand II

Les travaux présentés dans ce manuscrit proposent une architecture de processeur à chemin de données reconfigurable (PCDR) dédiée aux traitements d'images bas niveau. Afin de… (more)

Subjects/Keywords: Vision par ordinateur; Smart camera; FPGA; Traitement d'images; SOPC; Processeur à chemin de données reconfigurable; Computer vision; Smart camera; FPGA; Image processing; SOPC; Reconfigurable datapath processor

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Roudel, N. (2012). SEEPROC : un modèle de processeur à chemin de données reconfigurable pour le traitement d'images embarqué : SEEPROC : a reconfigurable data path processor model for embedded image processing. (Doctoral Dissertation). Université Blaise-Pascale, Clermont-Ferrand II. Retrieved from http://www.theses.fr/2012CLF22234

Chicago Manual of Style (16th Edition):

Roudel, Nicolas. “SEEPROC : un modèle de processeur à chemin de données reconfigurable pour le traitement d'images embarqué : SEEPROC : a reconfigurable data path processor model for embedded image processing.” 2012. Doctoral Dissertation, Université Blaise-Pascale, Clermont-Ferrand II. Accessed April 19, 2021. http://www.theses.fr/2012CLF22234.

MLA Handbook (7th Edition):

Roudel, Nicolas. “SEEPROC : un modèle de processeur à chemin de données reconfigurable pour le traitement d'images embarqué : SEEPROC : a reconfigurable data path processor model for embedded image processing.” 2012. Web. 19 Apr 2021.

Vancouver:

Roudel N. SEEPROC : un modèle de processeur à chemin de données reconfigurable pour le traitement d'images embarqué : SEEPROC : a reconfigurable data path processor model for embedded image processing. [Internet] [Doctoral dissertation]. Université Blaise-Pascale, Clermont-Ferrand II; 2012. [cited 2021 Apr 19]. Available from: http://www.theses.fr/2012CLF22234.

Council of Science Editors:

Roudel N. SEEPROC : un modèle de processeur à chemin de données reconfigurable pour le traitement d'images embarqué : SEEPROC : a reconfigurable data path processor model for embedded image processing. [Doctoral Dissertation]. Université Blaise-Pascale, Clermont-Ferrand II; 2012. Available from: http://www.theses.fr/2012CLF22234

8. Kolumban, Gaspar. Low Cost Floating-Point Extensions to a Fixed-Point SIMD Datapath.

Degree: The Institute of Technology, 2013, Linköping UniversityLinköping University

  The ePUMA architecture is a novel master-multi-SIMD DSP platform aimed at low-power computing, like for embedded or hand-held devices for example. It is both… (more)

Subjects/Keywords: ePUMA; floating-point; SIMD; VPE; fixed-point datapath; IEEE 754

…2.3.1 Data vectors 2.3.2 Datapath . . 2.4 Further Information… …modifications will be done to a fixed-point datapath. It is implied that the implementation needs to… …overview of the unified datapath that can handle all operations. • Chapter 6 - Verification: On… …point and non floating-point datapath. • Chapter 8 - Evaluation: Determine if and when the… …proposed design is worth adding to the datapath. • Chapter 9 - Conclusions: Conclusions from the… 

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APA (6th Edition):

Kolumban, G. (2013). Low Cost Floating-Point Extensions to a Fixed-Point SIMD Datapath. (Thesis). Linköping UniversityLinköping University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-101586

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kolumban, Gaspar. “Low Cost Floating-Point Extensions to a Fixed-Point SIMD Datapath.” 2013. Thesis, Linköping UniversityLinköping University. Accessed April 19, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-101586.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kolumban, Gaspar. “Low Cost Floating-Point Extensions to a Fixed-Point SIMD Datapath.” 2013. Web. 19 Apr 2021.

Vancouver:

Kolumban G. Low Cost Floating-Point Extensions to a Fixed-Point SIMD Datapath. [Internet] [Thesis]. Linköping UniversityLinköping University; 2013. [cited 2021 Apr 19]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-101586.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kolumban G. Low Cost Floating-Point Extensions to a Fixed-Point SIMD Datapath. [Thesis]. Linköping UniversityLinköping University; 2013. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-101586

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

9. Lin, Chen-Hsuan. Design automation for circuit reliability and energy efficiency.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 This dissertation presents approaches to improve circuit reliability and energy efficiency from different angles, such as verification, logic synthesis, and functional unit design. A variety… (more)

Subjects/Keywords: Electronic design automation; Reliability; Energy efficiency; Data mining; Satisfiability (SAT) solving; Logic restructuring; Assertion; Negative bias temperature instability (NBTI) effect; Modulo arithmetic; Shadow datapath

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APA (6th Edition):

Lin, C. (2017). Design automation for circuit reliability and energy efficiency. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99237

Chicago Manual of Style (16th Edition):

Lin, Chen-Hsuan. “Design automation for circuit reliability and energy efficiency.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 19, 2021. http://hdl.handle.net/2142/99237.

MLA Handbook (7th Edition):

Lin, Chen-Hsuan. “Design automation for circuit reliability and energy efficiency.” 2017. Web. 19 Apr 2021.

Vancouver:

Lin C. Design automation for circuit reliability and energy efficiency. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Apr 19]. Available from: http://hdl.handle.net/2142/99237.

Council of Science Editors:

Lin C. Design automation for circuit reliability and energy efficiency. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99237


University of South Florida

10. Thapliyal, Himanshu. Design, Synthesis and Test of Reversible Circuits for Emerging Nanotechnologies.

Degree: 2011, University of South Florida

 Reversible circuits are similar to conventional logic circuits except that they are built from reversible gates. In reversible gates, there is a unique, one-to-one mapping… (more)

Subjects/Keywords: Conservative Logic; Datapath Functional Units; Quantum Computing; Quantum Dot Cellular Automata; Reversible Logic; American Studies; Arts and Humanities; Computer Engineering; Nanoscience and Nanotechnology

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APA (6th Edition):

Thapliyal, H. (2011). Design, Synthesis and Test of Reversible Circuits for Emerging Nanotechnologies. (Thesis). University of South Florida. Retrieved from https://scholarcommons.usf.edu/etd/3379

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Thapliyal, Himanshu. “Design, Synthesis and Test of Reversible Circuits for Emerging Nanotechnologies.” 2011. Thesis, University of South Florida. Accessed April 19, 2021. https://scholarcommons.usf.edu/etd/3379.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Thapliyal, Himanshu. “Design, Synthesis and Test of Reversible Circuits for Emerging Nanotechnologies.” 2011. Web. 19 Apr 2021.

Vancouver:

Thapliyal H. Design, Synthesis and Test of Reversible Circuits for Emerging Nanotechnologies. [Internet] [Thesis]. University of South Florida; 2011. [cited 2021 Apr 19]. Available from: https://scholarcommons.usf.edu/etd/3379.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Thapliyal H. Design, Synthesis and Test of Reversible Circuits for Emerging Nanotechnologies. [Thesis]. University of South Florida; 2011. Available from: https://scholarcommons.usf.edu/etd/3379

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

11. Vlad, Ciubotariu. Automatic Datapath Abstraction Of Pipelined Circuits.

Degree: 2011, University of Waterloo

 Pipelined circuits operate as an assembly line that starts processing new instructions while older ones continue execution. Control properties specify the correct behaviour of the… (more)

Subjects/Keywords: Datapath abstraction pipelined circuits model checking formal verification

…35 3.4 Datapath Module… …36 3.5 Neg Datapath Module… …37 3.6 Add Datapath Module… …37 3.7 Mult Datapath Module… …datapath behaviour. . . . . . . . . . . . . . 89 4.33 Abstract parcel automaton… 

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APA (6th Edition):

Vlad, C. (2011). Automatic Datapath Abstraction Of Pipelined Circuits. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/5804

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vlad, Ciubotariu. “Automatic Datapath Abstraction Of Pipelined Circuits.” 2011. Thesis, University of Waterloo. Accessed April 19, 2021. http://hdl.handle.net/10012/5804.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vlad, Ciubotariu. “Automatic Datapath Abstraction Of Pipelined Circuits.” 2011. Web. 19 Apr 2021.

Vancouver:

Vlad C. Automatic Datapath Abstraction Of Pipelined Circuits. [Internet] [Thesis]. University of Waterloo; 2011. [cited 2021 Apr 19]. Available from: http://hdl.handle.net/10012/5804.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vlad C. Automatic Datapath Abstraction Of Pipelined Circuits. [Thesis]. University of Waterloo; 2011. Available from: http://hdl.handle.net/10012/5804

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

12. Tsoumanis, Konstantinos. Τεχνικές βελτιστοποίησης σύνθετων αριθμητικών συστημάτων.

Degree: 2016, National Technical University of Athens (NTUA); Εθνικό Μετσόβιο Πολυτεχνείο (ΕΜΠ)

 Modern embedded systems target domains of high-end applications, which require efficient implementations of computationally intensive Digital Signal Processing (DSP) functions. The performance of DSP systems… (more)

Subjects/Keywords: Αριθμητικές μέθοδοι; Βελτιστοποίηση σχεδίασης; Αύξηση απόδοσης; Μονοπάτι δεδομένων; Συγχωνευμένες αριθμητικές πράξεις; Αριθμητικά συστήματα υπολοίπων; Arithmetic techniques; Design optimization; Performance increase; Datapath; Fused arithmetic operations; Residue number systems

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APA (6th Edition):

Tsoumanis, K. (2016). Τεχνικές βελτιστοποίησης σύνθετων αριθμητικών συστημάτων. (Thesis). National Technical University of Athens (NTUA); Εθνικό Μετσόβιο Πολυτεχνείο (ΕΜΠ). Retrieved from http://hdl.handle.net/10442/hedi/38286

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tsoumanis, Konstantinos. “Τεχνικές βελτιστοποίησης σύνθετων αριθμητικών συστημάτων.” 2016. Thesis, National Technical University of Athens (NTUA); Εθνικό Μετσόβιο Πολυτεχνείο (ΕΜΠ). Accessed April 19, 2021. http://hdl.handle.net/10442/hedi/38286.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tsoumanis, Konstantinos. “Τεχνικές βελτιστοποίησης σύνθετων αριθμητικών συστημάτων.” 2016. Web. 19 Apr 2021.

Vancouver:

Tsoumanis K. Τεχνικές βελτιστοποίησης σύνθετων αριθμητικών συστημάτων. [Internet] [Thesis]. National Technical University of Athens (NTUA); Εθνικό Μετσόβιο Πολυτεχνείο (ΕΜΠ); 2016. [cited 2021 Apr 19]. Available from: http://hdl.handle.net/10442/hedi/38286.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tsoumanis K. Τεχνικές βελτιστοποίησης σύνθετων αριθμητικών συστημάτων. [Thesis]. National Technical University of Athens (NTUA); Εθνικό Μετσόβιο Πολυτεχνείο (ΕΜΠ); 2016. Available from: http://hdl.handle.net/10442/hedi/38286

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

13. Ward, Samuel Isaac. Physical design automation of structured high-performance integrated circuits.

Degree: PhD, Electrical and Computer Engineering, 2013, University of Texas – Austin

 During the last forty years, advancements have pushed state-of-the-art placers to impressive performance placing modern multimillion gate designs in under an hour. Wide industry adoption… (more)

Subjects/Keywords: Design automation; Circuit design; Structured placement; Placement; Datapath placement

…this work lead to discoveries in three key aspects of modern physical design flows. Datapath… …datapath style circuits that contain high fanout nets. As the datapath benchmarks showed, these… …and datapath cells. The flow is built on top of a leading academic force-directed placer and… …significantly improves the quality of datapath placement while leveraging the speed and flexibility of… …performance designs, datapath circuits are often embedded within a larger ASIC style circuit and… 

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APA (6th Edition):

Ward, S. I. (2013). Physical design automation of structured high-performance integrated circuits. (Doctoral Dissertation). University of Texas – Austin. Retrieved from http://hdl.handle.net/2152/23089

Chicago Manual of Style (16th Edition):

Ward, Samuel Isaac. “Physical design automation of structured high-performance integrated circuits.” 2013. Doctoral Dissertation, University of Texas – Austin. Accessed April 19, 2021. http://hdl.handle.net/2152/23089.

MLA Handbook (7th Edition):

Ward, Samuel Isaac. “Physical design automation of structured high-performance integrated circuits.” 2013. Web. 19 Apr 2021.

Vancouver:

Ward SI. Physical design automation of structured high-performance integrated circuits. [Internet] [Doctoral dissertation]. University of Texas – Austin; 2013. [cited 2021 Apr 19]. Available from: http://hdl.handle.net/2152/23089.

Council of Science Editors:

Ward SI. Physical design automation of structured high-performance integrated circuits. [Doctoral Dissertation]. University of Texas – Austin; 2013. Available from: http://hdl.handle.net/2152/23089

14. Ziesemer Junior, Adriel Mota. Geração automática de partes operativas de circuitos VLSI.

Degree: 2007, Brazil

Tanto nos circuitos integrados para processamento de sinais digitais quanto em microprocessadores, a parte operativa é o núcleo onde a computação dos dados é realizada.… (more)

Subjects/Keywords: Microeletrônica; Cmos; Vlsi; Automatic generation; Layout; Datapath; CMOS cells; CAD; Microelectronic

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APA (6th Edition):

Ziesemer Junior, A. M. (2007). Geração automática de partes operativas de circuitos VLSI. (Masters Thesis). Brazil. Retrieved from http://hdl.handle.net/10183/15530

Chicago Manual of Style (16th Edition):

Ziesemer Junior, Adriel Mota. “Geração automática de partes operativas de circuitos VLSI.” 2007. Masters Thesis, Brazil. Accessed April 19, 2021. http://hdl.handle.net/10183/15530.

MLA Handbook (7th Edition):

Ziesemer Junior, Adriel Mota. “Geração automática de partes operativas de circuitos VLSI.” 2007. Web. 19 Apr 2021.

Vancouver:

Ziesemer Junior AM. Geração automática de partes operativas de circuitos VLSI. [Internet] [Masters thesis]. Brazil; 2007. [cited 2021 Apr 19]. Available from: http://hdl.handle.net/10183/15530.

Council of Science Editors:

Ziesemer Junior AM. Geração automática de partes operativas de circuitos VLSI. [Masters Thesis]. Brazil; 2007. Available from: http://hdl.handle.net/10183/15530

15. 手原, 亮. タイミングスキュー調整可能データパスのための設計制約と合成法.

Degree: Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学

Supervisor:金子 峰雄

情報科学研究科

修士

Subjects/Keywords: スキュー, タイミングスキュー調整, データパス, 演算器割当て.; skew, timing-adjustability, datapath, allocation.

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APA (6th Edition):

手原, . (n.d.). タイミングスキュー調整可能データパスのための設計制約と合成法. (Thesis). Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学. Retrieved from http://hdl.handle.net/10119/8950

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

手原, 亮. “タイミングスキュー調整可能データパスのための設計制約と合成法.” Thesis, Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学. Accessed April 19, 2021. http://hdl.handle.net/10119/8950.

Note: this citation may be lacking information needed for this citation format:
No year of publication.
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

手原, 亮. “タイミングスキュー調整可能データパスのための設計制約と合成法.” Web. 19 Apr 2021.

Note: this citation may be lacking information needed for this citation format:
No year of publication.

Vancouver:

手原 . タイミングスキュー調整可能データパスのための設計制約と合成法. [Internet] [Thesis]. Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学; [cited 2021 Apr 19]. Available from: http://hdl.handle.net/10119/8950.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.

Council of Science Editors:

手原 . タイミングスキュー調整可能データパスのための設計制約と合成法. [Thesis]. Japan Advanced Institute of Science and Technology / 北陸先端科学技術大学院大学; Available from: http://hdl.handle.net/10119/8950

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
No year of publication.


University of Florida

16. Pansare, Niketan. Multi-Query Optimization in the Datapath System.

Degree: MS, Computer Engineering - Computer and Information Science and Engineering, 2009, University of Florida

 The performance of conventional databases on modern hardware is suboptimal as compared to the scientific and commercial applications. Recent studies have shown that this suboptimal… (more)

Subjects/Keywords: Algorithms; Cost functions; Costing; Databases; Engines; Experimental results; Heuristics; International conferences; Search strategies; Side tables; datapath, multi, optimization, query

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pansare, N. (2009). Multi-Query Optimization in the Datapath System. (Masters Thesis). University of Florida. Retrieved from https://ufdc.ufl.edu/UFE0025140

Chicago Manual of Style (16th Edition):

Pansare, Niketan. “Multi-Query Optimization in the Datapath System.” 2009. Masters Thesis, University of Florida. Accessed April 19, 2021. https://ufdc.ufl.edu/UFE0025140.

MLA Handbook (7th Edition):

Pansare, Niketan. “Multi-Query Optimization in the Datapath System.” 2009. Web. 19 Apr 2021.

Vancouver:

Pansare N. Multi-Query Optimization in the Datapath System. [Internet] [Masters thesis]. University of Florida; 2009. [cited 2021 Apr 19]. Available from: https://ufdc.ufl.edu/UFE0025140.

Council of Science Editors:

Pansare N. Multi-Query Optimization in the Datapath System. [Masters Thesis]. University of Florida; 2009. Available from: https://ufdc.ufl.edu/UFE0025140


University of South Florida

17. Mohanty, Saraju P. Energy and Transient Power Minimization During Behavioral Synthesis.

Degree: 2003, University of South Florida

 The proliferation of portable systems and mobile computing platforms has increased the need for the design of low power consuming integrated circuits. The increase in… (more)

Subjects/Keywords: peak power; average power; power fluctuation; low power synthesis; datapath scheduling; multiple supply voltages; dynamic frequency clocking; multicycling; digital watermarking; American Studies; Arts and Humanities

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APA (6th Edition):

Mohanty, S. P. (2003). Energy and Transient Power Minimization During Behavioral Synthesis. (Thesis). University of South Florida. Retrieved from https://scholarcommons.usf.edu/etd/1431

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mohanty, Saraju P. “Energy and Transient Power Minimization During Behavioral Synthesis.” 2003. Thesis, University of South Florida. Accessed April 19, 2021. https://scholarcommons.usf.edu/etd/1431.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mohanty, Saraju P. “Energy and Transient Power Minimization During Behavioral Synthesis.” 2003. Web. 19 Apr 2021.

Vancouver:

Mohanty SP. Energy and Transient Power Minimization During Behavioral Synthesis. [Internet] [Thesis]. University of South Florida; 2003. [cited 2021 Apr 19]. Available from: https://scholarcommons.usf.edu/etd/1431.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mohanty SP. Energy and Transient Power Minimization During Behavioral Synthesis. [Thesis]. University of South Florida; 2003. Available from: https://scholarcommons.usf.edu/etd/1431

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

18. Δημητρακόπουλος, Γεώργιος. Μονάδες επεξεργασίας δεδομένων για μικροεπεξεργαστές υψηλών αποδόσεων.

Degree: 2006, University of Patras

 Οι μονάδες επεξεργασίας δεδομένων αποτελούν τις βασικές δομικές μονάδες όλων των μικροεπεξεργαστών. Κάποια από τα κυκλώματα αυτής της κατηγορίας υλοποιούν τις βασικές αριθμητικές πράξεις πάνω… (more)

Subjects/Keywords: Μικροεπεξεργαστές; Ολοκληρωμένα μεγάλης κλίμακας ολοκλήρωσης; Μονάδες επεξεργασίας δεδομένων; Μονάδες παράλληλης επεξεργασίας υπολέξεων για πολυμεσικές εφαρμογές; Μονάδες κινητής υποδιαστολής; 621.39; Very large scale integration (VLSI); Datapath design; Floating point units; Multimedia single instruction multiple data units

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APA (6th Edition):

Δημητρακόπουλος, . (2006). Μονάδες επεξεργασίας δεδομένων για μικροεπεξεργαστές υψηλών αποδόσεων. (Doctoral Dissertation). University of Patras. Retrieved from http://nemertes.lis.upatras.gr/jspui/handle/10889/1480

Chicago Manual of Style (16th Edition):

Δημητρακόπουλος, Γεώργιος. “Μονάδες επεξεργασίας δεδομένων για μικροεπεξεργαστές υψηλών αποδόσεων.” 2006. Doctoral Dissertation, University of Patras. Accessed April 19, 2021. http://nemertes.lis.upatras.gr/jspui/handle/10889/1480.

MLA Handbook (7th Edition):

Δημητρακόπουλος, Γεώργιος. “Μονάδες επεξεργασίας δεδομένων για μικροεπεξεργαστές υψηλών αποδόσεων.” 2006. Web. 19 Apr 2021.

Vancouver:

Δημητρακόπουλος . Μονάδες επεξεργασίας δεδομένων για μικροεπεξεργαστές υψηλών αποδόσεων. [Internet] [Doctoral dissertation]. University of Patras; 2006. [cited 2021 Apr 19]. Available from: http://nemertes.lis.upatras.gr/jspui/handle/10889/1480.

Council of Science Editors:

Δημητρακόπουλος . Μονάδες επεξεργασίας δεδομένων για μικροεπεξεργαστές υψηλών αποδόσεων. [Doctoral Dissertation]. University of Patras; 2006. Available from: http://nemertes.lis.upatras.gr/jspui/handle/10889/1480

19. Δημητρακόπουλος, Γεώργιος. Μονάδες επεξεργασίας δεδομένων για μικροεπεξεργαστές υψηλών αποδόσεων.

Degree: 2007, University of Patras; Πανεπιστήμιο Πατρών

The basis of all circuits presented in this thesis is the derivation of an inherently simpler Algorithm that would allow then efficient implementation irrespective the… (more)

Subjects/Keywords: Μικροεπεξεργαστές; Ολοκληρωμένα μεγάλης κλίμακας ολοκλήρωσης; Μονάδες επεξεργασίας δεδομένων; Μονάδες παράλληλης επεξεργασίας υπολέξεων για πολυμεσικές εφαρμογές; Μονάδες κινητής υποδιαστολής; Very large scale integration (VLSI); Datapath design; Multimedia single instruction multiple data units; Floating point units

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Δημητρακόπουλος, . . (2007). Μονάδες επεξεργασίας δεδομένων για μικροεπεξεργαστές υψηλών αποδόσεων. (Thesis). University of Patras; Πανεπιστήμιο Πατρών. Retrieved from http://hdl.handle.net/10442/hedi/26712

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Δημητρακόπουλος, Γεώργιος. “Μονάδες επεξεργασίας δεδομένων για μικροεπεξεργαστές υψηλών αποδόσεων.” 2007. Thesis, University of Patras; Πανεπιστήμιο Πατρών. Accessed April 19, 2021. http://hdl.handle.net/10442/hedi/26712.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Δημητρακόπουλος, Γεώργιος. “Μονάδες επεξεργασίας δεδομένων για μικροεπεξεργαστές υψηλών αποδόσεων.” 2007. Web. 19 Apr 2021.

Vancouver:

Δημητρακόπουλος . Μονάδες επεξεργασίας δεδομένων για μικροεπεξεργαστές υψηλών αποδόσεων. [Internet] [Thesis]. University of Patras; Πανεπιστήμιο Πατρών; 2007. [cited 2021 Apr 19]. Available from: http://hdl.handle.net/10442/hedi/26712.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Δημητρακόπουλος . Μονάδες επεξεργασίας δεδομένων για μικροεπεξεργαστές υψηλών αποδόσεων. [Thesis]. University of Patras; Πανεπιστήμιο Πατρών; 2007. Available from: http://hdl.handle.net/10442/hedi/26712

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

20. Pasca, Bogdan Mihai. Calcul flottant haute performance sur circuits reconfigurables : High-performance floating-point computing on reconfigurable circuits.

Degree: Docteur es, Informatique, 2011, Lyon, École normale supérieure

De plus en plus de constructeurs proposent des accélérateurs de calculs à base de circuits reconfigurables FPGA, cette technologie présentant bien plus de souplesse que… (more)

Subjects/Keywords: FPGA; Virgule flottante; FloPoCo; Chemin de données arithmétique; Pipeline pour une fréquence donnée; Addition pipelinée; Additionneur rapide; Multiplication; Karatsuba-Offman; Carré; Multiplieur tronqué; Multiplication par pavage; Virgule fixe; Approximation polynomiale; Racine carrée flottante; Exponentielle flottante; Accumulation flottante; Schéma d'évaluation de Horner; Somme de carrés flottante; Synthèse de haut niveau; Nid de boucles parfait; Multiplication de matrices; Jacobi; Dilemme du fabricant de table; Méthode des différences tabulées; Communications pipelinées; FPGA; Floating-point; FloPoCo; Arithmetic datapath; Frequency-driven pipelining; Pipelined addition; Short-latency adder; Multiplication; Karatsuba-Offman; Squarer; Truncated multiplier; Multiplication tiling; Fixed-point; Polynomial approximation; Floating-point square root; Floating-point exponential; Floating-point accumulation; Horner datapath; Floating-point sum-of-products; High-level synthesis; Perfect loop nests; Matrix-matrix multiply; Jacobi stencil; Table maker's dilemma; Pipelined communications; Pipelined communications

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APA (6th Edition):

Pasca, B. M. (2011). Calcul flottant haute performance sur circuits reconfigurables : High-performance floating-point computing on reconfigurable circuits. (Doctoral Dissertation). Lyon, École normale supérieure. Retrieved from http://www.theses.fr/2011ENSL0656

Chicago Manual of Style (16th Edition):

Pasca, Bogdan Mihai. “Calcul flottant haute performance sur circuits reconfigurables : High-performance floating-point computing on reconfigurable circuits.” 2011. Doctoral Dissertation, Lyon, École normale supérieure. Accessed April 19, 2021. http://www.theses.fr/2011ENSL0656.

MLA Handbook (7th Edition):

Pasca, Bogdan Mihai. “Calcul flottant haute performance sur circuits reconfigurables : High-performance floating-point computing on reconfigurable circuits.” 2011. Web. 19 Apr 2021.

Vancouver:

Pasca BM. Calcul flottant haute performance sur circuits reconfigurables : High-performance floating-point computing on reconfigurable circuits. [Internet] [Doctoral dissertation]. Lyon, École normale supérieure; 2011. [cited 2021 Apr 19]. Available from: http://www.theses.fr/2011ENSL0656.

Council of Science Editors:

Pasca BM. Calcul flottant haute performance sur circuits reconfigurables : High-performance floating-point computing on reconfigurable circuits. [Doctoral Dissertation]. Lyon, École normale supérieure; 2011. Available from: http://www.theses.fr/2011ENSL0656

21. Vissa, Pranay. Toward high-level synthesis of reliable circuits through low-cost modulo shadow datapaths.

Degree: MS, Electrical & Computer Engr, 2015, University of Illinois – Urbana-Champaign

 With transistor dimensions shrinking to the atomic scale, a plethora of new reliability problems presents a barrier to continued Moore’s law scaling. Traditional modular redundancy… (more)

Subjects/Keywords: high-level synthesis; automation; error detection; scheduling; binding; optimization; pipelining; modulo arithmetic; logic optimization; state machine; datapath; shadow logic; low cost; high performance; electrical faults; Aliasing; stuck-at faults; soft errors; timing errors; checkpointing; rollback recovery

…consistency checker allocation 2. Pipelining for deferred scheduling of the shadow datapath to… …Generating an RTL description of the state machine and datapath from the scheduling and binding… …study because they are the most fundamental for datapath design. The choice of b is important… …original datapath uses an unsigned bit encoding for all variables. To modify our reducers to… …series of low-cost shadow datapath high-level synthesis transformations. An overview of how… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vissa, P. (2015). Toward high-level synthesis of reliable circuits through low-cost modulo shadow datapaths. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/78571

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vissa, Pranay. “Toward high-level synthesis of reliable circuits through low-cost modulo shadow datapaths.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed April 19, 2021. http://hdl.handle.net/2142/78571.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vissa, Pranay. “Toward high-level synthesis of reliable circuits through low-cost modulo shadow datapaths.” 2015. Web. 19 Apr 2021.

Vancouver:

Vissa P. Toward high-level synthesis of reliable circuits through low-cost modulo shadow datapaths. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2021 Apr 19]. Available from: http://hdl.handle.net/2142/78571.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vissa P. Toward high-level synthesis of reliable circuits through low-cost modulo shadow datapaths. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/78571

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

22. Campbell, Keith A. Low-cost error detection through high-level synthesis.

Degree: MS, Electrical & Computer Engineering, 2015, University of Illinois – Urbana-Champaign

 System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling and complexity has resulted in a… (more)

Subjects/Keywords: High-level synthesis; Automation; error detection; scheduling; binding; compiler transformation; compiler optimization; pipelining; modulo arithmetic; logic optimization; state machine; datapath, control logic; shadow logic; low cost; high performance; electrical bugs; Aliasing; stuck-at faults; soft errors; timing errors; checkpointing; rollback; recovery; post-silicon validation; Accelerators; system on a chip; signature generation; execution signatures; execution hashing; logic bugs; nondeterministic bugs; masked errors; circuit reliability; hot spots; wear out; silent data corruption; observability; detection latency; mixed datapath; diversity; checkpoint corruption; error injection; error removal; Quick Error Detection (QED); Hybrid Quick Error Detection (H-QED); hybrid hardware/software; execution tracing; address conversion; undefined behavior; High-Level Synthesis (HLS) engine bugs; detection coverage

…redundant, but smaller “shadow” datapath based on modulo arithmetic to detect reliability problems… …in a design’s main datapath. HLS is critical here because it provides a clear picture of… …the datapath of the design and enables e↵ective sharing of expensive checksum computing… …state machine and datapath solution. 15 CHAPTER 2 RELATED WORK 2.1 Hardware Reliability A… …propose creating a redundant, but smaller “shadow” datapath based on modulo arithmetic to detect… 

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APA (6th Edition):

Campbell, K. A. (2015). Low-cost error detection through high-level synthesis. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/89068

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Campbell, Keith A. “Low-cost error detection through high-level synthesis.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed April 19, 2021. http://hdl.handle.net/2142/89068.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Campbell, Keith A. “Low-cost error detection through high-level synthesis.” 2015. Web. 19 Apr 2021.

Vancouver:

Campbell KA. Low-cost error detection through high-level synthesis. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2021 Apr 19]. Available from: http://hdl.handle.net/2142/89068.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Campbell KA. Low-cost error detection through high-level synthesis. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/89068

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

23. Campbell, Keith A. Robust and reliable hardware accelerator design through high-level synthesis.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling-driven complexity has resulted in a variety… (more)

Subjects/Keywords: High-level synthesis (HLS); Automation; Error detection; Scheduling; Binding; Compiler transformation; Compiler optimization; Pipelining; Modulo arithmetic; Modulo-3; Logic optimization; State machine; Datapath; Control logic; Shadow datapath; Modulo datapath; Low cost; High performance; Electrical bug; Aliasing; Stuck-at fault; Soft error; Timing error; Checkpointing; Rollback; Recovery; Pre-silicon validation; Post-silicon validation; Pre-silicon debug; Post-silicon debug; Accelerator; System on a chip; Signature generation; Execution signature; Execution hash; Logic bug; Nondeterministic bug; Masked error; Circuit reliability; Hot spot; Wear out; Silent data corruption; Observability; Detection latency; Mixed datapath; Diversity; Checkpoint corruption; Error injection; Error removal; Quick Error Detection (QED); Hybrid Quick Error Detection (H-QED); Instrumentation; Hybrid co-simulation; Hardware/software; Integration testing; Hybrid tracing; Hybrid hashing; Source-code localization; Software debugging tool; Valgrind; Clang sanitizer; Clang static analyzer; Cppcheck; Root cause analysis; Execution tracing; Realtime error detection; Simulation trigger; Nonintrusive; Address conversion; Undefined behavior; High-level synthesis (HLS) bug; Detection coverage; Gate-level architecture; Mersenne modulus; Full adder; Half adder; Quarter adder; Wraparound; Modulo reducer; Modulo adder; Modulo multiplier; Modulo comparator; Cross-layer; Algorithm; Instruction; Architecture; Logic synthesis; Physical design; Algorithm-based fault tolerance (ABFT); Error detection by duplicated instructions (EDDI); Parity; Flip-flop hardening; Layout design through error-aware transistor positioning dual interlocked storage cell (LEAP-DICE); Cost-effective; Place-and-route; Field programmable gate array (FPGA) emulation; Application specific integrated circuit (ASIC); Field programmable gate array (FPGA); Energy; Area; Latency

…7, we propose creating a redundant, but smaller “shadow” datapath based on modulo… …arithmetic to detect reliability problems in a design’s main datapath. HLS is critical here because… …it provides a clear 2 picture of the datapath of the design and enables effective sharing… …datapath cost, and enables practical scaling to larger shadow datapath widths for improved error… …generates a complete RTL description of the final state machine and datapath solution. 18… 

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APA (6th Edition):

Campbell, K. A. (2017). Robust and reliable hardware accelerator design through high-level synthesis. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99294

Chicago Manual of Style (16th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed April 19, 2021. http://hdl.handle.net/2142/99294.

MLA Handbook (7th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Web. 19 Apr 2021.

Vancouver:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Apr 19]. Available from: http://hdl.handle.net/2142/99294.

Council of Science Editors:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99294

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