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You searched for subject:(crossbar switch). Showing records 1 – 6 of 6 total matches.

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Delft University of Technology

1. Karadeniz, T. Hardware design and implementation of a network-on-chip based high performance crossbar switch Fabric:.

Degree: 2010, Delft University of Technology

 High-performance routers have the task of transmitting traffic in between the nodes of the Internet, the network of networks that carries the vast amount of… (more)

Subjects/Keywords: Crossbar Switch NoC UDN MDN Network-on-Chip

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APA (6th Edition):

Karadeniz, T. (2010). Hardware design and implementation of a network-on-chip based high performance crossbar switch Fabric:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:2b95ac2a-09d7-4f14-ab08-864d33e61fea

Chicago Manual of Style (16th Edition):

Karadeniz, T. “Hardware design and implementation of a network-on-chip based high performance crossbar switch Fabric:.” 2010. Masters Thesis, Delft University of Technology. Accessed December 06, 2019. http://resolver.tudelft.nl/uuid:2b95ac2a-09d7-4f14-ab08-864d33e61fea.

MLA Handbook (7th Edition):

Karadeniz, T. “Hardware design and implementation of a network-on-chip based high performance crossbar switch Fabric:.” 2010. Web. 06 Dec 2019.

Vancouver:

Karadeniz T. Hardware design and implementation of a network-on-chip based high performance crossbar switch Fabric:. [Internet] [Masters thesis]. Delft University of Technology; 2010. [cited 2019 Dec 06]. Available from: http://resolver.tudelft.nl/uuid:2b95ac2a-09d7-4f14-ab08-864d33e61fea.

Council of Science Editors:

Karadeniz T. Hardware design and implementation of a network-on-chip based high performance crossbar switch Fabric:. [Masters Thesis]. Delft University of Technology; 2010. Available from: http://resolver.tudelft.nl/uuid:2b95ac2a-09d7-4f14-ab08-864d33e61fea


Universidade do Estado do Rio de Janeiro

2. Fábio Gonçalves Pessanha. Arquitetura de uma rede de interconexão com memória compartilhada baseada na topologia crossbar.

Degree: Master, 2013, Universidade do Estado do Rio de Janeiro

Multi-Processor System-on-Chip (MPSoC) possui vários processadores, em um único chip. Várias aplicações podem ser executadas de maneira paralela ou uma aplicação paralelizável pode ser particionada… (more)

Subjects/Keywords: Engenharia Eletrônica; Redes de Interconexão; Memória Compartilhada; Redes Crossbar; Arquitetura de redes; Electronic Engineering; Interconnection Network; Shared Memory; Crossbar Switch; Network architecture; ENGENHARIAS

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APA (6th Edition):

Pessanha, F. G. (2013). Arquitetura de uma rede de interconexão com memória compartilhada baseada na topologia crossbar. (Masters Thesis). Universidade do Estado do Rio de Janeiro. Retrieved from http://www.bdtd.uerj.br/tde_busca/arquivo.php?codArquivo=7436 ;

Chicago Manual of Style (16th Edition):

Pessanha, Fábio Gonçalves. “Arquitetura de uma rede de interconexão com memória compartilhada baseada na topologia crossbar.” 2013. Masters Thesis, Universidade do Estado do Rio de Janeiro. Accessed December 06, 2019. http://www.bdtd.uerj.br/tde_busca/arquivo.php?codArquivo=7436 ;.

MLA Handbook (7th Edition):

Pessanha, Fábio Gonçalves. “Arquitetura de uma rede de interconexão com memória compartilhada baseada na topologia crossbar.” 2013. Web. 06 Dec 2019.

Vancouver:

Pessanha FG. Arquitetura de uma rede de interconexão com memória compartilhada baseada na topologia crossbar. [Internet] [Masters thesis]. Universidade do Estado do Rio de Janeiro; 2013. [cited 2019 Dec 06]. Available from: http://www.bdtd.uerj.br/tde_busca/arquivo.php?codArquivo=7436 ;.

Council of Science Editors:

Pessanha FG. Arquitetura de uma rede de interconexão com memória compartilhada baseada na topologia crossbar. [Masters Thesis]. Universidade do Estado do Rio de Janeiro; 2013. Available from: http://www.bdtd.uerj.br/tde_busca/arquivo.php?codArquivo=7436 ;


New Jersey Institute of Technology

3. Guo, Zhen. Design and stability analysis of high performance packet switches.

Degree: PhD, Electrical and Computer Engineering, 2005, New Jersey Institute of Technology

  With the rapid development of optical interconnection technology, high-performance packet switches are required to resolve contentions in a fast manner to satisfy the demand… (more)

Subjects/Keywords: Packet switch; Buffered crossbar; Stability; Crosspoint buffer; Computer Engineering

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APA (6th Edition):

Guo, Z. (2005). Design and stability analysis of high performance packet switches. (Doctoral Dissertation). New Jersey Institute of Technology. Retrieved from https://digitalcommons.njit.edu/dissertations/746

Chicago Manual of Style (16th Edition):

Guo, Zhen. “Design and stability analysis of high performance packet switches.” 2005. Doctoral Dissertation, New Jersey Institute of Technology. Accessed December 06, 2019. https://digitalcommons.njit.edu/dissertations/746.

MLA Handbook (7th Edition):

Guo, Zhen. “Design and stability analysis of high performance packet switches.” 2005. Web. 06 Dec 2019.

Vancouver:

Guo Z. Design and stability analysis of high performance packet switches. [Internet] [Doctoral dissertation]. New Jersey Institute of Technology; 2005. [cited 2019 Dec 06]. Available from: https://digitalcommons.njit.edu/dissertations/746.

Council of Science Editors:

Guo Z. Design and stability analysis of high performance packet switches. [Doctoral Dissertation]. New Jersey Institute of Technology; 2005. Available from: https://digitalcommons.njit.edu/dissertations/746

4. Varela Senín, I. Design of a high-performance buffered crossbar switch fabric using network on chip:.

Degree: Electrical Engineering, Mathematics and Computer Science, Computer Engineering, 2008, Delft University of Technology

 High-performance routers constitute the basic building blocks of the Internet. The wide majority of today's high-performance routers are designed using a crossbar fabric switch as… (more)

Subjects/Keywords: buffered crossbar; network on chip; switch; high performance router

…memory. Among them, the crossbar-based fabric switch is the dominant architecture for today’s… …scheduling algorithm is required to configure the crossbar switch matrix, i.e. deciding which 3… …unbalanced internal buffers utilization. Additionally, whether a crossbar switch is buffered or not… …characteristics, it proposes to replace the actual crossbar switch fabric by a NoC crossbar. This new… …Card Line Card n n Line Card nxn crossbar switch 1 Buffer 2 Buffer n NoC Buffer 1… 

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APA (6th Edition):

Varela Senín, I. (2008). Design of a high-performance buffered crossbar switch fabric using network on chip:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:f66aa5a4-9f51-4846-9d9c-d064e942979e

Chicago Manual of Style (16th Edition):

Varela Senín, I. “Design of a high-performance buffered crossbar switch fabric using network on chip:.” 2008. Masters Thesis, Delft University of Technology. Accessed December 06, 2019. http://resolver.tudelft.nl/uuid:f66aa5a4-9f51-4846-9d9c-d064e942979e.

MLA Handbook (7th Edition):

Varela Senín, I. “Design of a high-performance buffered crossbar switch fabric using network on chip:.” 2008. Web. 06 Dec 2019.

Vancouver:

Varela Senín I. Design of a high-performance buffered crossbar switch fabric using network on chip:. [Internet] [Masters thesis]. Delft University of Technology; 2008. [cited 2019 Dec 06]. Available from: http://resolver.tudelft.nl/uuid:f66aa5a4-9f51-4846-9d9c-d064e942979e.

Council of Science Editors:

Varela Senín I. Design of a high-performance buffered crossbar switch fabric using network on chip:. [Masters Thesis]. Delft University of Technology; 2008. Available from: http://resolver.tudelft.nl/uuid:f66aa5a4-9f51-4846-9d9c-d064e942979e


Virginia Tech

5. Gold, Brian. Balancing Performance, Area, and Power in an On-Chip Network.

Degree: MS, Electrical and Computer Engineering, 2003, Virginia Tech

 Several trends can be observed in modern microprocessor design. Architectures have become increasingly complex while design time continues to dwindle. As feature sizes shrink, wire… (more)

Subjects/Keywords: area; virtual channels; SCMP; power; network; router; crossbar switch; single chip computer; message passing; system on chip

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APA (6th Edition):

Gold, B. (2003). Balancing Performance, Area, and Power in an On-Chip Network. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/34137

Chicago Manual of Style (16th Edition):

Gold, Brian. “Balancing Performance, Area, and Power in an On-Chip Network.” 2003. Masters Thesis, Virginia Tech. Accessed December 06, 2019. http://hdl.handle.net/10919/34137.

MLA Handbook (7th Edition):

Gold, Brian. “Balancing Performance, Area, and Power in an On-Chip Network.” 2003. Web. 06 Dec 2019.

Vancouver:

Gold B. Balancing Performance, Area, and Power in an On-Chip Network. [Internet] [Masters thesis]. Virginia Tech; 2003. [cited 2019 Dec 06]. Available from: http://hdl.handle.net/10919/34137.

Council of Science Editors:

Gold B. Balancing Performance, Area, and Power in an On-Chip Network. [Masters Thesis]. Virginia Tech; 2003. Available from: http://hdl.handle.net/10919/34137


Georgia Tech

6. Shin, Eung Seo. Automated Generation of Round-robin Arbitration and Crossbar Switch Logic.

Degree: PhD, Electrical and Computer Engineering, 2003, Georgia Tech

 The objective of this thesis is to automate the design of round-robin arbiter logic. The resulting arbitration logic is more than 1.8X times faster than… (more)

Subjects/Keywords: RAG; Distributed arbiter; Round-robin token passing; X-Gt; Crossbar switch; Arbiter; Terabit switch; Synthesis; Verilog; Silicon; Switching circuits Design and construction; Logic circuits Design and construction; Metal oxide semiconductors, Complementary Design and construction

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Shin, E. S. (2003). Automated Generation of Round-robin Arbitration and Crossbar Switch Logic. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/5280

Chicago Manual of Style (16th Edition):

Shin, Eung Seo. “Automated Generation of Round-robin Arbitration and Crossbar Switch Logic.” 2003. Doctoral Dissertation, Georgia Tech. Accessed December 06, 2019. http://hdl.handle.net/1853/5280.

MLA Handbook (7th Edition):

Shin, Eung Seo. “Automated Generation of Round-robin Arbitration and Crossbar Switch Logic.” 2003. Web. 06 Dec 2019.

Vancouver:

Shin ES. Automated Generation of Round-robin Arbitration and Crossbar Switch Logic. [Internet] [Doctoral dissertation]. Georgia Tech; 2003. [cited 2019 Dec 06]. Available from: http://hdl.handle.net/1853/5280.

Council of Science Editors:

Shin ES. Automated Generation of Round-robin Arbitration and Crossbar Switch Logic. [Doctoral Dissertation]. Georgia Tech; 2003. Available from: http://hdl.handle.net/1853/5280

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