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You searched for subject:(context switch). Showing records 1 – 4 of 4 total matches.

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1. Wicaksana, Arief. Infrastructure portable pour un système hétérogène reconfigurable dans un environnement de cloud-FPGA : Portable infrastructure for heterogeneous reconfigurable devices in a cloud-FPGA environment.

Degree: Docteur es, Nano electronique et nano technologies, 2018, Université Grenoble Alpes (ComUE)

La haute performance ainsi que la basse consommation d’énergie offertes par lesField-Programmable Gate Arrays (FPGAs) contribuent à leur popularité en tant queaccélérateurs matériels. Cet argument… (more)

Subjects/Keywords: Communication; Cloud; Cloud; Context Switch; 004; 620

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wicaksana, A. (2018). Infrastructure portable pour un système hétérogène reconfigurable dans un environnement de cloud-FPGA : Portable infrastructure for heterogeneous reconfigurable devices in a cloud-FPGA environment. (Doctoral Dissertation). Université Grenoble Alpes (ComUE). Retrieved from http://www.theses.fr/2018GREAT088

Chicago Manual of Style (16th Edition):

Wicaksana, Arief. “Infrastructure portable pour un système hétérogène reconfigurable dans un environnement de cloud-FPGA : Portable infrastructure for heterogeneous reconfigurable devices in a cloud-FPGA environment.” 2018. Doctoral Dissertation, Université Grenoble Alpes (ComUE). Accessed November 28, 2020. http://www.theses.fr/2018GREAT088.

MLA Handbook (7th Edition):

Wicaksana, Arief. “Infrastructure portable pour un système hétérogène reconfigurable dans un environnement de cloud-FPGA : Portable infrastructure for heterogeneous reconfigurable devices in a cloud-FPGA environment.” 2018. Web. 28 Nov 2020.

Vancouver:

Wicaksana A. Infrastructure portable pour un système hétérogène reconfigurable dans un environnement de cloud-FPGA : Portable infrastructure for heterogeneous reconfigurable devices in a cloud-FPGA environment. [Internet] [Doctoral dissertation]. Université Grenoble Alpes (ComUE); 2018. [cited 2020 Nov 28]. Available from: http://www.theses.fr/2018GREAT088.

Council of Science Editors:

Wicaksana A. Infrastructure portable pour un système hétérogène reconfigurable dans un environnement de cloud-FPGA : Portable infrastructure for heterogeneous reconfigurable devices in a cloud-FPGA environment. [Doctoral Dissertation]. Université Grenoble Alpes (ComUE); 2018. Available from: http://www.theses.fr/2018GREAT088


University of Ottawa

2. Wang, Wei. Accessing an FPGA-based Hardware Accelerator in a Paravirtualized Environment .

Degree: 2013, University of Ottawa

 In this thesis we present pvFPGA, the first system design solution for virtualizing an FPGA - based hardware accelerator on the x86 platform. The accelerator… (more)

Subjects/Keywords: FPGA; hardware accelerator; paravirtualization; pvFPGA; coprovisor; data pool; DMA context switch

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APA (6th Edition):

Wang, W. (2013). Accessing an FPGA-based Hardware Accelerator in a Paravirtualized Environment . (Thesis). University of Ottawa. Retrieved from http://hdl.handle.net/10393/24283

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Wei. “Accessing an FPGA-based Hardware Accelerator in a Paravirtualized Environment .” 2013. Thesis, University of Ottawa. Accessed November 28, 2020. http://hdl.handle.net/10393/24283.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Wei. “Accessing an FPGA-based Hardware Accelerator in a Paravirtualized Environment .” 2013. Web. 28 Nov 2020.

Vancouver:

Wang W. Accessing an FPGA-based Hardware Accelerator in a Paravirtualized Environment . [Internet] [Thesis]. University of Ottawa; 2013. [cited 2020 Nov 28]. Available from: http://hdl.handle.net/10393/24283.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang W. Accessing an FPGA-based Hardware Accelerator in a Paravirtualized Environment . [Thesis]. University of Ottawa; 2013. Available from: http://hdl.handle.net/10393/24283

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


York University

3. D'Souza, Annalise. Task Switching Over the Lifespan.

Degree: PhD, Psychology(Functional Area: Developmental Science), 2020, York University

 People often switch from one goal to another, in response to changing environmental demands. Task switching affords flexibility, but at a price. A robust switch(more)

Subjects/Keywords: Developmental psychology; Lifespan cognition; Switch cost; Task switching; Executive function; Web-based research; Cognitive psychology; Development; Aging; Multitasking; Context switching

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

D'Souza, A. (2020). Task Switching Over the Lifespan. (Doctoral Dissertation). York University. Retrieved from https://yorkspace.library.yorku.ca/xmlui/handle/10315/37342

Chicago Manual of Style (16th Edition):

D'Souza, Annalise. “Task Switching Over the Lifespan.” 2020. Doctoral Dissertation, York University. Accessed November 28, 2020. https://yorkspace.library.yorku.ca/xmlui/handle/10315/37342.

MLA Handbook (7th Edition):

D'Souza, Annalise. “Task Switching Over the Lifespan.” 2020. Web. 28 Nov 2020.

Vancouver:

D'Souza A. Task Switching Over the Lifespan. [Internet] [Doctoral dissertation]. York University; 2020. [cited 2020 Nov 28]. Available from: https://yorkspace.library.yorku.ca/xmlui/handle/10315/37342.

Council of Science Editors:

D'Souza A. Task Switching Over the Lifespan. [Doctoral Dissertation]. York University; 2020. Available from: https://yorkspace.library.yorku.ca/xmlui/handle/10315/37342


Brigham Young University

4. Isaacson, Spencer W. Hardware Support for a Configurable Architecture for Real-Time Embedded Systems on a Programmable Chip.

Degree: MS, 2007, Brigham Young University

 Current FPGA technology has advanced to the point that useful embedded SoPCs can now be designed. The Real Time Processor (RTP) project at Brigham Young… (more)

Subjects/Keywords: FPGA; hardware RTOS; real-time; fast context switch; register bank; task; task-resource matrix; embedded; computer architecture; hardware scheduler; task switch; hardware assisted RTOS; Electrical and Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Isaacson, S. W. (2007). Hardware Support for a Configurable Architecture for Real-Time Embedded Systems on a Programmable Chip. (Masters Thesis). Brigham Young University. Retrieved from https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=1970&context=etd

Chicago Manual of Style (16th Edition):

Isaacson, Spencer W. “Hardware Support for a Configurable Architecture for Real-Time Embedded Systems on a Programmable Chip.” 2007. Masters Thesis, Brigham Young University. Accessed November 28, 2020. https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=1970&context=etd.

MLA Handbook (7th Edition):

Isaacson, Spencer W. “Hardware Support for a Configurable Architecture for Real-Time Embedded Systems on a Programmable Chip.” 2007. Web. 28 Nov 2020.

Vancouver:

Isaacson SW. Hardware Support for a Configurable Architecture for Real-Time Embedded Systems on a Programmable Chip. [Internet] [Masters thesis]. Brigham Young University; 2007. [cited 2020 Nov 28]. Available from: https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=1970&context=etd.

Council of Science Editors:

Isaacson SW. Hardware Support for a Configurable Architecture for Real-Time Embedded Systems on a Programmable Chip. [Masters Thesis]. Brigham Young University; 2007. Available from: https://scholarsarchive.byu.edu/cgi/viewcontent.cgi?article=1970&context=etd

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