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1.
Cao, Man.
Efficient, Practical Dynamic Program Analyses for
Concurrency Correctness.
Degree: PhD, Computer Science and Engineering, 2017, The Ohio State University
URL: http://rave.ohiolink.edu/etdc/view?acc_num=osu1492703503634986 
► Shared-memory parallel programs are notoriously difficult to be both scalable and correct. One of the most problematic concurrency bugs is data race. Data races are…
(more)
▼ Shared-memory parallel programs are notoriously
difficult to be both scalable and correct. One of the most
problematic
concurrency bugs is
data race.
Data races are difficult
to avoid, find, fix, reproduce, and eliminate. A fundamental
problem is that language and hardware memory models provide few or
no guarantees for executions containing
data races. Researchers
have developed various program analyses and
runtime tools for
concurrency correctness properties. Examples includes
data race
detectors, multithreaded record & replay, transactional memory,
and enforcement of stronger memory models. However, in the presence
of
data races, many of these tools suffer from limitations that
impede their widespread use.The first challenge in handling racy
executions is the high overhead for tracking (i.e., detect or
control) cross-thread dependences, which is a necessary requirement
to ensure the soundness of many analyses. The second limitation is
that existing work has not covered the full range of possible
behaviors for racy executions in weak memory models. This thesis
explores several efficient and practical
dynamic program analyses
that aim to overcome these two key limitations, advancing the state
of the art for detecting, enforcing, and exposing issues related to
concurrency correctness.We present hybrid tracking and RegPlay to
address the first challenge. Hybrid tracking is a generalized
framework for tracking dependences, which hybridizes pessimistic
and optimistic tracking in order to get the best of both world. We
build hybrid-tracking-based versions of a dependence recorder and a
region serializability enforcer to demonstrate the usefulness of
hybrid tracking. RegPlay shows an
analysis-specifc way of
optimizing dependence tracking in the context of multithreaded
record & replay. RegPlay avoids recording read – write
dependences and many transitively implied dependences in order to
reduce run-time overhead, and enforces replay determinism by
detecting and resolving violations of read – write dependences.
Experiments show that hybrid tracking enables
runtime support to
overcome the
performance limitations of both pessimistic and
optimistic tracking alone, and RegPlay records much fewer
dependences than existing approach while preserves replay
determinism.To address the second limitation, we introduce
prescient memory (PM), a novel
dynamic analysis that exposes
behaviors due to future values – a value written by a store that
executes after the load that uses the value. A load could return a
future value in a racy execution in weak memory models, but
existing analyses fail to expose such behaviors. PM speculatively
returns a future value at a program load, and tries to validate the
speculative value at a later store. PM applies a novel approach
that profiles future values and guides execution to increase the
chances of successfully validating future values in real
application executions. Experiments shows that PM uncovers a few
previously unknown behaviors due to future values in real
applications.Overall, this thesis…
Advisors/Committee Members: Bond, Michael (Advisor).
Subjects/Keywords: Computer Science; Computer Engineering; concurrency, runtime, parallelism, correctness, bug
detection, performance, data race, dynamic analysis
…Lightweight Data Race Detection for Production Runs. In International Conference on
Compiler… …concurrency issues, such as deadlock, data race, atomicity violation,
and nondeterminism. General… …data races. Notable examples of runtime support include data race detectors (e.g., [… …practical dynamic program analyses
and runtime support must handle executions containing data… …races. Runtime support that
ignores data races is unsound and unreliable. For an analysis that…
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APA (6th Edition):
Cao, M. (2017). Efficient, Practical Dynamic Program Analyses for
Concurrency Correctness. (Doctoral Dissertation). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1492703503634986
Chicago Manual of Style (16th Edition):
Cao, Man. “Efficient, Practical Dynamic Program Analyses for
Concurrency Correctness.” 2017. Doctoral Dissertation, The Ohio State University. Accessed March 03, 2021.
http://rave.ohiolink.edu/etdc/view?acc_num=osu1492703503634986.
MLA Handbook (7th Edition):
Cao, Man. “Efficient, Practical Dynamic Program Analyses for
Concurrency Correctness.” 2017. Web. 03 Mar 2021.
Vancouver:
Cao M. Efficient, Practical Dynamic Program Analyses for
Concurrency Correctness. [Internet] [Doctoral dissertation]. The Ohio State University; 2017. [cited 2021 Mar 03].
Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1492703503634986.
Council of Science Editors:
Cao M. Efficient, Practical Dynamic Program Analyses for
Concurrency Correctness. [Doctoral Dissertation]. The Ohio State University; 2017. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1492703503634986
Texas A&M University
2.
Rajagopalan, Arun Krishnakumar.
Fast and Precise On-The-Fly Data Race Detection.
Degree: MS, Computer Science, 2016, Texas A&M University
URL: http://hdl.handle.net/1969.1/157131
► While concurrent programming is quickly gaining popularity lately, developing bug-free programs is still challenging. Although developers have a wide choice of race detection tools available,…
(more)
▼ While concurrent programming is quickly gaining popularity lately, developing
bug-free programs is still challenging. Although developers have a wide choice of
race detection tools available, we have found that the majority of these techniques do not scale well and developers are often forced to balance precision with speed. Additionally, various practical issues force even precise
race detectors to produce spurious warnings, defeating their purpose and burdening their users. We design and implement a novel
race detection technique that is both fast and precise, even in the face of missing program source information. Towards this goal, we have developed two separate tools, TREE and RDIT, that respectively improve
performance and precision over existing techniques.
TREE, implemented in the RoadRunner framework, acts as a filter and sends through only those events that might add value to
race detection while eliminating those events which are deemed redundant for this purpose. All the while, removing these redundant events does not affect its
race detection capability. We have evaluated TREE against a whole set of standard benchmarks, including two large real-world applications. We have found that there exists a significant number of redundant events in all these applications and on an average, TREE saves somewhere between 15-25% of
analysis time as compared to the state-of-the-art techniques.
Meanwhile, our next tool, RDIT, is able to precisely detect races in programs with incomplete source information, generating no false positives. RDIT is also maximal in the sense that it detects a maximal set of true races from the observed incomplete trace. It is underpinned by a sound BarrierPair model that abstracts away the missing events by capturing the invocation
data of their enclosing methods. By making the least conservative assumption that a missing method introduces synchronization only when its invocation
data overlaps with other missing methods, and by formulating maximal thread causality as a set of logical constraints, RDIT guarantees to precisely detect races with maximal capability. We tested RDIT against seven real-world large concurrent systems and have detected dozens of true races with zero false alarm. Comparatively, existing algorithms such as Happens-Before, Causal-Precede, and Maximal-Causality, which are all known to be precise, were observed reporting hundreds of false alarms due to trace incompleteness.
Advisors/Committee Members: Huang, Jeff (advisor), Welch, Jennifer L (committee member), Ji, Jim (committee member).
Subjects/Keywords: bug detection; concurrency; debugging; dynamic analysis; parallelism; performance analysis; runtime monitoring; software engineering; redundancy; data race; missing events; precise detection; happens-before; maximal thread causality
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APA (6th Edition):
Rajagopalan, A. K. (2016). Fast and Precise On-The-Fly Data Race Detection. (Masters Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/157131
Chicago Manual of Style (16th Edition):
Rajagopalan, Arun Krishnakumar. “Fast and Precise On-The-Fly Data Race Detection.” 2016. Masters Thesis, Texas A&M University. Accessed March 03, 2021.
http://hdl.handle.net/1969.1/157131.
MLA Handbook (7th Edition):
Rajagopalan, Arun Krishnakumar. “Fast and Precise On-The-Fly Data Race Detection.” 2016. Web. 03 Mar 2021.
Vancouver:
Rajagopalan AK. Fast and Precise On-The-Fly Data Race Detection. [Internet] [Masters thesis]. Texas A&M University; 2016. [cited 2021 Mar 03].
Available from: http://hdl.handle.net/1969.1/157131.
Council of Science Editors:
Rajagopalan AK. Fast and Precise On-The-Fly Data Race Detection. [Masters Thesis]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/157131
University of Illinois – Urbana-Champaign
3.
Qi, Shanxiang.
Techniques to detect and avert advanced software concurrency bugs.
Degree: PhD, 0112, 2013, University of Illinois – Urbana-Champaign
URL: http://hdl.handle.net/2142/45603
► Multicore machines have become pervasive and, as a result, parallel programming has received renewed interest. Unfortunately, writing correct parallel programs is notoriously hard. One challenging…
(more)
▼ Multicore machines have become pervasive and, as a result, parallel programming has received
renewed interest. Unfortunately, writing correct parallel programs is notoriously hard. One challenging
problem is how to ship correct programs.
Dynamic analysis tools are very useful to find
errors in parallel programs by automatically analyzing the
runtime information. They often capture
errors from well-tested programs.
However, existing
dynamic analysis tools suffer from two problems: high false positive rate
and high overhead. High false positive rate means lots of errors reported by the
dynamic analysis
tool may be benign or non-existent. For example, lots of
data races detected by a
race detection
tool could be relatively benign
data races. Also, many
dynamic software analyses cause orders-ofmagnitude
slowdowns, which users cannot tolerate at
runtime.
This dissertation contains three parts. The first two parts propose two different schemes to
reduce the false positives and overhead of
race detecting tools. These two schemes can detect
and tolerate two different types of harmful races with low overhead: asymmetric
data races and
IF-condition
data races.
An asymmetric
data race occurs when at least one of the racing threads is inside a critical
section. Our proposal to detect and tolerate asymmetric
data races is called Pacman. It exploits
cache coherence hardware to temporarily protect the variables that a thread accesses in a critical
section from other threads’s requests.
An IF-condition
data race is one where a memory location accessed by a thread (T1) in the
control expression of an IF statement suffers a
race while T1 is executing the THEN or ELSE
clauses. T1 may or may not access again the location in the THEN or ELSE clauses. Our second proposal presents two techniques to handle IF-condition races dynamically. They rely on simple
code transformations and, in one case, on additional hardware help.
The third part proposes a general hardware framework to provide fine-grained memory monitoring
with low overhead. This mechanism can be used to reduce the overhead of many
dynamic
software analyses.
Overall, this dissertation aims at designing novel schemes to reduce the false positive rate and
overhead of
dynamic software analyses in order to make parallel programs more robust.
Advisors/Committee Members: Torrellas, Josep (advisor), Torrellas, Josep (Committee Chair), Marinov, Darko (committee member), King, Samuel T. (committee member), Lu, Shan (committee member).
Subjects/Keywords: concurrency bugs; data race detection; dynamic analysis
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APA ·
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APA (6th Edition):
Qi, S. (2013). Techniques to detect and avert advanced software concurrency bugs. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/45603
Chicago Manual of Style (16th Edition):
Qi, Shanxiang. “Techniques to detect and avert advanced software concurrency bugs.” 2013. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 03, 2021.
http://hdl.handle.net/2142/45603.
MLA Handbook (7th Edition):
Qi, Shanxiang. “Techniques to detect and avert advanced software concurrency bugs.” 2013. Web. 03 Mar 2021.
Vancouver:
Qi S. Techniques to detect and avert advanced software concurrency bugs. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2013. [cited 2021 Mar 03].
Available from: http://hdl.handle.net/2142/45603.
Council of Science Editors:
Qi S. Techniques to detect and avert advanced software concurrency bugs. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2013. Available from: http://hdl.handle.net/2142/45603
University of New South Wales
4.
Xie, Xinwei.
Accurate and efficient on-the-fly data race detection for multithreaded programs.
Degree: Computer Science & Engineering, 2012, University of New South Wales
URL: http://handle.unsw.edu.au/1959.4/52125
;
https://unsworks.unsw.edu.au/fapi/datastream/unsworks:10795/SOURCE01?view=true
► Benefiting from the recent hardware improvement, multithreaded programs may still introduce concurrency defects which are notoriously difficult to detect, due to the non-deterministic program behavior.…
(more)
▼ Benefiting from the recent hardware improvement, multithreaded programs may still introduce concurrency defects which are notoriously difficult to detect, due to the non-deterministic program behavior. One of such defects is known as data race. Programs which have data races often results in inconsistent data and unpredictable behavior. Conventional hybrid approaches of detecting data races suffer from either excessive analysis overhead or precision loss.In this thesis, we introduce three hybrid algorithms for detecting data races in multithreaded programs. By leveraging recent advances on more efficiently tracking the happens-before relation and by developing new lockset algorithms, our detectors can find more potential data races with less false warnings at some slight performance degradation.We first propose Acculock, which is the first hybrid detector that combines lockset and epoch-based happens-before for data race detection. Acculock analyzes a program execution by reasoning about the subset of the happens-before relation, thereby making it less sensitive to thread interleaving than pure happens-before detectors. When this relaxed happens-before relation is violated, Acculock applies a new lockset algorithm to verify the locking discipline, hence making it report less false warnings than the pure lockset detectors.We also propose MPL, which records sets of locksets instead of locksets to detect data races caused by the use of the multiple-protecting-lock idiom, which cannot be detected by Acculock. We finally present an improved version of MPL, MultiLock-HB, which also leverages the epoch-based happens-before technique by combining with a new lockset algorithm to reduce excessive false warnings and to find more races than MPL.All the properties of Acculock have been validated and confirmed by comparing it six other detectors, which are implemented in Jikes RVM using a collection of large benchmarks. Porting Acculock and repeating experiments in a different platform, RoadRunner, yields similar observations and conclusions in terms of their effectiveness in race detection and instrumentation overhead. Replacing the lockset algorithm used in Acculock with MultiLock-HB only suppresses three false warnings in eclipse at the expense of 3X performance slowdown (on average). Therefore, we can selectively apply MultiLock-HB to certain complicated applications where Acculock fails to reason about the multiple-protecting-lock idiom.
Subjects/Keywords: concurrency; Concurrency; Data race; Dynamic analysis
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APA ·
Chicago ·
MLA ·
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CSE |
Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Xie, X. (2012). Accurate and efficient on-the-fly data race detection for multithreaded programs. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/52125 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:10795/SOURCE01?view=true
Chicago Manual of Style (16th Edition):
Xie, Xinwei. “Accurate and efficient on-the-fly data race detection for multithreaded programs.” 2012. Doctoral Dissertation, University of New South Wales. Accessed March 03, 2021.
http://handle.unsw.edu.au/1959.4/52125 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:10795/SOURCE01?view=true.
MLA Handbook (7th Edition):
Xie, Xinwei. “Accurate and efficient on-the-fly data race detection for multithreaded programs.” 2012. Web. 03 Mar 2021.
Vancouver:
Xie X. Accurate and efficient on-the-fly data race detection for multithreaded programs. [Internet] [Doctoral dissertation]. University of New South Wales; 2012. [cited 2021 Mar 03].
Available from: http://handle.unsw.edu.au/1959.4/52125 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:10795/SOURCE01?view=true.
Council of Science Editors:
Xie X. Accurate and efficient on-the-fly data race detection for multithreaded programs. [Doctoral Dissertation]. University of New South Wales; 2012. Available from: http://handle.unsw.edu.au/1959.4/52125 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:10795/SOURCE01?view=true
University of Illinois – Urbana-Champaign
5.
Dang, Hoang-Vu.
Fast and generic concurrent message-passing.
Degree: PhD, Computer Science, 2018, University of Illinois – Urbana-Champaign
URL: http://hdl.handle.net/2142/102842
► Communication hardware and software have a significant impact on the performance of clusters and supercomputers. Message passing model and the Message-Passing Interface (MPI) is a…
(more)
▼ Communication hardware and software have a significant impact on the
performance of clusters and supercomputers. Message passing model and the Message-Passing Interface (MPI) is a widely used model of communications in the High-
Performance Computing (HPC) community with great success. However, it has recently faced new challenges due to the emergence of many-core architecture and of programming models with
dynamic task
parallelism, assuming a large number of concurrent, light-weight threads. These applications come from important classes of applications such as graph and
data analytics. Using MPI with these languages/runtimes is inefficient because MPI implementation is not able to perform well with threads. Using MPI as a communication middleware is also not efficient since MPI has to provide many abstractions that are not needed for many of the frameworks, thus having extra overheads.
In this thesis, we studied MPI
performance under the new assumptions. We identified several factors in the message-passing model which were inherently problematic for scalability and
performance. Next, we analyzed the communication of a number of graph, threading and
data-flow frameworks to identify generic patterns. We then proposed a low-level communication interface (LCI) to bridge the gap between communication architecture and
runtime. The core of our idea is to attach to each message a few simple operations which fit better with the current hardware and can be implemented efficiently. We show that with only a few carefully chosen primitives and appropriate design, message-passing under this interface can easily outperform production MPI when running atop of multi-threaded environment. Further, using LCI is simple for various types of usage.
Advisors/Committee Members: Snir, Marc (advisor), Snir, Marc (Committee Chair), Gropp, William (committee member), Adve, Sarita (committee member), Hoefler, Torsten (committee member).
Subjects/Keywords: MPI; message-passing; communication; runtime; concurrency; parallelism; performance
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APA ·
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MLA ·
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Export
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Manager
APA (6th Edition):
Dang, H. (2018). Fast and generic concurrent message-passing. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/102842
Chicago Manual of Style (16th Edition):
Dang, Hoang-Vu. “Fast and generic concurrent message-passing.” 2018. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 03, 2021.
http://hdl.handle.net/2142/102842.
MLA Handbook (7th Edition):
Dang, Hoang-Vu. “Fast and generic concurrent message-passing.” 2018. Web. 03 Mar 2021.
Vancouver:
Dang H. Fast and generic concurrent message-passing. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2018. [cited 2021 Mar 03].
Available from: http://hdl.handle.net/2142/102842.
Council of Science Editors:
Dang H. Fast and generic concurrent message-passing. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2018. Available from: http://hdl.handle.net/2142/102842
University of Illinois – Chicago
6.
Gondi, Kalpana.
Program Transformation Techniques for Erasing Sensitive Data in Sequential and Concurrent Applications.
Degree: 2014, University of Illinois – Chicago
URL: http://hdl.handle.net/10027/11204
► The memory footprints of sensitive data in security critical systems programs and end user applications is generally not ensured to be kept small. This results…
(more)
▼ The memory footprints of sensitive
data in security critical systems programs and end user applications is generally not ensured to be kept small. This results in
data being left over in the memory long after it has been last used in the program. The prolonged presence of such memory resident
data that is sensitive (such as passwords and cryptographic keys) poses a number of security risks.
The onus of ensuring that sensitive
data does not remain in the program well beyond its intended use is left entirely to the programmer. Unfortunately this is only done by the most sophisticated of applications developers, as many developers are not simply aware of these issues. Consequently, there is a dire need to retrofit applications to minimize the prolonged life of sensitive
data in memory. A promising approach is to delete sensitive
data as soon as it becomes unnecessary.
In this thesis, we propose methods to reduce the lifetime of memory resident
data by erasing the memory footprint of sensitive
data after it’s last usage in programs. Our approach uses program transformation techniques to achieve the goal of precise and effective minimization of
data exposure in sequential and concurrent applications.
We first describe SWIPE, an approach to reduce the lifetime of sensitive, memory resident
data in large-scale sequential applications written in C. In contrast to prior approaches that used a delayed or lazy approach to the problem of erasing sensitive
data, SWIPE uses a novel eager erasure approach that minimizes the risk of accidental sensitive
data leakage. SWIPE achieves this by transforming a legacy sequential C program to include additional instructions that erase sensitive
data immediately after its intended use. SWIPE is guided by a highly scalable static
analysis technique that precisely identifies locations to introduce erase instructions in the original program. In our experiments, SWIPE is able to successfully and robustly transform several large applications with minimal
performance overheads. The sequential programs transformed using SWIPE enjoy several additional advantages: minimization of leaks that arise due to
data dependencies; erasure of sensitive
data with minimal developer guidance; and negligible
performance overheads (averaging 1.35%).
We subsequently tackle the challenge of minimizing
data lifetime in the realm of concurrent pro- grams. In this case, the issues are comparatively more challenging as the interleaving of threads in concurrent applications makes the determination of lifetime statically difficult. In this dissertation, we also address the problem of
data lifetime minimization for concurrent programs in addition to sequential programs. The major challenge for our approach is to ensure that the erasures introduced to the shared memory locations are done after anticipating all possible interleaving of threads, in order to en- sure soundness. We develop a new algorithm that anticipates shared variable lifetimes, and correctly introduce erase instructions. This algorithm is implemented in a…
Advisors/Committee Members: Sistla, Prasad A. (advisor), Eriksson, Jakob (committee member), Grechanik, Mark (committee member), Solworth, Jon A. (committee member), Jeffrey, Alan (committee member), Venkatesan Natarajan, Venkatakrishnan (committee member).
Subjects/Keywords: Security; Data lifetime; Static analysis; Program transformation; concurrency; race-detection; Confidentiality
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APA (6th Edition):
Gondi, K. (2014). Program Transformation Techniques for Erasing Sensitive Data in Sequential and Concurrent Applications. (Thesis). University of Illinois – Chicago. Retrieved from http://hdl.handle.net/10027/11204
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Gondi, Kalpana. “Program Transformation Techniques for Erasing Sensitive Data in Sequential and Concurrent Applications.” 2014. Thesis, University of Illinois – Chicago. Accessed March 03, 2021.
http://hdl.handle.net/10027/11204.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Gondi, Kalpana. “Program Transformation Techniques for Erasing Sensitive Data in Sequential and Concurrent Applications.” 2014. Web. 03 Mar 2021.
Vancouver:
Gondi K. Program Transformation Techniques for Erasing Sensitive Data in Sequential and Concurrent Applications. [Internet] [Thesis]. University of Illinois – Chicago; 2014. [cited 2021 Mar 03].
Available from: http://hdl.handle.net/10027/11204.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Gondi K. Program Transformation Techniques for Erasing Sensitive Data in Sequential and Concurrent Applications. [Thesis]. University of Illinois – Chicago; 2014. Available from: http://hdl.handle.net/10027/11204
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Virginia Tech
7.
Zhang, Tong.
Designing Practical Software Bug Detectors Using Commodity Hardware and Common Programming Patterns.
Degree: PhD, Computer Science and Applications, 2020, Virginia Tech
URL: http://hdl.handle.net/10919/96422
► Software bugs have caused many real-world problems, e.g., the 2003 Northeast blackout and the Facebook stock price mismatch. Finding bugs is critical to solving those…
(more)
▼ Software bugs have caused many real-world problems, e.g., the 2003 Northeast blackout and the Facebook stock price mismatch. Finding bugs is critical to solving those problems. Unfortunately, many existing
bug detectors suffer from high run-time and space overheads as well as scalability and precision issues. In this dissertation, we address the limitations of
bug detectors by leveraging commodity hardware and common programming patterns. Particularly, we focus on improving the run-time overhead of
dynamic data race detectors, the space overhead of a memory safety
bug detector, and the scalability and precision of the Linux kernel permission check
bug detector. We first present a
data race detector built upon commodity hardware transactional memory that can achieve 7x overhead reduction compared to the state-of-the-art solution (Google's TSAN). We then present a very lightweight sampling-based
data race detector which re-purposes
performance monitoring hardware features for lightweight sampling and uses a novel offline
analysis for better
race detection capability. Our result highlights very low overhead (2.6%) with 27.5%
detection probability with a sampling period of 10,000. Next, we present a space-efficient temporal memory safety
bug detector for a hardware spatial memory safety
bug detector, without additional hardware support. According to experimental results, our full memory safety solution incurs only a 36% memory overhead with a 60% run-time overhead. Finally, we present a permission check
bug detector for the Linux kernel. This
bug detector leverages indirect call usage patterns in the Linux kernel for scalable and precise
analysis. As a result, within a limited time budget (scalable), the detector discovered 14 previously unknown bugs (precise).
Advisors/Committee Members: Lee, Dongyoon (committeechair), Jung, Changhee (committeechair), Cameron, Kirk W. (committee member), Yao, Danfeng (committee member), Cui, Weidong (committee member).
Subjects/Keywords: Software Bug Detection; Compilers; Commodity Hardware; Data Race Detection; Memory Safety; Permission Check Placement Analysis
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APA ·
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to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Zhang, T. (2020). Designing Practical Software Bug Detectors Using Commodity Hardware and Common Programming Patterns. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/96422
Chicago Manual of Style (16th Edition):
Zhang, Tong. “Designing Practical Software Bug Detectors Using Commodity Hardware and Common Programming Patterns.” 2020. Doctoral Dissertation, Virginia Tech. Accessed March 03, 2021.
http://hdl.handle.net/10919/96422.
MLA Handbook (7th Edition):
Zhang, Tong. “Designing Practical Software Bug Detectors Using Commodity Hardware and Common Programming Patterns.” 2020. Web. 03 Mar 2021.
Vancouver:
Zhang T. Designing Practical Software Bug Detectors Using Commodity Hardware and Common Programming Patterns. [Internet] [Doctoral dissertation]. Virginia Tech; 2020. [cited 2021 Mar 03].
Available from: http://hdl.handle.net/10919/96422.
Council of Science Editors:
Zhang T. Designing Practical Software Bug Detectors Using Commodity Hardware and Common Programming Patterns. [Doctoral Dissertation]. Virginia Tech; 2020. Available from: http://hdl.handle.net/10919/96422
Indian Institute of Science
8.
Samak, Malavika.
Targeted Client Synthesis for Detecting Concurrency Bugs.
Degree: PhD, Faculty of Engineering, 2018, Indian Institute of Science
URL: http://etd.iisc.ac.in/handle/2005/2943
► Detecting concurrency bugs can be challenging due to the intricacies associated with their manifestation. These intricacies correspond to identifying the methods that need to be…
(more)
▼ Detecting
concurrency bugs can be challenging due to the intricacies associated with their manifestation. These intricacies correspond to identifying the methods that need to be invoked concurrently, the inputs passed to these methods and the interleaving of the threads that cause the erroneous behavior. Neither fuzzing-based testing techniques nor over-approximate static analyses are well positioned to detect subtle
concurrency defects while retaining high accuracy alongside satisfactory coverage. While
dynamic analysis techniques have been proposed to overcome some of the challenges in detecting
concurrency bugs, we observe that their success is critically dependent on the availability of effective multithreaded clients. Without a priori knowledge of the defects, manually constructing defect-revealing multithreaded clients is non-trivial.
In this thesis, we design an approach to address the problem of automatically generate clients for detecting
concurrency bugs in multithreaded libraries. The key insight underlying our design is that a subset of the properties observed when the defects manifest in a concur-rent execution can also be observed in a sequential execution. The input to our approach is a library implementation and a sequential testsuite, and the output is a set of multithreaded clients that can be used to reveal defects in the input library implementation.
Dynamic defect detectors can execute the clients and analyze the resulting traces to report various kinds of defects including deadlocks,
data races and atomicity violations. Furthermore, the clients can also be used by testing frameworks to report assertion violations.
We propose two variants of our design – (a) path-agnostic client generation, and (b) path-aware client generation. The path-agnostic client generation process helps in
detection of potential bugs present in the paths executed by the input sequential testsuite. It does not attempt to explore newer paths by satisfying path conditions either by modifying the input or by scheduling the threads appropriately. The generated clients are used to expose deadlocks,
data races and atomicity violations. Our
analysis analyzes the execution traces obtained from executing the input sequential clients and produces a concurrent client program that drives shared objects via library methods calls to states conducive for triggering deadlocks,
data races or atomicity violations.
For path-aware client generation, our approach explores newer paths that are not covered by the input sequential testsuite to generate clients. For this purpose, we design a directed, iterative and scalable engine that combines the strengths of static and
dynamic analysis to help synthesize both multithreaded clients and schedules that violate complex
correctness conditions expressed by the developer. Apart from the library implementation and the sequential testsuite as input, this engine also accepts a specification of
correctness as input. Then, it iteratively refines each client from the input sequential testsuite to generate…
Advisors/Committee Members: Ramanathan, Murali Krishna (advisor).
Subjects/Keywords: Concurrency Bugs; Dynamic Analysis; Program Synthesis; Deadlock Detection; Bytecode Instrumentation; Targeted Client Synthesis; Dynamic Deadlock Detection; Multithreaded Client Synthesis; Atomicity Violations; Shared Memory; Dynamic Concurrency Bug Detectors; Racy Tests; Bug Detection; Computer Science
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APA ·
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APA (6th Edition):
Samak, M. (2018). Targeted Client Synthesis for Detecting Concurrency Bugs. (Doctoral Dissertation). Indian Institute of Science. Retrieved from http://etd.iisc.ac.in/handle/2005/2943
Chicago Manual of Style (16th Edition):
Samak, Malavika. “Targeted Client Synthesis for Detecting Concurrency Bugs.” 2018. Doctoral Dissertation, Indian Institute of Science. Accessed March 03, 2021.
http://etd.iisc.ac.in/handle/2005/2943.
MLA Handbook (7th Edition):
Samak, Malavika. “Targeted Client Synthesis for Detecting Concurrency Bugs.” 2018. Web. 03 Mar 2021.
Vancouver:
Samak M. Targeted Client Synthesis for Detecting Concurrency Bugs. [Internet] [Doctoral dissertation]. Indian Institute of Science; 2018. [cited 2021 Mar 03].
Available from: http://etd.iisc.ac.in/handle/2005/2943.
Council of Science Editors:
Samak M. Targeted Client Synthesis for Detecting Concurrency Bugs. [Doctoral Dissertation]. Indian Institute of Science; 2018. Available from: http://etd.iisc.ac.in/handle/2005/2943
Virginia Tech
9.
Pyla, Hari Krishna.
Safe Concurrent Programming and Execution.
Degree: PhD, Computer Science and Applications, 2013, Virginia Tech
URL: http://hdl.handle.net/10919/19276
► The increasing prevalence of multi and many core processors has brought the issues of concurrency and parallelism to the forefront of everyday computing. Even for…
(more)
▼ The increasing prevalence of multi and many core processors has brought the issues of
concurrency and
parallelism to the forefront of everyday computing. Even for applications amenable to traditional parallelization techniques, the subtleties of concurrent programming are known to introduce
concurrency bugs. Due to the potential of
concurrency bugs, programmers find it hard to write correct concurrent code. To take full advantage of parallel shared memory platforms, application programmers need safe and efficient mechanisms that can support a wide range of parallel applications. In addition, a large body of applications are inherently hard-to-parallelize; their
data and control dependencies impose execution order constraints that preclude the use of traditional parallelization techniques. Sensitive to their input
data, a substantial number of applications fail to scale well, leaving cores idle. To improve the
performance of such applications, application programmers need effective mechanisms that can fully leverage multi and many core architectures. These challenges stand in the way of realizing the true potential of emerging many core platforms. The techniques described in this dissertation address these challenges. Specifically, this dissertation contributes techniques to transparently detect and eliminate several
concurrency bugs, including deadlocks, asymmetric write-write
data races, priority inversion, live-locks, order violations, and bugs that stem from the presence of asynchronous signaling and locks. A second major contribution of this dissertation is a programming framework that exploits coarse-grain speculative
parallelism to improve the
performance of otherwise hard-to-parallelize applications.
Advisors/Committee Members: Varadarajan, Srinidhi (committeechair), Ribbens, Calvin J. (committeechair), Adve, Vikram (committee member), Ramakrishnan, Naren (committee member), Tilevich, Eli (committee member), Lea, Douglas (committee member).
Subjects/Keywords: Concurrent Programming; Concurrency Bugs; Program Analysis; Runtime Systems; Deadlock Detection and Recovery; Speculative Parall
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APA (6th Edition):
Pyla, H. K. (2013). Safe Concurrent Programming and Execution. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/19276
Chicago Manual of Style (16th Edition):
Pyla, Hari Krishna. “Safe Concurrent Programming and Execution.” 2013. Doctoral Dissertation, Virginia Tech. Accessed March 03, 2021.
http://hdl.handle.net/10919/19276.
MLA Handbook (7th Edition):
Pyla, Hari Krishna. “Safe Concurrent Programming and Execution.” 2013. Web. 03 Mar 2021.
Vancouver:
Pyla HK. Safe Concurrent Programming and Execution. [Internet] [Doctoral dissertation]. Virginia Tech; 2013. [cited 2021 Mar 03].
Available from: http://hdl.handle.net/10919/19276.
Council of Science Editors:
Pyla HK. Safe Concurrent Programming and Execution. [Doctoral Dissertation]. Virginia Tech; 2013. Available from: http://hdl.handle.net/10919/19276
Universidade Nova
10.
Delgado, Nuno Miguel de Brito.
A system’s approach to cache hierarchy-aware decomposition of data-parallel computations.
Degree: 2014, Universidade Nova
URL: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/13014
► Dissertação para obtenção do Grau de Mestre em Engenharia Informática
The architecture of nowadays’ processors is very complex, comprising several computational cores and an intricate…
(more)
▼ Dissertação para obtenção do Grau de Mestre em
Engenharia Informática
The architecture of nowadays’ processors is very complex, comprising several computational cores and an intricate hierarchy of cache memories. The latter, in particular, differ considerably between the many processors currently available in the market, resulting in a wide variety of configurations. Application development is typically oblivious of this complexity and diversity, taking only into consideration the number of available execution cores. This oblivion prevents such applications from fully harnessing the computing power available in these architectures.
This problem has been recognized by the community, which has proposed languages
and models to express and tune applications according to the underlying machine’s hierarchy.
These, however, lack the desired abstraction level, forcing the programmer to have
deep knowledge of computer architecture and parallel programming, in order to ensure
performance portability across a wide range of architectures.
Realizing these limitations, the goal of this thesis is to delegate these hierarchy-aware optimizations to the runtime system. Accordingly, the programmer’s responsibilities are confined to the definition of procedures for decomposing an application’s domain, into an arbitrary number of partitions. With this, the programmer has only to reason about the application’s data representation and manipulation.
We prototyped our proposal on top of a Java parallel programming framework, and
evaluated it from a performance perspective, against cache neglectful domain decompositions.
The results demonstrate that our optimizations deliver significant speedups
against decomposition strategies based solely on the number of execution cores, without requiring the programmer to reason about the machine’s hardware. These facts allow us to conclude that it is possible to obtain performance gains by transferring hierarchyaware optimizations concerns to the runtime system.
Advisors/Committee Members: Paulino, Hervé.
Subjects/Keywords: Data-parallelism; Hierarchical parallelism; Domain decomposition; Runtime systems
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APA (6th Edition):
Delgado, N. M. d. B. (2014). A system’s approach to cache hierarchy-aware decomposition of data-parallel computations. (Thesis). Universidade Nova. Retrieved from http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/13014
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Delgado, Nuno Miguel de Brito. “A system’s approach to cache hierarchy-aware decomposition of data-parallel computations.” 2014. Thesis, Universidade Nova. Accessed March 03, 2021.
http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/13014.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Delgado, Nuno Miguel de Brito. “A system’s approach to cache hierarchy-aware decomposition of data-parallel computations.” 2014. Web. 03 Mar 2021.
Vancouver:
Delgado NMdB. A system’s approach to cache hierarchy-aware decomposition of data-parallel computations. [Internet] [Thesis]. Universidade Nova; 2014. [cited 2021 Mar 03].
Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/13014.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Delgado NMdB. A system’s approach to cache hierarchy-aware decomposition of data-parallel computations. [Thesis]. Universidade Nova; 2014. Available from: http://www.rcaap.pt/detail.jsp?id=oai:run.unl.pt:10362/13014
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
11.
Roemer, Jake.
Practical High-Coverage Sound Predictive Race
Detection.
Degree: PhD, Computer Science and Engineering, 2019, The Ohio State University
URL: http://rave.ohiolink.edu/etdc/view?acc_num=osu1563505463237874
► Data races pose a fundamental issue plaguing the reliability of parallel software. A shared-memory program has a data race if two conflicting memory accesses (accesses…
(more)
▼ Data races pose a fundamental issue plaguing the
reliability of parallel software. A shared-memory program has a
data race if two conflicting memory accesses (accesses to the same
memory location by different threads, where at least one access is
a write) can execute consecutively (no interleaving events exist).
Modern shared-memory programming languages including C++ and Java
provide undefined or ill-defined semantics for executions with
data
races. So in the presence of
data races, shared-memory programs are
vulnerable to fatal crashes,
data corruption, and other unexpected
errors.
Data races manifest nondeterministically creating the
complex task of writing and diagnosing shared-memory programs.
Existing research offers a variety of program analyses to detect
and report
data races to developers. Most notably, predictive
dynamic analyses detect
data races that can occur in executions
other than the observed execution. Predictive
analysis defines the
set of necessary ordering between events while ensuring the same
behavior as the observed execution to detect races that industry
standard happens-before
analysis cannot detect. The existing
techniques are sound (report only true races) but often miss races
because the techniques are impractical to run extensively on large
programs in practice due to performing costly reasoning about
reordered thread interleavings. Alternative partial-order-based
predictive techniques that scale to large programs fail to detect
all races knowable from the observed execution because of the
conservative ordering between events that preserve a valid
reordered execution for the techniques to be sound. The
partial-order-based predictive techniques remain impractical
compared to industry standard
race detectors. A major contributing
factor to predictive analyses poor
performance is the metadata
required to weaken the observed ordering. The metadata tracks
conflicting critical sections and is a vital component of
predictive
analysis that industry standard happens-before
race
detectors do not need to manage. Thus the limitations of predictive
analyses result in shared-memory programs remaining vulnerable in
the presence of extremely hard-to-detect
data races. The goal of
this work is to detect all races knowable from the observed
execution and close the
performance gap between predictive
analysis
and industry standard detectors by designing a practical
high-coverage sound predictive
data race detector. This
dissertation presents a body of work that advances
data race
coverage and run time and memory usage
performance of predictive
analysis. The first main focus for this dissertation is to maximize
race detection capability to detect all knowable races from an
observed execution. Our key insight to achieve high-coverage
predictive
analysis is to sacrifice soundness (may detect false
races) by relinquishing conservative ordering between events. Our
contributions reduce ordering between events more than prior work
by showing the conservative orderings are unnecessary to ensure the
same behavior as…
Advisors/Committee Members: Bond, Michael (Advisor).
Subjects/Keywords: Computer Science; Computer Engineering; Data race detection; dynamic predictive analysis; dynamic analysis; software testing and debugging; software and its engineering
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APA ·
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MLA ·
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Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Roemer, J. (2019). Practical High-Coverage Sound Predictive Race
Detection. (Doctoral Dissertation). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1563505463237874
Chicago Manual of Style (16th Edition):
Roemer, Jake. “Practical High-Coverage Sound Predictive Race
Detection.” 2019. Doctoral Dissertation, The Ohio State University. Accessed March 03, 2021.
http://rave.ohiolink.edu/etdc/view?acc_num=osu1563505463237874.
MLA Handbook (7th Edition):
Roemer, Jake. “Practical High-Coverage Sound Predictive Race
Detection.” 2019. Web. 03 Mar 2021.
Vancouver:
Roemer J. Practical High-Coverage Sound Predictive Race
Detection. [Internet] [Doctoral dissertation]. The Ohio State University; 2019. [cited 2021 Mar 03].
Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1563505463237874.
Council of Science Editors:
Roemer J. Practical High-Coverage Sound Predictive Race
Detection. [Doctoral Dissertation]. The Ohio State University; 2019. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1563505463237874
12.
Iqbal, Muhammad Shahid.
Runtime Analysis of Malware.
Degree: 2011, , School of Computing
URL: http://urn.kb.se/resolve?urn=urn:nbn:se:bth-2930
► Context: Every day increasing number of malwares are spreading around the world and infecting not only end users but also large organizations. This results…
(more)
▼ Context: Every day increasing number of malwares are spreading around the world and infecting not only end users but also large organizations. This results in massive security threat for private data and expensive computer resources. There is lot of research going on to cope up with this large amount of malicious software. Researchers and practitioners developed many new methods to deal with them. One of the most effective methods used to capture malicious software is dynamic malware analysis. Dynamic analysis methods used today are very time consuming and resource greedy. Normally it could take days or at least some hours to analyze a single instance of suspected software. This is not good enough especially if we look at amount of attacks occurring every day. Objective: To save time and expensive resources used to perform these analyses, AMA: an automated malware analysis system is developed to analyze large number of suspected software. Analysis of any software inside AMA, results in a detailed report of its behavior, which includes changes made to file system, registry, processes and network traffic consumed. Main focus of this study is to develop a model to automate the runtime analysis of software which provide detailed analysis report and evaluation of its effectiveness. Methods: A thorough background study is conducted to gain the knowledge about malicious software and their behavior. Further software analysis techniques are studied to come up with a model that will automate the runtime analysis of software. A prototype system is developed and quasi experiment performed on malicious and benign software to evaluate the accuracy of the newly developed system and generated reports are compared with Norman and Anubis. Results: Based on thorough background study an automated runtime analysis model is developed and quasi experiment performed using implemented prototype system on selected legitimate and benign software. The experiment results show AMA has captured more detailed software behavior then Norman and Anubis and it could be used to better classify software. Conclusions: We concluded that AMA could capture more detailed behavior of the software analyzed and it will give more accurate classification of the software. We also can see from experiment results that there is no concrete distinguishing factors between general behaviors of both types of software. However, by digging a bit deep into analysis report one could understand the intensions of the software. That means reports generated by AMA provide enough information about software behavior and can be used to draw correct conclusions.
+46 736 51 83 01
Subjects/Keywords: Malware; Automated analysis; Runtime analysis; Dynamic analysis; Malicious; behaviour; Characteristics; Detection; Computer Sciences; Datavetenskap (datalogi)
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APA (6th Edition):
Iqbal, M. S. (2011). Runtime Analysis of Malware. (Thesis). , School of Computing. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:bth-2930
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Iqbal, Muhammad Shahid. “Runtime Analysis of Malware.” 2011. Thesis, , School of Computing. Accessed March 03, 2021.
http://urn.kb.se/resolve?urn=urn:nbn:se:bth-2930.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Iqbal, Muhammad Shahid. “Runtime Analysis of Malware.” 2011. Web. 03 Mar 2021.
Vancouver:
Iqbal MS. Runtime Analysis of Malware. [Internet] [Thesis]. , School of Computing; 2011. [cited 2021 Mar 03].
Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:bth-2930.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Iqbal MS. Runtime Analysis of Malware. [Thesis]. , School of Computing; 2011. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:bth-2930
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
The Ohio State University
13.
Zhang, Minjia.
Efficient Runtime Support for Reliable and Scalable
Parallelism.
Degree: PhD, Computer Science and Engineering, 2016, The Ohio State University
URL: http://rave.ohiolink.edu/etdc/view?acc_num=osu1469557197
► Commodity hardware is becoming more parallel. To benefit from parallel hardware, software needs to become more parallel as well. Parallel execution of a concurrent program…
(more)
▼ Commodity hardware is becoming more parallel. To
benefit from parallel hardware, software needs to become more
parallel as well. Parallel execution of a concurrent program can
increase program throughput and reduce program execution time.
However, writing concurrent programs that are both correct and
scalable is known as notoriously more difficult than writing
sequential programs because of the interaction of multi-threaded
execution model, synchronization, and the memory hierarchy.
Concurrent programming therefore has been traditionally the
exclusive domain of a small portion of expert programmers.To make
concurrent programming more accessible, researchers and
practitioners have built various
runtime support to facilitate the
programmability, debuggability,
performance, and scalability of
concurrent programs on multiprocessor machines. This dissertation
makes several contributions by introducing novel approaches that
provide efficient
runtime support on modern commodity
multiprocessor hardware to support reliable and scalable concurrent
programming with available
parallelism.To address a common
challenge in building many types of efficient
runtime support – how
to efficiently track memory access dependences, the dissertation
introduces a novel design that tracks memory dependences in a
relaxed way which overlaps coordination with program execution to
hide coordination latency. The dissertation introduces client
analyses to demonstrate the practicality and caveats of the relaxed
tracking approach.Transactional memory is a promising high-level
abstraction for shared-memory
concurrency. However, it faces
challenges in both
performance and semantics. The dissertation
introduces LarkTM, a low-overhead, scalable software transactional
memory (STM) system with strong semantics and strong progress
guarantees. The dissertation also introduces LarkTM-S, which
extends LarkTM by hybridizing optimistic and pessimistic
concurrency control, and a variant of LarkTM which is based on
relaxed dependence tracking.Finally, the memory model is at the
heart of
concurrency semantics. To increase the practicality of
strong memory consistency models, the dissertation is the first
that identifies the availability issue in strong memory models with
fail-stop semantics. It introduces a new memory model based on
snapshot isolation which has strong, well-defined semantics and
devises a memory model enforcement approach that enforces the new
memory model while at the same time does best-effort tolerance of
consistency exceptions.
Advisors/Committee Members: Bond, Michael (Advisor).
Subjects/Keywords: Computer Engineering; Concurrency, Parallelism, Runtime Support, Dependence
Tracking, Transactional Memory, Memory Model
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APA ·
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to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Zhang, M. (2016). Efficient Runtime Support for Reliable and Scalable
Parallelism. (Doctoral Dissertation). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1469557197
Chicago Manual of Style (16th Edition):
Zhang, Minjia. “Efficient Runtime Support for Reliable and Scalable
Parallelism.” 2016. Doctoral Dissertation, The Ohio State University. Accessed March 03, 2021.
http://rave.ohiolink.edu/etdc/view?acc_num=osu1469557197.
MLA Handbook (7th Edition):
Zhang, Minjia. “Efficient Runtime Support for Reliable and Scalable
Parallelism.” 2016. Web. 03 Mar 2021.
Vancouver:
Zhang M. Efficient Runtime Support for Reliable and Scalable
Parallelism. [Internet] [Doctoral dissertation]. The Ohio State University; 2016. [cited 2021 Mar 03].
Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1469557197.
Council of Science Editors:
Zhang M. Efficient Runtime Support for Reliable and Scalable
Parallelism. [Doctoral Dissertation]. The Ohio State University; 2016. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1469557197
Carnegie Mellon University
14.
Hartman, Gregory S.
Attentiveness: Reactivity at Scale.
Degree: 2010, Carnegie Mellon University
URL: http://repository.cmu.edu/dissertations/15
► Clients of reactive systems often change their priorities. For example, a human user of an email viewer may attempt to display a message while a…
(more)
▼ Clients of reactive systems often change their priorities. For example, a human user of an email viewer may attempt to display a message while a large attachment is downloading. To the user, an email viewer that delayed display of the message would exhibit a failure similar to priority inversion in real-time systems.
We propose a new quality attribute, attentiveness, that provides a unified way to model the forms of redirection offered by application-level reactive systems to accommodate the changing priorities of their clients, which may be either humans or systems components. Modeling attentiveness as a quality attribute provides system designers with a single conceptual framework for policy and architectural decisions to address trade-offs among criteria such as responsiveness, overall performance, behavioral predictability, and state consistency.
Subjects/Keywords: Reactive systems; responsiveness; state consistency; concurrency; distributed systems; data race detection; cancel; rollback
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APA (6th Edition):
Hartman, G. S. (2010). Attentiveness: Reactivity at Scale. (Thesis). Carnegie Mellon University. Retrieved from http://repository.cmu.edu/dissertations/15
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Hartman, Gregory S. “Attentiveness: Reactivity at Scale.” 2010. Thesis, Carnegie Mellon University. Accessed March 03, 2021.
http://repository.cmu.edu/dissertations/15.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Hartman, Gregory S. “Attentiveness: Reactivity at Scale.” 2010. Web. 03 Mar 2021.
Vancouver:
Hartman GS. Attentiveness: Reactivity at Scale. [Internet] [Thesis]. Carnegie Mellon University; 2010. [cited 2021 Mar 03].
Available from: http://repository.cmu.edu/dissertations/15.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Hartman GS. Attentiveness: Reactivity at Scale. [Thesis]. Carnegie Mellon University; 2010. Available from: http://repository.cmu.edu/dissertations/15
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
University of Illinois – Urbana-Champaign
15.
Kumar, Rajesh.
Efficient execution of fine-grained actors on multicore processors.
Degree: PhD, 0112, 2013, University of Illinois – Urbana-Champaign
URL: http://hdl.handle.net/2142/44758
► The Actor model is a promising model for programming new computing platforms such as the multicores and cloud computers, primarily due to features such as…
(more)
▼ The Actor model is a promising model for programming new computing platforms such as the multicores and cloud computers, primarily due to features such as inherent
concurrency and isolation of state. However, the model is often perceived to be fundamentally inefficient on stock multicore processors. Consequently, we find that standard semantic properties of the model, including encapsulation and fairness, are ignored even by languages and frameworks that claim to be based on the Actor model.
In this work, we propose and implement both static (compiler) and
dynamic (
runtime) techniques that overcome these perceived inefficiencies, while retaining key actor semantics, even in a framework setting. We compare the
performance of ActorFoundry with other frameworks for small benchmarks and programs. The results suggest that key actor semantics can be supported in an actor framework without compromising execution efficiency.
We also validate our results for a large real-world application, i.e. a Java game called Quantum having more than 25k lines of code. Quantum is a real-time strategy game, which employs a few threads for handling IO, UI and network events. We port the Quantum game to ActorFoundry, so that the asynchrony due to threads and communication between them is expressed using actors and messages.
Next, we introduce additional
concurrency in Quantum by actorizing all game objects. This results in relatively fine-grained actors. We are able to run a game instance with more than 10,000 game objects, which keeps an 8-core computer at full throttle. According to our knowledge, this is the largest execution of a real client-side actor program.
The
performance is comparable to an Actor framework implementation that does not provide the standard actor semantics. Moreover, our set of static (compiler) and
dynamic (
runtime) techniques allow an actor framework to compare well against a shared memory model in terms of execution efficiency.
Advisors/Committee Members: Agha, Gul A. (advisor), Agha, Gul A. (Committee Chair), Marinov, Darko (committee member), Johnson, Ralph E. (committee member), Miller, Mark S. (committee member).
Subjects/Keywords: multicore; efficiency; performance; actor model; concurrency; parallelism; programming; ActorFoundry; games
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Manager
APA (6th Edition):
Kumar, R. (2013). Efficient execution of fine-grained actors on multicore processors. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/44758
Chicago Manual of Style (16th Edition):
Kumar, Rajesh. “Efficient execution of fine-grained actors on multicore processors.” 2013. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 03, 2021.
http://hdl.handle.net/2142/44758.
MLA Handbook (7th Edition):
Kumar, Rajesh. “Efficient execution of fine-grained actors on multicore processors.” 2013. Web. 03 Mar 2021.
Vancouver:
Kumar R. Efficient execution of fine-grained actors on multicore processors. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2013. [cited 2021 Mar 03].
Available from: http://hdl.handle.net/2142/44758.
Council of Science Editors:
Kumar R. Efficient execution of fine-grained actors on multicore processors. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2013. Available from: http://hdl.handle.net/2142/44758
Rice University
16.
Chatarasi, Prasanth.
Extending the Polyhedral Compilation Model for Debugging and Optimization of SPMD-style Explicitly-Parallel Programs.
Degree: MS, Engineering, 2017, Rice University
URL: http://hdl.handle.net/1911/105463
► The SPMD (Single Program Multiple Data) parallelism continues to be one of the most popular parallel execution models in use today, as exemplified by OpenMP…
(more)
▼ The SPMD (Single Program Multiple
Data)
parallelism continues to be one of the most popular parallel execution models in use today, as exemplified by OpenMP for multi-core systems, CUDA and OpenCL for accelerator systems, and MPI for distributed-memory systems.
The basic idea behind the SPMD model, which differentiates it from task-parallel models, is that all logical processors (worker threads) execute the same program with sequential code executed redundantly and parallel code executed cooperatively.
This thesis extends the polyhedral compilation model to enable
analysis of SPMD-style explicitly-parallel programs.
This thesis demonstrates the value of this extended polyhedral model by describing its use in two applications to help developers of SPMD programs – identification of
data races, as well as identification and removal of redundant barriers.
This thesis evaluates the effectiveness of these two applications using 34 OpenMP programs from the {\tt OmpSCR} and {\tt PolyBench/ACC} OpenMP benchmark suites.
Advisors/Committee Members: Sarkar, Vivek (advisor), Shirako, Jun (committee member).
Subjects/Keywords: SPMD parallelism; Data race detection; Redundant barriers; Polyhedral model; Phase mapping; Space mapping; May-Happen-in-Parallel relations
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APA (6th Edition):
Chatarasi, P. (2017). Extending the Polyhedral Compilation Model for Debugging and Optimization of SPMD-style Explicitly-Parallel Programs. (Masters Thesis). Rice University. Retrieved from http://hdl.handle.net/1911/105463
Chicago Manual of Style (16th Edition):
Chatarasi, Prasanth. “Extending the Polyhedral Compilation Model for Debugging and Optimization of SPMD-style Explicitly-Parallel Programs.” 2017. Masters Thesis, Rice University. Accessed March 03, 2021.
http://hdl.handle.net/1911/105463.
MLA Handbook (7th Edition):
Chatarasi, Prasanth. “Extending the Polyhedral Compilation Model for Debugging and Optimization of SPMD-style Explicitly-Parallel Programs.” 2017. Web. 03 Mar 2021.
Vancouver:
Chatarasi P. Extending the Polyhedral Compilation Model for Debugging and Optimization of SPMD-style Explicitly-Parallel Programs. [Internet] [Masters thesis]. Rice University; 2017. [cited 2021 Mar 03].
Available from: http://hdl.handle.net/1911/105463.
Council of Science Editors:
Chatarasi P. Extending the Polyhedral Compilation Model for Debugging and Optimization of SPMD-style Explicitly-Parallel Programs. [Masters Thesis]. Rice University; 2017. Available from: http://hdl.handle.net/1911/105463
University of New South Wales
17.
Yan, Hua.
Program analysis of temporal memory mismanagement.
Degree: Computer Science & Engineering, 2018, University of New South Wales
URL: http://handle.unsw.edu.au/1959.4/59503
;
https://unsworks.unsw.edu.au/fapi/datastream/unsworks:48807/SOURCE02?view=true
► In the use of C/C++ programs, the performance benefits obtained from flexible low-level memory access and management sacrifice language-level support for memory safety and garbage…
(more)
▼ In the use of C/C++ programs, the
performance benefits obtained from flexible low-level memory access and management sacrifice language-level support for memory safety and garbage collection. Memory-related programming mistakes are introduced as a result, rendering C/C++ programs prone to memory errors. A common category of programming mistakes is defined by the misplacement of deallocation operations, also known as temporal memory mismanagement, which can generate two types of bugs: (1) use-after-free (UAF) bugs and (2) memory leaks. The former are severe security vulnerabilities that expose programs to both
data and control-flow exploits, while the latter are critical
performance bugs that compromise software availability and reliability. In the case of UAF bugs, existing solutions that almost exclusively rely on
dynamic analysis suffer from limitations, including low code coverage, binary incompatibility, and high overheads. In the case of memory leaks,
detection techniques are abundant; however, fixing techniques have been poorly investigated.In this thesis, we present three novel program
analysis frameworks to address temporal memory mismanagement in C/C++. First, we introduce Tac, the first static UAF
detection framework to combine typestate
analysis with machine learning. Tac identifies representative features to train a Support Vector Machine to classify likely true/false UAF candidates, thereby providing guidance for typestate
analysis used to locate bugs with precision.We then present CRed, a pointer
analysis-based framework for UAF
detection with a novel context-reduction technique and a new demand-driven path-sensitive pointer
analysis to boost scalability and precision. A major advantage of CRed is its ability to substantially and soundly reduce search space without losing
bug-finding ability. This is achieved by utilizing must-not-alias information to truncate unnecessary segments of calling contexts.Finally, we propose AutoFix, an automated memory leak fixing framework based on value-flow
analysis and static instrumentation that can fix all leaks reported by any front-end detector with negligible overheads safely and with precision. AutoFix tolerates false leaks with a shadow memory
data structure carefully designed to keep track of the allocation and deallocation of potentially leaked memory objects.The contribution of this thesis is threefold. First, we advance existing state-of-the-art solutions to detecting memory leaks by proposing a series of novel program
analysis techniques to address temporal memory mismanagement. Second, corresponding prototype tools are fully implemented in the LLVM compiler framework. Third, an extensive evaluation of open-source C/C++ benchmarks is conducted to validate the effectiveness of the proposed techniques.
Advisors/Committee Members: Xue, Jingling, Computer Science & Engineering, Faculty of Engineering, UNSW, Chen, Shiping, Data61, CSIRO.
Subjects/Keywords: Bug detection; Program analysis; Memory error
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APA (6th Edition):
Yan, H. (2018). Program analysis of temporal memory mismanagement. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/59503 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:48807/SOURCE02?view=true
Chicago Manual of Style (16th Edition):
Yan, Hua. “Program analysis of temporal memory mismanagement.” 2018. Doctoral Dissertation, University of New South Wales. Accessed March 03, 2021.
http://handle.unsw.edu.au/1959.4/59503 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:48807/SOURCE02?view=true.
MLA Handbook (7th Edition):
Yan, Hua. “Program analysis of temporal memory mismanagement.” 2018. Web. 03 Mar 2021.
Vancouver:
Yan H. Program analysis of temporal memory mismanagement. [Internet] [Doctoral dissertation]. University of New South Wales; 2018. [cited 2021 Mar 03].
Available from: http://handle.unsw.edu.au/1959.4/59503 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:48807/SOURCE02?view=true.
Council of Science Editors:
Yan H. Program analysis of temporal memory mismanagement. [Doctoral Dissertation]. University of New South Wales; 2018. Available from: http://handle.unsw.edu.au/1959.4/59503 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:48807/SOURCE02?view=true
Brno University of Technology
18.
Mužikovská, Monika.
Podpora pro monitorování procesů za běhu v prostředí ANaConDA: Support of Run-time Monitoring of Processes in ANaConDA Framework.
Degree: 2020, Brno University of Technology
URL: http://hdl.handle.net/11012/192462
► This work extends ANaConDA framework for dynamic analysis of multi-threaded programs with support for multi-process monitoring. This thesis summarizes ANaConDA's approach to analysis and differences…
(more)
▼ This work extends ANaConDA framework for
dynamic analysis of multi-threaded programs with support for multi-process monitoring. This thesis summarizes ANaConDA's approach to
analysis and differences between threads and processes. The most important ones involve inter-process communication, separate logical address spaces, and synchronisation with general semaphores. The implemented extension provides API for inter-process communication via shared memory, monitors operations with shared memory in order to translate virtual addresses to their unique representation among processes, and monitors synchronisation operations with semaphores and provides information about them to analysers. The extension significantly simplifies the development of multi-process analysers. This is shown on implementation of two analysers for
data race detection, AtomRace and FastTrack, which were, until now, available for multi-threaded programs only. The implementation of FastTrack algorithm uses happens-before relation for general semaphores which is also defined in this thesis. Proposed and implemented solutions were verified on a set of automatic tests and the two analysers were used for experiments on a set of students' projects. Experiments showed that ANaConDA framework is now able to detect
concurrency-related errors in multi-process programs and, as such, provide support with implementation of large category of parallel programs.
Advisors/Committee Members: Smrčka, Aleš (advisor), Rogalewicz, Adam (referee).
Subjects/Keywords: analýza procesů; dynamická analýza; ANaConDA; synchronizace; happens-before relace; vektorové hodiny; obecné semafory; sdílená paměť; logické adresy; paralelní chyby; souběh; AtomRace; FastTrack; multi-process analysis; dynamic analysis; ANaConDA; synchronisation; happens-before relation; vector clocks; general semaphores; shared memory; virtual address; concurrency-related errors; data race; AtomRace; FastTrack
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Export
to Zotero / EndNote / Reference
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APA (6th Edition):
Mužikovská, M. (2020). Podpora pro monitorování procesů za běhu v prostředí ANaConDA: Support of Run-time Monitoring of Processes in ANaConDA Framework. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/192462
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Mužikovská, Monika. “Podpora pro monitorování procesů za běhu v prostředí ANaConDA: Support of Run-time Monitoring of Processes in ANaConDA Framework.” 2020. Thesis, Brno University of Technology. Accessed March 03, 2021.
http://hdl.handle.net/11012/192462.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Mužikovská, Monika. “Podpora pro monitorování procesů za běhu v prostředí ANaConDA: Support of Run-time Monitoring of Processes in ANaConDA Framework.” 2020. Web. 03 Mar 2021.
Vancouver:
Mužikovská M. Podpora pro monitorování procesů za běhu v prostředí ANaConDA: Support of Run-time Monitoring of Processes in ANaConDA Framework. [Internet] [Thesis]. Brno University of Technology; 2020. [cited 2021 Mar 03].
Available from: http://hdl.handle.net/11012/192462.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Mužikovská M. Podpora pro monitorování procesů za běhu v prostředí ANaConDA: Support of Run-time Monitoring of Processes in ANaConDA Framework. [Thesis]. Brno University of Technology; 2020. Available from: http://hdl.handle.net/11012/192462
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Texas A&M University
19.
Papadopoulos, Ioannis.
STAPL-RTS: A Runtime System for Massive Parallelism.
Degree: PhD, Computer Science, 2016, Texas A&M University
URL: http://hdl.handle.net/1969.1/156985
► Modern High Performance Computing (HPC) systems are complex, with deep memory hierarchies and increasing use of computational heterogeneity via accelerators. When developing applications for these…
(more)
▼ Modern High
Performance Computing (HPC) systems are complex, with deep memory hierarchies and increasing use of computational heterogeneity via accelerators. When developing applications for these platforms, programmers are faced with two bad choices. On one hand, they can explicitly manage machine resources, writing programs using low level primitives from multiple APIs (e.g., MPI+OpenMP), creating efficient but rigid, difficult to extend, and non-portable implementations. Alternatively, users can adopt higher level programming environments, often at the cost of lost
performance. Our approach is to maintain the high level nature of the application without sacrificing
performance by relying on the transfer of high level, application semantic knowledge between layers of the software stack at an appropriate level of abstraction and performing optimizations on a per-layer basis. In this dissertation, we present the STAPL
Runtime System (STAPL-RTS), a
runtime system built for portable
performance, suitable for massively parallel machines. While the STAPL-RTS abstracts and virtualizes the underlying platform for portability, it uses information from the upper layers to perform the appropriate low level optimizations that restore the
performance characteristics.
We outline the fundamental ideas behind the design of the STAPL-RTS, such as the always distributed communication model and its asynchronous operations. Through appropriate code examples and benchmarks, we prove that high level information allows applications written on top of the STAPL-RTS to attain the
performance of optimized, but ad hoc solutions. Using the STAPL library, we demonstrate how this information guides important decisions in the STAPL-RTS, such as multi-protocol communication coordination and request aggregation using established C++ programming idioms.
Recognizing that nested
parallelism is of increasing interest for both expressivity and
performance, we present a parallel model that combines asynchronous, one-sided operations with isolated nested parallel sections. Previous approaches to nested
parallelism targeted either static applications through the use of blocking, isolated sections, or
dynamic applications by using asynchronous mechanisms (i.e., recursive task spawning) which come at the expense of isolation. We combine the flexibility of
dynamic task creation with the isolation guarantees of the static models by allowing the creation of asynchronous, one-sided nested parallel sections that work in tandem with the more traditional, synchronous, collective nested
parallelism. This allows selective, run-time customizable use of
parallelism in an application, based on the input and the algorithm.
Advisors/Committee Members: Rauchwerger, Lawrence (advisor), Amato, Nancy M. (committee member), Welch, Jennifer L. (committee member), Adams, Marvin L. (committee member).
Subjects/Keywords: parallel; runtime system; high performance; nested parallelism; asynchronous; shared memory; distributed memory
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APA (6th Edition):
Papadopoulos, I. (2016). STAPL-RTS: A Runtime System for Massive Parallelism. (Doctoral Dissertation). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/156985
Chicago Manual of Style (16th Edition):
Papadopoulos, Ioannis. “STAPL-RTS: A Runtime System for Massive Parallelism.” 2016. Doctoral Dissertation, Texas A&M University. Accessed March 03, 2021.
http://hdl.handle.net/1969.1/156985.
MLA Handbook (7th Edition):
Papadopoulos, Ioannis. “STAPL-RTS: A Runtime System for Massive Parallelism.” 2016. Web. 03 Mar 2021.
Vancouver:
Papadopoulos I. STAPL-RTS: A Runtime System for Massive Parallelism. [Internet] [Doctoral dissertation]. Texas A&M University; 2016. [cited 2021 Mar 03].
Available from: http://hdl.handle.net/1969.1/156985.
Council of Science Editors:
Papadopoulos I. STAPL-RTS: A Runtime System for Massive Parallelism. [Doctoral Dissertation]. Texas A&M University; 2016. Available from: http://hdl.handle.net/1969.1/156985
University of Colorado
20.
Price, Graham David.
Dynamic Trace Analysis with Zero-Suppressed BDDs.
Degree: PhD, Electrical, Computer & Energy Engineering, 2011, University of Colorado
URL: https://scholar.colorado.edu/ecen_gradetds/27
► Instruction level parallelism (ILP) limitations have forced processor manufacturers to develop multi-core platforms with the expectation that programs will be able to exploit thread…
(more)
▼ Instruction level
parallelism (ILP) limitations have forced processor manufacturers to develop multi-core platforms with the expectation that programs will be able to exploit thread level
parallelism (TLP). Multi-core programming shifts the burden of locating additional
performance away from computer hardware to the software developers, who often attempt high-level redesigns focused on exposing thread level
parallelism, as well as explore aggressive optimizations for sequential codes. Precise
dynamic analysis can provide useful guidance for program optimization efforts, including efforts to find and extract thread level
parallelism. Unfortunately, finding regions of code amenable to further optimization efforts requires analyzing traces that can quickly grow in size.
Analysis of large
dynamic traces (e.g. one billion instructions or more) is often impractical for commodity hardware. An ideal representation for
dynamic trace
data would provide compression. However, decompressing large software traces, even if decompressed
data is never permanently stored, would make many
analysis impractical. A better solution would allow
analysis of the compressed
data, without a costly decompression step. Prior works have developed trace compressors that generate an analyzable representation, but often limit the precision or scope of analyses. Zero-suppressed binary decision diagram (ZDDs) exhibit many of the desired properties of an ideal trace representation. This thesis shows: (1)
dynamic trace
data may be represented by zero-suppressed binary decision diagrams (ZDDs); (2) ZDDs allow many analyses to scale; (3) encoding traces as ZDDs can be performed in a reasonable amount of time; and, (4) ZDD-based analyses, such as irrelevant instruction
detection and potential coarse-grained thread level
parallelism extraction, can reveal a number of
performance
Advisors/Committee Members: Manish Vachharajani, Fabio Somenzi, Bor-Yuh Evan Chang.
Subjects/Keywords: Dynamic Program Analysis; Parallelism; Computer Sciences; Engineering
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APA (6th Edition):
Price, G. D. (2011). Dynamic Trace Analysis with Zero-Suppressed BDDs. (Doctoral Dissertation). University of Colorado. Retrieved from https://scholar.colorado.edu/ecen_gradetds/27
Chicago Manual of Style (16th Edition):
Price, Graham David. “Dynamic Trace Analysis with Zero-Suppressed BDDs.” 2011. Doctoral Dissertation, University of Colorado. Accessed March 03, 2021.
https://scholar.colorado.edu/ecen_gradetds/27.
MLA Handbook (7th Edition):
Price, Graham David. “Dynamic Trace Analysis with Zero-Suppressed BDDs.” 2011. Web. 03 Mar 2021.
Vancouver:
Price GD. Dynamic Trace Analysis with Zero-Suppressed BDDs. [Internet] [Doctoral dissertation]. University of Colorado; 2011. [cited 2021 Mar 03].
Available from: https://scholar.colorado.edu/ecen_gradetds/27.
Council of Science Editors:
Price GD. Dynamic Trace Analysis with Zero-Suppressed BDDs. [Doctoral Dissertation]. University of Colorado; 2011. Available from: https://scholar.colorado.edu/ecen_gradetds/27
Rice University
21.
Chatterjee, Sanjay.
Runtime Systems for Extreme Scale Platforms.
Degree: PhD, Engineering, 2013, Rice University
URL: http://hdl.handle.net/1911/76173
► Future extreme-scale systems are expected to contain homogeneous and heterogeneous many-core processors, with O(103) cores per node and O(106) nodes overall. Effective combination of inter…
(more)
▼ Future extreme-scale systems are expected to contain homogeneous and heterogeneous many-core processors, with O(10
3) cores per node and O(10
6) nodes overall. Effective combination of inter node and intra-node
parallelism is recognized to be a major software challenge for such systems. Further, applications will have to deal with constrained energy budgets as well as frequent faults and failures. To aid programmers manage these complexities and enhance programmability, much of recent research has focused on designing state-of-art software
runtime systems. Such
runtime systems are expected to be a critical component of the software ecosystem for the management of
parallelism, locality, load balancing, energy and resilience on extreme-scale systems.
In this dissertation, we address three key challenges faced by a
runtime system using a
dynamic task parallel framework for extreme-scale computing. First, we address the challenge of integrating an intra-node task parallel
runtime with a communication system for scalable
performance. We present a
runtime communication system, called HC-COMM, designed to use dedicated communication cores on a system. We introduce the HCMPI programming model which integrates the Habanero-C asynchronous
dynamic task parallel language with the MPI message passing communication model on the HC-COMM
runtime. We also introduce the HAPGNS model that enables dataflow programming for extreme-scale systems in which the user does not require knowledge of MPI. Second, we address the challenge of separating locality optimizations from a programmer with domain specific knowledge. We present a tuning framework, through which
performance experts can optimize existing applications by specifying
runtime operations aimed at co-scheduling of affinitized tasks. Finally, we address the challenge of scalable synchronization for long running tasks on a
dynamic task parallel
runtime. We use the phaser construct to present a generalized tree-based synchronization algorithm and support unified collective operations at both inter-node and intra-node levels. Overcoming these
runtime challenges are a first step towards effective programming on extreme-scale systems.
Advisors/Committee Members: Sarkar, Vivek (advisor), Mellor-Crummey, John (committee member), Zhong, Lin (committee member), Budimlic, Zoran (committee member).
Subjects/Keywords: Task parallelism; Data-flow; Runtime; Extreme-scale; Exascale; Communications; Locality; Tuning; Phaser; Synchronization
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Manager
APA (6th Edition):
Chatterjee, S. (2013). Runtime Systems for Extreme Scale Platforms. (Doctoral Dissertation). Rice University. Retrieved from http://hdl.handle.net/1911/76173
Chicago Manual of Style (16th Edition):
Chatterjee, Sanjay. “Runtime Systems for Extreme Scale Platforms.” 2013. Doctoral Dissertation, Rice University. Accessed March 03, 2021.
http://hdl.handle.net/1911/76173.
MLA Handbook (7th Edition):
Chatterjee, Sanjay. “Runtime Systems for Extreme Scale Platforms.” 2013. Web. 03 Mar 2021.
Vancouver:
Chatterjee S. Runtime Systems for Extreme Scale Platforms. [Internet] [Doctoral dissertation]. Rice University; 2013. [cited 2021 Mar 03].
Available from: http://hdl.handle.net/1911/76173.
Council of Science Editors:
Chatterjee S. Runtime Systems for Extreme Scale Platforms. [Doctoral Dissertation]. Rice University; 2013. Available from: http://hdl.handle.net/1911/76173
Rice University
22.
Chatterjee, Sanjay.
Runtime Models for Extreme Scale Systems.
Degree: PhD, Engineering, 2013, Rice University
URL: http://hdl.handle.net/1911/76416
► Future extreme-scale systems are expected to contain homogeneous and heterogeneous many-core processors, with up to O(103) cores per node and O(106) nodes overall. Effective combination…
(more)
▼ Future extreme-scale systems are expected to contain homogeneous and heterogeneous
many-core processors, with up to O(10
3) cores per node and O(10
6) nodes overall.
Effective combination of inter-node and intra-node
parallelism is recognized to
be a major software challenge for such systems.
Dynamic task
parallelism, which forms the basis of our research, has proven to
be an effective execution model enabled by efficient
runtime systems for scalable
performance on shared-memory programs.
This work builds on the Habanero-C task parallel language.
We focus on
runtime execution models for scalable locality aware task scheduling
and synchronization at both intra-node and inter-node levels.
A scalable
runtime communication system is a critical requirement for extreme-scale computing.
We present our
runtime communication system, called HC-COMM, which can integrate
any popular communication system, such as MPI, with
dynamic asynchronous tasks.
The
runtime uses dedicated computation and communication cores for scalable
performance.
We introduce the HC-MPI execution model, where all MPI calls are treated as
asynchronous tasks, thereby enabling unified handling of messages and tasking constructs.
HC-MPI provides easy portability of existing MPI applications.
We also introduce the HAPGNS programming model that uses the HC-COMM
runtime
to extend shared-memory
data flow programming onto distributed-memory.
In this model, the user does not require any knowledge of MPI.
We believe locality of computation and
data will be critical for higher
performance
and lower energy resulting from
data reuse on faster memories and redundant
communication avoidance.
Our locality optimization framework can enable
performance experts to optimize
existing applications via tuning operations.
These optimizations aim to benefit from spatial and temporal task locality using
runtime co-scheduling of tasks on a hierarchical place tree construct which
models the system memory hierarchy.
In the HAPGNS model, user provided
data distribution functions act as
data
locality directives at inter-node level.
Finally, we present efficient algorithms to enable the Phaser synchronization
model on long running tasks.
We have extended the Phaser construct to support unified collective operations
at both inter-node and intra-node levels.
Our experimental results on current large scale systems serve to validate the
design and implementation of our
runtime system for extreme-scale computing.
Advisors/Committee Members: Sarkar, Vivek (advisor), Mellor-Crummey, John (committee member), Zhong, Lin (committee member), Budimlic, Zoran (committee member).
Subjects/Keywords: Task parallelism; Data-flow; Runtime; Extreme-scale; Exascale; Communications; Locality; Tuning; Phaser; Synchronization
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APA ·
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MLA ·
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Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Chatterjee, S. (2013). Runtime Models for Extreme Scale Systems. (Doctoral Dissertation). Rice University. Retrieved from http://hdl.handle.net/1911/76416
Chicago Manual of Style (16th Edition):
Chatterjee, Sanjay. “Runtime Models for Extreme Scale Systems.” 2013. Doctoral Dissertation, Rice University. Accessed March 03, 2021.
http://hdl.handle.net/1911/76416.
MLA Handbook (7th Edition):
Chatterjee, Sanjay. “Runtime Models for Extreme Scale Systems.” 2013. Web. 03 Mar 2021.
Vancouver:
Chatterjee S. Runtime Models for Extreme Scale Systems. [Internet] [Doctoral dissertation]. Rice University; 2013. [cited 2021 Mar 03].
Available from: http://hdl.handle.net/1911/76416.
Council of Science Editors:
Chatterjee S. Runtime Models for Extreme Scale Systems. [Doctoral Dissertation]. Rice University; 2013. Available from: http://hdl.handle.net/1911/76416
University of Illinois – Urbana-Champaign
23.
Luo, Qingzhou.
Testing, runtime verification, and analysis of concurrent programs.
Degree: PhD, Computer Science, 2015, University of Illinois – Urbana-Champaign
URL: http://hdl.handle.net/2142/87955
► With the development of multi-core processors, concurrent programs are becoming more and more popular. Among several models, the multithreaded shared-memory model is the predominant programming…
(more)
▼ With the development of multi-core processors, concurrent programs are becoming more and more popular. Among several models, the multithreaded shared-memory model is the predominant programming paradigm for developing concurrent programs. However, because of non-deterministic scheduling, multithreaded code is hard to develop and test.
Concurrency bugs, such as
data races, atomicity violations, and deadlocks, are hard to detect and fix in multithreaded programs.
To test and verify multithreaded programs, two sets of techniques are needed. The first one is to enforce thread schedules and
runtime properties efficiently. Being able to enforce desired thread schedules and
runtime properties would greatly help developers to develop reliable multithreaded code. The second one is to explore the state space of multithreaded programs efficiently. Systematic state-space exploration could guarantee
correctness for mul-
tithreaded code, however, it is usually time consuming and thus infeasible in most cases.
This dissertation presents several techniques to address challenges arising in testing and
runtime verification of multithreaded programs. The first two techniques are the IMUnit
framework for enforcing testing schedules and the EnforceMOP system for enforcing
runtime properties for multithreaded programs. An experimental evaluation shows that our
techniques can enforce thread schedules and
runtime properties effectively and efficiently, and have their own advantages over existing techniques. The other techniques are the RV-Causal framework and the CAPP technique in the ReEx framework for efficient state-space
exploration of multithreaded code. RV-Causal employs the idea of the maximal causal model for state-space exploration in a novel way to reduce the exploration cost, without
losing the ability to detect certain types of
concurrency bugs. The results show that RV-Causal outperforms existing techniques by finding
concurrency bugs and exploring the entire state space much more efficiently.
Advisors/Committee Members: Rosu, Grigore (advisor), Rosu, Grigore (Committee Chair), Marinov, Darko (committee member), Xie, Tao (committee member), Havelund, Klaus (committee member).
Subjects/Keywords: Runtime verification; concurrency; testing
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APA (6th Edition):
Luo, Q. (2015). Testing, runtime verification, and analysis of concurrent programs. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/87955
Chicago Manual of Style (16th Edition):
Luo, Qingzhou. “Testing, runtime verification, and analysis of concurrent programs.” 2015. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 03, 2021.
http://hdl.handle.net/2142/87955.
MLA Handbook (7th Edition):
Luo, Qingzhou. “Testing, runtime verification, and analysis of concurrent programs.” 2015. Web. 03 Mar 2021.
Vancouver:
Luo Q. Testing, runtime verification, and analysis of concurrent programs. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2015. [cited 2021 Mar 03].
Available from: http://hdl.handle.net/2142/87955.
Council of Science Editors:
Luo Q. Testing, runtime verification, and analysis of concurrent programs. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/87955
University of Waterloo
24.
Radhakrishnan, Srihari.
High Performance Web Servers: A Study In Concurrent Programming Models.
Degree: 2019, University of Waterloo
URL: http://hdl.handle.net/10012/14706
► With the advent of commodity large-scale multi-core computers, the performance of software running on these computers has become a challenge to researchers and enterprise developers.…
(more)
▼ With the advent of commodity large-scale multi-core computers, the performance of software running on these computers has become a challenge to researchers and enterprise developers. While academic research and industrial products have moved in the direction of writing scalable and highly available services using distributed computing, single machine performance remains an active domain, one which is far from saturated.
This thesis selects an archetypal software example and workload in this domain, and describes software characteristics affecting performance. The example is highly-parallel web-servers processing a static workload. Particularly, this work examines concurrent programming models in the context of high-performance web-servers across different architectures — threaded (Apache, Go and μKnot), event-driven (Nginx, μServer) and staged (WatPipe) — compared with two static workloads in two different domains. The two workloads are a Zipf distribution of file sizes representing a user session pulling an assortment of many small and a few large files, and a 50KB file representing chunked streaming of a large audio or video file. Significant effort is made to fairly compare eight web-servers by carefully tuning each via their adjustment parameters. Tuning plays a significant role in workload-specific performance. The two domains are no disk I/O (in-memory file set) and medium disk I/O. The domains are created by lowering the amount of RAM available to the web-server from 4GB to 2GB, forcing files to be evicted from the file-system cache. Both domains are also restricted to 4 CPUs.
The primary goal of this thesis is to examine fundamental performance differences between threaded and event-driven concurrency models, with particular emphasis on user-level threading models. Additionally, a secondary goal of the work is to examine high-performance software under restricted hardware environments. Over-provisioned hardware environments can mask architectural and implementation shortcomings in software – the hypothesis in this work is that restricting resources stresses the application, bringing out important performance characteristics and properties. Experimental results for the given workload show that memory pressure is one of the most significant factors for the degradation of web-server performance, because it forces both the onset and amount of disk I/O. With an ever increasing need to support more content at faster rates, a web-server relies heavily on in-memory caching of files and related content. In fact, personal and small business web-servers are even run on minimal hardware, like the Raspberry Pi, with only 1GB of RAM and a small SD card for the file system. Therefore, understanding behaviour and performance in restricted contexts should be a normal aspect of testing a web server (and other software systems).
Subjects/Keywords: concurrency; parallelism; web-servers; high-performance concurrent application; distributed system; user-level threading
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APA (6th Edition):
Radhakrishnan, S. (2019). High Performance Web Servers: A Study In Concurrent Programming Models. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/14706
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Radhakrishnan, Srihari. “High Performance Web Servers: A Study In Concurrent Programming Models.” 2019. Thesis, University of Waterloo. Accessed March 03, 2021.
http://hdl.handle.net/10012/14706.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Radhakrishnan, Srihari. “High Performance Web Servers: A Study In Concurrent Programming Models.” 2019. Web. 03 Mar 2021.
Vancouver:
Radhakrishnan S. High Performance Web Servers: A Study In Concurrent Programming Models. [Internet] [Thesis]. University of Waterloo; 2019. [cited 2021 Mar 03].
Available from: http://hdl.handle.net/10012/14706.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Radhakrishnan S. High Performance Web Servers: A Study In Concurrent Programming Models. [Thesis]. University of Waterloo; 2019. Available from: http://hdl.handle.net/10012/14706
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
25.
Kiemele, Liam.
KFusion: obtaining modularity and performance with regards to general purpose GPU computing and co-processors.
Degree: Dept. of Computer Science, 2012, University of Victoria
URL: http://hdl.handle.net/1828/4357
► Concurrency has recently come to the forefront of computing as multi-core processors become more and more common. General purpose graphics processing unit computing brings with…
(more)
▼ Concurrency has recently come to the forefront of computing as multi-core processors
become more and more common. General purpose graphics processing unit
computing brings with them new language support for dealing with co-processor environments
such as OpenCL and CUDA. Programming language support for multi-core
architectures introduces a fundamentally new mechanism for modularity – a kernel.
Developers attempting to leverage these mechanism to separate concerns often
incur unanticipated
performance penalties. My proposed solution aims to preserve
the benefits of kernel boundaries for modularity, while at the same time eliminate
these inherent costs at compile time and execution.
KFusion is a prototype tool for transforming programs written in OpenCL to make
them more efficient. By leveraging loop fusion and deforestation, it can eliminate the
costs associated with compositions of kernels that share
data. Case studies show that
Kfusion can address key memory bandwidth and latency bottlenecks and result in
substantial
performance improvements.
Advisors/Committee Members: Coady, Yvonne (supervisor).
Subjects/Keywords: modularity; performance; OpenCL; concurrency; parallelism
…of concurrency
and parallelism. Co-processors are also becoming more and more common and… …significant performance increase through parallelism, but also brings challenges associated with… …simulation. Image manipulation provides a very data intensive
example and the best performance case… …in terms of performance and usability. I do
a qualitative analysis of Kfusion’s usability… …performance using aspects.
2.2
Concurrency
In 2005, Herb Stutter put forth a paper The Free Lunch…
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APA (6th Edition):
Kiemele, L. (2012). KFusion: obtaining modularity and performance with regards to general purpose GPU computing and co-processors. (Masters Thesis). University of Victoria. Retrieved from http://hdl.handle.net/1828/4357
Chicago Manual of Style (16th Edition):
Kiemele, Liam. “KFusion: obtaining modularity and performance with regards to general purpose GPU computing and co-processors.” 2012. Masters Thesis, University of Victoria. Accessed March 03, 2021.
http://hdl.handle.net/1828/4357.
MLA Handbook (7th Edition):
Kiemele, Liam. “KFusion: obtaining modularity and performance with regards to general purpose GPU computing and co-processors.” 2012. Web. 03 Mar 2021.
Vancouver:
Kiemele L. KFusion: obtaining modularity and performance with regards to general purpose GPU computing and co-processors. [Internet] [Masters thesis]. University of Victoria; 2012. [cited 2021 Mar 03].
Available from: http://hdl.handle.net/1828/4357.
Council of Science Editors:
Kiemele L. KFusion: obtaining modularity and performance with regards to general purpose GPU computing and co-processors. [Masters Thesis]. University of Victoria; 2012. Available from: http://hdl.handle.net/1828/4357
Northeastern University
26.
Turon, Aaron Joseph.
Understanding and expressing scalable concurrency.
Degree: PhD, Department of Computer Science, 2013, Northeastern University
URL: http://hdl.handle.net/2047/d20003058
► The Holy Grail of parallel programming is to provide good speedup while hiding or avoiding the pitfalls of concurrency. But some level in the tower…
(more)
▼ The Holy Grail of parallel programming is to provide good speedup while hiding or avoiding the pitfalls of concurrency. But some level in the tower of abstraction must face facts: parallel processors execute code concurrently, and the interplay between concurrent code, synchronization, and the memory subsystem is a major determiner of performance. Effective parallel programming must ultimately be supported by scalable concurrent algorithms-algorithms that tolerate (or even embrace) concurrency for the sake of scaling with available parallelism. This dissertation makes several contributions to the understanding and expression of such algorithms: It shows how to understand scalable algorithms in terms of local protocols governing each part of their hidden state. These protocols are visual artifacts that can be used to informally explain an algorithm at a whiteboard. But they also play a formal role in a new logic for verifying concurrent algorithms, enabling correctness proofs that are local in space, time, and thread execution. Correctness is stated in terms of refinement: clients of an algorithm can reason as if they were using the much simpler specification code it refines. It shows how to express synchronization in a declarative but scalable way, based on a new library providing "join patterns". By declarative, we mean that the programmer needs only to write down the constraints of a synchronization problem, and the library will automatically derive a correct solution. By scalable, we mean that the derived solutions deliver robust performance with increasing processor count and problem complexity. For common synchronization problems, join patterns perform as well as specialized algorithms from the literature. It shows how to express scalable algorithms through reagents, a new monadic abstraction. With reagents, algorithms no longer need to be constructed from "whole cloth," i.e. by using system-level primitives directly. Instead, they are built using a mixture of shared-state and message-passing combinators. Concurrency experts benefit, because they can write libraries at a higher level, with more reuse, without sacrificing scalability. Their clients benefit, because composition empowers them to extend and tailor a library without knowing the details of its underlying algorithms.
Subjects/Keywords: concurrency; lock-free data structures; parallelism; programming languages; verification; Computer Sciences; Programming Languages and Compilers
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APA ·
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APA (6th Edition):
Turon, A. J. (2013). Understanding and expressing scalable concurrency. (Doctoral Dissertation). Northeastern University. Retrieved from http://hdl.handle.net/2047/d20003058
Chicago Manual of Style (16th Edition):
Turon, Aaron Joseph. “Understanding and expressing scalable concurrency.” 2013. Doctoral Dissertation, Northeastern University. Accessed March 03, 2021.
http://hdl.handle.net/2047/d20003058.
MLA Handbook (7th Edition):
Turon, Aaron Joseph. “Understanding and expressing scalable concurrency.” 2013. Web. 03 Mar 2021.
Vancouver:
Turon AJ. Understanding and expressing scalable concurrency. [Internet] [Doctoral dissertation]. Northeastern University; 2013. [cited 2021 Mar 03].
Available from: http://hdl.handle.net/2047/d20003058.
Council of Science Editors:
Turon AJ. Understanding and expressing scalable concurrency. [Doctoral Dissertation]. Northeastern University; 2013. Available from: http://hdl.handle.net/2047/d20003058
27.
Jimborean, Alexandra.
Adapting the polytope model for dynamic and speculative parallelization : Adaptation du modèle polyhédrique à la parallélisation dynamique et spéculatice.
Degree: Docteur es, Informatique, 2012, Université de Strasbourg
URL: http://www.theses.fr/2012STRAD020
► Dans cette thèse, nous décrivons la conception et l'implémentation d'une plate-forme logicielle de spéculation de threads, ou fils d'exécution, appelée VMAD, pour "Virtual Machine for…
(more)
▼ Dans cette thèse, nous décrivons la conception et l'implémentation d'une plate-forme logicielle de spéculation de threads, ou fils d'exécution, appelée VMAD, pour "Virtual Machine for Advanced Dynamic analysis and transformation", et dont la fonction principale est d'être capable de paralléliser de manière spéculative un nid de boucles séquentiel de différentes façons, en ré-ordonnançant ses itérations. La transformation à appliquer est sélectionnée au cours de l'exécution avec pour objectifs de minimiser le nombre de retours arrières et de maximiser la performance. Nous effectuons des transformations de code en appliquant le modèle polyédrique que nous avons adapté à la parallélisation spéculative au cours de l'exécution. Pour cela, nous construisons au préalable un patron de code qui est "patché" par notre "runtime", ou support d'exécution logiciel, selon des informations de profilage collectées sur des échantillons du temps d'exécution. L'adaptabilité est assurée en considérant des tranches de code de tailles différentes, qui sont exécutées successivement, chacune étant parallélisée différemment, ou exécutée en séquentiel, selon le comportement des accès à la mémoire observé. Nous montrons, sur plusieurs programmes que notre plate-forme offre de bonnes performances, pour des codes qui n'auraient pas pu être traités efficacement par les systèmes spéculatifs de threads proposés précédemment.
In this thesis, we present a Thread-Level Speculation (TLS) framework whose main feature is to speculatively parallelize a sequential loop nest in various ways, to maximize performance. We perform code transformations by applying the polyhedral model that we adapted for speculative and runtime code parallelization. For this purpose, we designed a parallel code pattern which is patched by our runtime system according to the profiling information collected on some execution samples. We show on several benchmarks that our framework yields good performance on codes which could not be handled efficiently by previously proposed TLS systems.
Advisors/Committee Members: Clauss, Philippe (thesis director).
Subjects/Keywords: Programmation parallèle; Speculative parallelization; Runtime system; Compiler; Polyhedral model; Dynamic optimizations; Loops; Partial parallelism; LLVM; Automatic parallelization; 005
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APA (6th Edition):
Jimborean, A. (2012). Adapting the polytope model for dynamic and speculative parallelization : Adaptation du modèle polyhédrique à la parallélisation dynamique et spéculatice. (Doctoral Dissertation). Université de Strasbourg. Retrieved from http://www.theses.fr/2012STRAD020
Chicago Manual of Style (16th Edition):
Jimborean, Alexandra. “Adapting the polytope model for dynamic and speculative parallelization : Adaptation du modèle polyhédrique à la parallélisation dynamique et spéculatice.” 2012. Doctoral Dissertation, Université de Strasbourg. Accessed March 03, 2021.
http://www.theses.fr/2012STRAD020.
MLA Handbook (7th Edition):
Jimborean, Alexandra. “Adapting the polytope model for dynamic and speculative parallelization : Adaptation du modèle polyhédrique à la parallélisation dynamique et spéculatice.” 2012. Web. 03 Mar 2021.
Vancouver:
Jimborean A. Adapting the polytope model for dynamic and speculative parallelization : Adaptation du modèle polyhédrique à la parallélisation dynamique et spéculatice. [Internet] [Doctoral dissertation]. Université de Strasbourg; 2012. [cited 2021 Mar 03].
Available from: http://www.theses.fr/2012STRAD020.
Council of Science Editors:
Jimborean A. Adapting the polytope model for dynamic and speculative parallelization : Adaptation du modèle polyhédrique à la parallélisation dynamique et spéculatice. [Doctoral Dissertation]. Université de Strasbourg; 2012. Available from: http://www.theses.fr/2012STRAD020
University of Sydney
28.
Alomari, Mohammad.
Ensuring Serializable Executions with Snapshot Isolation DBMS
.
Degree: 2009, University of Sydney
URL: http://hdl.handle.net/2123/4211
► Snapshot Isolation (SI) is a multiversion concurrency control that has been implemented by open source and commercial database systems such as PostgreSQL and Oracle. The…
(more)
▼ Snapshot Isolation (SI) is a multiversion concurrency control that has been implemented by open source and commercial database systems such as PostgreSQL and Oracle. The main feature of SI is that a read operation does not block a write operation and vice versa, which allows higher degree of concurrency than traditional two-phase locking. SI prevents many anomalies that appear in other isolation levels, but it still can result in non-serializable execution, in which database integrity constraints can be violated. Several techniques have been proposed to ensure serializable execution with engines running SI; these techniques are based on modifying the applications by introducing conflicting SQL statements. However, with each of these techniques the DBA has to make a difficult choice among possible transactions to modify. This thesis helps the DBA’s to choose between these different techniques and choices by understanding how the choices affect system performance. It also proposes a novel technique called ’External Lock Manager’ (ELM) which introduces conflicts in a separate lock-manager object so that every execution will be serializable. We build a prototype system for ELM and we run experiments to demonstrate the robustness of the new technique compare to the previous techniques. Experiments show that modifying the application code for some transactions has a high impact on performance for some choices, which makes it very hard for DBA’s to choose wisely. However, ELM has peak performance which is similar to SI, no matter which transactions are chosen for modification. Thus we say that ELM is a robust technique for ensure serializable execution.
Subjects/Keywords: Concurrency Control; Serializability; Correctness; Snapshot Isolation; Multiversion concurrency control; performance
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APA (6th Edition):
Alomari, M. (2009). Ensuring Serializable Executions with Snapshot Isolation DBMS
. (Thesis). University of Sydney. Retrieved from http://hdl.handle.net/2123/4211
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Alomari, Mohammad. “Ensuring Serializable Executions with Snapshot Isolation DBMS
.” 2009. Thesis, University of Sydney. Accessed March 03, 2021.
http://hdl.handle.net/2123/4211.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Alomari, Mohammad. “Ensuring Serializable Executions with Snapshot Isolation DBMS
.” 2009. Web. 03 Mar 2021.
Vancouver:
Alomari M. Ensuring Serializable Executions with Snapshot Isolation DBMS
. [Internet] [Thesis]. University of Sydney; 2009. [cited 2021 Mar 03].
Available from: http://hdl.handle.net/2123/4211.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Alomari M. Ensuring Serializable Executions with Snapshot Isolation DBMS
. [Thesis]. University of Sydney; 2009. Available from: http://hdl.handle.net/2123/4211
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
The Ohio State University
29.
Wei, Pihui.
Dynamic Bug Detection in TinyOS Operating
Environments.
Degree: MS, Computer Science and Engineering, 2009, The Ohio State University
URL: http://rave.ohiolink.edu/etdc/view?acc_num=osu1238166929
► Wireless sensor network applications run on resource scarce sensor nodes. A sensor node usually has extremely limited resources in order to run long time…
(more)
▼ Wireless sensor network applications run on
resource scarce sensor nodes. A sensor node usually has extremely
limited resources in order to run long time with limited power
supply to sense its environment. For example, a XSM[6] sensor node
has only 4KB flash memory, a 4MHz processor and a low power radio
device. Sensor network applications are
different from computer applications. Most sensor network
applications are event driven to run longer with limited power
supply. They are in passive mode or sleeping in most of time and
can only be activated by some events. It is very
hard to debug sensor network applications because (1) the event
driven character of sensor network application makes it hard to
predict program behavior; (2) sensor network usually run batched
jobs which means people cannot run or debug wireless sensor
applications interactively; (3) sensor network application bugs can
only be detected after the software is deployed because of the
highly distributed and faulty nature of sensor nodes;(4) there is
extremely limited of visibility to the running
program. This thesis proposals a source-code
based
dynamic analysis approach to debug wireless sensor network
applications. The NesC compiler is modified to automatically insert
data collecting code at each program point where program control
flow changes. When wireless sensor network applications run on
sensor nodes, the reached program point information will be
automatically recorded. When program finished, the collected
data
can show exactly how program runs. The benefit of this approach is
that the
data collected are from program product run, it shows the
program behavior in real running environment. So the bugs found
here are more valuable.
Advisors/Committee Members: Arora, Anish (Advisor).
Subjects/Keywords: Computer Science; Sensor network; Bug detection; Dynamic analysis; TinyOS; NesC
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APA (6th Edition):
Wei, P. (2009). Dynamic Bug Detection in TinyOS Operating
Environments. (Masters Thesis). The Ohio State University. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=osu1238166929
Chicago Manual of Style (16th Edition):
Wei, Pihui. “Dynamic Bug Detection in TinyOS Operating
Environments.” 2009. Masters Thesis, The Ohio State University. Accessed March 03, 2021.
http://rave.ohiolink.edu/etdc/view?acc_num=osu1238166929.
MLA Handbook (7th Edition):
Wei, Pihui. “Dynamic Bug Detection in TinyOS Operating
Environments.” 2009. Web. 03 Mar 2021.
Vancouver:
Wei P. Dynamic Bug Detection in TinyOS Operating
Environments. [Internet] [Masters thesis]. The Ohio State University; 2009. [cited 2021 Mar 03].
Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1238166929.
Council of Science Editors:
Wei P. Dynamic Bug Detection in TinyOS Operating
Environments. [Masters Thesis]. The Ohio State University; 2009. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=osu1238166929
30.
Haverås, Daniel.
Data Race Detection for Parallel Programs Using a Virtual Platform.
Degree: Electrical Engineering and Computer Science (EECS), 2018, KTH
URL: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-230189
► Data races are highly destructive bugs found in concurrent programs. Because of unordered thread interleavings, data races can randomly appear and disappear during the…
(more)
▼ Data races are highly destructive bugs found in concurrent programs. Because of unordered thread interleavings, data races can randomly appear and disappear during the debugging process which makes them difficult to find and reproduce. A data race exists when multiple threads or processes concurrently access a shared memory address, with at least one of the accesses being a write. Such a scenario can cause data corruption, memory leaks, crashes, or incorrect execution. It is therefore important that data races are absent from production software. This thesis explores dynamic data race detection in programs running on Ericsson’s System Virtualization Platform (SVP), a SystemC/TLM-2.0-based virtual platform used for running software on simulated hardware. SVP is a bit-accurate simulator of Ericsson Many-Core Architecture (EMCA) hardware, enabling software and hardware to be developed in parallel, as well as providing unique insight into software execution. This latter property of SVP has been utilized to implement SVPracer, a proof-of-concept dynamic data race detector. SVPracer is based on a happens-before algorithm similar to Google’s ThreadSanitizer v2, but is significantly different in implementation as it relies entirely on instrumenting binary code during runtime without requiring code modification during build time. A set of test programs exhibiting various data races were written and compiled for EOS, the operating system (OS) running on EMCA Digital Signal Processors (DSPs). Similar programs were created for Linux using POSIX APIs, to compare SVPracer against ThreadSanitizer v2. Both SVPracer and ThreadSanitizer v2 correctly detect the data races present in the respective test programs. Further work must be done in SVPracer to eliminate some false positive results, caused by missing support for some OS functionality such as semaphores. Still, the present state of SVPracer is sufficient proof that dynamic data race detection is possible using a virtual platform. Future work could involve exploring other data race detection algorithms as well as implementing deadlock/livelock detection in virtual platforms.
Datakapplöpning är en mycket destruktiv typ av bugg i samtidig programvara. På grund av icke-ordnad sammanvävning av trådar kan datakapplöpning slumpmässigt dyka upp och försvinna under avlusning (debugging), vilket gör dem svåra att hitta och återskapa. Datakapplöpning existerar när flera trådar eller processer samtidigt accessar en delad minnesaddress och minst en av accesserna är en skrivning. Ett sådant scenario kan orsaka datakorruption, minnesläckor, krascher eller felaktig exekvering. Det är därför viktigt att datakapplöpning inte finns med i programvara för slutlig release. Det här examensarbetet utforskar dynamisk detektion av datakapplöpning i program som körs på Ericssons System Virtualization Platform (SVP), en SystemC/TLM-2.0baserad virtuell platform som används för att köra program på simulerad hårdvara. SVP är en bit-exakt simulator för hårdvara av typen…
Subjects/Keywords: Concurrency; multiprocessing; data race detection; virtual platforms; dynamic analysis; Samtidighet i programvara; multiprocessing; detektion av datakapplöpning; virtuella platformar; dynamisk analys; Electrical Engineering, Electronic Engineering, Information Engineering; Elektroteknik och elektronik
…optimisations is almost unavoidable for dynamic data race detection,
to improve performance and avoid… …Data Race
Detection
2.1
2.1.1
Parallelism with processes and threads
Processes
A modern… …x5D;
2.4
Implementing dynamic data race detection
Detecting data races requires rather… …software developers with data race
detection tools that can be activated during run-time… …detection of data races. The instrumentation shall be used to perform
analysis of program…
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APA (6th Edition):
Haverås, D. (2018). Data Race Detection for Parallel Programs Using a Virtual Platform. (Thesis). KTH. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-230189
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Haverås, Daniel. “Data Race Detection for Parallel Programs Using a Virtual Platform.” 2018. Thesis, KTH. Accessed March 03, 2021.
http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-230189.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Haverås, Daniel. “Data Race Detection for Parallel Programs Using a Virtual Platform.” 2018. Web. 03 Mar 2021.
Vancouver:
Haverås D. Data Race Detection for Parallel Programs Using a Virtual Platform. [Internet] [Thesis]. KTH; 2018. [cited 2021 Mar 03].
Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-230189.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Haverås D. Data Race Detection for Parallel Programs Using a Virtual Platform. [Thesis]. KTH; 2018. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-230189
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
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Open Access Theses and Dissertations
