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You searched for subject:(complementary metal oxide semiconductor CMOS integrated circuits). Showing records 1 – 30 of 31022 total matches.

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University of Limerick

1. Zaidi, Muhaned Ali Hussein. Design and evaluation of high-speed operational amplifier designs using the negative Miller capacitance design technique.

Degree: 2018, University of Limerick

 The operational amplifier (op-amp) is one of the most commonly used analogue circuits for analogue and mixed-signal Integrated Circuit (IC) designs. The op-amp is widely… (more)

Subjects/Keywords: operational amplifier (op-amp); analogue circuits; complementary metal-oxide-semiconductor (CMOS)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zaidi, M. A. H. (2018). Design and evaluation of high-speed operational amplifier designs using the negative Miller capacitance design technique. (Thesis). University of Limerick. Retrieved from http://hdl.handle.net/10344/7599

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Zaidi, Muhaned Ali Hussein. “Design and evaluation of high-speed operational amplifier designs using the negative Miller capacitance design technique.” 2018. Thesis, University of Limerick. Accessed December 12, 2019. http://hdl.handle.net/10344/7599.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Zaidi, Muhaned Ali Hussein. “Design and evaluation of high-speed operational amplifier designs using the negative Miller capacitance design technique.” 2018. Web. 12 Dec 2019.

Vancouver:

Zaidi MAH. Design and evaluation of high-speed operational amplifier designs using the negative Miller capacitance design technique. [Internet] [Thesis]. University of Limerick; 2018. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/10344/7599.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Zaidi MAH. Design and evaluation of high-speed operational amplifier designs using the negative Miller capacitance design technique. [Thesis]. University of Limerick; 2018. Available from: http://hdl.handle.net/10344/7599

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

2. Ho, Aaron Daniel. Asymmetric interleaving in low-voltage CMOS power management with multiple supply rails.

Degree: MS, Electrical & Computer Engineering, 2015, University of Illinois – Urbana-Champaign

 Recent years have seen the proliferation of electronic devices that require multi-phase power converters to provide heterogeneous power rails to different systems. Typical systems will… (more)

Subjects/Keywords: complementary metal–oxide–semiconductor (CMOS) integrated circuits; digital control; low-power electronics; power convertors; asymmetric interleaving; digital control; heterogeneous power rails; low voltage complementary metal–oxide–semiconductor (CMOS) power management; multiphase (complementary metal–oxide–semiconductor) CMOS power management IC system; multiphase power converters; multiple supply rails; reduced input current ripple; size 180 nm; Hardware; Mathematical model; Prototypes; Table lookup; Time-domain analysis

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ho, A. D. (2015). Asymmetric interleaving in low-voltage CMOS power management with multiple supply rails. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/88219

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ho, Aaron Daniel. “Asymmetric interleaving in low-voltage CMOS power management with multiple supply rails.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed December 12, 2019. http://hdl.handle.net/2142/88219.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ho, Aaron Daniel. “Asymmetric interleaving in low-voltage CMOS power management with multiple supply rails.” 2015. Web. 12 Dec 2019.

Vancouver:

Ho AD. Asymmetric interleaving in low-voltage CMOS power management with multiple supply rails. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2142/88219.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ho AD. Asymmetric interleaving in low-voltage CMOS power management with multiple supply rails. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/88219

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Dublin City University

3. Liu, Jun. Compact modelling in RF CMOS technology.

Degree: School of Electronic Engineering, 2011, Dublin City University

 With the continuous downscaling of complementary metal-oxide-semiconductor (CMOS) technology, the RF performance of metal-oxide-semiconductor field transistors (MOSFETs) has considerably improved over the past years. Today,… (more)

Subjects/Keywords: Electronic engineering; complementary metal-oxide-semiconductor; CMOS

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APA (6th Edition):

Liu, J. (2011). Compact modelling in RF CMOS technology. (Thesis). Dublin City University. Retrieved from http://doras.dcu.ie/16590/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Jun. “Compact modelling in RF CMOS technology.” 2011. Thesis, Dublin City University. Accessed December 12, 2019. http://doras.dcu.ie/16590/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Jun. “Compact modelling in RF CMOS technology.” 2011. Web. 12 Dec 2019.

Vancouver:

Liu J. Compact modelling in RF CMOS technology. [Internet] [Thesis]. Dublin City University; 2011. [cited 2019 Dec 12]. Available from: http://doras.dcu.ie/16590/.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu J. Compact modelling in RF CMOS technology. [Thesis]. Dublin City University; 2011. Available from: http://doras.dcu.ie/16590/

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

4. Ajayan, K R. Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology.

Degree: 2014, Indian Institute of Science

 Process variability is a major challenge for the design of nano scale MOSFETs due to fundamental physical limits as well as process control limitations. As… (more)

Subjects/Keywords: Metal Oxide Semiconductors (MOS); Digital Integrated Circuits; Complementary Metal Oxide Semiconductors (CMOS); N-type Metal-Oxide Semiconductors (NMOS); P-type Metal-Oxide Semiconductors (PMOS); Metal Oxode Semiconductor Device Modeling; Look Up Table Model (LUT); Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET); MOSFET Models; BSIM Models; Variability Aware Device Modeling; Integrated Circuit Modeling; Circuit Design; 45nm Analog CMOS Technology; Electrical Communication Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ajayan, K. R. (2014). Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/2005/3516 ; http://etd.iisc.ernet.in/abstracts/4383/G26726-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ajayan, K R. “Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology.” 2014. Thesis, Indian Institute of Science. Accessed December 12, 2019. http://etd.iisc.ernet.in/2005/3516 ; http://etd.iisc.ernet.in/abstracts/4383/G26726-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ajayan, K R. “Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology.” 2014. Web. 12 Dec 2019.

Vancouver:

Ajayan KR. Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology. [Internet] [Thesis]. Indian Institute of Science; 2014. [cited 2019 Dec 12]. Available from: http://etd.iisc.ernet.in/2005/3516 ; http://etd.iisc.ernet.in/abstracts/4383/G26726-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ajayan KR. Variability Aware Device Modeling and Circuit Design in 45nm Analog CMOS Technology. [Thesis]. Indian Institute of Science; 2014. Available from: http://etd.iisc.ernet.in/2005/3516 ; http://etd.iisc.ernet.in/abstracts/4383/G26726-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

5. Chung, Chun-lin. Back-contact photovoltaic device realized by standard CMOS foundry process and its application.

Degree: Master, Electro-Optical Engineering, 2015, NSYSU

 In this thesis, an interdigitated back-contact photovoltaic device is realized by high-resolution doping and multi-layer interconnections provided by standard bulk CMOS processes. Since the device… (more)

Subjects/Keywords: complementary metal-oxide-semiconductor (CMOS); interdigitated back-contact solar cell; integrated passive device; implantable device; surface texture

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APA (6th Edition):

Chung, C. (2015). Back-contact photovoltaic device realized by standard CMOS foundry process and its application. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0628115-150138

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chung, Chun-lin. “Back-contact photovoltaic device realized by standard CMOS foundry process and its application.” 2015. Thesis, NSYSU. Accessed December 12, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0628115-150138.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chung, Chun-lin. “Back-contact photovoltaic device realized by standard CMOS foundry process and its application.” 2015. Web. 12 Dec 2019.

Vancouver:

Chung C. Back-contact photovoltaic device realized by standard CMOS foundry process and its application. [Internet] [Thesis]. NSYSU; 2015. [cited 2019 Dec 12]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0628115-150138.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chung C. Back-contact photovoltaic device realized by standard CMOS foundry process and its application. [Thesis]. NSYSU; 2015. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0628115-150138

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

6. Sun, Yanan. High-performance, low-power, and compact CMOS VLSI circuits with carbon nanotube transistor technology.

Degree: 2014, Hong Kong University of Science and Technology

 Carbon nanotube Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) provides better scalability and performance with suppressed short-channel effects and higher carrier mobility as compared to the conventional silicon… (more)

Subjects/Keywords: Metal oxide semiconductors, Complementary; Design and construction; Integrated circuits; Very large scale integration; Low voltage integrated circuits; Carbon nanotubes; Metal oxide semiconductor field-effect transistors

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APA (6th Edition):

Sun, Y. (2014). High-performance, low-power, and compact CMOS VLSI circuits with carbon nanotube transistor technology. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b1432180 ; http://repository.ust.hk/ir/bitstream/1783.1-72512/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sun, Yanan. “High-performance, low-power, and compact CMOS VLSI circuits with carbon nanotube transistor technology.” 2014. Thesis, Hong Kong University of Science and Technology. Accessed December 12, 2019. https://doi.org/10.14711/thesis-b1432180 ; http://repository.ust.hk/ir/bitstream/1783.1-72512/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sun, Yanan. “High-performance, low-power, and compact CMOS VLSI circuits with carbon nanotube transistor technology.” 2014. Web. 12 Dec 2019.

Vancouver:

Sun Y. High-performance, low-power, and compact CMOS VLSI circuits with carbon nanotube transistor technology. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2014. [cited 2019 Dec 12]. Available from: https://doi.org/10.14711/thesis-b1432180 ; http://repository.ust.hk/ir/bitstream/1783.1-72512/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sun Y. High-performance, low-power, and compact CMOS VLSI circuits with carbon nanotube transistor technology. [Thesis]. Hong Kong University of Science and Technology; 2014. Available from: https://doi.org/10.14711/thesis-b1432180 ; http://repository.ust.hk/ir/bitstream/1783.1-72512/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

7. Manikandan, R R. Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters.

Degree: 2015, Indian Institute of Science

 There has been a huge rise in interest in the design of energy efficient wireless sensor networks (WSN) and body area networks (BAN) with the… (more)

Subjects/Keywords: Transmitter Architecture; Radio Frequency (RF) Transmitter Circuits; Energy Efficient Wireless Transmitters; Wireless Sensor Networks; Phase-Locked Loop (PLL); Frequency Synthesizer Circuits; Wireless Communication; Charge Pump Phase-Locked Loop (CP-PLL); Analog Integrated Circuits; Complementary Metal Oxide Semiconductor (CMOS) Integrated Circuits; Charge Pump Circuits; Electronic Circuits; Spur Suppression Technique; Energy Efficient Transmitters; Communication Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Manikandan, R. R. (2015). Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/handle/2005/2656 ; http://etd.ncsi.iisc.ernet.in/abstracts/3467/G26869-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Manikandan, R R. “Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters.” 2015. Thesis, Indian Institute of Science. Accessed December 12, 2019. http://etd.iisc.ernet.in/handle/2005/2656 ; http://etd.ncsi.iisc.ernet.in/abstracts/3467/G26869-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Manikandan, R R. “Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters.” 2015. Web. 12 Dec 2019.

Vancouver:

Manikandan RR. Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters. [Internet] [Thesis]. Indian Institute of Science; 2015. [cited 2019 Dec 12]. Available from: http://etd.iisc.ernet.in/handle/2005/2656 ; http://etd.ncsi.iisc.ernet.in/abstracts/3467/G26869-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Manikandan RR. Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters. [Thesis]. Indian Institute of Science; 2015. Available from: http://etd.iisc.ernet.in/handle/2005/2656 ; http://etd.ncsi.iisc.ernet.in/abstracts/3467/G26869-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Indian Institute of Science

8. Manikandan, R R. Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters.

Degree: 2015, Indian Institute of Science

 There has been a huge rise in interest in the design of energy efficient wireless sensor networks (WSN) and body area networks (BAN) with the… (more)

Subjects/Keywords: Transmitter Architecture; Radio Frequency (RF) Transmitter Circuits; Energy Efficient Wireless Transmitters; Wireless Sensor Networks; Phase-Locked Loop (PLL); Frequency Synthesizer Circuits; Wireless Communication; Charge Pump Phase-Locked Loop (CP-PLL); Analog Integrated Circuits; Complementary Metal Oxide Semiconductor (CMOS) Integrated Circuits; Charge Pump Circuits; Electronic Circuits; Spur Suppression Technique; Energy Efficient Transmitters; Communication Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Manikandan, R. R. (2015). Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters. (Thesis). Indian Institute of Science. Retrieved from http://hdl.handle.net/2005/2656

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Manikandan, R R. “Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters.” 2015. Thesis, Indian Institute of Science. Accessed December 12, 2019. http://hdl.handle.net/2005/2656.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Manikandan, R R. “Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters.” 2015. Web. 12 Dec 2019.

Vancouver:

Manikandan RR. Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters. [Internet] [Thesis]. Indian Institute of Science; 2015. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2005/2656.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Manikandan RR. Low Power And Low Spur Frequency Synthesizer Circuit Techniques For Energy Efficient Wireless Transmitters. [Thesis]. Indian Institute of Science; 2015. Available from: http://hdl.handle.net/2005/2656

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

9. Graham, Sean R. Distributed scalable model for CMOS FET power amplifier.

Degree: MS, 1200, 2011, University of Illinois – Urbana-Champaign

Integrated circuits are very popular for understandable reasons. A circuit implemented within an IC is more cost effective and reliable. A vast majority of ICs… (more)

Subjects/Keywords: Radio Frequency (RF)+; Complementary metal???oxide???semiconductor (CMOS); Power Amplifier

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APA (6th Edition):

Graham, S. R. (2011). Distributed scalable model for CMOS FET power amplifier. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/18454

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Graham, Sean R. “Distributed scalable model for CMOS FET power amplifier.” 2011. Thesis, University of Illinois – Urbana-Champaign. Accessed December 12, 2019. http://hdl.handle.net/2142/18454.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Graham, Sean R. “Distributed scalable model for CMOS FET power amplifier.” 2011. Web. 12 Dec 2019.

Vancouver:

Graham SR. Distributed scalable model for CMOS FET power amplifier. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2011. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2142/18454.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Graham SR. Distributed scalable model for CMOS FET power amplifier. [Thesis]. University of Illinois – Urbana-Champaign; 2011. Available from: http://hdl.handle.net/2142/18454

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

10. Mertens, Robert. A compact model for silicon controlled rectifiers in low voltage CMOS processes.

Degree: MS, 1200, 2014, University of Illinois – Urbana-Champaign

 This thesis presents an SCR compact model for simulating ESD protection circuits. The aspects of the compact model that are necessary to reproduce measurement data,… (more)

Subjects/Keywords: Complementary metal–oxide–semiconductor (CMOS); integrated circuits; silicon; silicon controlled rectifiers (SCR); Electrostatic discharge (ESD)

…though it is observed) in the majority of the low voltage CMOS devices considered… …by metal interconnects, allowing the resistance RPW-PGR to be ignored. RC-PW is a linear… …resistance network in a CMOS SCR. For N-well triggered devices, the PW and PGR terminals are both… …determine the resistance between node BNPN and the metal connecting the PGR, PW tap, and cathode… …SCR test structures fabricated in 65 nm and 130 nm CMOS technologies. VFTLP measurements… 

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APA (6th Edition):

Mertens, R. (2014). A compact model for silicon controlled rectifiers in low voltage CMOS processes. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/49624

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mertens, Robert. “A compact model for silicon controlled rectifiers in low voltage CMOS processes.” 2014. Thesis, University of Illinois – Urbana-Champaign. Accessed December 12, 2019. http://hdl.handle.net/2142/49624.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mertens, Robert. “A compact model for silicon controlled rectifiers in low voltage CMOS processes.” 2014. Web. 12 Dec 2019.

Vancouver:

Mertens R. A compact model for silicon controlled rectifiers in low voltage CMOS processes. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2014. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2142/49624.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mertens R. A compact model for silicon controlled rectifiers in low voltage CMOS processes. [Thesis]. University of Illinois – Urbana-Champaign; 2014. Available from: http://hdl.handle.net/2142/49624

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

11. Neveu, Florian. Design and implementation of high frequency 3D DC-DC converter : Conception et implémentation d'un convertisseur 3D DC-DC à haute fréquence.

Degree: Docteur es, Génie électrique, 2015, INSA Lyon

L’intégration ultime de convertisseurs à découpage repose sur deux axes de recherche. Le premier axe est de développer les convertisseurs à capacités commutées. Cette approche… (more)

Subjects/Keywords: Electronique de puissance; Convertisseur DC-DC; Haute fréquence; Système embarqué; Circuit intégré Complementary Metal Oxide SemiConductor - CMOS; Power Electronics; DC-DC converters; High fraquency; Integrated circuit; CMOS circuit; 621.317 072

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APA (6th Edition):

Neveu, F. (2015). Design and implementation of high frequency 3D DC-DC converter : Conception et implémentation d'un convertisseur 3D DC-DC à haute fréquence. (Doctoral Dissertation). INSA Lyon. Retrieved from http://www.theses.fr/2015ISAL0133

Chicago Manual of Style (16th Edition):

Neveu, Florian. “Design and implementation of high frequency 3D DC-DC converter : Conception et implémentation d'un convertisseur 3D DC-DC à haute fréquence.” 2015. Doctoral Dissertation, INSA Lyon. Accessed December 12, 2019. http://www.theses.fr/2015ISAL0133.

MLA Handbook (7th Edition):

Neveu, Florian. “Design and implementation of high frequency 3D DC-DC converter : Conception et implémentation d'un convertisseur 3D DC-DC à haute fréquence.” 2015. Web. 12 Dec 2019.

Vancouver:

Neveu F. Design and implementation of high frequency 3D DC-DC converter : Conception et implémentation d'un convertisseur 3D DC-DC à haute fréquence. [Internet] [Doctoral dissertation]. INSA Lyon; 2015. [cited 2019 Dec 12]. Available from: http://www.theses.fr/2015ISAL0133.

Council of Science Editors:

Neveu F. Design and implementation of high frequency 3D DC-DC converter : Conception et implémentation d'un convertisseur 3D DC-DC à haute fréquence. [Doctoral Dissertation]. INSA Lyon; 2015. Available from: http://www.theses.fr/2015ISAL0133


University of Hong Kong

12. Ng, Chik-wai. Design techniques of advanced CMOS building blocks for high-performance power management integrated circuits.

Degree: PhD, 2011, University of Hong Kong

published_or_final_version

Electrical and Electronic Engineering

Doctoral

Doctor of Philosophy

Advisors/Committee Members: Wong, N.

Subjects/Keywords: Metal oxide semiconductors, Complementary - Design and construction.; Integrated circuits - Power supply.

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APA (6th Edition):

Ng, C. (2011). Design techniques of advanced CMOS building blocks for high-performance power management integrated circuits. (Doctoral Dissertation). University of Hong Kong. Retrieved from Ng, C. [吳植偉]. (2011). Design techniques of advanced CMOS building blocks for high-performance power management integrated circuits. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4589692 ; http://dx.doi.org/10.5353/th_b4589692 ; http://hdl.handle.net/10722/163587

Chicago Manual of Style (16th Edition):

Ng, Chik-wai. “Design techniques of advanced CMOS building blocks for high-performance power management integrated circuits.” 2011. Doctoral Dissertation, University of Hong Kong. Accessed December 12, 2019. Ng, C. [吳植偉]. (2011). Design techniques of advanced CMOS building blocks for high-performance power management integrated circuits. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4589692 ; http://dx.doi.org/10.5353/th_b4589692 ; http://hdl.handle.net/10722/163587.

MLA Handbook (7th Edition):

Ng, Chik-wai. “Design techniques of advanced CMOS building blocks for high-performance power management integrated circuits.” 2011. Web. 12 Dec 2019.

Vancouver:

Ng C. Design techniques of advanced CMOS building blocks for high-performance power management integrated circuits. [Internet] [Doctoral dissertation]. University of Hong Kong; 2011. [cited 2019 Dec 12]. Available from: Ng, C. [吳植偉]. (2011). Design techniques of advanced CMOS building blocks for high-performance power management integrated circuits. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4589692 ; http://dx.doi.org/10.5353/th_b4589692 ; http://hdl.handle.net/10722/163587.

Council of Science Editors:

Ng C. Design techniques of advanced CMOS building blocks for high-performance power management integrated circuits. [Doctoral Dissertation]. University of Hong Kong; 2011. Available from: Ng, C. [吳植偉]. (2011). Design techniques of advanced CMOS building blocks for high-performance power management integrated circuits. (Thesis). University of Hong Kong, Pokfulam, Hong Kong SAR. Retrieved from http://dx.doi.org/10.5353/th_b4589692 ; http://dx.doi.org/10.5353/th_b4589692 ; http://hdl.handle.net/10722/163587


Montana State University

13. Hollender, Reinhold Frederick William III. Improved control system for process, voltage, and temperature compensation of CMOS active inductors.

Degree: College of Engineering, 2011, Montana State University

 Wireless communications play an increasingly large role in today's society. Today, many wireless functions are necessarily integrated into chips and other small packages to support… (more)

Subjects/Keywords: Wireless communication systems.; Radio frequency integrated circuits.; Metal oxide semiconductors, Complementary.

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APA (6th Edition):

Hollender, R. F. W. I. (2011). Improved control system for process, voltage, and temperature compensation of CMOS active inductors. (Thesis). Montana State University. Retrieved from https://scholarworks.montana.edu/xmlui/handle/1/1491

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hollender, Reinhold Frederick William III. “Improved control system for process, voltage, and temperature compensation of CMOS active inductors.” 2011. Thesis, Montana State University. Accessed December 12, 2019. https://scholarworks.montana.edu/xmlui/handle/1/1491.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hollender, Reinhold Frederick William III. “Improved control system for process, voltage, and temperature compensation of CMOS active inductors.” 2011. Web. 12 Dec 2019.

Vancouver:

Hollender RFWI. Improved control system for process, voltage, and temperature compensation of CMOS active inductors. [Internet] [Thesis]. Montana State University; 2011. [cited 2019 Dec 12]. Available from: https://scholarworks.montana.edu/xmlui/handle/1/1491.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hollender RFWI. Improved control system for process, voltage, and temperature compensation of CMOS active inductors. [Thesis]. Montana State University; 2011. Available from: https://scholarworks.montana.edu/xmlui/handle/1/1491

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Massey University

14. Abbas, Ibtisam. Biomedical integrated circuit design for an electro-therapy device : a thesis presented in partial fulfilment of the requirements for the degree of Doctor of Philosophy in Electronics and Computer Engineering (Bioelectronics) at School of Engineering and Advanced Technology, Massey University, Albany Campus, New Zealand .

Degree: 2017, Massey University

 A biomedical integrated circuit design (IC) is utilized for the development of a novel non-invasive electro-therapy device, for low frequency multi-channel biomedical stimulation to transform… (more)

Subjects/Keywords: Integrated circuits  – Design and construction; Metal oxide semiconductors, Complementary; Electrotherapeutics  – Instruments

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Abbas, I. (2017). Biomedical integrated circuit design for an electro-therapy device : a thesis presented in partial fulfilment of the requirements for the degree of Doctor of Philosophy in Electronics and Computer Engineering (Bioelectronics) at School of Engineering and Advanced Technology, Massey University, Albany Campus, New Zealand . (Thesis). Massey University. Retrieved from http://hdl.handle.net/10179/14415

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Abbas, Ibtisam. “Biomedical integrated circuit design for an electro-therapy device : a thesis presented in partial fulfilment of the requirements for the degree of Doctor of Philosophy in Electronics and Computer Engineering (Bioelectronics) at School of Engineering and Advanced Technology, Massey University, Albany Campus, New Zealand .” 2017. Thesis, Massey University. Accessed December 12, 2019. http://hdl.handle.net/10179/14415.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Abbas, Ibtisam. “Biomedical integrated circuit design for an electro-therapy device : a thesis presented in partial fulfilment of the requirements for the degree of Doctor of Philosophy in Electronics and Computer Engineering (Bioelectronics) at School of Engineering and Advanced Technology, Massey University, Albany Campus, New Zealand .” 2017. Web. 12 Dec 2019.

Vancouver:

Abbas I. Biomedical integrated circuit design for an electro-therapy device : a thesis presented in partial fulfilment of the requirements for the degree of Doctor of Philosophy in Electronics and Computer Engineering (Bioelectronics) at School of Engineering and Advanced Technology, Massey University, Albany Campus, New Zealand . [Internet] [Thesis]. Massey University; 2017. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/10179/14415.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Abbas I. Biomedical integrated circuit design for an electro-therapy device : a thesis presented in partial fulfilment of the requirements for the degree of Doctor of Philosophy in Electronics and Computer Engineering (Bioelectronics) at School of Engineering and Advanced Technology, Massey University, Albany Campus, New Zealand . [Thesis]. Massey University; 2017. Available from: http://hdl.handle.net/10179/14415

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

15. Ding, Hao. Key concepts for implementing SoC-Holter : Les concepts clés pour la réalisation d'un Holter intégré sur puce.

Degree: Docteur es, Informatique, 2011, Université Blaise-Pascale, Clermont-Ferrand II

En dépit du développement rapide de la médecine, les maladies cardiovasculaires restent la première cause de mortalité dans le monde. En France, chaque année, plus… (more)

Subjects/Keywords: Électrocardiographie (ECG); Complementary Metal Oxide Semiconductor (CMOS); Acquisition Comprimée (CS); Arythmies cardiaques; Vectocardiographie (VCG); Electrocardiography (ECG); Complementary Metal Oxide Semiconductor (CMOS); Compressed Sensing (CS); Cardiac arrhythmias; Vectorcardiography (VCG)

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APA (6th Edition):

Ding, H. (2011). Key concepts for implementing SoC-Holter : Les concepts clés pour la réalisation d'un Holter intégré sur puce. (Doctoral Dissertation). Université Blaise-Pascale, Clermont-Ferrand II. Retrieved from http://www.theses.fr/2011CLF22166

Chicago Manual of Style (16th Edition):

Ding, Hao. “Key concepts for implementing SoC-Holter : Les concepts clés pour la réalisation d'un Holter intégré sur puce.” 2011. Doctoral Dissertation, Université Blaise-Pascale, Clermont-Ferrand II. Accessed December 12, 2019. http://www.theses.fr/2011CLF22166.

MLA Handbook (7th Edition):

Ding, Hao. “Key concepts for implementing SoC-Holter : Les concepts clés pour la réalisation d'un Holter intégré sur puce.” 2011. Web. 12 Dec 2019.

Vancouver:

Ding H. Key concepts for implementing SoC-Holter : Les concepts clés pour la réalisation d'un Holter intégré sur puce. [Internet] [Doctoral dissertation]. Université Blaise-Pascale, Clermont-Ferrand II; 2011. [cited 2019 Dec 12]. Available from: http://www.theses.fr/2011CLF22166.

Council of Science Editors:

Ding H. Key concepts for implementing SoC-Holter : Les concepts clés pour la réalisation d'un Holter intégré sur puce. [Doctoral Dissertation]. Université Blaise-Pascale, Clermont-Ferrand II; 2011. Available from: http://www.theses.fr/2011CLF22166


University of Edinburgh

16. Walker, Richard John. Fully digital, phase-domain ΔΣ 3D range image sensor in 130nm CMOS imaging technology.

Degree: PhD, 2012, University of Edinburgh

 Three-Dimensional (3D) optical range-imaging is a field experiencing rapid growth, expanding into a wide variety of machine vision applications, most recently including consumer gaming. Time… (more)

Subjects/Keywords: 621.3; 3D camera; 3D imaging; CMOS; ?S; sigma-delta; Complementary Metal Oxide semiconductor

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APA (6th Edition):

Walker, R. J. (2012). Fully digital, phase-domain ΔΣ 3D range image sensor in 130nm CMOS imaging technology. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/6214

Chicago Manual of Style (16th Edition):

Walker, Richard John. “Fully digital, phase-domain ΔΣ 3D range image sensor in 130nm CMOS imaging technology.” 2012. Doctoral Dissertation, University of Edinburgh. Accessed December 12, 2019. http://hdl.handle.net/1842/6214.

MLA Handbook (7th Edition):

Walker, Richard John. “Fully digital, phase-domain ΔΣ 3D range image sensor in 130nm CMOS imaging technology.” 2012. Web. 12 Dec 2019.

Vancouver:

Walker RJ. Fully digital, phase-domain ΔΣ 3D range image sensor in 130nm CMOS imaging technology. [Internet] [Doctoral dissertation]. University of Edinburgh; 2012. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/1842/6214.

Council of Science Editors:

Walker RJ. Fully digital, phase-domain ΔΣ 3D range image sensor in 130nm CMOS imaging technology. [Doctoral Dissertation]. University of Edinburgh; 2012. Available from: http://hdl.handle.net/1842/6214

17. Morais, Paulo Sérgio Nogueira. Circuitos digitais em modo de corrente .

Degree: 2010, Universidade de Aveiro

 Este trabalho de dissertação insere-se na área da electrónica digital, e consiste no projecto, construção e caracterização de circuitos digitais em Modo de Corrente, empregando… (more)

Subjects/Keywords: Engenharia electrónica; Electrónica digital; Circuitos integrados; Semicondutores de óxidos metálicos; CMOS (Complementary metal-oxide-semiconductor)

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APA (6th Edition):

Morais, P. S. N. (2010). Circuitos digitais em modo de corrente . (Thesis). Universidade de Aveiro. Retrieved from http://hdl.handle.net/10773/3710

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Morais, Paulo Sérgio Nogueira. “Circuitos digitais em modo de corrente .” 2010. Thesis, Universidade de Aveiro. Accessed December 12, 2019. http://hdl.handle.net/10773/3710.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Morais, Paulo Sérgio Nogueira. “Circuitos digitais em modo de corrente .” 2010. Web. 12 Dec 2019.

Vancouver:

Morais PSN. Circuitos digitais em modo de corrente . [Internet] [Thesis]. Universidade de Aveiro; 2010. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/10773/3710.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Morais PSN. Circuitos digitais em modo de corrente . [Thesis]. Universidade de Aveiro; 2010. Available from: http://hdl.handle.net/10773/3710

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Urbana-Champaign

18. Almulla, Saoud A E A. Absorption and fluorescence spectroscopic analysis using compact, linear variable filter based, detection platforms.

Degree: MS, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 Spectroscopic analysis is an integral part of biological and chemical sensing. However, most spectroscopic equipment is relegated to laboratories. Compact and portable alternatives to conventional… (more)

Subjects/Keywords: Linear variable filter; Spectroscopy; Colorimetry; Fluorometry; Complementary metal-oxide semiconductor (CMOS) sensor

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APA (6th Edition):

Almulla, S. A. E. A. (2017). Absorption and fluorescence spectroscopic analysis using compact, linear variable filter based, detection platforms. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/98318

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Almulla, Saoud A E A. “Absorption and fluorescence spectroscopic analysis using compact, linear variable filter based, detection platforms.” 2017. Thesis, University of Illinois – Urbana-Champaign. Accessed December 12, 2019. http://hdl.handle.net/2142/98318.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Almulla, Saoud A E A. “Absorption and fluorescence spectroscopic analysis using compact, linear variable filter based, detection platforms.” 2017. Web. 12 Dec 2019.

Vancouver:

Almulla SAEA. Absorption and fluorescence spectroscopic analysis using compact, linear variable filter based, detection platforms. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2017. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/2142/98318.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Almulla SAEA. Absorption and fluorescence spectroscopic analysis using compact, linear variable filter based, detection platforms. [Thesis]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/98318

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Dalhousie University

19. Yu, Haoran. Techniques for enhancing the performance of bulk-driven circuits in nano-scale CMOS technology.

Degree: PhD, Department of Electrical & Computer Engineering, 2014, Dalhousie University

 Bulk-driven (BD) technique has been proposed to remedy the voltage swing limitation problem in modern CMOS technology. However, challenges exist when the CMOS technologies move… (more)

Subjects/Keywords: CMOS; bulk-driven; Metal oxide semiconductors, Complementary; Metal oxide semiconductors, Complementary

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APA (6th Edition):

Yu, H. (2014). Techniques for enhancing the performance of bulk-driven circuits in nano-scale CMOS technology. (Doctoral Dissertation). Dalhousie University. Retrieved from http://hdl.handle.net/10222/55992

Chicago Manual of Style (16th Edition):

Yu, Haoran. “Techniques for enhancing the performance of bulk-driven circuits in nano-scale CMOS technology.” 2014. Doctoral Dissertation, Dalhousie University. Accessed December 12, 2019. http://hdl.handle.net/10222/55992.

MLA Handbook (7th Edition):

Yu, Haoran. “Techniques for enhancing the performance of bulk-driven circuits in nano-scale CMOS technology.” 2014. Web. 12 Dec 2019.

Vancouver:

Yu H. Techniques for enhancing the performance of bulk-driven circuits in nano-scale CMOS technology. [Internet] [Doctoral dissertation]. Dalhousie University; 2014. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/10222/55992.

Council of Science Editors:

Yu H. Techniques for enhancing the performance of bulk-driven circuits in nano-scale CMOS technology. [Doctoral Dissertation]. Dalhousie University; 2014. Available from: http://hdl.handle.net/10222/55992


Indian Institute of Science

20. Sai, Ranajit. Development of CMOS-Compatible, Microwave-Assisted Solution Processing of Nanostructured Zine Ferrite Films for Gigahertz Circuits.

Degree: 2013, Indian Institute of Science

 The development of radio frequency integrated circuits (RFICs), especially the dream of integrating analog, digital and radio frequency (RF) components on the same chip that… (more)

Subjects/Keywords: Radio Frequency Integrated Circuits (RFICs); Radio Frequency Inductors; Nanostructured Zinc Ferrite Thin Films; CMOS (Complementary Metal Oxide Semiconductors) Fabrication; Gigahertz Circuits; Nanocrystalline Zinc Ferrite; Zinc Ferrite Thin Film; ZnFe2O4; Zinc Ferrite Nanocrystals; Integrated Circuits; Zinc Ferrite Films; Nanotechnology

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APA (6th Edition):

Sai, R. (2013). Development of CMOS-Compatible, Microwave-Assisted Solution Processing of Nanostructured Zine Ferrite Films for Gigahertz Circuits. (Thesis). Indian Institute of Science. Retrieved from http://etd.iisc.ernet.in/2005/3412 ; http://etd.iisc.ernet.in/abstracts/4279/G25915-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sai, Ranajit. “Development of CMOS-Compatible, Microwave-Assisted Solution Processing of Nanostructured Zine Ferrite Films for Gigahertz Circuits.” 2013. Thesis, Indian Institute of Science. Accessed December 12, 2019. http://etd.iisc.ernet.in/2005/3412 ; http://etd.iisc.ernet.in/abstracts/4279/G25915-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sai, Ranajit. “Development of CMOS-Compatible, Microwave-Assisted Solution Processing of Nanostructured Zine Ferrite Films for Gigahertz Circuits.” 2013. Web. 12 Dec 2019.

Vancouver:

Sai R. Development of CMOS-Compatible, Microwave-Assisted Solution Processing of Nanostructured Zine Ferrite Films for Gigahertz Circuits. [Internet] [Thesis]. Indian Institute of Science; 2013. [cited 2019 Dec 12]. Available from: http://etd.iisc.ernet.in/2005/3412 ; http://etd.iisc.ernet.in/abstracts/4279/G25915-Abs.pdf.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sai R. Development of CMOS-Compatible, Microwave-Assisted Solution Processing of Nanostructured Zine Ferrite Films for Gigahertz Circuits. [Thesis]. Indian Institute of Science; 2013. Available from: http://etd.iisc.ernet.in/2005/3412 ; http://etd.iisc.ernet.in/abstracts/4279/G25915-Abs.pdf

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

21. Mills, Richard P., III. Design and optimization of RF test structures for mm-wave circuit design.

Degree: MS, Electrical and Computer Engineering, 2011, Georgia Tech

This work discusses a methodology developed for robust RF test structure design for SiGe HBTs operating at mm-wave frequencies. Advisors/Committee Members: Cressler, John (Committee Chair), Davis, Jeff (Committee Member), Papapolymerou, John (Committee Member).

Subjects/Keywords: Mm-wave; RF; Test structures; Semiconductors; Metal oxide semiconductors, Complementary; Silicon; Radio frequency integrated circuits

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APA (6th Edition):

Mills, Richard P., I. (2011). Design and optimization of RF test structures for mm-wave circuit design. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/42922

Chicago Manual of Style (16th Edition):

Mills, Richard P., III. “Design and optimization of RF test structures for mm-wave circuit design.” 2011. Masters Thesis, Georgia Tech. Accessed December 12, 2019. http://hdl.handle.net/1853/42922.

MLA Handbook (7th Edition):

Mills, Richard P., III. “Design and optimization of RF test structures for mm-wave circuit design.” 2011. Web. 12 Dec 2019.

Vancouver:

Mills, Richard P. I. Design and optimization of RF test structures for mm-wave circuit design. [Internet] [Masters thesis]. Georgia Tech; 2011. [cited 2019 Dec 12]. Available from: http://hdl.handle.net/1853/42922.

Council of Science Editors:

Mills, Richard P. I. Design and optimization of RF test structures for mm-wave circuit design. [Masters Thesis]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/42922


Hong Kong University of Science and Technology

22. Mohamad, Saqib. A low power CMOS temperature sensor.

Degree: 2014, Hong Kong University of Science and Technology

 Temperature sensing in an important new paradigm in Complementary Metal Oxide Semiconductor (CMOS) system design. Traditionally temperature sens- ing has been achieved via resistive platinum… (more)

Subjects/Keywords: Metal oxide semiconductors, Complementary; Design and construction; Integrated circuits; Detectors; Temperature measuring instruments

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APA (6th Edition):

Mohamad, S. (2014). A low power CMOS temperature sensor. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b1333738 ; http://repository.ust.hk/ir/bitstream/1783.1-73376/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mohamad, Saqib. “A low power CMOS temperature sensor.” 2014. Thesis, Hong Kong University of Science and Technology. Accessed December 12, 2019. https://doi.org/10.14711/thesis-b1333738 ; http://repository.ust.hk/ir/bitstream/1783.1-73376/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mohamad, Saqib. “A low power CMOS temperature sensor.” 2014. Web. 12 Dec 2019.

Vancouver:

Mohamad S. A low power CMOS temperature sensor. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2014. [cited 2019 Dec 12]. Available from: https://doi.org/10.14711/thesis-b1333738 ; http://repository.ust.hk/ir/bitstream/1783.1-73376/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mohamad S. A low power CMOS temperature sensor. [Thesis]. Hong Kong University of Science and Technology; 2014. Available from: https://doi.org/10.14711/thesis-b1333738 ; http://repository.ust.hk/ir/bitstream/1783.1-73376/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

23. Wang, Bo. Voltage reference/incremental data converter designs for low-cost CMOS temperature sensor.

Degree: 2015, Hong Kong University of Science and Technology

 Emerging applications like internet-of-things (IoT) and wireless sensor network (WSN) are the new driving forces behind the Complementary Metal-Oxide Semiconductor (CMOS) temperature sensor market. In… (more)

Subjects/Keywords: Integrated circuits; Design and construction; Metal oxide semiconductors, Complementary; Detectors; Temperature measuring instruments

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APA (6th Edition):

Wang, B. (2015). Voltage reference/incremental data converter designs for low-cost CMOS temperature sensor. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b1477691 ; http://repository.ust.hk/ir/bitstream/1783.1-84792/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wang, Bo. “Voltage reference/incremental data converter designs for low-cost CMOS temperature sensor.” 2015. Thesis, Hong Kong University of Science and Technology. Accessed December 12, 2019. https://doi.org/10.14711/thesis-b1477691 ; http://repository.ust.hk/ir/bitstream/1783.1-84792/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wang, Bo. “Voltage reference/incremental data converter designs for low-cost CMOS temperature sensor.” 2015. Web. 12 Dec 2019.

Vancouver:

Wang B. Voltage reference/incremental data converter designs for low-cost CMOS temperature sensor. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2015. [cited 2019 Dec 12]. Available from: https://doi.org/10.14711/thesis-b1477691 ; http://repository.ust.hk/ir/bitstream/1783.1-84792/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wang B. Voltage reference/incremental data converter designs for low-cost CMOS temperature sensor. [Thesis]. Hong Kong University of Science and Technology; 2015. Available from: https://doi.org/10.14711/thesis-b1477691 ; http://repository.ust.hk/ir/bitstream/1783.1-84792/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

24. Shi, Chao. Energy harvesting CMOS image sensor.

Degree: 2009, Hong Kong University of Science and Technology

 Modern portable imaging systems are expected to consume higher power due to increased image resolution and improved processing features. However, low power operation is needed… (more)

Subjects/Keywords: Metal oxide semiconductors, Complementary; Low voltage integrated circuits; Image processing  – Digital techniques; Image converters

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APA (6th Edition):

Shi, C. (2009). Energy harvesting CMOS image sensor. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b1071143 ; http://repository.ust.hk/ir/bitstream/1783.1-7554/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Shi, Chao. “Energy harvesting CMOS image sensor.” 2009. Thesis, Hong Kong University of Science and Technology. Accessed December 12, 2019. https://doi.org/10.14711/thesis-b1071143 ; http://repository.ust.hk/ir/bitstream/1783.1-7554/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Shi, Chao. “Energy harvesting CMOS image sensor.” 2009. Web. 12 Dec 2019.

Vancouver:

Shi C. Energy harvesting CMOS image sensor. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2009. [cited 2019 Dec 12]. Available from: https://doi.org/10.14711/thesis-b1071143 ; http://repository.ust.hk/ir/bitstream/1783.1-7554/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Shi C. Energy harvesting CMOS image sensor. [Thesis]. Hong Kong University of Science and Technology; 2009. Available from: https://doi.org/10.14711/thesis-b1071143 ; http://repository.ust.hk/ir/bitstream/1783.1-7554/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

25. Wu, Xiajun. Low power and compact digital pixel image sensor using multiple sampling scheme.

Degree: 2009, Hong Kong University of Science and Technology

CMOS image sensors are widely used in many electronic devices such as smart phone and digital camera because of their easy integration with standard CMOS(more)

Subjects/Keywords: Image processing  – Digital techniques; Metal oxide semiconductors, Complementary; Low voltage integrated circuits; Image converters

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Wu, X. (2009). Low power and compact digital pixel image sensor using multiple sampling scheme. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b1071107 ; http://repository.ust.hk/ir/bitstream/1783.1-7551/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Wu, Xiajun. “Low power and compact digital pixel image sensor using multiple sampling scheme.” 2009. Thesis, Hong Kong University of Science and Technology. Accessed December 12, 2019. https://doi.org/10.14711/thesis-b1071107 ; http://repository.ust.hk/ir/bitstream/1783.1-7551/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Wu, Xiajun. “Low power and compact digital pixel image sensor using multiple sampling scheme.” 2009. Web. 12 Dec 2019.

Vancouver:

Wu X. Low power and compact digital pixel image sensor using multiple sampling scheme. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2009. [cited 2019 Dec 12]. Available from: https://doi.org/10.14711/thesis-b1071107 ; http://repository.ust.hk/ir/bitstream/1783.1-7551/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Wu X. Low power and compact digital pixel image sensor using multiple sampling scheme. [Thesis]. Hong Kong University of Science and Technology; 2009. Available from: https://doi.org/10.14711/thesis-b1071107 ; http://repository.ust.hk/ir/bitstream/1783.1-7551/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Hong Kong University of Science and Technology

26. Tang, Fang. Low-power compact control mechanism linear-output current-mediated CMOS imager.

Degree: 2009, Hong Kong University of Science and Technology

CMOS image sensor technology is developing rapidly as the device feature size is continuously being scaled down with the trend that strictly following the Moore's… (more)

Subjects/Keywords: Metal oxide semiconductors, Complementary; Image converters; Low voltage integrated circuits; Image processing  – Digital techniques

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tang, F. (2009). Low-power compact control mechanism linear-output current-mediated CMOS imager. (Thesis). Hong Kong University of Science and Technology. Retrieved from https://doi.org/10.14711/thesis-b1071151 ; http://repository.ust.hk/ir/bitstream/1783.1-7555/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tang, Fang. “Low-power compact control mechanism linear-output current-mediated CMOS imager.” 2009. Thesis, Hong Kong University of Science and Technology. Accessed December 12, 2019. https://doi.org/10.14711/thesis-b1071151 ; http://repository.ust.hk/ir/bitstream/1783.1-7555/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tang, Fang. “Low-power compact control mechanism linear-output current-mediated CMOS imager.” 2009. Web. 12 Dec 2019.

Vancouver:

Tang F. Low-power compact control mechanism linear-output current-mediated CMOS imager. [Internet] [Thesis]. Hong Kong University of Science and Technology; 2009. [cited 2019 Dec 12]. Available from: https://doi.org/10.14711/thesis-b1071151 ; http://repository.ust.hk/ir/bitstream/1783.1-7555/1/th_redirect.html.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tang F. Low-power compact control mechanism linear-output current-mediated CMOS imager. [Thesis]. Hong Kong University of Science and Technology; 2009. Available from: https://doi.org/10.14711/thesis-b1071151 ; http://repository.ust.hk/ir/bitstream/1783.1-7555/1/th_redirect.html

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Ryerson University

27. Parekh, Parth. All-digital ΔΣ time-to-digital converter with bi-directional gated delay line time integrator.

Degree: 2017, Ryerson University

 This report presents a low-power time integrator and its applications in an all-digital first-order ΔΣ time-to-digital converter (TDC). Time-to-Digital Converter (TDC) that map a time… (more)

Subjects/Keywords: Metal oxide semiconductors, Complementary.; Signal processing  – Digital techniques.; Analog-to-digital converters.; Integrated circuits.

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APA (6th Edition):

Parekh, P. (2017). All-digital ΔΣ time-to-digital converter with bi-directional gated delay line time integrator. (Thesis). Ryerson University. Retrieved from https://digital.library.ryerson.ca/islandora/object/RULA%3A6877

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Parekh, Parth. “All-digital ΔΣ time-to-digital converter with bi-directional gated delay line time integrator.” 2017. Thesis, Ryerson University. Accessed December 12, 2019. https://digital.library.ryerson.ca/islandora/object/RULA%3A6877.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Parekh, Parth. “All-digital ΔΣ time-to-digital converter with bi-directional gated delay line time integrator.” 2017. Web. 12 Dec 2019.

Vancouver:

Parekh P. All-digital ΔΣ time-to-digital converter with bi-directional gated delay line time integrator. [Internet] [Thesis]. Ryerson University; 2017. [cited 2019 Dec 12]. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6877.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Parekh P. All-digital ΔΣ time-to-digital converter with bi-directional gated delay line time integrator. [Thesis]. Ryerson University; 2017. Available from: https://digital.library.ryerson.ca/islandora/object/RULA%3A6877

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Columbia University

28. Realov, Simeon Dimitrov. Combined C-V/I-V and RTN CMOS Variability Characterization Using An On-Chip Measurement System.

Degree: 2012, Columbia University

 With the number of transistors integrated into a single integrated circuit (IC) crossing the one-billion mark and complementary metal-oxide-semiconductor (CMOS) technology scaling pushing device dimensions… (more)

Subjects/Keywords: Electrical engineering; Metal oxide semiconductors, Complementary; Systems on a chip; Integrated circuits

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Realov, S. D. (2012). Combined C-V/I-V and RTN CMOS Variability Characterization Using An On-Chip Measurement System. (Doctoral Dissertation). Columbia University. Retrieved from https://doi.org/10.7916/D85H8P3D

Chicago Manual of Style (16th Edition):

Realov, Simeon Dimitrov. “Combined C-V/I-V and RTN CMOS Variability Characterization Using An On-Chip Measurement System.” 2012. Doctoral Dissertation, Columbia University. Accessed December 12, 2019. https://doi.org/10.7916/D85H8P3D.

MLA Handbook (7th Edition):

Realov, Simeon Dimitrov. “Combined C-V/I-V and RTN CMOS Variability Characterization Using An On-Chip Measurement System.” 2012. Web. 12 Dec 2019.

Vancouver:

Realov SD. Combined C-V/I-V and RTN CMOS Variability Characterization Using An On-Chip Measurement System. [Internet] [Doctoral dissertation]. Columbia University; 2012. [cited 2019 Dec 12]. Available from: https://doi.org/10.7916/D85H8P3D.

Council of Science Editors:

Realov SD. Combined C-V/I-V and RTN CMOS Variability Characterization Using An On-Chip Measurement System. [Doctoral Dissertation]. Columbia University; 2012. Available from: https://doi.org/10.7916/D85H8P3D


Columbia University

29. Edrees, Hassan. Monolithically Integrated Acoustic Resonators on CMOS for Radio-Frequency Circuit Applications.

Degree: 2016, Columbia University

 Wireless communication circuits rely on the use of high-quality passive elements (inductor-capacitor resonant tanks) for the implementation of selective filters and high-purity frequency references (oscillators).… (more)

Subjects/Keywords: Piezoelectric devices; Metal oxide semiconductors, Complementary; Radio frequency integrated circuits; Resonators; Electrical engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Edrees, H. (2016). Monolithically Integrated Acoustic Resonators on CMOS for Radio-Frequency Circuit Applications. (Doctoral Dissertation). Columbia University. Retrieved from https://doi.org/10.7916/D8X63N7M

Chicago Manual of Style (16th Edition):

Edrees, Hassan. “Monolithically Integrated Acoustic Resonators on CMOS for Radio-Frequency Circuit Applications.” 2016. Doctoral Dissertation, Columbia University. Accessed December 12, 2019. https://doi.org/10.7916/D8X63N7M.

MLA Handbook (7th Edition):

Edrees, Hassan. “Monolithically Integrated Acoustic Resonators on CMOS for Radio-Frequency Circuit Applications.” 2016. Web. 12 Dec 2019.

Vancouver:

Edrees H. Monolithically Integrated Acoustic Resonators on CMOS for Radio-Frequency Circuit Applications. [Internet] [Doctoral dissertation]. Columbia University; 2016. [cited 2019 Dec 12]. Available from: https://doi.org/10.7916/D8X63N7M.

Council of Science Editors:

Edrees H. Monolithically Integrated Acoustic Resonators on CMOS for Radio-Frequency Circuit Applications. [Doctoral Dissertation]. Columbia University; 2016. Available from: https://doi.org/10.7916/D8X63N7M


Drexel University

30. Filippini, Leo. Charge Recovery Circuits.

Degree: 2019, Drexel University

Modern VLSI systems are under strict power and performance constraints, and the trade-offs between these two aspects drive industry and academic research alike. Static CMOS(more)

Subjects/Keywords: Electrical engineering; Integrated circuits – Very large scale integration; Metal oxide semiconductors, Complementary

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Filippini, L. (2019). Charge Recovery Circuits. (Thesis). Drexel University. Retrieved from https://idea.library.drexel.edu/islandora/object/idea%3A9440

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Filippini, Leo. “Charge Recovery Circuits.” 2019. Thesis, Drexel University. Accessed December 12, 2019. https://idea.library.drexel.edu/islandora/object/idea%3A9440.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Filippini, Leo. “Charge Recovery Circuits.” 2019. Web. 12 Dec 2019.

Vancouver:

Filippini L. Charge Recovery Circuits. [Internet] [Thesis]. Drexel University; 2019. [cited 2019 Dec 12]. Available from: https://idea.library.drexel.edu/islandora/object/idea%3A9440.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Filippini L. Charge Recovery Circuits. [Thesis]. Drexel University; 2019. Available from: https://idea.library.drexel.edu/islandora/object/idea%3A9440

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

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