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University of Waterloo
1.
Selby, Jason W. A.
Unconventional Applications of Compiler Analysis.
Degree: 2011, University of Waterloo
URL: http://hdl.handle.net/10012/6184 
► Previously, compiler transformations have primarily focused on minimizing program execution time. This thesis explores some examples of applying compiler technology outside of its original scope.…
(more)
▼ Previously, compiler transformations have primarily focused on
minimizing program execution time. This thesis explores some examples
of applying compiler technology outside of its original scope.
Specifically, we apply compiler analysis to the field of software
maintenance and evolution by examining the use of global data
throughout the lifetimes of many open source projects. Also, we
investigate the effects of compiler optimizations on the power
consumption of small battery powered devices. Finally, in an area
closer to traditional compiler research we examine automatic program
parallelization in the form of thread-level speculation.
Subjects/Keywords: Compiler Analysis; Compiler Optimization
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APA (6th Edition):
Selby, J. W. A. (2011). Unconventional Applications of Compiler Analysis. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/6184
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Selby, Jason W A. “Unconventional Applications of Compiler Analysis.” 2011. Thesis, University of Waterloo. Accessed January 22, 2020.
http://hdl.handle.net/10012/6184.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Selby, Jason W A. “Unconventional Applications of Compiler Analysis.” 2011. Web. 22 Jan 2020.
Vancouver:
Selby JWA. Unconventional Applications of Compiler Analysis. [Internet] [Thesis]. University of Waterloo; 2011. [cited 2020 Jan 22].
Available from: http://hdl.handle.net/10012/6184.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Selby JWA. Unconventional Applications of Compiler Analysis. [Thesis]. University of Waterloo; 2011. Available from: http://hdl.handle.net/10012/6184
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
University of Georgia
2.
Li, Nan.
Energy-efficient program layout for multi-bank architectures.
Degree: MS, Computer Science, 2003, University of Georgia
URL: http://purl.galileo.usg.edu/uga_etd/li_nan_200312_ms
► Energy conservation is an important problem for battery-powered embedded or portable systems. New technology such as RDRAM enables memory to operate at different power levels.…
(more)
▼ Energy conservation is an important problem for battery-powered embedded or portable systems. New technology such as RDRAM enables memory to operate at different power levels. This allows memory to be partitioned such that only the necessary parts of memory are in active mode, while the others are in low power modes. The traditional program layout has code and heap at one end, and stack at the other end. However, it is possible to place the code in the high address range (next to the stack) without loss of functionality. This thesis explores the energy impact of those two layouts in a partitioned power aware memory system and presents a static program analysis technique to predict the more energy-efficient layout for a given program. We verify the effectiveness of our analysis by running MiBench programs on an enhanced Simplescalar-based power simulator. Our experimental results show that the new layout saves up to 43% of the memory subsystem energy when compared to the traditional layout, with an average improvement of 12%, on a cache-less CPU(such as the widely used ARM7TDMI) . Our static analysis correctly predicts 13 out of 15 benchmarks from the MiBench suite. We also evaluate our scheme on a processor with several cache configurations. The cached configurations benefit much less (averaging less than 1%), though some programs see as much as a 25% energy savings from the non-traditional layout.
Advisors/Committee Members: David Lowenthal.
Subjects/Keywords: Compiler
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APA (6th Edition):
Li, N. (2003). Energy-efficient program layout for multi-bank architectures. (Masters Thesis). University of Georgia. Retrieved from http://purl.galileo.usg.edu/uga_etd/li_nan_200312_ms
Chicago Manual of Style (16th Edition):
Li, Nan. “Energy-efficient program layout for multi-bank architectures.” 2003. Masters Thesis, University of Georgia. Accessed January 22, 2020.
http://purl.galileo.usg.edu/uga_etd/li_nan_200312_ms.
MLA Handbook (7th Edition):
Li, Nan. “Energy-efficient program layout for multi-bank architectures.” 2003. Web. 22 Jan 2020.
Vancouver:
Li N. Energy-efficient program layout for multi-bank architectures. [Internet] [Masters thesis]. University of Georgia; 2003. [cited 2020 Jan 22].
Available from: http://purl.galileo.usg.edu/uga_etd/li_nan_200312_ms.
Council of Science Editors:
Li N. Energy-efficient program layout for multi-bank architectures. [Masters Thesis]. University of Georgia; 2003. Available from: http://purl.galileo.usg.edu/uga_etd/li_nan_200312_ms
University of Alberta
3.
Garg, Rahul.
A compiler for parallel execution of numerical Python
programs on graphics processing units.
Degree: MS, Department of Computing Science, 2009, University of Alberta
URL: https://era.library.ualberta.ca/files/4j03d0630
► Modern Graphics Processing Units (GPUs) are providing breakthrough performance for numerical computing at the cost of increased programming complexity. Current programming models for GPUs require…
(more)
▼ Modern Graphics Processing Units (GPUs) are providing
breakthrough performance for numerical computing at the cost of
increased programming complexity. Current programming models for
GPUs require that the programmer manually manage the data transfer
between CPU and GPU. This thesis proposes a simpler programming
model and introduces a new compilation framework to enable Python
applications containing numerical computations to be executed on
GPUs and multi-core CPUs. The new programming model minimally
extends Python to include type and parallel-loop annotations. Our
compiler framework then automatically identifies the data to be
transferred between the main memory and the GPU for a particular
class of affine array accesses. The compiler also automatically
performs loop transformations to improve performance on GPUs. For
kernels with regular loop structure and simple memory access
patterns, the GPU code generated by the compiler achieves
significant performance improvement over multi-core CPU
codes.
Subjects/Keywords: gpgpu; compiler
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APA (6th Edition):
Garg, R. (2009). A compiler for parallel execution of numerical Python
programs on graphics processing units. (Masters Thesis). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/4j03d0630
Chicago Manual of Style (16th Edition):
Garg, Rahul. “A compiler for parallel execution of numerical Python
programs on graphics processing units.” 2009. Masters Thesis, University of Alberta. Accessed January 22, 2020.
https://era.library.ualberta.ca/files/4j03d0630.
MLA Handbook (7th Edition):
Garg, Rahul. “A compiler for parallel execution of numerical Python
programs on graphics processing units.” 2009. Web. 22 Jan 2020.
Vancouver:
Garg R. A compiler for parallel execution of numerical Python
programs on graphics processing units. [Internet] [Masters thesis]. University of Alberta; 2009. [cited 2020 Jan 22].
Available from: https://era.library.ualberta.ca/files/4j03d0630.
Council of Science Editors:
Garg R. A compiler for parallel execution of numerical Python
programs on graphics processing units. [Masters Thesis]. University of Alberta; 2009. Available from: https://era.library.ualberta.ca/files/4j03d0630
University of Alberta
4.
Xunhao, Li.
Jit4OpenCL: a compiler from Python to OpenCL.
Degree: MS, Department of Computing Science, 2010, University of Alberta
URL: https://era.library.ualberta.ca/files/1v53jx087
► Heterogeneous computing platforms that use GPUs and CPUs in tandem for computation have become an important choice to build low-cost high-performance computing platforms. The computing…
(more)
▼ Heterogeneous computing platforms that use GPUs and
CPUs in tandem for computation have become an important choice to
build low-cost high-performance computing platforms. The computing
ability of modern GPUs surpasses that of CPUs can offer for certain
classes of applications. GPUs can deliver several Tera-Flops in
peak performance. However, programmers must adopt a more
complicated and more difficult new programming paradigm. To
alleviate the burden of programming for heterogeneous systems, Garg
and Amaral developed a Python compiling framework that combines an
ahead-of-time compiler called unPython with a just-in-time compiler
called jit4GPU. This compilation framework generates code for
systems with AMD GPUs. We extend the framework to retarget it to
generate OpenCL code, an industry standard that is implemented for
most GPUs. Therefore, by generating OpenCL code, this new compiler,
called jit4OpenCL, enables the execution of the same program in a
wider selection of heterogeneous platforms. To further improve the
target-code performance on nVidia GPUs, we developed an
array-access analysis tool that helps to exploit the data
reusability by utilizing the shared (local) memory space hierarchy
in OpenCL. The thesis presents an experimental performance
evaluation indicating that, in comparison with jit4GPU, jit4OpenCL
has performance degradation because of the current performance of
implementations of OpenCL, and also because of the extra time
needed for the additional just-in-time compilation. However, the
portable code generated by jit4OpenCL still have performance gains
in some applications compared to highly optimized CPU
code.
Subjects/Keywords: Python; compiler; OpenCL
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APA (6th Edition):
Xunhao, L. (2010). Jit4OpenCL: a compiler from Python to OpenCL. (Masters Thesis). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/1v53jx087
Chicago Manual of Style (16th Edition):
Xunhao, Li. “Jit4OpenCL: a compiler from Python to OpenCL.” 2010. Masters Thesis, University of Alberta. Accessed January 22, 2020.
https://era.library.ualberta.ca/files/1v53jx087.
MLA Handbook (7th Edition):
Xunhao, Li. “Jit4OpenCL: a compiler from Python to OpenCL.” 2010. Web. 22 Jan 2020.
Vancouver:
Xunhao L. Jit4OpenCL: a compiler from Python to OpenCL. [Internet] [Masters thesis]. University of Alberta; 2010. [cited 2020 Jan 22].
Available from: https://era.library.ualberta.ca/files/1v53jx087.
Council of Science Editors:
Xunhao L. Jit4OpenCL: a compiler from Python to OpenCL. [Masters Thesis]. University of Alberta; 2010. Available from: https://era.library.ualberta.ca/files/1v53jx087
University of Delaware
5.
Chen, Yuanfang.
Software simultaneous multithreading through compilation
.
Degree: 2018, University of Delaware
URL: http://udspace.udel.edu/handle/19716/23594
► With the Dennard Scaling law break for a long time, the computer architecture design progress towards the wider rather than deeper organization. There are three…
(more)
▼ With the Dennard Scaling law break for a long time, the computer architecture design progress towards the wider rather than deeper organization. There are three ways to design wider architecture: 1. Putting more cores on the die to utilize thread level parallelism(TLP); 2. Putting more execution ports in the pipeline to utilize instruction level parallelism(ILP); 3. Making vector register wider to utilize data level parallelism(DLP). To speed up a wide spectrum of applications, modern CPU processors usually have all these characteristics at the same time. However, not all applications could make effective use of these characteristics simultaneously. To efficiently use any of these is still a challenging problem in the optimizing compiler research community even though these problems are not new. Processor architect designed simultaneous multithreading (SMT) to alleviate the problem. ☐ Simultaneous multithreading is an essential technique for improving pipeline resource utilization and the overall power efficiency of chips especially when the processor is either wide or comprised of an in-order pipeline. For a wide-issue superscalar processor, there are two kinds of wasted issue slots: vertical waste where all issue slots in a cycle are empty; and horizontal waste where the issue slots in a cycle are partially empty [74]. Simultaneous multithreading, contrary to its other two counterparts: fine- grained multithreading and coarse-grained multithreading, can fill both vertical and horizontal waste, hence enhancing the overall efficiency. From the user applications point of view, there are two ways to improve the speed or the throughput: thread level parallelism (TLP) and instruction level parallelism (ILP). Simultaneous multithreading can exploit both TLP and ILP in the same cycle whereas fine-grained or coarse-grained multithreading can only exploit either TLP or ILP in a single cycle. ☐ Despite all the benefits brought by simultaneous multithreading (SMT), it's adopted by semiconductor chip makers at a slow pace. AMD most recent Zen processor is its first CPU product featuring SMT. The only other well-known chip makers that offer SMT enabled processors are Intel and IBM. The reason for this is that SMT is very complex to implement. Many of the pipeline stages and memory system need hardware logic to have an efficient SMT implementation. For embedded chips, SMT is not even an affordable choice. ☐ To harvest the benefits provided by SMT with incurring significant hardware costs, we propose a Compiler Based SMT implementation framework called CSSMT that achieves comparable performance to hardware-based SMT. With the help of advanced profiling techniques enabled by precise PMU counters in modern CPU, CSSMT can identify those applications that could potentially benefit from SMT and guide our LLVM based compiler to merge the hot spots in respective threads co-running in the same pipeline. CSSMT is orthogonal to the effect of hardware SMT and can bail out when the merging is not profitable based on its cost model derived…
Subjects/Keywords: Applied sciences;
Compiler;
LLVM;
SMT
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APA (6th Edition):
Chen, Y. (2018). Software simultaneous multithreading through compilation
. (Doctoral Dissertation). University of Delaware. Retrieved from http://udspace.udel.edu/handle/19716/23594
Chicago Manual of Style (16th Edition):
Chen, Yuanfang. “Software simultaneous multithreading through compilation
.” 2018. Doctoral Dissertation, University of Delaware. Accessed January 22, 2020.
http://udspace.udel.edu/handle/19716/23594.
MLA Handbook (7th Edition):
Chen, Yuanfang. “Software simultaneous multithreading through compilation
.” 2018. Web. 22 Jan 2020.
Vancouver:
Chen Y. Software simultaneous multithreading through compilation
. [Internet] [Doctoral dissertation]. University of Delaware; 2018. [cited 2020 Jan 22].
Available from: http://udspace.udel.edu/handle/19716/23594.
Council of Science Editors:
Chen Y. Software simultaneous multithreading through compilation
. [Doctoral Dissertation]. University of Delaware; 2018. Available from: http://udspace.udel.edu/handle/19716/23594
University of Notre Dame
6.
Peter James Bui.
A Compiler Toolchain for Distributed Data Intensive
Scientific Workflows</h1>.
Degree: PhD, Computer Science and Engineering, 2012, University of Notre Dame
URL: https://curate.nd.edu/show/pk02c823v2f
► With the growing amount of computational resources available to researchers today and the explosion of scientific data in modern research, it is imperative that…
(more)
▼ With the growing amount of computational
resources available to researchers today and the explosion of
scientific data in modern research, it is imperative that
scientists be able to construct data processing applications that
harness these vast computing systems. To address this need, I
propose applying concepts from traditional compilers, linkers, and
profilers to the construction of distributed workflows and evaluate
this approach by implementing a
compiler toolchain that allows
users to compose scientific workflows in a high-level programming
language. In this dissertation, I describe the
execution and programming model of this
compiler toolchain. Next, I
examine four
compiler optimizations and evaluate their
effectiveness at improving the performance of various distributed
workflows. Afterwards, I present a set of linking utilities for
packaging workflows and a group of profiling tools for analyzing
and debugging workflows. Finally, I discuss modifications made to
the run-time system to support features such as enhanced provenance
information and garbage collection. Altogether, these components
form a
compiler toolchain that demonstrates the effectiveness of
applying traditional
compiler techniques to the challenges of
constructing distributed data intensive scientific workflows.
Advisors/Committee Members: Patrick Flynn, Committee Member, Scott Emrich, Committee Member, Douglas Thain, Committee Chair, Jesus Izaguirre, Committee Member.
Subjects/Keywords: compiler; distributed systems; workflows; python
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APA (6th Edition):
Bui, P. J. (2012). A Compiler Toolchain for Distributed Data Intensive
Scientific Workflows</h1>. (Doctoral Dissertation). University of Notre Dame. Retrieved from https://curate.nd.edu/show/pk02c823v2f
Chicago Manual of Style (16th Edition):
Bui, Peter James. “A Compiler Toolchain for Distributed Data Intensive
Scientific Workflows</h1>.” 2012. Doctoral Dissertation, University of Notre Dame. Accessed January 22, 2020.
https://curate.nd.edu/show/pk02c823v2f.
MLA Handbook (7th Edition):
Bui, Peter James. “A Compiler Toolchain for Distributed Data Intensive
Scientific Workflows</h1>.” 2012. Web. 22 Jan 2020.
Vancouver:
Bui PJ. A Compiler Toolchain for Distributed Data Intensive
Scientific Workflows</h1>. [Internet] [Doctoral dissertation]. University of Notre Dame; 2012. [cited 2020 Jan 22].
Available from: https://curate.nd.edu/show/pk02c823v2f.
Council of Science Editors:
Bui PJ. A Compiler Toolchain for Distributed Data Intensive
Scientific Workflows</h1>. [Doctoral Dissertation]. University of Notre Dame; 2012. Available from: https://curate.nd.edu/show/pk02c823v2f
7.
Mitropoulou, Konstantina.
Performance optimizations for compiler-based error detection.
Degree: PhD, 2015, University of Edinburgh
URL: http://hdl.handle.net/1842/10473
► The trend towards smaller transistor technologies and lower operating voltages stresses the hardware and makes transistors more susceptible to transient errors. In future systems, performance…
(more)
▼ The trend towards smaller transistor technologies and lower operating voltages stresses the hardware and makes transistors more susceptible to transient errors. In future systems, performance and power gains will come at the cost of unreliable areas on the chip. For this reason, there is an increased need for low-overhead highly-reliable error detection methodologies. In the last years, several techniques have been proposed. The majority of them are based on redundancy which can be implemented at several levels (e.g., hardware, instruction, thread, process, etc). In instruction-level error detection approaches, the compiler replicates the instructions of the program and inserts checks wherever they are needed. The checks evaluate code correctness and decide whether or not an error has occurred. This type of error detection is more flexible than the hardware alternatives. It allows the programmer to choose the protected area of the program and it can be applied without any hardware modifications. On the other hand, the replicated instructions and the checks cause a large slowdown making software techniques less appealing. In this thesis, we propose two techniques that aim at reducing the error detection overhead of compiler-based approaches and improving system’s performance without sacrificing the fault-coverage. The first technique, DRIFT, achieves this by decoupling the execution of the code (original and replicated) from the checks. The checks are compare and jump instructions. The latter ones tend to make the code sequential and prohibit the compiler from performing aggressive instruction scheduling optimizations. We call this phenomenon basic-block fragmentation. DRIFT reduces the impact of basic-block fragmentation by breaking the synchronized execute-check-confirm-execute cycle. In this way, DRIFT generates a scheduler-friendly code with more instruction-level parallelism (ILP). As a result, it reduces the performance overhead down to 1.29× (on average) and outperforms the state-of-the-art by up to 29.7% retaining the same fault-coverage. Next, CASTED focuses on reducing the impact of error detection overhead on single-chip scalable architectures that are composed of tightly-coupled cores. The proposed compiler methodology adaptively distributes the error detection overhead to the available resources across multiple cores, fully exploiting the abundant ILP of these architectures. CASTED adapts to a wide range of architecture configurations (issue-width, inter-core communication). The results show that CASTED matches the performance of, and often outperforms, sometimes by as mush as 21.2%, the best fixed state-of-the-art approach while maintaining the same fault coverage.
Subjects/Keywords: 005.75; fault tolerance; compiler
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APA (6th Edition):
Mitropoulou, K. (2015). Performance optimizations for compiler-based error detection. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/10473
Chicago Manual of Style (16th Edition):
Mitropoulou, Konstantina. “Performance optimizations for compiler-based error detection.” 2015. Doctoral Dissertation, University of Edinburgh. Accessed January 22, 2020.
http://hdl.handle.net/1842/10473.
MLA Handbook (7th Edition):
Mitropoulou, Konstantina. “Performance optimizations for compiler-based error detection.” 2015. Web. 22 Jan 2020.
Vancouver:
Mitropoulou K. Performance optimizations for compiler-based error detection. [Internet] [Doctoral dissertation]. University of Edinburgh; 2015. [cited 2020 Jan 22].
Available from: http://hdl.handle.net/1842/10473.
Council of Science Editors:
Mitropoulou K. Performance optimizations for compiler-based error detection. [Doctoral Dissertation]. University of Edinburgh; 2015. Available from: http://hdl.handle.net/1842/10473
Louisiana State University
8.
Hanagodimath, Pratik Prabhu.
Performance Comparison Between Patus and Pluto Compilers on Stencils.
Degree: MSEE, Electrical and Computer Engineering, 2014, Louisiana State University
URL: etd-04142014-090546
;
https://digitalcommons.lsu.edu/gradschool_theses/2636
Comparing the performances of Patus and Pluto compilers on stencil applications. Stencils are written in Jacobi and Seidel style of coding and performances of both these compilers are analysed based on these coding styles.
Subjects/Keywords: Compiler optimization; parallel execution.
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APA (6th Edition):
Hanagodimath, P. P. (2014). Performance Comparison Between Patus and Pluto Compilers on Stencils. (Masters Thesis). Louisiana State University. Retrieved from etd-04142014-090546 ; https://digitalcommons.lsu.edu/gradschool_theses/2636
Chicago Manual of Style (16th Edition):
Hanagodimath, Pratik Prabhu. “Performance Comparison Between Patus and Pluto Compilers on Stencils.” 2014. Masters Thesis, Louisiana State University. Accessed January 22, 2020.
etd-04142014-090546 ; https://digitalcommons.lsu.edu/gradschool_theses/2636.
MLA Handbook (7th Edition):
Hanagodimath, Pratik Prabhu. “Performance Comparison Between Patus and Pluto Compilers on Stencils.” 2014. Web. 22 Jan 2020.
Vancouver:
Hanagodimath PP. Performance Comparison Between Patus and Pluto Compilers on Stencils. [Internet] [Masters thesis]. Louisiana State University; 2014. [cited 2020 Jan 22].
Available from: etd-04142014-090546 ; https://digitalcommons.lsu.edu/gradschool_theses/2636.
Council of Science Editors:
Hanagodimath PP. Performance Comparison Between Patus and Pluto Compilers on Stencils. [Masters Thesis]. Louisiana State University; 2014. Available from: etd-04142014-090546 ; https://digitalcommons.lsu.edu/gradschool_theses/2636
University of Kansas
9.
Smith, Adam R.
Compiler Transformations to Generate Reentrant C Programs to Assist Software Parallelization.
Degree: MS, Electrical Engineering & Computer Science, 2009, University of Kansas
URL: http://hdl.handle.net/1808/5314
► As we move through the multi-core era into the many-core era it becomes obvi- ous that thread-based programming is here to stay. This trend in…
(more)
▼ As we move through the multi-core era into the many-core era it becomes obvi- ous that thread-based programming is here to stay. This trend in the development of general purpose hardware is augmented by the fact that while writing sequential programs is considered a non-trivial task, writing parallel applications to take ad- vantage of the advances in the number of cores in a processor severely complicates the process. Writing parallel applications requires programs and functions to be reentrant. Therefore, we cannot use globals and statics. However, globals and statics are useful in certain contexts. Globals allow an easy programming mecha- nism to share data between several functions. Statics provide the only mechanism of data hiding in C for variables that are global in scope. Writing parallel programs restricts users from using globals and statics in their programs, as doing so would make the program non-reentrant. Moreover, there is a large existing legacy code base of sequential programs that are non-reentrant, since they rely on statics and globals. Several of these sequential programs dis- play significant amounts of data parallelism by operating on independent chunks of input data, and therefore can be easily converted into parallel versions to ex- ploit multi-core processors. Indeed, several such programs have been manually converted into parallel versions. However, manually eliminating all globals and statics to make the program reentrant is tedious, time-consuming, and error-prone. In this paper we describe a system to provide a semi-automated mechanism for users to still be able to use statics and globals in their programs, and to let the
compiler automatically convert them into their semantically-equivalent reentrant versions enabling their parallelization later.
Advisors/Committee Members: Kulkarni, Prasad (advisor), Alexander, Perry (cmtemember), Gill, Andrew (cmtemember).
Subjects/Keywords: Computer science; Compiler; Parallel; Reentrant
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APA (6th Edition):
Smith, A. R. (2009). Compiler Transformations to Generate Reentrant C Programs to Assist Software Parallelization. (Masters Thesis). University of Kansas. Retrieved from http://hdl.handle.net/1808/5314
Chicago Manual of Style (16th Edition):
Smith, Adam R. “Compiler Transformations to Generate Reentrant C Programs to Assist Software Parallelization.” 2009. Masters Thesis, University of Kansas. Accessed January 22, 2020.
http://hdl.handle.net/1808/5314.
MLA Handbook (7th Edition):
Smith, Adam R. “Compiler Transformations to Generate Reentrant C Programs to Assist Software Parallelization.” 2009. Web. 22 Jan 2020.
Vancouver:
Smith AR. Compiler Transformations to Generate Reentrant C Programs to Assist Software Parallelization. [Internet] [Masters thesis]. University of Kansas; 2009. [cited 2020 Jan 22].
Available from: http://hdl.handle.net/1808/5314.
Council of Science Editors:
Smith AR. Compiler Transformations to Generate Reentrant C Programs to Assist Software Parallelization. [Masters Thesis]. University of Kansas; 2009. Available from: http://hdl.handle.net/1808/5314
Virginia Tech
10.
Liu, Qingrui.
Compiler-Directed Error Resilience for Reliable Computing.
Degree: PhD, Electrical and Computer Engineering, 2018, Virginia Tech
URL: http://hdl.handle.net/10919/84526
► Error resilience has become as important as power and performance in modern computing architecture. There are various sources of errors that can paralyze real-world computing…
(more)
▼ Error resilience has become as important as power and performance in modern computing
architecture. There are various sources of errors that can paralyze real-world computing
systems. Of particular interest to this dissertation are single-event errors. They can be
the results of energetic particle strike or abrupt power outage that corrupts the program
states leading to system failures. Specifically, energetic particle strike is the major cause of
soft error while abrupt power outage can result in memory inconsistency in the nonvolatile
memory systems.
Unfortunately, existing techniques to handle those single-event errors are either resource consuming (e.g., hardware approaches) or heavy-weight (e.g., software approaches). To
address this problem, this dissertation identifies idempotent processing as an alternative recovery technique to handle the system failures in an efficient and low-cost manner. Then, this
dissertation first proposes to design and develop a
compiler-directed lightweight methodology which leverages idempotent processing and the state-of-the-art sensor-based detection to
achieve soft error resilience at low-cost. This dissertation also introduces a lightweight soft error tolerant hardware design that redefines idempotent processing where the idempotent
regions can be created, verified and recovered from the processor's point of view. Furthermore, this dissertation proposes a series of
compiler optimizations that significantly reduce
the hardware and runtime overhead of the idempotent processing. Lastly, this dissertation
proposes a failure-atomic system integrated with idempotent processing to resolve another
type of single-event error, i.e., failure-induced memory inconsistency in the nonvolatile memory systems.
Advisors/Committee Members: Jung, Changhee (committeechair), Zeng, Haibo (committeechair), Ravindran, Binoy (committee member), Schaumont, Patrick Robert (committee member), Min, Chang Woo (committee member).
Subjects/Keywords: Reliability; Compiler Optimization; Computer Architecture
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APA (6th Edition):
Liu, Q. (2018). Compiler-Directed Error Resilience for Reliable Computing. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/84526
Chicago Manual of Style (16th Edition):
Liu, Qingrui. “Compiler-Directed Error Resilience for Reliable Computing.” 2018. Doctoral Dissertation, Virginia Tech. Accessed January 22, 2020.
http://hdl.handle.net/10919/84526.
MLA Handbook (7th Edition):
Liu, Qingrui. “Compiler-Directed Error Resilience for Reliable Computing.” 2018. Web. 22 Jan 2020.
Vancouver:
Liu Q. Compiler-Directed Error Resilience for Reliable Computing. [Internet] [Doctoral dissertation]. Virginia Tech; 2018. [cited 2020 Jan 22].
Available from: http://hdl.handle.net/10919/84526.
Council of Science Editors:
Liu Q. Compiler-Directed Error Resilience for Reliable Computing. [Doctoral Dissertation]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/84526
University of Illinois – Chicago
11.
Casula, Dario.
Witnessing Control Flow Graph Optimizations.
Degree: 2016, University of Illinois – Chicago
URL: http://hdl.handle.net/10027/20974
► Proving the correctness of a program transformation, and specifically, of a compiler op- timization, is a long-standing research problem. Trusting the compiler requires to guarantee…
(more)
▼ Proving the correctness of a program transformation, and specifically, of a
compiler op- timization, is a long-standing research problem. Trusting the
compiler requires to guarantee that the properties verified on the source program hold for the compiled target-code as well. Thus, the primary objective of formal correctness verification is to preserve the semantics of the source code, maintaining untouched its logical behavior.
Traditional methods for formal correctness verification are not convenient to validate large and complex programs like compilers, and intensive testing, despite its proven efficacy, cannot guarantee the absence of bugs.
This thesis is part of a larger on-going research project aimed to demonstrate the feasibility to overcome the difficulties of traditional formal methods. K. Namjoshi and L. Zuck propose a new methodology for creating an automated proof to guarantee the correctness of every execution of an optimization. A witness is a run-time generated relation between the source code and the target code, before and after the transformation. The relation is able to represent all the properties that must be valid throughout the optimization, offering a mathematical formula to prove, through a SMT-Solver (typically Microsoft Z3), if the invariants hold and the semantics is preserved. This work is a further step towards the implementation of a witnessing
compiler: the SimplifyCFG pass of the LLVM
compiler framework is augmented with a witness generator procedure which constructs, run-time, the relations to prove the correctness of every single simplification in the control flow graph, performed by the
compiler.
We show that it is feasible to augment the SimplifyCFG pass with a witness generation procedure. We describe the structure of the code and the mathematical relations designed to demonstrate the correctness of a transformation on the Control Flow Graph. Benchmarks and tests will prove the correct behavior of our implementation and the effectiveness of the witness- ing procedure. We provide details about the witnesses and the results of the benchmarks.
Advisors/Committee Members: Zuck, Lenore D. (advisor), Gjomemo, Rigel (committee member), Santambrogio, Marco (committee member).
Subjects/Keywords: llvm; witness; z3; CFG; compiler
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APA (6th Edition):
Casula, D. (2016). Witnessing Control Flow Graph Optimizations. (Thesis). University of Illinois – Chicago. Retrieved from http://hdl.handle.net/10027/20974
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Casula, Dario. “Witnessing Control Flow Graph Optimizations.” 2016. Thesis, University of Illinois – Chicago. Accessed January 22, 2020.
http://hdl.handle.net/10027/20974.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Casula, Dario. “Witnessing Control Flow Graph Optimizations.” 2016. Web. 22 Jan 2020.
Vancouver:
Casula D. Witnessing Control Flow Graph Optimizations. [Internet] [Thesis]. University of Illinois – Chicago; 2016. [cited 2020 Jan 22].
Available from: http://hdl.handle.net/10027/20974.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Casula D. Witnessing Control Flow Graph Optimizations. [Thesis]. University of Illinois – Chicago; 2016. Available from: http://hdl.handle.net/10027/20974
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Delft University of Technology
12.
De Smalen, S.
A solution to misaligned data access in a vectorizing compiler framework:.
Degree: 2009, Delft University of Technology
URL: http://resolver.tudelft.nl/uuid:ee641d0f-b8c2-4194-bc46-a3e5326bea5f
► Vectorizing code for short vector architectures as employed by today’s multimedia extensions comes with a number of issues. The responsibilities of these issues are moved…
(more)
▼ Vectorizing code for short vector architectures as employed by today’s multimedia extensions comes with a number of issues. The responsibilities of these issues are moved to the
compiler in order to keep hardware simple. One of those issues is memory-alignment, which requires the
compiler to guarantee loading and storing vectors at aligned addresses.
Previous work that covered this issue proposed a mechanism to reorder vectors at runtime to ensure proper alignments, while other work has focussed on finding a minimal number of reorderings. We combined these subjects into an in-depth research and implemented the optimization for the retar- getable CoSy(R)
compiler framework. Instead of solely focussing on the minimal number of reorder- ings, we also considered dynamic (runtime) properties which may enable latency-hiding of reordering operations. Furthermore, we performed a comparison of the presented reordering-techniques and researched the impact of other
compiler optimizations on the proposed transformation. Finally, we placed our results into perspective with unaligned load/store operations supplied by our target architecture.
With our implementation, we were able to vectorize a number of applications for SSE and SSE2 vector extensions where alignment-issues were involved. For randomly generated loops we were able to achieve between 50% and 80% of the speedup obtained by unaligned memory instructions. (Our targeted architecture is less strict on memory alignment and supplies instructions that can handle misalignments by hardware). As for the benchmarks, we were able to achieve speedup factors of about 2.25x for a block-matching algorithm (combined with loop versioning to avoid runtime alignment), 1.6x for the SPEC95 Swim benchmark and a factor 4x for a Sobel FIR filter.
Advisors/Committee Members: Juurlink, B.H.H..
Subjects/Keywords: SIMD; vectorization; compiler; alignment
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APA (6th Edition):
De Smalen, S. (2009). A solution to misaligned data access in a vectorizing compiler framework:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:ee641d0f-b8c2-4194-bc46-a3e5326bea5f
Chicago Manual of Style (16th Edition):
De Smalen, S. “A solution to misaligned data access in a vectorizing compiler framework:.” 2009. Masters Thesis, Delft University of Technology. Accessed January 22, 2020.
http://resolver.tudelft.nl/uuid:ee641d0f-b8c2-4194-bc46-a3e5326bea5f.
MLA Handbook (7th Edition):
De Smalen, S. “A solution to misaligned data access in a vectorizing compiler framework:.” 2009. Web. 22 Jan 2020.
Vancouver:
De Smalen S. A solution to misaligned data access in a vectorizing compiler framework:. [Internet] [Masters thesis]. Delft University of Technology; 2009. [cited 2020 Jan 22].
Available from: http://resolver.tudelft.nl/uuid:ee641d0f-b8c2-4194-bc46-a3e5326bea5f.
Council of Science Editors:
De Smalen S. A solution to misaligned data access in a vectorizing compiler framework:. [Masters Thesis]. Delft University of Technology; 2009. Available from: http://resolver.tudelft.nl/uuid:ee641d0f-b8c2-4194-bc46-a3e5326bea5f
Delft University of Technology
13.
Schoneveld, G.J.
VHDL to SystemC: The Design of a Translator:.
Degree: 2009, Delft University of Technology
URL: http://resolver.tudelft.nl/uuid:f2ecf719-d8d4-4197-be07-1822e84f6968
► VHDL and SystemC are both languages to describe or model circuits and systems. Reasons could exist for wanting to translate a model in VHDL to…
(more)
▼ VHDL and SystemC are both languages to describe or model circuits and systems. Reasons could exist for wanting to translate a model in VHDL to an equivalent model in SystemC. A system in SystemC can be needed for modeling a system with a software part, for a faster simulation, or because some tools only support SystemC.
This thesis presents a tool that performs this translation from VHDL to SystemC. The tool is constructed like a regular
compiler: It consists of a front-end that reads and analyzes VHDL code and a back-end that generates SystemC code. The front-end came from the FreeHDL project and we have made the back-end ourselves. The back-end generates SystemC code by traversing the tree that comes from the front-end.
We have validated that the tool is suitable for simulation purposes and we have verified that the tool translates VHDL without problems in most cases we have seen in the wild.
Advisors/Committee Members: Van Leuken, T.G.R.M., Van der Veen, A.J..
Subjects/Keywords: VHDL; SystemC; translator; converter; compiler
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Manager
APA (6th Edition):
Schoneveld, G. J. (2009). VHDL to SystemC: The Design of a Translator:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:f2ecf719-d8d4-4197-be07-1822e84f6968
Chicago Manual of Style (16th Edition):
Schoneveld, G J. “VHDL to SystemC: The Design of a Translator:.” 2009. Masters Thesis, Delft University of Technology. Accessed January 22, 2020.
http://resolver.tudelft.nl/uuid:f2ecf719-d8d4-4197-be07-1822e84f6968.
MLA Handbook (7th Edition):
Schoneveld, G J. “VHDL to SystemC: The Design of a Translator:.” 2009. Web. 22 Jan 2020.
Vancouver:
Schoneveld GJ. VHDL to SystemC: The Design of a Translator:. [Internet] [Masters thesis]. Delft University of Technology; 2009. [cited 2020 Jan 22].
Available from: http://resolver.tudelft.nl/uuid:f2ecf719-d8d4-4197-be07-1822e84f6968.
Council of Science Editors:
Schoneveld GJ. VHDL to SystemC: The Design of a Translator:. [Masters Thesis]. Delft University of Technology; 2009. Available from: http://resolver.tudelft.nl/uuid:f2ecf719-d8d4-4197-be07-1822e84f6968
Delft University of Technology
14.
Vielvoije, E.
SPIN's Promela to Java Compiler: with help from Stratego:.
Degree: Electrical Engineering, Mathematics and Computer Science, Computer Science, 2008, Delft University of Technology
URL: http://resolver.tudelft.nl/uuid:c7106f0b-5b8f-44fe-bca7-421653ec76c5
► In model checking a formal model of a software system is constructed. That model is verified against a set of properties expressed in some logic.…
(more)
▼ In model checking a formal model of a software system is constructed. That model is verified against a set of properties expressed in some logic. Once a model has been created and verified, it is still necessary to write the application itself completely by hand. No tools have yet been developed that can automatically create a system or application using a model written in Promela. ... until now! The Promela2Java
Compiler to be described in this paper is a unique tool transforming a Promela model into an executable Java application. The Promela2Java
Compiler has been constructed using the Stratego/XT tool set. Developers can use SPIN to check their designs for certain properties and use the Promela2Java
compiler to successfully create executable Java code from their designs.
Advisors/Committee Members: Pronk, C..
Subjects/Keywords: promela; java; compiler; stratego
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APA (6th Edition):
Vielvoije, E. (2008). SPIN's Promela to Java Compiler: with help from Stratego:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:c7106f0b-5b8f-44fe-bca7-421653ec76c5
Chicago Manual of Style (16th Edition):
Vielvoije, E. “SPIN's Promela to Java Compiler: with help from Stratego:.” 2008. Masters Thesis, Delft University of Technology. Accessed January 22, 2020.
http://resolver.tudelft.nl/uuid:c7106f0b-5b8f-44fe-bca7-421653ec76c5.
MLA Handbook (7th Edition):
Vielvoije, E. “SPIN's Promela to Java Compiler: with help from Stratego:.” 2008. Web. 22 Jan 2020.
Vancouver:
Vielvoije E. SPIN's Promela to Java Compiler: with help from Stratego:. [Internet] [Masters thesis]. Delft University of Technology; 2008. [cited 2020 Jan 22].
Available from: http://resolver.tudelft.nl/uuid:c7106f0b-5b8f-44fe-bca7-421653ec76c5.
Council of Science Editors:
Vielvoije E. SPIN's Promela to Java Compiler: with help from Stratego:. [Masters Thesis]. Delft University of Technology; 2008. Available from: http://resolver.tudelft.nl/uuid:c7106f0b-5b8f-44fe-bca7-421653ec76c5
University of Oregon
15.
Clauson, Aran.
Search-based Optimization for Compiler Machine-code Generation.
Degree: 2013, University of Oregon
URL: http://hdl.handle.net/1794/13433
► Compilation encompasses many steps. Parsing turns the input program into a more manageable syntax tree. Verification ensures that the program makes some semblance of sense.…
(more)
▼ Compilation encompasses many steps. Parsing turns the input program into a more manageable syntax tree. Verification ensures that the program makes some semblance of sense. Finally, code generation transforms the internal abstract program representation into an executable program. Compilers strive to produce the best possible programs. Optimizations are applied at nearly every level of compilation.
Instruction Scheduling is one of the last compilation tasks. It is part of code generation. Instruction Scheduling replaces the internal graph representation of the program with an instruction sequence. The scheduler should produce some sequence that the hardware can execute quickly. Considering that Instruction Scheduling is an NP-Complete optimization problem, it is interesting that schedules are usually generated by a greedy, heuristic algorithm called List Scheduling.
Given search-based algorithms' successes in other NP-Complete optimization domains, we ask whether search-based algorithms can be applied to Instruction Scheduling to generate superior schedules without unacceptably increasing compilation time.
To answer this question, we formulate a problem description that captures practical scheduling constraints. We show that this problem is NP-Complete given modest requirements on the actual hardware. We adapt three different search algorithms to Instruction Scheduling in order to show that search is an effective Instruction Scheduling technique. The schedules generated by our algorithms are generally shorter than those generated by List Scheduling. Search-based scheduling does take more time, but the increases are acceptable for some compilation domains.
Advisors/Committee Members: Wilson, Christopher (advisor).
Subjects/Keywords: Code-generation; Compiler; Search
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APA (6th Edition):
Clauson, A. (2013). Search-based Optimization for Compiler Machine-code Generation. (Thesis). University of Oregon. Retrieved from http://hdl.handle.net/1794/13433
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Clauson, Aran. “Search-based Optimization for Compiler Machine-code Generation.” 2013. Thesis, University of Oregon. Accessed January 22, 2020.
http://hdl.handle.net/1794/13433.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Clauson, Aran. “Search-based Optimization for Compiler Machine-code Generation.” 2013. Web. 22 Jan 2020.
Vancouver:
Clauson A. Search-based Optimization for Compiler Machine-code Generation. [Internet] [Thesis]. University of Oregon; 2013. [cited 2020 Jan 22].
Available from: http://hdl.handle.net/1794/13433.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Clauson A. Search-based Optimization for Compiler Machine-code Generation. [Thesis]. University of Oregon; 2013. Available from: http://hdl.handle.net/1794/13433
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Oklahoma State University
16.
Sundararajan, Gopalakrishnan.
Osuspram: Design of a Single Port Sram Compiler in Ncsu FreePDK45 Process.
Degree: School of Electrical & Computer Engineering, 2010, Oklahoma State University
URL: http://hdl.handle.net/11244/10280
► The main focus of this thesis is to design a Static Random Access Memory (SRAM) Compiler that could generate memories of required configurations. The layout…
(more)
▼ The main focus of this thesis is to design a Static Random Access Memory (SRAM) Compiler that could generate memories of required configurations. The layout designs are created using Cadence Virtuoso in NCSU FreePDK45 technology process and simulated using Synopsys Nanosim. Findings and Conclusions: A high speed embedded single port SRAM compiler has been realized in NCSU FreePDK45 Process technology. The simulation results of certain configurations are given and compared. The areas are calculated along with the access times. This compiler can generate the whole SRAM array including layout, LVS netlist, verilog model, LEF file and data-sheet.
Subjects/Keywords: compiler; freepdk45; memory; skill; sram
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APA (6th Edition):
Sundararajan, G. (2010). Osuspram: Design of a Single Port Sram Compiler in Ncsu FreePDK45 Process. (Thesis). Oklahoma State University. Retrieved from http://hdl.handle.net/11244/10280
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Sundararajan, Gopalakrishnan. “Osuspram: Design of a Single Port Sram Compiler in Ncsu FreePDK45 Process.” 2010. Thesis, Oklahoma State University. Accessed January 22, 2020.
http://hdl.handle.net/11244/10280.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Sundararajan, Gopalakrishnan. “Osuspram: Design of a Single Port Sram Compiler in Ncsu FreePDK45 Process.” 2010. Web. 22 Jan 2020.
Vancouver:
Sundararajan G. Osuspram: Design of a Single Port Sram Compiler in Ncsu FreePDK45 Process. [Internet] [Thesis]. Oklahoma State University; 2010. [cited 2020 Jan 22].
Available from: http://hdl.handle.net/11244/10280.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Sundararajan G. Osuspram: Design of a Single Port Sram Compiler in Ncsu FreePDK45 Process. [Thesis]. Oklahoma State University; 2010. Available from: http://hdl.handle.net/11244/10280
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
17.
Hebert, Chris.
Inferring Types to Eliminate Ownership Checks in an Intentional JavaScript Compiler.
Degree: MS, 2015, University of New Hampshire
URL: https://scholars.unh.edu/thesis/1021
► Concurrent programs are notoriously difficult to develop due to the non-deterministic nature of thread scheduling. It is desirable to have a programming language to make…
(more)
▼ Concurrent programs are notoriously difficult to develop due to the non-deterministic nature of thread scheduling. It is desirable to have a programming language to make such development easier. Tscript comprises such a system. Tscript is an extension of JavaScript that provides multithreading support along with intent specification. These intents allow a programmer to specify how parts of the program interact in a multithreaded context. However, enforcing intents requires run-time memory checks which can be inefficient. This thesis implements an optimization in the Tscript
compiler that seeks to improve this inefficiency through static analysis. Our approach utilizes both type inference and dataflow analysis to eliminate unnecessary run-time checks.
Advisors/Committee Members: Phil Hatcher, Michel Charpentier, Wheeler Ruml.
Subjects/Keywords: compiler; javascript; optimization; Computer science
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APA (6th Edition):
Hebert, C. (2015). Inferring Types to Eliminate Ownership Checks in an Intentional JavaScript Compiler. (Thesis). University of New Hampshire. Retrieved from https://scholars.unh.edu/thesis/1021
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Hebert, Chris. “Inferring Types to Eliminate Ownership Checks in an Intentional JavaScript Compiler.” 2015. Thesis, University of New Hampshire. Accessed January 22, 2020.
https://scholars.unh.edu/thesis/1021.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Hebert, Chris. “Inferring Types to Eliminate Ownership Checks in an Intentional JavaScript Compiler.” 2015. Web. 22 Jan 2020.
Vancouver:
Hebert C. Inferring Types to Eliminate Ownership Checks in an Intentional JavaScript Compiler. [Internet] [Thesis]. University of New Hampshire; 2015. [cited 2020 Jan 22].
Available from: https://scholars.unh.edu/thesis/1021.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Hebert C. Inferring Types to Eliminate Ownership Checks in an Intentional JavaScript Compiler. [Thesis]. University of New Hampshire; 2015. Available from: https://scholars.unh.edu/thesis/1021
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
University of Edinburgh
18.
Chandramohan, Kiran.
Mapping parallelism to heterogeneous processors.
Degree: PhD, 2016, University of Edinburgh
URL: http://hdl.handle.net/1842/22028
► Most embedded devices are based on heterogeneous Multiprocessor System on Chips (MPSoCs). These contain a variety of processors like CPUs, micro-controllers, DSPs, GPUs and specialised…
(more)
▼ Most embedded devices are based on heterogeneous Multiprocessor System on Chips (MPSoCs). These contain a variety of processors like CPUs, micro-controllers, DSPs, GPUs and specialised accelerators. The heterogeneity of these systems helps in achieving good performance and energy efficiency but makes programming inherently difficult. There is no single programming language or runtime to program such platforms. This thesis makes three contributions to these problems. First, it presents a framework that allows code in Single Program Multiple Data (SPMD) form to be mapped to a heterogeneous platform. The mapping space is explored, and it is shown that the best mapping depends on the metric used. Next, a compiler framework is presented which bridges the gap between the high -level programming model of OpenMP and the heterogeneous resources of MPSoCs. It takes OpenMP programs and generates code which runs on all processors. It delivers programming ease while exploiting heterogeneous resources. Finally, a compiler-based approach to runtime power management for heterogeneous cores is presented. Given an externally provided budget, the approach generates heterogeneous, partitioned code that attempts to give the best performance within that budget.
Subjects/Keywords: 004; heterogeneous processors; compiler
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APA (6th Edition):
Chandramohan, K. (2016). Mapping parallelism to heterogeneous processors. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/22028
Chicago Manual of Style (16th Edition):
Chandramohan, Kiran. “Mapping parallelism to heterogeneous processors.” 2016. Doctoral Dissertation, University of Edinburgh. Accessed January 22, 2020.
http://hdl.handle.net/1842/22028.
MLA Handbook (7th Edition):
Chandramohan, Kiran. “Mapping parallelism to heterogeneous processors.” 2016. Web. 22 Jan 2020.
Vancouver:
Chandramohan K. Mapping parallelism to heterogeneous processors. [Internet] [Doctoral dissertation]. University of Edinburgh; 2016. [cited 2020 Jan 22].
Available from: http://hdl.handle.net/1842/22028.
Council of Science Editors:
Chandramohan K. Mapping parallelism to heterogeneous processors. [Doctoral Dissertation]. University of Edinburgh; 2016. Available from: http://hdl.handle.net/1842/22028
University of New South Wales
19.
Ye, Ding.
Accelerating Dynamic Detection of Memory Errors for C Programs via Static Analysis.
Degree: Computer Science & Engineering, 2015, University of New South Wales
URL: http://handle.unsw.edu.au/1959.4/54507
;
https://unsworks.unsw.edu.au/fapi/datastream/unsworks:35127/SOURCE02?view=true
► Memory errors in C programs are the root causes of many defects and vulnerabilitiesin software engineering. Among the available error detection techniques,dynamic analysis is widely…
(more)
▼ Memory errors in C programs are the root causes of many defects and vulnerabilitiesin software engineering. Among the available error detection techniques,dynamic analysis is widely used in industries due to its high precision. Unfortunately,existing approaches su↵er from considerable runtime overheads, owing tounguided and overly conservative instrumentation. With the massive growth ofsoftware nowadays, such inefficiency prevents testing with comprehensive programinputs, leaving some input-specific memory errors undetected.This thesis presents novel techniques to address the efficiency problem by eliminatingsome unnecessary instrumentation guided by static analysis. Targeting twomajor types of memory errors, the research has developed two tools, Usher andWPBound, both implemented in the LLVM
compiler infrastructure, to acceleratethe dynamic detection.To facilitate efficient detection of undefined value uses, Usher infers the definednessof values using a value-flow graph that captures def-use information forboth top-level and address-taken variables interprocedurally, and removes unnecessaryinstrumentation by solving a graph reachability problem. Usher works wellwith any pointer analysis (done a priori) and enables advanced instrumentationreducingoptimizations.For efficient detection of spatial errors (e.g., bu↵er overflows), WPBound enhances the performance by reducing unnecessary bounds checks. The basic ideais to guard a bounds check at a memory access inside a loop, where the guard iscomputed outside the loop based on the notion of weakest precondition. The falsehoodof the guard implies the absence of out-of-bounds errors at the dereference,thereby avoiding the corresponding bounds check inside the loop.For each tool, this thesis presents the methodology and evaluates the implementationwith a set of C benchmarks. Their e↵ectiveness is demonstrated withsignificant speedups over the state-of-the-art tools.
Advisors/Committee Members: Xue, Jingling, Computer Science & Engineering, Faculty of Engineering, UNSW.
Subjects/Keywords: C programs; LLVM Compiler architecture
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APA (6th Edition):
Ye, D. (2015). Accelerating Dynamic Detection of Memory Errors for C Programs via Static Analysis. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/54507 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:35127/SOURCE02?view=true
Chicago Manual of Style (16th Edition):
Ye, Ding. “Accelerating Dynamic Detection of Memory Errors for C Programs via Static Analysis.” 2015. Doctoral Dissertation, University of New South Wales. Accessed January 22, 2020.
http://handle.unsw.edu.au/1959.4/54507 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:35127/SOURCE02?view=true.
MLA Handbook (7th Edition):
Ye, Ding. “Accelerating Dynamic Detection of Memory Errors for C Programs via Static Analysis.” 2015. Web. 22 Jan 2020.
Vancouver:
Ye D. Accelerating Dynamic Detection of Memory Errors for C Programs via Static Analysis. [Internet] [Doctoral dissertation]. University of New South Wales; 2015. [cited 2020 Jan 22].
Available from: http://handle.unsw.edu.au/1959.4/54507 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:35127/SOURCE02?view=true.
Council of Science Editors:
Ye D. Accelerating Dynamic Detection of Memory Errors for C Programs via Static Analysis. [Doctoral Dissertation]. University of New South Wales; 2015. Available from: http://handle.unsw.edu.au/1959.4/54507 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:35127/SOURCE02?view=true
University of New South Wales
20.
Sewell, Thomas.
Translation validation for verified, efficient and timely operating systems.
Degree: Computer Science & Engineering, 2017, University of New South Wales
URL: http://handle.unsw.edu.au/1959.4/58861
;
https://unsworks.unsw.edu.au/fapi/datastream/unsworks:47819/SOURCE02?view=true
► Computer software is typically written in one language and then translatedout of that language into the native binary languages of the machines thesoftware will run…
(more)
▼ Computer software is typically written in one language and then translatedout of that language into the native binary languages of the machines thesoftware will run on. Most operating systems, for instance, are written in thelow-level language C and translated by a C
compiler. Translationvalidation is the act of checking that this translation is correct. Thisdissertation presents an approach and framework for validating the translationof C programs, and three experiments which test the approach. Our validation approach consists of three components, a frontend, a backend anda core, which broadly mirrors the design of the C
compiler. The threeexperiments in this dissertation exercise these three components. Each of thesecomponents produces a formal proof of refinement, and theserefinement proofs compose to produce a proof that the binary is a refinement ofthe source semantics. This notion of refinement can then compose withcorrectness proofs for a C program, resulting in a verified binary.Throughout this work, our case study of interest will be the seL4 verifiedoperating system kernel, compiled for the ARM instruction-set architecture, forwhich we will produce a verified efficient binary.The thesis of this work is that our translation validation approachoffers us great flexibility. We can quickly produce verified binariesproduced via many complex transformations without specifically addressing eachsuch transformation. We can adapt our frontend to handle low-level source codewhich does not strictly respect the rules of the C language it is written in.We can also retarget our backend to address important timing concerns as wellas correctness ones.
Advisors/Committee Members: Klein, Gerwin, Computer Science & Engineering, Faculty of Engineering, UNSW, Keller, Gabriele, Computer Science & Engineering, Faculty of Engineering, UNSW.
Subjects/Keywords: Compiler; Translation Validation; Operating System
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APA (6th Edition):
Sewell, T. (2017). Translation validation for verified, efficient and timely operating systems. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/58861 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:47819/SOURCE02?view=true
Chicago Manual of Style (16th Edition):
Sewell, Thomas. “Translation validation for verified, efficient and timely operating systems.” 2017. Doctoral Dissertation, University of New South Wales. Accessed January 22, 2020.
http://handle.unsw.edu.au/1959.4/58861 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:47819/SOURCE02?view=true.
MLA Handbook (7th Edition):
Sewell, Thomas. “Translation validation for verified, efficient and timely operating systems.” 2017. Web. 22 Jan 2020.
Vancouver:
Sewell T. Translation validation for verified, efficient and timely operating systems. [Internet] [Doctoral dissertation]. University of New South Wales; 2017. [cited 2020 Jan 22].
Available from: http://handle.unsw.edu.au/1959.4/58861 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:47819/SOURCE02?view=true.
Council of Science Editors:
Sewell T. Translation validation for verified, efficient and timely operating systems. [Doctoral Dissertation]. University of New South Wales; 2017. Available from: http://handle.unsw.edu.au/1959.4/58861 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:47819/SOURCE02?view=true
Georgia Tech
21.
Gupta, Meghana.
Code generation and adaptive control divergence management for light weight SIMT processors.
Degree: MS, Computer Science, 2016, Georgia Tech
URL: http://hdl.handle.net/1853/55044
► The energy costs of data movement are limiting the performance scaling of future generations of high performance computing architectures targeted to data intensive applications. The…
(more)
▼ The energy costs of data movement are limiting the performance scaling of future generations of high performance computing architectures targeted to data intensive applications. The result has been a resurgence in the interest in processing-in-memory (PIM) architectures. This challenge has spawned the development of a scalable, parametric data parallel architecture referred at the Heterogeneous Architecture Research Prototype (HARP) - a single instruction multiple thread (SIMT) architecture for integration into DRAM systems, particularly 3D memory stacks as a distinct processing layer to exploit the enormous internal memory bandwidth. However, this potential can only be realized with an optimizing compilation environment. This thesis addresses this challenge by i) the construction of an open source
compiler for HARP, and ii) integrating optimizations for handling control flow divergence for HARP instances. The HARP
compiler is built using the LLVM open source
compiler infrastructure. Apart from traditional code generation, the HARP
compiler backend handles unique challenges associated with the HARP instruction set. Chief among them is code generation for control divergence management techniques. The HARP architecture and
compiler supports i) a hardware reconvergence stack and ii) predication to handle divergent branches. The HARP
compiler addresses several challenges associated with generating code for these two control divergence management techniques and implements multiple analyses and transformations for code generation. Both of these techniques have unique advantages and disadvantages depending upon whether the conditional branch is likely to be unanimous or not. Two decision frameworks, guided by static analysis and dynamic profile information are implemented to choose between the control divergence management techniques by analyzing the nature of the conditional branches and utilizing this information during compilation.
Advisors/Committee Members: Yalamanchili, Sudhakar (advisor), Kim, Hyesoon (committee member), Pande, Santosh (committee member).
Subjects/Keywords: Compiler; SIMT; Control divergence
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APA (6th Edition):
Gupta, M. (2016). Code generation and adaptive control divergence management for light weight SIMT processors. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55044
Chicago Manual of Style (16th Edition):
Gupta, Meghana. “Code generation and adaptive control divergence management for light weight SIMT processors.” 2016. Masters Thesis, Georgia Tech. Accessed January 22, 2020.
http://hdl.handle.net/1853/55044.
MLA Handbook (7th Edition):
Gupta, Meghana. “Code generation and adaptive control divergence management for light weight SIMT processors.” 2016. Web. 22 Jan 2020.
Vancouver:
Gupta M. Code generation and adaptive control divergence management for light weight SIMT processors. [Internet] [Masters thesis]. Georgia Tech; 2016. [cited 2020 Jan 22].
Available from: http://hdl.handle.net/1853/55044.
Council of Science Editors:
Gupta M. Code generation and adaptive control divergence management for light weight SIMT processors. [Masters Thesis]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/55044
NSYSU
22.
HSU, CHUN-TO.
Implementations and Automatic Synthesis of Programmable Logic Array (PLA) ROM.
Degree: Master, Computer Science and Engineering, 2014, NSYSU
URL: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726114-101438
► Read-only memory (ROM) plays an important role In modern System-on-Chip (SoC) designs. Due to the regularity of ROM structure, ROM components are usually generated through…
(more)
▼ Read-only memory (ROM) plays an important role In modern System-on-Chip (SoC) designs. Due to the regularity of ROM structure, ROM components are usually generated through automatic ROM
compiler/generator. For example, ARM TSMC cell library provides ROM
compiler to automatic synthesize ROM of arbitrary size. In general, there are two different types of ROM implementations, conventional ROM structure or programmable logic array (PLA). For the implementation with the conventional ROM structure, we adopt the dynamic NAND-based circuit design with multi-level decoder to reduce the area cost. Regarding PLA-based implementation, the dynamic NOR-NOR structure is used where the logic optimization of product terms is performed using the Espresso logic minimization tool.We develop automatic ROM generators for both ROM structures and make comparison with those obtained from ARM ROM
compiler and those directly synthesized from combination logic using Synopsys RTL (Register Transfer Level) Design
Compiler. Based on the extensive comparisons of area, delay and power for ROM in various sizes, we make several interesting observations, and try to improve our ROM generators in order to make them more competitive for synthesis of large ROM size.
Advisors/Committee Members: Shiann-Rong Kuang (chair), Shen-Fu Hsiao. (committee member), Chuen-Yau Chen (chair), Jih-ching Chiu (chair), Ming-Chin Chen (chair).
Subjects/Keywords: RTL Compiler; ROM generator; Programmable Logic Array (PLA); ROM Compiler
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APA (6th Edition):
HSU, C. (2014). Implementations and Automatic Synthesis of Programmable Logic Array (PLA) ROM. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726114-101438
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
HSU, CHUN-TO. “Implementations and Automatic Synthesis of Programmable Logic Array (PLA) ROM.” 2014. Thesis, NSYSU. Accessed January 22, 2020.
http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726114-101438.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
HSU, CHUN-TO. “Implementations and Automatic Synthesis of Programmable Logic Array (PLA) ROM.” 2014. Web. 22 Jan 2020.
Vancouver:
HSU C. Implementations and Automatic Synthesis of Programmable Logic Array (PLA) ROM. [Internet] [Thesis]. NSYSU; 2014. [cited 2020 Jan 22].
Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726114-101438.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
HSU C. Implementations and Automatic Synthesis of Programmable Logic Array (PLA) ROM. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726114-101438
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Brno University of Technology
23.
Horník, Jakub.
Zadní část překladače podmnožiny jazyka C pro 8-bitový procesor
.
Degree: 2011, Brno University of Technology
URL: http://hdl.handle.net/11012/54208
► Překladač umožňuje programátorovi popisovat algoritmus ve vysokoúrovňovém programovacím jazyce s vyšší mírou abstrakce a strukturovaností, než poskytuje nízkoúrovňový strojový kód. Tato práce se týká návrhu…
(more)
▼ Překladač umožňuje programátorovi popisovat algoritmus ve vysokoúrovňovém programovacím jazyce s vyšší mírou abstrakce a strukturovaností, než poskytuje nízkoúrovňový strojový kód. Tato práce se týká návrhu zadní části překladače podmnožiny jazyka C pro 8bitový procesor Xilinx PicoBlaze-3, který je zde popsán od počátečního výběru vhodné přední části, návrhu architektury, až po samotnou implementaci. Jedním z důvodů této práce je, že není k dispozici uspokojující překladač pro tento procesor.; A
compiler allows us to describe an algorithm in a high-level programming language with a higher level of abstraction and readability than a low-level machine code. This work describes design of the
compiler back-end of subset of language C for 8-bit soft-core microcontroller Xilinx PicoBlaze-3. Design is described from the initial selection of a suitable framework to the implementation itself. One of the main reasons of this work is that there is not any suitable
compiler for this processor.
Advisors/Committee Members: Křivka, Zbyněk (advisor).
Subjects/Keywords: kompilátor;
Low Level Virtual Machine Compiler;
mezikód;
překladač;
PicoBlaze;
PicoBlaze C Compiler;
Small Device C Compiler;
zadní část překladače;
back-end;
compiler;
intermediate code;
Low Level Virtual Machine Compiler;
PicoBlaze;
PicoBlaze C Compiler;
Small Device C Compiler
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APA ·
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MLA ·
Vancouver ·
CSE |
Export
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Manager
APA (6th Edition):
Horník, J. (2011). Zadní část překladače podmnožiny jazyka C pro 8-bitový procesor
. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/54208
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Chicago Manual of Style (16th Edition):
Horník, Jakub. “Zadní část překladače podmnožiny jazyka C pro 8-bitový procesor
.” 2011. Thesis, Brno University of Technology. Accessed January 22, 2020.
http://hdl.handle.net/11012/54208.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
MLA Handbook (7th Edition):
Horník, Jakub. “Zadní část překladače podmnožiny jazyka C pro 8-bitový procesor
.” 2011. Web. 22 Jan 2020.
Vancouver:
Horník J. Zadní část překladače podmnožiny jazyka C pro 8-bitový procesor
. [Internet] [Thesis]. Brno University of Technology; 2011. [cited 2020 Jan 22].
Available from: http://hdl.handle.net/11012/54208.
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
Council of Science Editors:
Horník J. Zadní část překladače podmnožiny jazyka C pro 8-bitový procesor
. [Thesis]. Brno University of Technology; 2011. Available from: http://hdl.handle.net/11012/54208
Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation
University of Utah
24.
Pagariya, Rohit.
Direct equivalence testing of embedded software.
Degree: MS, School of Computing, 2011, University of Utah
URL: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/48/rec/740
► Direct equivalence testing is a framework for detecting errors in C compilers and application programs that exploits the fact that program semantics should be preserved…
(more)
▼ Direct equivalence testing is a framework for detecting errors in C compilers and application programs that exploits the fact that program semantics should be preserved during the compilation process. Binaries generated from the same piece of code should remain equivalent irrespective of the compiler, or compiler optimizations, used. Compiler errors as well as program errors such as out of bounds memory access, stack over ow, and use of uninitialized local variables cause nonequivalence in the generated binaries. Direct equivalence testing has detected previously unknown errors in real world embedded software like TinyOS and in di fferent compilers like msp430-gcc and llvm-msp430.
Subjects/Keywords: Compiler testing; Embedded software; Equivalence testing; Verification
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APA ·
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APA (6th Edition):
Pagariya, R. (2011). Direct equivalence testing of embedded software. (Masters Thesis). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/48/rec/740
Chicago Manual of Style (16th Edition):
Pagariya, Rohit. “Direct equivalence testing of embedded software.” 2011. Masters Thesis, University of Utah. Accessed January 22, 2020.
http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/48/rec/740.
MLA Handbook (7th Edition):
Pagariya, Rohit. “Direct equivalence testing of embedded software.” 2011. Web. 22 Jan 2020.
Vancouver:
Pagariya R. Direct equivalence testing of embedded software. [Internet] [Masters thesis]. University of Utah; 2011. [cited 2020 Jan 22].
Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/48/rec/740.
Council of Science Editors:
Pagariya R. Direct equivalence testing of embedded software. [Masters Thesis]. University of Utah; 2011. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/48/rec/740
University of Edinburgh
25.
Tournavitis, Georgios.
Profile-driven parallelisation of sequential programs.
Degree: 2011, University of Edinburgh
URL: http://hdl.handle.net/1842/5287
► Traditional parallelism detection in compilers is performed by means of static analysis and more specifically data and control dependence analysis. The information that is available…
(more)
▼ Traditional parallelism detection in compilers is performed by means of static analysis and more specifically data and control dependence analysis. The information that is available at compile time, however, is inherently limited and therefore restricts the parallelisation opportunities. Furthermore, applications written in C – which represent the majority of today’s scientific, embedded and system software – utilise many lowlevel features and an intricate programming style that forces the compiler to even more conservative assumptions. Despite the numerous proposals to handle this uncertainty at compile time using speculative optimisation and parallelisation, the software industry still lacks any pragmatic approaches that extracts coarse-grain parallelism to exploit the multiple processing units of modern commodity hardware. This thesis introduces a novel approach for extracting and exploiting multiple forms of coarse-grain parallelism from sequential applications written in C. We utilise profiling information to overcome the limitations of static data and control-flow analysis enabling more aggressive parallelisation. Profiling is performed using an instrumentation scheme operating at the Intermediate Representation (Ir) level of the compiler. In contrast to existing approaches that depend on low-level binary tools and debugging information, Ir-profiling provides precise and direct correlation of profiling information back to the Ir structures of the compiler. Additionally, our approach is orthogonal to existing automatic parallelisation approaches and additional fine-grain parallelism may be exploited. We demonstrate the applicability and versatility of the proposed methodology using two studies that target different forms of parallelism. First, we focus on the exploitation of loop-level parallelism that is abundant in many scientific and embedded applications. We evaluate our parallelisation strategy against the Nas and Spec Fp benchmarks and two different multi-core platforms (a shared-memory Intel Xeon Smp and a heterogeneous distributed-memory Ibm Cell blade). Empirical evaluation shows that our approach not only yields significant improvements when compared with state-of- the-art parallelising compilers, but comes close to and sometimes exceeds the performance of manually parallelised codes. On average, our methodology achieves 96% of the performance of the hand-tuned parallel benchmarks on the Intel Xeon platform, and a significant speedup for the Cell platform. The second study, addresses the problem of partially sequential loops, typically found in implementations of multimedia codecs. We develop a more powerful whole-program representation based on the Program Dependence Graph (Pdg) that supports profiling, partitioning and codegeneration for pipeline parallelism. In addition we demonstrate how this enhances conventional pipeline parallelisation by incorporating support for multi-level loops and pipeline stage replication in a uniform and automatic way. Experimental results using a set of complex…
Subjects/Keywords: 005.3; compiler; multi-core; parallelisation; pipeline
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APA ·
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MLA ·
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CSE |
Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Tournavitis, G. (2011). Profile-driven parallelisation of sequential programs. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/5287
Chicago Manual of Style (16th Edition):
Tournavitis, Georgios. “Profile-driven parallelisation of sequential programs.” 2011. Doctoral Dissertation, University of Edinburgh. Accessed January 22, 2020.
http://hdl.handle.net/1842/5287.
MLA Handbook (7th Edition):
Tournavitis, Georgios. “Profile-driven parallelisation of sequential programs.” 2011. Web. 22 Jan 2020.
Vancouver:
Tournavitis G. Profile-driven parallelisation of sequential programs. [Internet] [Doctoral dissertation]. University of Edinburgh; 2011. [cited 2020 Jan 22].
Available from: http://hdl.handle.net/1842/5287.
Council of Science Editors:
Tournavitis G. Profile-driven parallelisation of sequential programs. [Doctoral Dissertation]. University of Edinburgh; 2011. Available from: http://hdl.handle.net/1842/5287
University of New Mexico
26.
Mohr, David.
Stella: A Python-based Domain-Specific Language for Simulations.
Degree: Department of Computer Science, 2015, University of New Mexico
URL: http://hdl.handle.net/1928/31733
► Stella is a domain-specific language that (1) has single thread performance competitive with low-level languages, (2) supports object-oriented programming (OOP) to properly structure the code,…
(more)
▼ Stella is a domain-specific language that (1) has single thread performance competitive with low-level languages, (2) supports object-oriented programming (OOP) to properly structure the code, and (3) is very easy to use. Instead of prototyping in a high-level language and then rewriting in a lower-level language, Stella is embedded in Python, is transparently usable, retains some OOP features, compiles to machine code, and executes at speed similar to C. Stella's source code is compatible with Python, and allows easy integration of C libraries. Its features are focused on the needs of scientific simulations. Other projects to speed up Python focus on easy integration, and smaller critical sections. In contrast, Stella supports translating larger programs in their entirety, and does not allow interaction with the Python run-time, to ensure predictable performance. My experience developing Stella shows that by carefully selecting language features, high run-time performance can be achieved in a high-level language that has in practice very few restrictions.
Advisors/Committee Members: Stefanovic, Darko, Hermenegildo, Manuel, Tapia, Lydia, Lakin, Matthew.
Subjects/Keywords: python; domain specific language; simulation; compiler
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APA (6th Edition):
Mohr, D. (2015). Stella: A Python-based Domain-Specific Language for Simulations. (Doctoral Dissertation). University of New Mexico. Retrieved from http://hdl.handle.net/1928/31733
Chicago Manual of Style (16th Edition):
Mohr, David. “Stella: A Python-based Domain-Specific Language for Simulations.” 2015. Doctoral Dissertation, University of New Mexico. Accessed January 22, 2020.
http://hdl.handle.net/1928/31733.
MLA Handbook (7th Edition):
Mohr, David. “Stella: A Python-based Domain-Specific Language for Simulations.” 2015. Web. 22 Jan 2020.
Vancouver:
Mohr D. Stella: A Python-based Domain-Specific Language for Simulations. [Internet] [Doctoral dissertation]. University of New Mexico; 2015. [cited 2020 Jan 22].
Available from: http://hdl.handle.net/1928/31733.
Council of Science Editors:
Mohr D. Stella: A Python-based Domain-Specific Language for Simulations. [Doctoral Dissertation]. University of New Mexico; 2015. Available from: http://hdl.handle.net/1928/31733
University of Delaware
27.
Vanderbruggen, Tristan.
Application of deep-learning to compiler-based graphs
.
Degree: 2018, University of Delaware
URL: http://udspace.udel.edu/handle/19716/23587
► Graph-structured data is used in many domains to represent complex objects, such as the molecular structure of chemicals or interactions between members of a social…
(more)
▼ Graph-structured data is used in many domains to represent complex objects, such as the molecular structure of chemicals or interactions between members of a social network. However, extracting meaningful information from these graphs is a difficult task, which is often undertaken on a case by case basis. Devising automated methods to mine information from graphs has become increasingly important as the use of graphs becomes more prevalent. Techniques have been developed that adapt algorithms, like support vector machine, to extract information from graphs with minimal preprocessing. Unfortunately, none of these techniques permit the use of deep neural networks (DNNs) to learn from graphs. Given the potential of DNNs to learn from large amounts of data, this has become an important area of interest. Recently, a technique based on graph spectral analysis was proposed to characterize graphs in a way that allows them to be used as input by DNNs. ☐ We used this technique to apply DNNs to two different systems problems, i.e., 1) classifying malicious applications based on graph-structured representations of executable code and 2) developing prediction models that assist in iterative compilation to optimize and parallelize scientific code. Our results on malicious application classification show that graph-based characterizations increase the ability of DNN to distinguish malware from different families. We performed a detailed evaluation of deep learning applied to state-of-the-art and graph-based malware characterizations. The graph-based characterizations are obtained by reverse engineering potentially malicious applications. For performance prediction, the graphs represent versions of optimized code. We use machine learning to rank these versions and inform an iterative compilation process. The models are trained using only five percent of the search space. ☐ Our work shows that graph structured data can be used to build powerful deep learning models. The techniques developed for this dissertation shows great potential in a diverse pair of systems.
Subjects/Keywords: Applied sciences;
Compiler;
GPGPU;
Graph;
Neural network
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APA ·
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Export
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APA (6th Edition):
Vanderbruggen, T. (2018). Application of deep-learning to compiler-based graphs
. (Doctoral Dissertation). University of Delaware. Retrieved from http://udspace.udel.edu/handle/19716/23587
Chicago Manual of Style (16th Edition):
Vanderbruggen, Tristan. “Application of deep-learning to compiler-based graphs
.” 2018. Doctoral Dissertation, University of Delaware. Accessed January 22, 2020.
http://udspace.udel.edu/handle/19716/23587.
MLA Handbook (7th Edition):
Vanderbruggen, Tristan. “Application of deep-learning to compiler-based graphs
.” 2018. Web. 22 Jan 2020.
Vancouver:
Vanderbruggen T. Application of deep-learning to compiler-based graphs
. [Internet] [Doctoral dissertation]. University of Delaware; 2018. [cited 2020 Jan 22].
Available from: http://udspace.udel.edu/handle/19716/23587.
Council of Science Editors:
Vanderbruggen T. Application of deep-learning to compiler-based graphs
. [Doctoral Dissertation]. University of Delaware; 2018. Available from: http://udspace.udel.edu/handle/19716/23587
University of Southern California
28.
Nelson, Yoonju Lee.
Model-guided performance tuning for application-level
parameters.
Degree: PhD, Computer Science, 2009, University of Southern California
URL: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/405965/rec/4114
► The enormous and growing complexity of today's high-end systems has increased the already significant challenge of maximizing performance on today's equally complex scientific applications. In…
(more)
▼ The enormous and growing complexity of today's
high-end systems has increased the already significant challenge of
maximizing performance on today's equally complex scientific
applications. In this research, we address the question of how
application programmers can interface with tools and automatically
search a space of application-level parameters that are believed to
significantly impact the performance of an application. We begin
with applications for which a programmer has identified a set of
integer-valued parameters believed to impact the performance of the
application significantly.; We explore two techniques for modeling
performance sensitivity of application-level parameters. First, we
propose qualitative parameter models that capture common behaviors
of an optimization parameter, and use high-level
programmer-specified models of the expected performance behavior of
individual parameters. A second modeling technique uses statistical
methods on a small sample of parameter values to derive a
functional model, and to dynamically identify the neighborhood of
the best-performing result. By capitalizing on properties of these
models, we develop search algorithms to prune the multi-variate
search space for the collection of parameters associated with an
application.; We study performance tuning of three large scientific
applications: the LS-DYNA Solver, the visualization component of
molecular dynamics simulation, and warping component of biomedical
image analysis. We validate our models by comparing against
performance results from an exhaustive set of experiments across
the parameter range. When compared with the exhaustive experimental
data, we show that we are able to drastically reduce search time,
examining an average of less than 5% of the search space. Our
experimental results show speedups of up to 12.83X as compared to
the worst-case in user-given parameter ranges, and speedups of up
to 1.75X as compared to the user default parameter value.; To
support model-guided performance tuning, we have developed a tool
called a code isolator. Its purpose is to extract a key computation
from the application and creates an executable program, including
representative input data. To derive an isolated code fragment that
uses storage efficiently and has similar memory hierarchy behavior
to the original computation, we develop
compiler and runtime
optimizations to limit the input data and number of parameters as
well as to warm up the cache state. We applied this tool to two
case study applications, UMT2K and the LS-DYNA Solver, reducing
their size and execution time by several orders of magnitude.; In
considering the burden of achieving high performance for developers
of current scientific and engineering applications on complex
high-end computing platforms, model-guided performance tuning is a
feasible and useful tool for finding the best-performing
application-level parameters.
Advisors/Committee Members: Hall, Mary W. (Committee Chair), Nakano, Aiichiro (Committee Member), Lerman, Kristina (Committee Member), Lucas, Robert F. (Committee Member), Prasanna, Viktor K. (Committee Member).
Subjects/Keywords: performance tuning; empirical optimization; compiler technique
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APA (6th Edition):
Nelson, Y. L. (2009). Model-guided performance tuning for application-level
parameters. (Doctoral Dissertation). University of Southern California. Retrieved from http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/405965/rec/4114
Chicago Manual of Style (16th Edition):
Nelson, Yoonju Lee. “Model-guided performance tuning for application-level
parameters.” 2009. Doctoral Dissertation, University of Southern California. Accessed January 22, 2020.
http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/405965/rec/4114.
MLA Handbook (7th Edition):
Nelson, Yoonju Lee. “Model-guided performance tuning for application-level
parameters.” 2009. Web. 22 Jan 2020.
Vancouver:
Nelson YL. Model-guided performance tuning for application-level
parameters. [Internet] [Doctoral dissertation]. University of Southern California; 2009. [cited 2020 Jan 22].
Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/405965/rec/4114.
Council of Science Editors:
Nelson YL. Model-guided performance tuning for application-level
parameters. [Doctoral Dissertation]. University of Southern California; 2009. Available from: http://digitallibrary.usc.edu/cdm/compoundobject/collection/p15799coll127/id/405965/rec/4114
Penn State University
29.
Ding, Wei.
A Fresh Look At Data Locality On Emerging Multicores And
Manycores.
Degree: PhD, Computer Science and Engineering, 2014, Penn State University
URL: https://etda.libraries.psu.edu/catalog/22506
► The emergence of multicore platforms offers several opportunities for boosting ap- plication performance. These opportunities, which include parallelism and data locality benefits, require strong support…
(more)
▼ The emergence of multicore platforms offers several
opportunities for boosting ap- plication performance. These
opportunities, which include parallelism and data locality
benefits, require strong support from compilers as well as
operating sys- tems. However, architectural abstractions relevant
to memory system are scarce in current programming and compiler
systems. In fact, most compilers do not take any memory system
specific parameter into account even when they are perform- ing
data locality optimizations. Instead, their locality optimizations
are driven by rule-of-thumbs such as “maximizing stride-1 accesses
in innermost loop positions”. There are a few compilers that take
cache and memory specific parameters into account to look at the
data locality problem in a global sense. One of these parameters is
the on-chip cache hierarchy, which determines the core connection
and thus data sharing between computations on different cores.
Another parameter is the memory controller. In a network-on-chip
(NoC) based multicore architecture, an off-chip data access (main
memory access) needs to travel through the on-chip network,
spending considerable amount of time within the chip (in addition
to the memory access latency). In addition, it contends with
on-chip (cache) accesses as both use the same NoC resources. The
third parameter that will be discussed in this thesis is the
row-buffer. Many emerging multicores employ banked memory systems
and each bank is attached a row-buffer that holds the most-recently
accessed memory row (page). A last-level cache miss that also
misses in the row-buffer can experience much higher latency than a
cache miss that hits in the row-buffer. Consequently, optimizing
for row-buffer locality can be as important as optimizing for cache
locality. Motivated by this, in this thesis, we propose four
different compiler-directed “ locality” optimization schemes that
take these parameters into account. Specifi- cally, our first
scheme targets cache hierarchy-aware loop transformation strategy
for multicore architectures. It determines a loop iteration-to-core
mapping by iii taking into account application data access pattern
and multicore on-chip cache hierarchy. It employs “core vectors” to
exploit data reuses at different layers of cache hierarchy based on
their reuse distances, with the goal of maximizing data lo- cality
at each level while minimizing the data dependences across the
cores. In case of dependence free loop nest, we customize our loop
scheduling strategy, which, on the other hand, determines a
schedule for the iterations assigned to each core, with the goal of
reducing data reuse distances across the cores. Our experimental
evaluation shows that the proposed loop transformation scheme
reduces miss rates at all levels of caches and application
execution time significantly, and when sup- ported by scheduling,
the reduction in cache miss rates and execution time become much
larger. The second scheme explores automatic data layout
transformation targeting multithreaded applications…
Subjects/Keywords: Data Locality; Multicore; Manycore; Compiler;
Loop
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APA ·
Chicago ·
MLA ·
Vancouver ·
CSE |
Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Ding, W. (2014). A Fresh Look At Data Locality On Emerging Multicores And
Manycores. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/22506
Chicago Manual of Style (16th Edition):
Ding, Wei. “A Fresh Look At Data Locality On Emerging Multicores And
Manycores.” 2014. Doctoral Dissertation, Penn State University. Accessed January 22, 2020.
https://etda.libraries.psu.edu/catalog/22506.
MLA Handbook (7th Edition):
Ding, Wei. “A Fresh Look At Data Locality On Emerging Multicores And
Manycores.” 2014. Web. 22 Jan 2020.
Vancouver:
Ding W. A Fresh Look At Data Locality On Emerging Multicores And
Manycores. [Internet] [Doctoral dissertation]. Penn State University; 2014. [cited 2020 Jan 22].
Available from: https://etda.libraries.psu.edu/catalog/22506.
Council of Science Editors:
Ding W. A Fresh Look At Data Locality On Emerging Multicores And
Manycores. [Doctoral Dissertation]. Penn State University; 2014. Available from: https://etda.libraries.psu.edu/catalog/22506
Louisiana State University
30.
Gilkey, Ronald William.
Object protocols as a tool for debugging method call sequencing constraints.
Degree: MSCS, Computer Sciences, 2012, Louisiana State University
URL: etd-04262012-101634
;
https://digitalcommons.lsu.edu/gradschool_theses/3948
► Clearly conveying and enforcing the proper ordering of method calls on objects has become a common problem among developers and interface designers. Without the ability…
(more)
▼ Clearly conveying and enforcing the proper ordering of method calls on objects has become a common problem among developers and interface designers. Without the ability of the compilation environment to enforce these constraints, programmers must rely on clear documentation being provided and diligence in programming to ensure that a proper sequence of operations is performed. Commonly, though, type-checking becomes the only tool to help support the correctness of operation sequences as API documentation rarely describes inter-object communications. Thus, the likeliness of producing erroneous and buggy software increases. Object protocols provide a simple and straight-forward approach to solving this problem. They do so by providing simple grammatical constructs for expressing valid call sequences on objects. These constructs can be parsed by a compiler and then used for conformance analysis on subclasses and objects that implement interfaces. Once parsing is complete, the compiler will implement code in the target binaries for run-time enforcement of sequencing constraints. This thesis builds upon the foundation provided by Butkevich et al. to provide the design of a comprehensive tool for utilizing object protocols within the Java compilation and runtime environments. In addition to the existing work, we provide language constructs that allow the enforcement of object protocols on classes and the designation of objects and interfaces to be traced programmatically. We will consider the problems that are introduced when protocols are enforced upon classes and discuss the strategy for resolving these issues. We present the results of testing the object tracing framework to determine the impact of protocols on the performance of software. Baseline timings are drawn on the operations of data types and then protocols are manually added to the code in the same manner that would be done by the compiler in a fully working implementation; including the implementation of the tracing framework. We show that the overhead introduced is minimal, making the run-time monitoring of protocols practical. Along with support for basic sequencing constraints, we also show how other constraints, such as timing constraints, can be added to the framework with minimal adjustments. Such applications of constraints can help debug different environments, such as embedded, real-time, and near real-time environments.
Subjects/Keywords: object protocols; java; compiler; sequencing constraints
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APA ·
Chicago ·
MLA ·
Vancouver ·
CSE |
Export
to Zotero / EndNote / Reference
Manager
APA (6th Edition):
Gilkey, R. W. (2012). Object protocols as a tool for debugging method call sequencing constraints. (Masters Thesis). Louisiana State University. Retrieved from etd-04262012-101634 ; https://digitalcommons.lsu.edu/gradschool_theses/3948
Chicago Manual of Style (16th Edition):
Gilkey, Ronald William. “Object protocols as a tool for debugging method call sequencing constraints.” 2012. Masters Thesis, Louisiana State University. Accessed January 22, 2020.
etd-04262012-101634 ; https://digitalcommons.lsu.edu/gradschool_theses/3948.
MLA Handbook (7th Edition):
Gilkey, Ronald William. “Object protocols as a tool for debugging method call sequencing constraints.” 2012. Web. 22 Jan 2020.
Vancouver:
Gilkey RW. Object protocols as a tool for debugging method call sequencing constraints. [Internet] [Masters thesis]. Louisiana State University; 2012. [cited 2020 Jan 22].
Available from: etd-04262012-101634 ; https://digitalcommons.lsu.edu/gradschool_theses/3948.
Council of Science Editors:
Gilkey RW. Object protocols as a tool for debugging method call sequencing constraints. [Masters Thesis]. Louisiana State University; 2012. Available from: etd-04262012-101634 ; https://digitalcommons.lsu.edu/gradschool_theses/3948
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