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You searched for subject:(compiler). Showing records 1 – 30 of 564 total matches.

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University of Waterloo

1. Selby, Jason W. A. Unconventional Applications of Compiler Analysis.

Degree: 2011, University of Waterloo

 Previously, compiler transformations have primarily focused on minimizing program execution time. This thesis explores some examples of applying compiler technology outside of its original scope.… (more)

Subjects/Keywords: Compiler Analysis; Compiler Optimization

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APA (6th Edition):

Selby, J. W. A. (2011). Unconventional Applications of Compiler Analysis. (Thesis). University of Waterloo. Retrieved from http://hdl.handle.net/10012/6184

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Selby, Jason W A. “Unconventional Applications of Compiler Analysis.” 2011. Thesis, University of Waterloo. Accessed April 18, 2021. http://hdl.handle.net/10012/6184.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Selby, Jason W A. “Unconventional Applications of Compiler Analysis.” 2011. Web. 18 Apr 2021.

Vancouver:

Selby JWA. Unconventional Applications of Compiler Analysis. [Internet] [Thesis]. University of Waterloo; 2011. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/10012/6184.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Selby JWA. Unconventional Applications of Compiler Analysis. [Thesis]. University of Waterloo; 2011. Available from: http://hdl.handle.net/10012/6184

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Alberta

2. Garg, Rahul. A compiler for parallel execution of numerical Python programs on graphics processing units.

Degree: MS, Department of Computing Science, 2009, University of Alberta

 Modern Graphics Processing Units (GPUs) are providing breakthrough performance for numerical computing at the cost of increased programming complexity. Current programming models for GPUs require… (more)

Subjects/Keywords: gpgpu; compiler

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APA (6th Edition):

Garg, R. (2009). A compiler for parallel execution of numerical Python programs on graphics processing units. (Masters Thesis). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/4j03d0630

Chicago Manual of Style (16th Edition):

Garg, Rahul. “A compiler for parallel execution of numerical Python programs on graphics processing units.” 2009. Masters Thesis, University of Alberta. Accessed April 18, 2021. https://era.library.ualberta.ca/files/4j03d0630.

MLA Handbook (7th Edition):

Garg, Rahul. “A compiler for parallel execution of numerical Python programs on graphics processing units.” 2009. Web. 18 Apr 2021.

Vancouver:

Garg R. A compiler for parallel execution of numerical Python programs on graphics processing units. [Internet] [Masters thesis]. University of Alberta; 2009. [cited 2021 Apr 18]. Available from: https://era.library.ualberta.ca/files/4j03d0630.

Council of Science Editors:

Garg R. A compiler for parallel execution of numerical Python programs on graphics processing units. [Masters Thesis]. University of Alberta; 2009. Available from: https://era.library.ualberta.ca/files/4j03d0630


University of Alberta

3. Xunhao, Li. Jit4OpenCL: a compiler from Python to OpenCL.

Degree: MS, Department of Computing Science, 2010, University of Alberta

 Heterogeneous computing platforms that use GPUs and CPUs in tandem for computation have become an important choice to build low-cost high-performance computing platforms. The computing… (more)

Subjects/Keywords: Python; compiler; OpenCL

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APA (6th Edition):

Xunhao, L. (2010). Jit4OpenCL: a compiler from Python to OpenCL. (Masters Thesis). University of Alberta. Retrieved from https://era.library.ualberta.ca/files/1v53jx087

Chicago Manual of Style (16th Edition):

Xunhao, Li. “Jit4OpenCL: a compiler from Python to OpenCL.” 2010. Masters Thesis, University of Alberta. Accessed April 18, 2021. https://era.library.ualberta.ca/files/1v53jx087.

MLA Handbook (7th Edition):

Xunhao, Li. “Jit4OpenCL: a compiler from Python to OpenCL.” 2010. Web. 18 Apr 2021.

Vancouver:

Xunhao L. Jit4OpenCL: a compiler from Python to OpenCL. [Internet] [Masters thesis]. University of Alberta; 2010. [cited 2021 Apr 18]. Available from: https://era.library.ualberta.ca/files/1v53jx087.

Council of Science Editors:

Xunhao L. Jit4OpenCL: a compiler from Python to OpenCL. [Masters Thesis]. University of Alberta; 2010. Available from: https://era.library.ualberta.ca/files/1v53jx087


University of Toronto

4. Calman, Silvian. Interprocedural Static Single Assignment Form.

Degree: 2011, University of Toronto

Static Single Assignment (SSA) is an Intermediate Representation (IR) that simplifies the design and implementation of analyses and optimizations. While intraprocedural SSA is ubiquitous in… (more)

Subjects/Keywords: compiler; analysis; 0544

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APA (6th Edition):

Calman, S. (2011). Interprocedural Static Single Assignment Form. (Doctoral Dissertation). University of Toronto. Retrieved from http://hdl.handle.net/1807/27573

Chicago Manual of Style (16th Edition):

Calman, Silvian. “Interprocedural Static Single Assignment Form.” 2011. Doctoral Dissertation, University of Toronto. Accessed April 18, 2021. http://hdl.handle.net/1807/27573.

MLA Handbook (7th Edition):

Calman, Silvian. “Interprocedural Static Single Assignment Form.” 2011. Web. 18 Apr 2021.

Vancouver:

Calman S. Interprocedural Static Single Assignment Form. [Internet] [Doctoral dissertation]. University of Toronto; 2011. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1807/27573.

Council of Science Editors:

Calman S. Interprocedural Static Single Assignment Form. [Doctoral Dissertation]. University of Toronto; 2011. Available from: http://hdl.handle.net/1807/27573


University of Edinburgh

5. Cummins, Christopher Edward. Deep learning for compilers.

Degree: PhD, 2020, University of Edinburgh

 Constructing compilers is hard. Optimising compilers are multi-million dollar projects spanning years of development, yet remain unable to fully exploit the available performance, and are… (more)

Subjects/Keywords: optimising compilers; compiler construction; deep learning; generative model; compiler fuzzer; compiler heuristics

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cummins, C. E. (2020). Deep learning for compilers. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/36866

Chicago Manual of Style (16th Edition):

Cummins, Christopher Edward. “Deep learning for compilers.” 2020. Doctoral Dissertation, University of Edinburgh. Accessed April 18, 2021. http://hdl.handle.net/1842/36866.

MLA Handbook (7th Edition):

Cummins, Christopher Edward. “Deep learning for compilers.” 2020. Web. 18 Apr 2021.

Vancouver:

Cummins CE. Deep learning for compilers. [Internet] [Doctoral dissertation]. University of Edinburgh; 2020. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1842/36866.

Council of Science Editors:

Cummins CE. Deep learning for compilers. [Doctoral Dissertation]. University of Edinburgh; 2020. Available from: http://hdl.handle.net/1842/36866


University of Edinburgh

6. Cummins, Christopher Edward. Deep learning for compilers.

Degree: PhD, 2020, University of Edinburgh

 Constructing compilers is hard. Optimising compilers are multi-million dollar projects spanning years of development, yet remain unable to fully exploit the available performance, and are… (more)

Subjects/Keywords: optimising compilers; compiler construction; deep learning; generative model; compiler fuzzer; compiler heuristics

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Cummins, C. E. (2020). Deep learning for compilers. (Doctoral Dissertation). University of Edinburgh. Retrieved from https://doi.org/10.7488/era/168 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.802366

Chicago Manual of Style (16th Edition):

Cummins, Christopher Edward. “Deep learning for compilers.” 2020. Doctoral Dissertation, University of Edinburgh. Accessed April 18, 2021. https://doi.org/10.7488/era/168 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.802366.

MLA Handbook (7th Edition):

Cummins, Christopher Edward. “Deep learning for compilers.” 2020. Web. 18 Apr 2021.

Vancouver:

Cummins CE. Deep learning for compilers. [Internet] [Doctoral dissertation]. University of Edinburgh; 2020. [cited 2021 Apr 18]. Available from: https://doi.org/10.7488/era/168 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.802366.

Council of Science Editors:

Cummins CE. Deep learning for compilers. [Doctoral Dissertation]. University of Edinburgh; 2020. Available from: https://doi.org/10.7488/era/168 ; https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.802366


Penn State University

7. Kislal, Orhan Memduh. Hardware-Aware Computation Reorganization for Memory Intensive Applications.

Degree: 2018, Penn State University

 After hitting the power wall, the dramatic change in computer architecture from single core to multicore/manycore brings us new challenges on high performance computing, especially… (more)

Subjects/Keywords: memory; performance; compiler; approximate computing

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APA (6th Edition):

Kislal, O. M. (2018). Hardware-Aware Computation Reorganization for Memory Intensive Applications. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/15032omk103

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kislal, Orhan Memduh. “Hardware-Aware Computation Reorganization for Memory Intensive Applications.” 2018. Thesis, Penn State University. Accessed April 18, 2021. https://submit-etda.libraries.psu.edu/catalog/15032omk103.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kislal, Orhan Memduh. “Hardware-Aware Computation Reorganization for Memory Intensive Applications.” 2018. Web. 18 Apr 2021.

Vancouver:

Kislal OM. Hardware-Aware Computation Reorganization for Memory Intensive Applications. [Internet] [Thesis]. Penn State University; 2018. [cited 2021 Apr 18]. Available from: https://submit-etda.libraries.psu.edu/catalog/15032omk103.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kislal OM. Hardware-Aware Computation Reorganization for Memory Intensive Applications. [Thesis]. Penn State University; 2018. Available from: https://submit-etda.libraries.psu.edu/catalog/15032omk103

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Illinois – Chicago

8. Casula, Dario. Witnessing Control Flow Graph Optimizations.

Degree: 2016, University of Illinois – Chicago

 Proving the correctness of a program transformation, and specifically, of a compiler op- timization, is a long-standing research problem. Trusting the compiler requires to guarantee… (more)

Subjects/Keywords: llvm; witness; z3; CFG; compiler

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APA (6th Edition):

Casula, D. (2016). Witnessing Control Flow Graph Optimizations. (Thesis). University of Illinois – Chicago. Retrieved from http://hdl.handle.net/10027/20974

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Casula, Dario. “Witnessing Control Flow Graph Optimizations.” 2016. Thesis, University of Illinois – Chicago. Accessed April 18, 2021. http://hdl.handle.net/10027/20974.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Casula, Dario. “Witnessing Control Flow Graph Optimizations.” 2016. Web. 18 Apr 2021.

Vancouver:

Casula D. Witnessing Control Flow Graph Optimizations. [Internet] [Thesis]. University of Illinois – Chicago; 2016. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/10027/20974.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Casula D. Witnessing Control Flow Graph Optimizations. [Thesis]. University of Illinois – Chicago; 2016. Available from: http://hdl.handle.net/10027/20974

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Delaware

9. Chen, Yuanfang. Software simultaneous multithreading through compilation.

Degree: PhD, University of Delaware, Department of Electrical and Computer Engineering, 2018, University of Delaware

 With the Dennard Scaling law break for a long time, the computer architecture design progress towards the wider rather than deeper organization. There are three… (more)

Subjects/Keywords: Applied sciences; Compiler; LLVM; SMT

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APA (6th Edition):

Chen, Y. (2018). Software simultaneous multithreading through compilation. (Doctoral Dissertation). University of Delaware. Retrieved from http://udspace.udel.edu/handle/19716/23594

Chicago Manual of Style (16th Edition):

Chen, Yuanfang. “Software simultaneous multithreading through compilation.” 2018. Doctoral Dissertation, University of Delaware. Accessed April 18, 2021. http://udspace.udel.edu/handle/19716/23594.

MLA Handbook (7th Edition):

Chen, Yuanfang. “Software simultaneous multithreading through compilation.” 2018. Web. 18 Apr 2021.

Vancouver:

Chen Y. Software simultaneous multithreading through compilation. [Internet] [Doctoral dissertation]. University of Delaware; 2018. [cited 2021 Apr 18]. Available from: http://udspace.udel.edu/handle/19716/23594.

Council of Science Editors:

Chen Y. Software simultaneous multithreading through compilation. [Doctoral Dissertation]. University of Delaware; 2018. Available from: http://udspace.udel.edu/handle/19716/23594


Brno University of Technology

10. Hranáč, Jan. Překlad do různých asemblerů: Translation to Various Assembly Languages.

Degree: 2019, Brno University of Technology

 The goal of this project is to create a compiler capable of compilation of the input language into various assemblers (by the choice of the… (more)

Subjects/Keywords: překladač; asembler; compiler; assembler

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APA (6th Edition):

Hranáč, J. (2019). Překlad do různých asemblerů: Translation to Various Assembly Languages. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/55429

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hranáč, Jan. “Překlad do různých asemblerů: Translation to Various Assembly Languages.” 2019. Thesis, Brno University of Technology. Accessed April 18, 2021. http://hdl.handle.net/11012/55429.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hranáč, Jan. “Překlad do různých asemblerů: Translation to Various Assembly Languages.” 2019. Web. 18 Apr 2021.

Vancouver:

Hranáč J. Překlad do různých asemblerů: Translation to Various Assembly Languages. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/11012/55429.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hranáč J. Překlad do různých asemblerů: Translation to Various Assembly Languages. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/55429

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Oregon

11. Clauson, Aran. Search-based Optimization for Compiler Machine-code Generation.

Degree: PhD, Department of Computer and Information Science, 2013, University of Oregon

 Compilation encompasses many steps. Parsing turns the input program into a more manageable syntax tree. Verification ensures that the program makes some semblance of sense.… (more)

Subjects/Keywords: Code-generation; Compiler; Search

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APA (6th Edition):

Clauson, A. (2013). Search-based Optimization for Compiler Machine-code Generation. (Doctoral Dissertation). University of Oregon. Retrieved from http://hdl.handle.net/1794/13433

Chicago Manual of Style (16th Edition):

Clauson, Aran. “Search-based Optimization for Compiler Machine-code Generation.” 2013. Doctoral Dissertation, University of Oregon. Accessed April 18, 2021. http://hdl.handle.net/1794/13433.

MLA Handbook (7th Edition):

Clauson, Aran. “Search-based Optimization for Compiler Machine-code Generation.” 2013. Web. 18 Apr 2021.

Vancouver:

Clauson A. Search-based Optimization for Compiler Machine-code Generation. [Internet] [Doctoral dissertation]. University of Oregon; 2013. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1794/13433.

Council of Science Editors:

Clauson A. Search-based Optimization for Compiler Machine-code Generation. [Doctoral Dissertation]. University of Oregon; 2013. Available from: http://hdl.handle.net/1794/13433


University of Notre Dame

12. Peter James Bui. A Compiler Toolchain for Distributed Data Intensive Scientific Workflows</h1>.

Degree: Computer Science and Engineering, 2012, University of Notre Dame

  With the growing amount of computational resources available to researchers today and the explosion of scientific data in modern research, it is imperative that… (more)

Subjects/Keywords: compiler; distributed systems; workflows; python

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APA (6th Edition):

Bui, P. J. (2012). A Compiler Toolchain for Distributed Data Intensive Scientific Workflows</h1>. (Thesis). University of Notre Dame. Retrieved from https://curate.nd.edu/show/pk02c823v2f

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Bui, Peter James. “A Compiler Toolchain for Distributed Data Intensive Scientific Workflows</h1>.” 2012. Thesis, University of Notre Dame. Accessed April 18, 2021. https://curate.nd.edu/show/pk02c823v2f.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Bui, Peter James. “A Compiler Toolchain for Distributed Data Intensive Scientific Workflows</h1>.” 2012. Web. 18 Apr 2021.

Vancouver:

Bui PJ. A Compiler Toolchain for Distributed Data Intensive Scientific Workflows</h1>. [Internet] [Thesis]. University of Notre Dame; 2012. [cited 2021 Apr 18]. Available from: https://curate.nd.edu/show/pk02c823v2f.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Bui PJ. A Compiler Toolchain for Distributed Data Intensive Scientific Workflows</h1>. [Thesis]. University of Notre Dame; 2012. Available from: https://curate.nd.edu/show/pk02c823v2f

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

13. Hebert, Chris. Inferring Types to Eliminate Ownership Checks in an Intentional JavaScript Compiler.

Degree: MS, 2015, University of New Hampshire

 Concurrent programs are notoriously difficult to develop due to the non-deterministic nature of thread scheduling. It is desirable to have a programming language to make… (more)

Subjects/Keywords: compiler; javascript; optimization; Computer science

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APA (6th Edition):

Hebert, C. (2015). Inferring Types to Eliminate Ownership Checks in an Intentional JavaScript Compiler. (Thesis). University of New Hampshire. Retrieved from https://scholars.unh.edu/thesis/1021

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hebert, Chris. “Inferring Types to Eliminate Ownership Checks in an Intentional JavaScript Compiler.” 2015. Thesis, University of New Hampshire. Accessed April 18, 2021. https://scholars.unh.edu/thesis/1021.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hebert, Chris. “Inferring Types to Eliminate Ownership Checks in an Intentional JavaScript Compiler.” 2015. Web. 18 Apr 2021.

Vancouver:

Hebert C. Inferring Types to Eliminate Ownership Checks in an Intentional JavaScript Compiler. [Internet] [Thesis]. University of New Hampshire; 2015. [cited 2021 Apr 18]. Available from: https://scholars.unh.edu/thesis/1021.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hebert C. Inferring Types to Eliminate Ownership Checks in an Intentional JavaScript Compiler. [Thesis]. University of New Hampshire; 2015. Available from: https://scholars.unh.edu/thesis/1021

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Georgia Tech

14. Gupta, Meghana. Code generation and adaptive control divergence management for light weight SIMT processors.

Degree: MS, Computer Science, 2016, Georgia Tech

 The energy costs of data movement are limiting the performance scaling of future generations of high performance computing architectures targeted to data intensive applications. The… (more)

Subjects/Keywords: Compiler; SIMT; Control divergence

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Gupta, M. (2016). Code generation and adaptive control divergence management for light weight SIMT processors. (Masters Thesis). Georgia Tech. Retrieved from http://hdl.handle.net/1853/55044

Chicago Manual of Style (16th Edition):

Gupta, Meghana. “Code generation and adaptive control divergence management for light weight SIMT processors.” 2016. Masters Thesis, Georgia Tech. Accessed April 18, 2021. http://hdl.handle.net/1853/55044.

MLA Handbook (7th Edition):

Gupta, Meghana. “Code generation and adaptive control divergence management for light weight SIMT processors.” 2016. Web. 18 Apr 2021.

Vancouver:

Gupta M. Code generation and adaptive control divergence management for light weight SIMT processors. [Internet] [Masters thesis]. Georgia Tech; 2016. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1853/55044.

Council of Science Editors:

Gupta M. Code generation and adaptive control divergence management for light weight SIMT processors. [Masters Thesis]. Georgia Tech; 2016. Available from: http://hdl.handle.net/1853/55044


University of Edinburgh

15. Chandramohan, Kiran. Mapping parallelism to heterogeneous processors.

Degree: PhD, 2016, University of Edinburgh

 Most embedded devices are based on heterogeneous Multiprocessor System on Chips (MPSoCs). These contain a variety of processors like CPUs, micro-controllers, DSPs, GPUs and specialised… (more)

Subjects/Keywords: 004; heterogeneous processors; compiler

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Chandramohan, K. (2016). Mapping parallelism to heterogeneous processors. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/22028

Chicago Manual of Style (16th Edition):

Chandramohan, Kiran. “Mapping parallelism to heterogeneous processors.” 2016. Doctoral Dissertation, University of Edinburgh. Accessed April 18, 2021. http://hdl.handle.net/1842/22028.

MLA Handbook (7th Edition):

Chandramohan, Kiran. “Mapping parallelism to heterogeneous processors.” 2016. Web. 18 Apr 2021.

Vancouver:

Chandramohan K. Mapping parallelism to heterogeneous processors. [Internet] [Doctoral dissertation]. University of Edinburgh; 2016. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1842/22028.

Council of Science Editors:

Chandramohan K. Mapping parallelism to heterogeneous processors. [Doctoral Dissertation]. University of Edinburgh; 2016. Available from: http://hdl.handle.net/1842/22028

16. Mitropoulou, Konstantina. Performance optimizations for compiler-based error detection.

Degree: PhD, 2015, University of Edinburgh

 The trend towards smaller transistor technologies and lower operating voltages stresses the hardware and makes transistors more susceptible to transient errors. In future systems, performance… (more)

Subjects/Keywords: 005.75; fault tolerance; compiler

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APA (6th Edition):

Mitropoulou, K. (2015). Performance optimizations for compiler-based error detection. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/10473

Chicago Manual of Style (16th Edition):

Mitropoulou, Konstantina. “Performance optimizations for compiler-based error detection.” 2015. Doctoral Dissertation, University of Edinburgh. Accessed April 18, 2021. http://hdl.handle.net/1842/10473.

MLA Handbook (7th Edition):

Mitropoulou, Konstantina. “Performance optimizations for compiler-based error detection.” 2015. Web. 18 Apr 2021.

Vancouver:

Mitropoulou K. Performance optimizations for compiler-based error detection. [Internet] [Doctoral dissertation]. University of Edinburgh; 2015. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1842/10473.

Council of Science Editors:

Mitropoulou K. Performance optimizations for compiler-based error detection. [Doctoral Dissertation]. University of Edinburgh; 2015. Available from: http://hdl.handle.net/1842/10473


Louisiana State University

17. Hanagodimath, Pratik Prabhu. Performance Comparison Between Patus and Pluto Compilers on Stencils.

Degree: MSEE, Electrical and Computer Engineering, 2014, Louisiana State University

Comparing the performances of Patus and Pluto compilers on stencil applications. Stencils are written in Jacobi and Seidel style of coding and performances of both these compilers are analysed based on these coding styles.

Subjects/Keywords: Compiler optimization; parallel execution.

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hanagodimath, P. P. (2014). Performance Comparison Between Patus and Pluto Compilers on Stencils. (Masters Thesis). Louisiana State University. Retrieved from etd-04142014-090546 ; https://digitalcommons.lsu.edu/gradschool_theses/2636

Chicago Manual of Style (16th Edition):

Hanagodimath, Pratik Prabhu. “Performance Comparison Between Patus and Pluto Compilers on Stencils.” 2014. Masters Thesis, Louisiana State University. Accessed April 18, 2021. etd-04142014-090546 ; https://digitalcommons.lsu.edu/gradschool_theses/2636.

MLA Handbook (7th Edition):

Hanagodimath, Pratik Prabhu. “Performance Comparison Between Patus and Pluto Compilers on Stencils.” 2014. Web. 18 Apr 2021.

Vancouver:

Hanagodimath PP. Performance Comparison Between Patus and Pluto Compilers on Stencils. [Internet] [Masters thesis]. Louisiana State University; 2014. [cited 2021 Apr 18]. Available from: etd-04142014-090546 ; https://digitalcommons.lsu.edu/gradschool_theses/2636.

Council of Science Editors:

Hanagodimath PP. Performance Comparison Between Patus and Pluto Compilers on Stencils. [Masters Thesis]. Louisiana State University; 2014. Available from: etd-04142014-090546 ; https://digitalcommons.lsu.edu/gradschool_theses/2636


University of Georgia

18. Li, Nan. Energy-efficient program layout for multi-bank architectures.

Degree: 2014, University of Georgia

 Energy conservation is an important problem for battery-powered embedded or portable systems. New technology such as RDRAM enables memory to operate at different power levels.… (more)

Subjects/Keywords: Compiler; Linker; Energy Saving; RDRAM

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Li, N. (2014). Energy-efficient program layout for multi-bank architectures. (Thesis). University of Georgia. Retrieved from http://hdl.handle.net/10724/21321

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Li, Nan. “Energy-efficient program layout for multi-bank architectures.” 2014. Thesis, University of Georgia. Accessed April 18, 2021. http://hdl.handle.net/10724/21321.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Li, Nan. “Energy-efficient program layout for multi-bank architectures.” 2014. Web. 18 Apr 2021.

Vancouver:

Li N. Energy-efficient program layout for multi-bank architectures. [Internet] [Thesis]. University of Georgia; 2014. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/10724/21321.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Li N. Energy-efficient program layout for multi-bank architectures. [Thesis]. University of Georgia; 2014. Available from: http://hdl.handle.net/10724/21321

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

19. Liu, Qingrui. Compiler-Directed Error Resilience for Reliable Computing.

Degree: PhD, Computer Engineering, 2018, Virginia Tech

 Error resilience has become as important as power and performance in modern computing architecture. There are various sources of errors that can paralyze real-world computing… (more)

Subjects/Keywords: Reliability; Compiler Optimization; Computer Architecture

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APA (6th Edition):

Liu, Q. (2018). Compiler-Directed Error Resilience for Reliable Computing. (Doctoral Dissertation). Virginia Tech. Retrieved from http://hdl.handle.net/10919/84526

Chicago Manual of Style (16th Edition):

Liu, Qingrui. “Compiler-Directed Error Resilience for Reliable Computing.” 2018. Doctoral Dissertation, Virginia Tech. Accessed April 18, 2021. http://hdl.handle.net/10919/84526.

MLA Handbook (7th Edition):

Liu, Qingrui. “Compiler-Directed Error Resilience for Reliable Computing.” 2018. Web. 18 Apr 2021.

Vancouver:

Liu Q. Compiler-Directed Error Resilience for Reliable Computing. [Internet] [Doctoral dissertation]. Virginia Tech; 2018. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/10919/84526.

Council of Science Editors:

Liu Q. Compiler-Directed Error Resilience for Reliable Computing. [Doctoral Dissertation]. Virginia Tech; 2018. Available from: http://hdl.handle.net/10919/84526


University of New South Wales

20. Sewell, Thomas. Translation validation for verified, efficient and timely operating systems.

Degree: Computer Science & Engineering, 2017, University of New South Wales

 Computer software is typically written in one language and then translatedout of that language into the native binary languages of the machines thesoftware will run… (more)

Subjects/Keywords: Compiler; Translation Validation; Operating System

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APA (6th Edition):

Sewell, T. (2017). Translation validation for verified, efficient and timely operating systems. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/58861 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:47819/SOURCE02?view=true

Chicago Manual of Style (16th Edition):

Sewell, Thomas. “Translation validation for verified, efficient and timely operating systems.” 2017. Doctoral Dissertation, University of New South Wales. Accessed April 18, 2021. http://handle.unsw.edu.au/1959.4/58861 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:47819/SOURCE02?view=true.

MLA Handbook (7th Edition):

Sewell, Thomas. “Translation validation for verified, efficient and timely operating systems.” 2017. Web. 18 Apr 2021.

Vancouver:

Sewell T. Translation validation for verified, efficient and timely operating systems. [Internet] [Doctoral dissertation]. University of New South Wales; 2017. [cited 2021 Apr 18]. Available from: http://handle.unsw.edu.au/1959.4/58861 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:47819/SOURCE02?view=true.

Council of Science Editors:

Sewell T. Translation validation for verified, efficient and timely operating systems. [Doctoral Dissertation]. University of New South Wales; 2017. Available from: http://handle.unsw.edu.au/1959.4/58861 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:47819/SOURCE02?view=true


University of New South Wales

21. Ye, Ding. Accelerating Dynamic Detection of Memory Errors for C Programs via Static Analysis.

Degree: Computer Science & Engineering, 2015, University of New South Wales

 Memory errors in C programs are the root causes of many defects and vulnerabilitiesin software engineering. Among the available error detection techniques,dynamic analysis is widely… (more)

Subjects/Keywords: C programs; LLVM Compiler architecture

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ye, D. (2015). Accelerating Dynamic Detection of Memory Errors for C Programs via Static Analysis. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/54507 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:35127/SOURCE02?view=true

Chicago Manual of Style (16th Edition):

Ye, Ding. “Accelerating Dynamic Detection of Memory Errors for C Programs via Static Analysis.” 2015. Doctoral Dissertation, University of New South Wales. Accessed April 18, 2021. http://handle.unsw.edu.au/1959.4/54507 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:35127/SOURCE02?view=true.

MLA Handbook (7th Edition):

Ye, Ding. “Accelerating Dynamic Detection of Memory Errors for C Programs via Static Analysis.” 2015. Web. 18 Apr 2021.

Vancouver:

Ye D. Accelerating Dynamic Detection of Memory Errors for C Programs via Static Analysis. [Internet] [Doctoral dissertation]. University of New South Wales; 2015. [cited 2021 Apr 18]. Available from: http://handle.unsw.edu.au/1959.4/54507 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:35127/SOURCE02?view=true.

Council of Science Editors:

Ye D. Accelerating Dynamic Detection of Memory Errors for C Programs via Static Analysis. [Doctoral Dissertation]. University of New South Wales; 2015. Available from: http://handle.unsw.edu.au/1959.4/54507 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:35127/SOURCE02?view=true


NSYSU

22. HSU, CHUN-TO. Implementations and Automatic Synthesis of Programmable Logic Array (PLA) ROM.

Degree: Master, Computer Science and Engineering, 2014, NSYSU

 Read-only memory (ROM) plays an important role In modern System-on-Chip (SoC) designs. Due to the regularity of ROM structure, ROM components are usually generated through… (more)

Subjects/Keywords: RTL Compiler; ROM generator; Programmable Logic Array (PLA); ROM Compiler

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

HSU, C. (2014). Implementations and Automatic Synthesis of Programmable Logic Array (PLA) ROM. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726114-101438

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

HSU, CHUN-TO. “Implementations and Automatic Synthesis of Programmable Logic Array (PLA) ROM.” 2014. Thesis, NSYSU. Accessed April 18, 2021. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726114-101438.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

HSU, CHUN-TO. “Implementations and Automatic Synthesis of Programmable Logic Array (PLA) ROM.” 2014. Web. 18 Apr 2021.

Vancouver:

HSU C. Implementations and Automatic Synthesis of Programmable Logic Array (PLA) ROM. [Internet] [Thesis]. NSYSU; 2014. [cited 2021 Apr 18]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726114-101438.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

HSU C. Implementations and Automatic Synthesis of Programmable Logic Array (PLA) ROM. [Thesis]. NSYSU; 2014. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0726114-101438

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Princeton University

23. Paraskevopoulou, Zoe. Verified Optimizations for Functional Languages .

Degree: PhD, 2020, Princeton University

 Coq is one of the most widely adopted proof development systems. Itallows programmers to write purely functional programs and verify them against specifications with machine-checked… (more)

Subjects/Keywords: compiler correctness; compositional compiler correctness; Coq; functional programming languagegs; logical relations

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APA (6th Edition):

Paraskevopoulou, Z. (2020). Verified Optimizations for Functional Languages . (Doctoral Dissertation). Princeton University. Retrieved from http://arks.princeton.edu/ark:/88435/dsp01pr76f648c

Chicago Manual of Style (16th Edition):

Paraskevopoulou, Zoe. “Verified Optimizations for Functional Languages .” 2020. Doctoral Dissertation, Princeton University. Accessed April 18, 2021. http://arks.princeton.edu/ark:/88435/dsp01pr76f648c.

MLA Handbook (7th Edition):

Paraskevopoulou, Zoe. “Verified Optimizations for Functional Languages .” 2020. Web. 18 Apr 2021.

Vancouver:

Paraskevopoulou Z. Verified Optimizations for Functional Languages . [Internet] [Doctoral dissertation]. Princeton University; 2020. [cited 2021 Apr 18]. Available from: http://arks.princeton.edu/ark:/88435/dsp01pr76f648c.

Council of Science Editors:

Paraskevopoulou Z. Verified Optimizations for Functional Languages . [Doctoral Dissertation]. Princeton University; 2020. Available from: http://arks.princeton.edu/ark:/88435/dsp01pr76f648c


Brno University of Technology

24. Horník, Jakub. Zadní část překladače podmnožiny jazyka C pro 8-bitový procesor: Compiler Back-End of Subset of Language C for 8-Bit Processor.

Degree: 2019, Brno University of Technology

 A compiler allows us to describe an algorithm in a high-level programming language with a higher level of abstraction and readability than a low-level machine… (more)

Subjects/Keywords: kompilátor; Low Level Virtual Machine Compiler; mezikód; překladač; PicoBlaze; PicoBlaze C Compiler; Small Device C Compiler; zadní část překladače; back-end; compiler; intermediate code; Low Level Virtual Machine Compiler; PicoBlaze; PicoBlaze C Compiler; Small Device C Compiler

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Horník, J. (2019). Zadní část překladače podmnožiny jazyka C pro 8-bitový procesor: Compiler Back-End of Subset of Language C for 8-Bit Processor. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/54208

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Horník, Jakub. “Zadní část překladače podmnožiny jazyka C pro 8-bitový procesor: Compiler Back-End of Subset of Language C for 8-Bit Processor.” 2019. Thesis, Brno University of Technology. Accessed April 18, 2021. http://hdl.handle.net/11012/54208.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Horník, Jakub. “Zadní část překladače podmnožiny jazyka C pro 8-bitový procesor: Compiler Back-End of Subset of Language C for 8-Bit Processor.” 2019. Web. 18 Apr 2021.

Vancouver:

Horník J. Zadní část překladače podmnožiny jazyka C pro 8-bitový procesor: Compiler Back-End of Subset of Language C for 8-Bit Processor. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/11012/54208.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Horník J. Zadní část překladače podmnožiny jazyka C pro 8-bitový procesor: Compiler Back-End of Subset of Language C for 8-Bit Processor. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/54208

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

25. Machata, Petr. Methodology of Construction Compiler Front-End and Its Integration into the GNU Compiler Collection: Methodology of Construction Compiler Front-End and Its Integration into the GNU Compiler Collection.

Degree: 2020, Brno University of Technology

 This MSc Thesis was performed in English with the support of the ANF DATA s.r.o., Brno. The entry barrier to the development for GCC got… (more)

Subjects/Keywords: GCC; GNU Compiler Collection; přední část; Algol 60; kompilátor; GCC; GNU Compiler Collection; frontend; front end; Algol 60; compiler

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Machata, P. (2020). Methodology of Construction Compiler Front-End and Its Integration into the GNU Compiler Collection: Methodology of Construction Compiler Front-End and Its Integration into the GNU Compiler Collection. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/187782

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Machata, Petr. “Methodology of Construction Compiler Front-End and Its Integration into the GNU Compiler Collection: Methodology of Construction Compiler Front-End and Its Integration into the GNU Compiler Collection.” 2020. Thesis, Brno University of Technology. Accessed April 18, 2021. http://hdl.handle.net/11012/187782.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Machata, Petr. “Methodology of Construction Compiler Front-End and Its Integration into the GNU Compiler Collection: Methodology of Construction Compiler Front-End and Its Integration into the GNU Compiler Collection.” 2020. Web. 18 Apr 2021.

Vancouver:

Machata P. Methodology of Construction Compiler Front-End and Its Integration into the GNU Compiler Collection: Methodology of Construction Compiler Front-End and Its Integration into the GNU Compiler Collection. [Internet] [Thesis]. Brno University of Technology; 2020. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/11012/187782.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Machata P. Methodology of Construction Compiler Front-End and Its Integration into the GNU Compiler Collection: Methodology of Construction Compiler Front-End and Its Integration into the GNU Compiler Collection. [Thesis]. Brno University of Technology; 2020. Available from: http://hdl.handle.net/11012/187782

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

26. Machata, Petr. Methodology of Construction Compiler Front-End and Its Integration into the GNU Compiler Collection: Methodology of Construction Compiler Front-End and Its Integration into the GNU Compiler Collection.

Degree: 2020, Brno University of Technology

 This MSc Thesis was performed in English with the support of the ANF DATA s.r.o., Brno. The entry barrier to the development for GCC got… (more)

Subjects/Keywords: GCC; GNU Compiler Collection; frontend; front end; Algol 60; compiler; GCC; GNU Compiler Collection; přední část; Algol 60; kompilátor

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Machata, P. (2020). Methodology of Construction Compiler Front-End and Its Integration into the GNU Compiler Collection: Methodology of Construction Compiler Front-End and Its Integration into the GNU Compiler Collection. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/54013

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Machata, Petr. “Methodology of Construction Compiler Front-End and Its Integration into the GNU Compiler Collection: Methodology of Construction Compiler Front-End and Its Integration into the GNU Compiler Collection.” 2020. Thesis, Brno University of Technology. Accessed April 18, 2021. http://hdl.handle.net/11012/54013.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Machata, Petr. “Methodology of Construction Compiler Front-End and Its Integration into the GNU Compiler Collection: Methodology of Construction Compiler Front-End and Its Integration into the GNU Compiler Collection.” 2020. Web. 18 Apr 2021.

Vancouver:

Machata P. Methodology of Construction Compiler Front-End and Its Integration into the GNU Compiler Collection: Methodology of Construction Compiler Front-End and Its Integration into the GNU Compiler Collection. [Internet] [Thesis]. Brno University of Technology; 2020. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/11012/54013.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Machata P. Methodology of Construction Compiler Front-End and Its Integration into the GNU Compiler Collection: Methodology of Construction Compiler Front-End and Its Integration into the GNU Compiler Collection. [Thesis]. Brno University of Technology; 2020. Available from: http://hdl.handle.net/11012/54013

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Utah

27. Pagariya, Rohit. Direct equivalence testing of embedded software.

Degree: MS, School of Computing, 2011, University of Utah

 Direct equivalence testing is a framework for detecting errors in C compilers and application programs that exploits the fact that program semantics should be preserved… (more)

Subjects/Keywords: Compiler testing; Embedded software; Equivalence testing; Verification

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Pagariya, R. (2011). Direct equivalence testing of embedded software. (Masters Thesis). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/48/rec/740

Chicago Manual of Style (16th Edition):

Pagariya, Rohit. “Direct equivalence testing of embedded software.” 2011. Masters Thesis, University of Utah. Accessed April 18, 2021. http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/48/rec/740.

MLA Handbook (7th Edition):

Pagariya, Rohit. “Direct equivalence testing of embedded software.” 2011. Web. 18 Apr 2021.

Vancouver:

Pagariya R. Direct equivalence testing of embedded software. [Internet] [Masters thesis]. University of Utah; 2011. [cited 2021 Apr 18]. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/48/rec/740.

Council of Science Editors:

Pagariya R. Direct equivalence testing of embedded software. [Masters Thesis]. University of Utah; 2011. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd3/id/48/rec/740


Cornell University

28. Deng, Yawen. Scalable Compiler for TERMES Distributed Assembly System.

Degree: M.S., Mechanical Engineering, Mechanical Engineering, 2018, Cornell University

 The TERMES system is a robot collective capable of autonomously constructing user-specified structures in three dimensions. The compiler is one of the key components that… (more)

Subjects/Keywords: Robotics; Collective Construction; Mechanical engineering; Scalable Compiler

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Deng, Y. (2018). Scalable Compiler for TERMES Distributed Assembly System. (Masters Thesis). Cornell University. Retrieved from http://hdl.handle.net/1813/59408

Chicago Manual of Style (16th Edition):

Deng, Yawen. “Scalable Compiler for TERMES Distributed Assembly System.” 2018. Masters Thesis, Cornell University. Accessed April 18, 2021. http://hdl.handle.net/1813/59408.

MLA Handbook (7th Edition):

Deng, Yawen. “Scalable Compiler for TERMES Distributed Assembly System.” 2018. Web. 18 Apr 2021.

Vancouver:

Deng Y. Scalable Compiler for TERMES Distributed Assembly System. [Internet] [Masters thesis]. Cornell University; 2018. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/1813/59408.

Council of Science Editors:

Deng Y. Scalable Compiler for TERMES Distributed Assembly System. [Masters Thesis]. Cornell University; 2018. Available from: http://hdl.handle.net/1813/59408

29. Peckner, Justin E. XML-based form creation.

Degree: MS, Computer Science, 2013, California State University – Northridge

 While web-based forms have become essential for any organization collecting and processing large amounts of data, CSUN currently has no central electronic form management system.… (more)

Subjects/Keywords: Compiler; Dissertations, Academic  – CSUN  – Computer Science.

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Peckner, J. E. (2013). XML-based form creation. (Masters Thesis). California State University – Northridge. Retrieved from http://hdl.handle.net/10211.2/3188

Chicago Manual of Style (16th Edition):

Peckner, Justin E. “XML-based form creation.” 2013. Masters Thesis, California State University – Northridge. Accessed April 18, 2021. http://hdl.handle.net/10211.2/3188.

MLA Handbook (7th Edition):

Peckner, Justin E. “XML-based form creation.” 2013. Web. 18 Apr 2021.

Vancouver:

Peckner JE. XML-based form creation. [Internet] [Masters thesis]. California State University – Northridge; 2013. [cited 2021 Apr 18]. Available from: http://hdl.handle.net/10211.2/3188.

Council of Science Editors:

Peckner JE. XML-based form creation. [Masters Thesis]. California State University – Northridge; 2013. Available from: http://hdl.handle.net/10211.2/3188


Penn State University

30. Ding, Wei. A Fresh Look At Data Locality On Emerging Multicores And Manycores.

Degree: 2014, Penn State University

 The emergence of multicore platforms offers several opportunities for boosting ap- plication performance. These opportunities, which include parallelism and data locality benefits, require strong support… (more)

Subjects/Keywords: Data Locality; Multicore; Manycore; Compiler; Loop

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ding, W. (2014). A Fresh Look At Data Locality On Emerging Multicores And Manycores. (Thesis). Penn State University. Retrieved from https://submit-etda.libraries.psu.edu/catalog/22506

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ding, Wei. “A Fresh Look At Data Locality On Emerging Multicores And Manycores.” 2014. Thesis, Penn State University. Accessed April 18, 2021. https://submit-etda.libraries.psu.edu/catalog/22506.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ding, Wei. “A Fresh Look At Data Locality On Emerging Multicores And Manycores.” 2014. Web. 18 Apr 2021.

Vancouver:

Ding W. A Fresh Look At Data Locality On Emerging Multicores And Manycores. [Internet] [Thesis]. Penn State University; 2014. [cited 2021 Apr 18]. Available from: https://submit-etda.libraries.psu.edu/catalog/22506.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ding W. A Fresh Look At Data Locality On Emerging Multicores And Manycores. [Thesis]. Penn State University; 2014. Available from: https://submit-etda.libraries.psu.edu/catalog/22506

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

[1] [2] [3] [4] [5] … [19]

.