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You searched for subject:(combinational circuit). Showing records 1 – 15 of 15 total matches.

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University of Windsor

1. Zhan, Suoyue. Reliability Analysis and Optimization Models for Large Scale Combinational Circuits.

Degree: MA, Electrical and Computer Engineering, 2018, University of Windsor

 With increasingly high density, today’s integrated circuit chips become sensitive to minor effects such as temperature and environmental noises, which may lead to unreliable operation.… (more)

Subjects/Keywords: Combinational Circuit; Digital; Reliability

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhan, S. (2018). Reliability Analysis and Optimization Models for Large Scale Combinational Circuits. (Masters Thesis). University of Windsor. Retrieved from https://scholar.uwindsor.ca/etd/7591

Chicago Manual of Style (16th Edition):

Zhan, Suoyue. “Reliability Analysis and Optimization Models for Large Scale Combinational Circuits.” 2018. Masters Thesis, University of Windsor. Accessed August 05, 2020. https://scholar.uwindsor.ca/etd/7591.

MLA Handbook (7th Edition):

Zhan, Suoyue. “Reliability Analysis and Optimization Models for Large Scale Combinational Circuits.” 2018. Web. 05 Aug 2020.

Vancouver:

Zhan S. Reliability Analysis and Optimization Models for Large Scale Combinational Circuits. [Internet] [Masters thesis]. University of Windsor; 2018. [cited 2020 Aug 05]. Available from: https://scholar.uwindsor.ca/etd/7591.

Council of Science Editors:

Zhan S. Reliability Analysis and Optimization Models for Large Scale Combinational Circuits. [Masters Thesis]. University of Windsor; 2018. Available from: https://scholar.uwindsor.ca/etd/7591


Université Montpellier II

2. Tran, Duc Anh. Architecture hybride tolérante aux fautes pour l'amélioration de la robustesse des circuits et systèmes intégrés numériques. : A Hybrid Fault-Tolerant Architecture for Robustness Improvement of Digital Integrated Circuits and Systems.

Degree: Docteur es, SYAM - Systèmes Automatiques et Microélectroniques, 2012, Université Montpellier II

L'évolution de la technologie CMOS consiste à la miniaturisation continue de la taille des transistors. Cela permet la réalisation de circuits et systèmes intégrés de… (more)

Subjects/Keywords: Tolérance aux fautes; Circuit numérique; Logique combinatoire; Fault tolerance; Digital circuit; Combinational logic

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APA (6th Edition):

Tran, D. A. (2012). Architecture hybride tolérante aux fautes pour l'amélioration de la robustesse des circuits et systèmes intégrés numériques. : A Hybrid Fault-Tolerant Architecture for Robustness Improvement of Digital Integrated Circuits and Systems. (Doctoral Dissertation). Université Montpellier II. Retrieved from http://www.theses.fr/2012MON20132

Chicago Manual of Style (16th Edition):

Tran, Duc Anh. “Architecture hybride tolérante aux fautes pour l'amélioration de la robustesse des circuits et systèmes intégrés numériques. : A Hybrid Fault-Tolerant Architecture for Robustness Improvement of Digital Integrated Circuits and Systems.” 2012. Doctoral Dissertation, Université Montpellier II. Accessed August 05, 2020. http://www.theses.fr/2012MON20132.

MLA Handbook (7th Edition):

Tran, Duc Anh. “Architecture hybride tolérante aux fautes pour l'amélioration de la robustesse des circuits et systèmes intégrés numériques. : A Hybrid Fault-Tolerant Architecture for Robustness Improvement of Digital Integrated Circuits and Systems.” 2012. Web. 05 Aug 2020.

Vancouver:

Tran DA. Architecture hybride tolérante aux fautes pour l'amélioration de la robustesse des circuits et systèmes intégrés numériques. : A Hybrid Fault-Tolerant Architecture for Robustness Improvement of Digital Integrated Circuits and Systems. [Internet] [Doctoral dissertation]. Université Montpellier II; 2012. [cited 2020 Aug 05]. Available from: http://www.theses.fr/2012MON20132.

Council of Science Editors:

Tran DA. Architecture hybride tolérante aux fautes pour l'amélioration de la robustesse des circuits et systèmes intégrés numériques. : A Hybrid Fault-Tolerant Architecture for Robustness Improvement of Digital Integrated Circuits and Systems. [Doctoral Dissertation]. Université Montpellier II; 2012. Available from: http://www.theses.fr/2012MON20132

3. Matsumoto, Takashi. Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits : バイアス温度不安定性とランダムテレグラフノイズがCMOS論理回路特性に及ぼす影響.

Degree: 博士(情報学), 2015, Kyoto University / 京都大学

新制・課程博士

甲第19137号

情博第583号

Subjects/Keywords: CMOS; NBTI; RTN; combinational circuit; gate oxide; reliability; noise

Page 1 Page 2 Page 3 Page 4

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APA (6th Edition):

Matsumoto, T. (2015). Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits : バイアス温度不安定性とランダムテレグラフノイズがCMOS論理回路特性に及ぼす影響. (Thesis). Kyoto University / 京都大学. Retrieved from http://hdl.handle.net/2433/199461 ; http://dx.doi.org/10.14989/doctor.k19137

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Matsumoto, Takashi. “Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits : バイアス温度不安定性とランダムテレグラフノイズがCMOS論理回路特性に及ぼす影響.” 2015. Thesis, Kyoto University / 京都大学. Accessed August 05, 2020. http://hdl.handle.net/2433/199461 ; http://dx.doi.org/10.14989/doctor.k19137.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Matsumoto, Takashi. “Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits : バイアス温度不安定性とランダムテレグラフノイズがCMOS論理回路特性に及ぼす影響.” 2015. Web. 05 Aug 2020.

Vancouver:

Matsumoto T. Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits : バイアス温度不安定性とランダムテレグラフノイズがCMOS論理回路特性に及ぼす影響. [Internet] [Thesis]. Kyoto University / 京都大学; 2015. [cited 2020 Aug 05]. Available from: http://hdl.handle.net/2433/199461 ; http://dx.doi.org/10.14989/doctor.k19137.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Matsumoto T. Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits : バイアス温度不安定性とランダムテレグラフノイズがCMOS論理回路特性に及ぼす影響. [Thesis]. Kyoto University / 京都大学; 2015. Available from: http://hdl.handle.net/2433/199461 ; http://dx.doi.org/10.14989/doctor.k19137

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Kyoto University / 京都大学

4. 松本, 高士. バイアス温度不安定性とランダムテレグラフノイズがCMOS論理回路特性に及ぼす影響 : Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits.

Degree: 博士(情報学), 2015, Kyoto University / 京都大学

新制・課程博士

甲第19137号

情博第583号

Subjects/Keywords: CMOS; NBTI; RTN; combinational circuit; gate oxide; reliability; noise

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

松本, . (2015). バイアス温度不安定性とランダムテレグラフノイズがCMOS論理回路特性に及ぼす影響 : Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits. (Thesis). Kyoto University / 京都大学. Retrieved from http://hdl.handle.net/2433/199558

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

松本, 高士. “バイアス温度不安定性とランダムテレグラフノイズがCMOS論理回路特性に及ぼす影響 : Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits.” 2015. Thesis, Kyoto University / 京都大学. Accessed August 05, 2020. http://hdl.handle.net/2433/199558.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

松本, 高士. “バイアス温度不安定性とランダムテレグラフノイズがCMOS論理回路特性に及ぼす影響 : Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits.” 2015. Web. 05 Aug 2020.

Vancouver:

松本 . バイアス温度不安定性とランダムテレグラフノイズがCMOS論理回路特性に及ぼす影響 : Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits. [Internet] [Thesis]. Kyoto University / 京都大学; 2015. [cited 2020 Aug 05]. Available from: http://hdl.handle.net/2433/199558.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

松本 . バイアス温度不安定性とランダムテレグラフノイズがCMOS論理回路特性に及ぼす影響 : Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits. [Thesis]. Kyoto University / 京都大学; 2015. Available from: http://hdl.handle.net/2433/199558

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Kyoto University

5. Matsumoto, Takashi. Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits .

Degree: 2015, Kyoto University

Subjects/Keywords: CMOS; NBTI; RTN; combinational circuit; gate oxide; reliability; noise

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Matsumoto, T. (2015). Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits . (Thesis). Kyoto University. Retrieved from http://hdl.handle.net/2433/199461

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Matsumoto, Takashi. “Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits .” 2015. Thesis, Kyoto University. Accessed August 05, 2020. http://hdl.handle.net/2433/199461.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Matsumoto, Takashi. “Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits .” 2015. Web. 05 Aug 2020.

Vancouver:

Matsumoto T. Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits . [Internet] [Thesis]. Kyoto University; 2015. [cited 2020 Aug 05]. Available from: http://hdl.handle.net/2433/199461.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Matsumoto T. Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits . [Thesis]. Kyoto University; 2015. Available from: http://hdl.handle.net/2433/199461

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

6. Mahatme, Nihaar Nilesh. Design Techniques for Power-Aware Combinational Logic SER Mitigation.

Degree: PhD, Electrical Engineering, 2014, Vanderbilt University

 Ensuring low power operation is a major challenge for designers in the era of portable devices, cloud computing and networked sensor systems. Concomitantly, combinational logic… (more)

Subjects/Keywords: combinational logic; circuit reliability; soft errors

…consumption and combinational logic error rate. Different approaches at the gate-level, circuit… …Circuit Overhead… …205 2. Test Circuit Description & Experiments… …207 2.1 Circuit Description… …211 2.4 Impact of voltage and frequency on combinational and flip-flop SER… 

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APA (6th Edition):

Mahatme, N. N. (2014). Design Techniques for Power-Aware Combinational Logic SER Mitigation. (Doctoral Dissertation). Vanderbilt University. Retrieved from http://etd.library.vanderbilt.edu/available/etd-12092014-230739/ ;

Chicago Manual of Style (16th Edition):

Mahatme, Nihaar Nilesh. “Design Techniques for Power-Aware Combinational Logic SER Mitigation.” 2014. Doctoral Dissertation, Vanderbilt University. Accessed August 05, 2020. http://etd.library.vanderbilt.edu/available/etd-12092014-230739/ ;.

MLA Handbook (7th Edition):

Mahatme, Nihaar Nilesh. “Design Techniques for Power-Aware Combinational Logic SER Mitigation.” 2014. Web. 05 Aug 2020.

Vancouver:

Mahatme NN. Design Techniques for Power-Aware Combinational Logic SER Mitigation. [Internet] [Doctoral dissertation]. Vanderbilt University; 2014. [cited 2020 Aug 05]. Available from: http://etd.library.vanderbilt.edu/available/etd-12092014-230739/ ;.

Council of Science Editors:

Mahatme NN. Design Techniques for Power-Aware Combinational Logic SER Mitigation. [Doctoral Dissertation]. Vanderbilt University; 2014. Available from: http://etd.library.vanderbilt.edu/available/etd-12092014-230739/ ;


Brno University of Technology

7. Michálik, Juraj. Simulace kvantových celulárních automatů: Quantum Dot Cellular Automata Simulation.

Degree: 2019, Brno University of Technology

 This bachelor thesis describes the origin and purpose of quantum cellular automata (QCA), their function and physical construction. It also describes the quantum cellular cell… (more)

Subjects/Keywords: kvantové celulární automaty; kvantový bod; simulace; kombinační obvod; quantum cellular automata; quantum dot; simulation; combinational circuit

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APA (6th Edition):

Michálik, J. (2019). Simulace kvantových celulárních automatů: Quantum Dot Cellular Automata Simulation. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/56535

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Michálik, Juraj. “Simulace kvantových celulárních automatů: Quantum Dot Cellular Automata Simulation.” 2019. Thesis, Brno University of Technology. Accessed August 05, 2020. http://hdl.handle.net/11012/56535.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Michálik, Juraj. “Simulace kvantových celulárních automatů: Quantum Dot Cellular Automata Simulation.” 2019. Web. 05 Aug 2020.

Vancouver:

Michálik J. Simulace kvantových celulárních automatů: Quantum Dot Cellular Automata Simulation. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2020 Aug 05]. Available from: http://hdl.handle.net/11012/56535.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Michálik J. Simulace kvantových celulárních automatů: Quantum Dot Cellular Automata Simulation. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/56535

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

8. Sileská, Silvia. Ukázkové úlohy pro výuku automatizace: Sample tasks for automation education.

Degree: 2019, Brno University of Technology

 This bachelor´s thesis deals with the design and demonstration of tasks addressing combinatorial and sequential logic circuits. To resolve the assignment must be familiar with… (more)

Subjects/Keywords: Programovateľný automat; LOGO! Soft Comfort; Kombinačný logický obvod; Sekvenčný logický obvod; Programmable logic computer; LOGO! Soft Comfort; Combinational logic circuit; Sequential logic circuit

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APA (6th Edition):

Sileská, S. (2019). Ukázkové úlohy pro výuku automatizace: Sample tasks for automation education. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/14804

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Sileská, Silvia. “Ukázkové úlohy pro výuku automatizace: Sample tasks for automation education.” 2019. Thesis, Brno University of Technology. Accessed August 05, 2020. http://hdl.handle.net/11012/14804.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Sileská, Silvia. “Ukázkové úlohy pro výuku automatizace: Sample tasks for automation education.” 2019. Web. 05 Aug 2020.

Vancouver:

Sileská S. Ukázkové úlohy pro výuku automatizace: Sample tasks for automation education. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2020 Aug 05]. Available from: http://hdl.handle.net/11012/14804.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Sileská S. Ukázkové úlohy pro výuku automatizace: Sample tasks for automation education. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/14804

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

9. Hejč, Michal. Celulární automat v evolučním procesu: Cellular Automaton in Evolutionary Process.

Degree: 2020, Brno University of Technology

 The aim of this master's theses it to focuse on the usage of genetic algorithms in combination with a technique of biologically inspired development in… (more)

Subjects/Keywords: Genetický algoritmus; celulární automat; development; evoluční návrh; kombinační logický obvod; polymorfní obvod; Genetic algorithm; cellular automaton; development; evolutionary design; combinational logic circuit; polymorph circuit

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hejč, M. (2020). Celulární automat v evolučním procesu: Cellular Automaton in Evolutionary Process. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/187755

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hejč, Michal. “Celulární automat v evolučním procesu: Cellular Automaton in Evolutionary Process.” 2020. Thesis, Brno University of Technology. Accessed August 05, 2020. http://hdl.handle.net/11012/187755.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hejč, Michal. “Celulární automat v evolučním procesu: Cellular Automaton in Evolutionary Process.” 2020. Web. 05 Aug 2020.

Vancouver:

Hejč M. Celulární automat v evolučním procesu: Cellular Automaton in Evolutionary Process. [Internet] [Thesis]. Brno University of Technology; 2020. [cited 2020 Aug 05]. Available from: http://hdl.handle.net/11012/187755.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hejč M. Celulární automat v evolučním procesu: Cellular Automaton in Evolutionary Process. [Thesis]. Brno University of Technology; 2020. Available from: http://hdl.handle.net/11012/187755

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

10. Hejč, Michal. Celulární automat v evolučním procesu: Cellular Automaton in Evolutionary Process.

Degree: 2020, Brno University of Technology

 The aim of this master's theses it to focuse on the usage of genetic algorithms in combination with a technique of biologically inspired development in… (more)

Subjects/Keywords: Genetický algoritmus; celulární automat; development; evoluční návrh; kombinační logický obvod; polymorfní obvod; Genetic algorithm; cellular automaton; development; evolutionary design; combinational logic circuit; polymorph circuit

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Hejč, M. (2020). Celulární automat v evolučním procesu: Cellular Automaton in Evolutionary Process. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/52754

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Hejč, Michal. “Celulární automat v evolučním procesu: Cellular Automaton in Evolutionary Process.” 2020. Thesis, Brno University of Technology. Accessed August 05, 2020. http://hdl.handle.net/11012/52754.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Hejč, Michal. “Celulární automat v evolučním procesu: Cellular Automaton in Evolutionary Process.” 2020. Web. 05 Aug 2020.

Vancouver:

Hejč M. Celulární automat v evolučním procesu: Cellular Automaton in Evolutionary Process. [Internet] [Thesis]. Brno University of Technology; 2020. [cited 2020 Aug 05]. Available from: http://hdl.handle.net/11012/52754.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Hejč M. Celulární automat v evolučním procesu: Cellular Automaton in Evolutionary Process. [Thesis]. Brno University of Technology; 2020. Available from: http://hdl.handle.net/11012/52754

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

11. Mrnuštík, Michal. Evoluční návrh využívající booleovské sítě: Evolutionary Design Using Random Boolean Networks.

Degree: 2020, Brno University of Technology

 This master's thesis introduces the Random Boolean Networks as a developmental model in the evolutionary design. The representation of the Random Boolean Networks is described.… (more)

Subjects/Keywords: Evoluční algoritmus; development; booleovská síť; kombinační obvod; řadicí síť; obrazový filtr.; Evolutionary design; development; Random Boolean Network; combinational circuit; sorting network; image filter.

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mrnuštík, M. (2020). Evoluční návrh využívající booleovské sítě: Evolutionary Design Using Random Boolean Networks. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/190105

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mrnuštík, Michal. “Evoluční návrh využívající booleovské sítě: Evolutionary Design Using Random Boolean Networks.” 2020. Thesis, Brno University of Technology. Accessed August 05, 2020. http://hdl.handle.net/11012/190105.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mrnuštík, Michal. “Evoluční návrh využívající booleovské sítě: Evolutionary Design Using Random Boolean Networks.” 2020. Web. 05 Aug 2020.

Vancouver:

Mrnuštík M. Evoluční návrh využívající booleovské sítě: Evolutionary Design Using Random Boolean Networks. [Internet] [Thesis]. Brno University of Technology; 2020. [cited 2020 Aug 05]. Available from: http://hdl.handle.net/11012/190105.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mrnuštík M. Evoluční návrh využívající booleovské sítě: Evolutionary Design Using Random Boolean Networks. [Thesis]. Brno University of Technology; 2020. Available from: http://hdl.handle.net/11012/190105

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

12. Kocnová, Jitka. Evoluční resyntéza kombinačních obvodů: Evolutionary Resynthesis of Combinational Circuits.

Degree: 2018, Brno University of Technology

 This master thesis is concerned about the resynthesis of combinational circuits with the help of evolutional principles. The first part of this text describes logic… (more)

Subjects/Keywords: kombinační obvod; syntéza; resyntéza; evoluční syntéza; evoluce; řez; graf; grafový algoritmus; combinational circuit; synthesis; resynthesis; evolutional synthesis; evolution; cut; graph; graph algorithm

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Kocnová, J. (2018). Evoluční resyntéza kombinačních obvodů: Evolutionary Resynthesis of Combinational Circuits. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/69596

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Kocnová, Jitka. “Evoluční resyntéza kombinačních obvodů: Evolutionary Resynthesis of Combinational Circuits.” 2018. Thesis, Brno University of Technology. Accessed August 05, 2020. http://hdl.handle.net/11012/69596.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Kocnová, Jitka. “Evoluční resyntéza kombinačních obvodů: Evolutionary Resynthesis of Combinational Circuits.” 2018. Web. 05 Aug 2020.

Vancouver:

Kocnová J. Evoluční resyntéza kombinačních obvodů: Evolutionary Resynthesis of Combinational Circuits. [Internet] [Thesis]. Brno University of Technology; 2018. [cited 2020 Aug 05]. Available from: http://hdl.handle.net/11012/69596.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Kocnová J. Evoluční resyntéza kombinačních obvodů: Evolutionary Resynthesis of Combinational Circuits. [Thesis]. Brno University of Technology; 2018. Available from: http://hdl.handle.net/11012/69596

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

13. Mrnuštík, Michal. Evoluční návrh využívající booleovské sítě: Evolutionary Design Using Random Boolean Networks.

Degree: 2019, Brno University of Technology

 This master's thesis introduces the Random Boolean Networks as a developmental model in the evolutionary design. The representation of the Random Boolean Networks is described.… (more)

Subjects/Keywords: Evoluční algoritmus; development; booleovská síť;  kombinační obvod; řadicí síť; obrazový filtr.; Evolutionary design; development; Random Boolean Network;   combinational circuit; sorting network; image filter.

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mrnuštík, M. (2019). Evoluční návrh využívající booleovské sítě: Evolutionary Design Using Random Boolean Networks. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/54263

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mrnuštík, Michal. “Evoluční návrh využívající booleovské sítě: Evolutionary Design Using Random Boolean Networks.” 2019. Thesis, Brno University of Technology. Accessed August 05, 2020. http://hdl.handle.net/11012/54263.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mrnuštík, Michal. “Evoluční návrh využívající booleovské sítě: Evolutionary Design Using Random Boolean Networks.” 2019. Web. 05 Aug 2020.

Vancouver:

Mrnuštík M. Evoluční návrh využívající booleovské sítě: Evolutionary Design Using Random Boolean Networks. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2020 Aug 05]. Available from: http://hdl.handle.net/11012/54263.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mrnuštík M. Evoluční návrh využívající booleovské sítě: Evolutionary Design Using Random Boolean Networks. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/54263

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

14. Mrnuštík, Michal. Evoluční návrh využívající booleovské sítě: Evolutionary Design Using Random Boolean Networks.

Degree: 2020, Brno University of Technology

 This master's thesis introduces the Random Boolean Networks as a developmental model in the evolutionary design. The representation of the Random Boolean Networks is described.… (more)

Subjects/Keywords: Evoluční algoritmus; development; booleovská síť; kombinační obvod; řadicí síť; obrazový filtr.; Evolutionary design; development; Random Boolean Network; combinational circuit; sorting network; image filter.

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mrnuštík, M. (2020). Evoluční návrh využívající booleovské sítě: Evolutionary Design Using Random Boolean Networks. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/188682

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mrnuštík, Michal. “Evoluční návrh využívající booleovské sítě: Evolutionary Design Using Random Boolean Networks.” 2020. Thesis, Brno University of Technology. Accessed August 05, 2020. http://hdl.handle.net/11012/188682.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mrnuštík, Michal. “Evoluční návrh využívající booleovské sítě: Evolutionary Design Using Random Boolean Networks.” 2020. Web. 05 Aug 2020.

Vancouver:

Mrnuštík M. Evoluční návrh využívající booleovské sítě: Evolutionary Design Using Random Boolean Networks. [Internet] [Thesis]. Brno University of Technology; 2020. [cited 2020 Aug 05]. Available from: http://hdl.handle.net/11012/188682.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mrnuštík M. Evoluční návrh využívající booleovské sítě: Evolutionary Design Using Random Boolean Networks. [Thesis]. Brno University of Technology; 2020. Available from: http://hdl.handle.net/11012/188682

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

15. Vašíček, Zdeněk. Acceleration Methods for Evolutionary Design of Digital Circuits: Acceleration Methods for Evolutionary Design of Digital Circuits.

Degree: 2019, Brno University of Technology

 Although many examples showing the merits of evolutionary design over conventional design techniques utilized in the field of digital circuits design have been published, the… (more)

Subjects/Keywords: návrh číslicových obvodů; evoluční optimalizace; evoluční návrh; násobička s konstantními koeficienty; filtrace obrazu; nelineární filtr; optimalizace kombinačních obvodů; FPGA akcelerace; digital circuit design; evolutionary optimization; evolutionary design; multiplier with constant coefficients; image filtering; nonlinear filter; optimization of combinational circuits; FPGA acceleration

Record DetailsSimilar RecordsGoogle PlusoneFacebookTwitterCiteULikeMendeleyreddit

APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Vašíček, Z. (2019). Acceleration Methods for Evolutionary Design of Digital Circuits: Acceleration Methods for Evolutionary Design of Digital Circuits. (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/63260

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Vašíček, Zdeněk. “Acceleration Methods for Evolutionary Design of Digital Circuits: Acceleration Methods for Evolutionary Design of Digital Circuits.” 2019. Thesis, Brno University of Technology. Accessed August 05, 2020. http://hdl.handle.net/11012/63260.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Vašíček, Zdeněk. “Acceleration Methods for Evolutionary Design of Digital Circuits: Acceleration Methods for Evolutionary Design of Digital Circuits.” 2019. Web. 05 Aug 2020.

Vancouver:

Vašíček Z. Acceleration Methods for Evolutionary Design of Digital Circuits: Acceleration Methods for Evolutionary Design of Digital Circuits. [Internet] [Thesis]. Brno University of Technology; 2019. [cited 2020 Aug 05]. Available from: http://hdl.handle.net/11012/63260.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Vašíček Z. Acceleration Methods for Evolutionary Design of Digital Circuits: Acceleration Methods for Evolutionary Design of Digital Circuits. [Thesis]. Brno University of Technology; 2019. Available from: http://hdl.handle.net/11012/63260

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

.