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You searched for subject:(clock jitter tolerance). Showing records 1 – 3 of 3 total matches.

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Texas A&M University

1. Ahmed, Ramy 1981-. Jitter-Tolerance and Blocker-Tolerance of Delta-Sigma Analog-to-Digital Converters for Saw-Less Multi-Standard Receivers.

Degree: 2012, Texas A&M University

The quest for multi-standard and software-defined radio (SDR) receivers calls for high flexibility in the receiver building-blocks so that to accommodate several wireless services using a single receiver chain in mobile handsets. A potential approach to achieve flexibility in the receiver is to move the analog-to-digital converter (ADC) closer to the antenna so that to exploit the enormous advances in digital signal processing, in terms of technology scaling, speed, and programmability. In this context, continuous-time (CT) delta-sigma (??) ADCs show up as an attractive option. CT ?? ADCs have gained significant attention in wideband receivers, owing to their amenability to operate at a higher-speed with lower power consumption compared to discrete-time (DT) implementations, inherent anti-aliasing, and robustness to sampling errors in the loop quantizer. However, as the ADC moves closer to the antenna, several blockers and interferers are present at the ADC input. Thus, it is important to investigate the sensitivities of CT ?? ADCs to out-of-band (OOB) blockers and find the design considerations and solutions needed to maintain the performance of CT ?? modulators in presence of OOB blockers. Also, CT ?? modulators suffer from a critical limitation due to their high sensitivity to the clock-jitter in the feedback digital-to-analog converter (DAC) sampling-clock. In this context, the research work presented in this thesis is divided into two main parts. First, the effects of OOB blockers on the performance of CT ?? modulators are investigated and analyzed through a detailed study. A potential solution is proposed to alleviate the effect of noise folding caused by intermodulation between OOB blockers and shaped quantization noise at the modulator input stage through current-mode integration. Second, a novel DAC solution that achieves tolerance to pulse-width jitter by spectrally shaping the jitter induced errors is presented. This jitter-tolerant DAC doesn?t add extra requirements on the slew-rate or the gain-bandwidth product of the loop filter amplifiers. The proposed DAC was implemented in a 90nm CMOS prototype chip and provided a measured attenuation for in-band jitter induced noise by 26.7dB and in-band DAC noise by 5dB, compared to conventional current-steering DAC, and consumes 719?watts from 1.3V supply. Advisors/Committee Members: Hoyos, Sebastian (advisor), Silva-Mart?nez, Jose (committee member), Kish, Laszlo (committee member), El-Halwagi, Mahmoud (committee member).

Subjects/Keywords: Delta-Sigma (??) modulators; analog-to-digital converter (ADC); blocker-tolerance; clock-jitter; continuous-time (CT) ??; multi-standard receivers; software-defined radio (SDR)

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ahmed, R. 1. (2012). Jitter-Tolerance and Blocker-Tolerance of Delta-Sigma Analog-to-Digital Converters for Saw-Less Multi-Standard Receivers. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/148047

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Ahmed, Ramy 1981-. “Jitter-Tolerance and Blocker-Tolerance of Delta-Sigma Analog-to-Digital Converters for Saw-Less Multi-Standard Receivers.” 2012. Thesis, Texas A&M University. Accessed December 15, 2018. http://hdl.handle.net/1969.1/148047.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Ahmed, Ramy 1981-. “Jitter-Tolerance and Blocker-Tolerance of Delta-Sigma Analog-to-Digital Converters for Saw-Less Multi-Standard Receivers.” 2012. Web. 15 Dec 2018.

Vancouver:

Ahmed R1. Jitter-Tolerance and Blocker-Tolerance of Delta-Sigma Analog-to-Digital Converters for Saw-Less Multi-Standard Receivers. [Internet] [Thesis]. Texas A&M University; 2012. [cited 2018 Dec 15]. Available from: http://hdl.handle.net/1969.1/148047.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Ahmed R1. Jitter-Tolerance and Blocker-Tolerance of Delta-Sigma Analog-to-Digital Converters for Saw-Less Multi-Standard Receivers. [Thesis]. Texas A&M University; 2012. Available from: http://hdl.handle.net/1969.1/148047

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Texas A&M University

2. Padyana, Aravind 1983-. Design Considerations for Wide Bandwidth Continuous-Time Low-Pass Delta-Sigma Analog-to-Digital Converters.

Degree: 2010, Texas A&M University

Continuous-time (CT) delta-sigma (??) analog-to-digital converters (ADC) have emerged as the popular choice to achieve high resolution and large bandwidth due to their low cost, power efficiency, inherent anti-alias filtering and digital post processing capabilities. This work presents a detailed system-level design methodology for a low-power CT ?? ADC. Design considerations and trade-offs at the system-level are presented. A novel technique to reduce the sensitivity of the proposed ADC to clock jitter-induced feedback charge variations by employing a hybrid digital-to-analog converter (DAC) based on switched-capacitor circuits is also presented. The proposed technique provides a clock jitter tolerance of up to 5ps (rms). The system is implemented using a 5th order active-RC loop filter, 9-level quantizer and DAC, achieving 74dB SNDR over 20MHz signal bandwidth, at 400MHz sampling frequency in a 1.2V, 90 nm CMOS technology. A novel technique to improve the linearity of the feedback digital-to-analog converters (DAC) in a target 11-bits resolution, 100MHz bandwidth, 2GHz sampling frequency CT ?? ADC is also presented in this work. DAC linearity is improved by combining dynamic element matching and automatic background calibration to achieve up to 18dB improvement in the SNR. Transistor-level circuit implementation of the proposed technique was done in a 1.8V, 0.18?m BiCMOS process. Advisors/Committee Members: Silva-Martinez, Jose (advisor), Karsilayan, Aydin I (advisor), Li, Peng (committee member), Friesen, Donald K (committee member).

Subjects/Keywords: self-calibration; dynamic element matching; multi-bit dac; digital-to-analog converter; clock jitter tolerance; delta-sigma adc; analog-to-digital converter

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Padyana, A. 1. (2010). Design Considerations for Wide Bandwidth Continuous-Time Low-Pass Delta-Sigma Analog-to-Digital Converters. (Thesis). Texas A&M University. Retrieved from http://hdl.handle.net/1969.1/148453

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Padyana, Aravind 1983-. “Design Considerations for Wide Bandwidth Continuous-Time Low-Pass Delta-Sigma Analog-to-Digital Converters.” 2010. Thesis, Texas A&M University. Accessed December 15, 2018. http://hdl.handle.net/1969.1/148453.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Padyana, Aravind 1983-. “Design Considerations for Wide Bandwidth Continuous-Time Low-Pass Delta-Sigma Analog-to-Digital Converters.” 2010. Web. 15 Dec 2018.

Vancouver:

Padyana A1. Design Considerations for Wide Bandwidth Continuous-Time Low-Pass Delta-Sigma Analog-to-Digital Converters. [Internet] [Thesis]. Texas A&M University; 2010. [cited 2018 Dec 15]. Available from: http://hdl.handle.net/1969.1/148453.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Padyana A1. Design Considerations for Wide Bandwidth Continuous-Time Low-Pass Delta-Sigma Analog-to-Digital Converters. [Thesis]. Texas A&M University; 2010. Available from: http://hdl.handle.net/1969.1/148453

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Toronto

3. Sarvari, Siamak. A 5Gb/s Speculative DFE for 2x Blind ADC-based Receivers in 65-nm CMOS.

Degree: 2010, University of Toronto

This thesis proposes a decision-feedback equalizer (DFE) scheme for blind ADC-based receivers to overcome the challenges introduced by blind sampling. It presents the design, simulation, and implementation of a 5Gb/s speculative DFE for a 2x blind ADC-based receiver. The complete receiver, including the ADC, the DFE, and a 2x blind clock and data recovery (CDR) circuit, is implemented in Fujitsu’s 65-nm CMOS process. Measurements of the fabricated test-chip confirm 5Gb/s data recovery with bit error rate (BER) less than 1e−12 in the presence of a test channel introducing 13.3dB of attenuation at the Nyquist frequency of 2.5GHz. The receiver tolerates 0.24UIpp of high-frequency sinusoidal jitter (SJ) in this case. Without the DFE, the BER exceeds 1e−8 even when no SJ is applied.

MAST

Advisors/Committee Members: Sheikholeslami, Ali, Electrical and Computer Engineering.

Subjects/Keywords: high-speed signaling; decision-feedback equalizer (DFE); blind sampling; ADC-based receiver; speculative; look-ahead; clock and data recovery (CDR); blind oversampling; CMOS; jitter tolerance; eye diagram; equalizer; 0544

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sarvari, S. (2010). A 5Gb/s Speculative DFE for 2x Blind ADC-based Receivers in 65-nm CMOS. (Masters Thesis). University of Toronto. Retrieved from http://hdl.handle.net/1807/29987

Chicago Manual of Style (16th Edition):

Sarvari, Siamak. “A 5Gb/s Speculative DFE for 2x Blind ADC-based Receivers in 65-nm CMOS.” 2010. Masters Thesis, University of Toronto. Accessed December 15, 2018. http://hdl.handle.net/1807/29987.

MLA Handbook (7th Edition):

Sarvari, Siamak. “A 5Gb/s Speculative DFE for 2x Blind ADC-based Receivers in 65-nm CMOS.” 2010. Web. 15 Dec 2018.

Vancouver:

Sarvari S. A 5Gb/s Speculative DFE for 2x Blind ADC-based Receivers in 65-nm CMOS. [Internet] [Masters thesis]. University of Toronto; 2010. [cited 2018 Dec 15]. Available from: http://hdl.handle.net/1807/29987.

Council of Science Editors:

Sarvari S. A 5Gb/s Speculative DFE for 2x Blind ADC-based Receivers in 65-nm CMOS. [Masters Thesis]. University of Toronto; 2010. Available from: http://hdl.handle.net/1807/29987

.