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You searched for subject:(biasing). Showing records 1 – 30 of 57 total matches.

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University of New Mexico

1. Desjardins, Tiffany. Dynamics of Turbulence and Flows in a Helicon Plasma Under Electrode Biasing.

Degree: Electrical and Computer Engineering, 2016, University of New Mexico

 Experimental studies investigating turbulence, and sheared flow were carried out using the linear Helicon-Cathode (HelCat) device. Without any outside influence, such as biasing or momentum… (more)

Subjects/Keywords: helcat; plasma; turbulence; biasing; helicon

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APA (6th Edition):

Desjardins, T. (2016). Dynamics of Turbulence and Flows in a Helicon Plasma Under Electrode Biasing. (Doctoral Dissertation). University of New Mexico. Retrieved from http://hdl.handle.net/1928/32286

Chicago Manual of Style (16th Edition):

Desjardins, Tiffany. “Dynamics of Turbulence and Flows in a Helicon Plasma Under Electrode Biasing.” 2016. Doctoral Dissertation, University of New Mexico. Accessed September 23, 2019. http://hdl.handle.net/1928/32286.

MLA Handbook (7th Edition):

Desjardins, Tiffany. “Dynamics of Turbulence and Flows in a Helicon Plasma Under Electrode Biasing.” 2016. Web. 23 Sep 2019.

Vancouver:

Desjardins T. Dynamics of Turbulence and Flows in a Helicon Plasma Under Electrode Biasing. [Internet] [Doctoral dissertation]. University of New Mexico; 2016. [cited 2019 Sep 23]. Available from: http://hdl.handle.net/1928/32286.

Council of Science Editors:

Desjardins T. Dynamics of Turbulence and Flows in a Helicon Plasma Under Electrode Biasing. [Doctoral Dissertation]. University of New Mexico; 2016. Available from: http://hdl.handle.net/1928/32286


University of Minnesota

2. Palani, Rakesh Kumar. Design of PVT Tolerant Inverter Based Circuits for Low Supply Voltages.

Degree: PhD, Electrical Engineering, 2015, University of Minnesota

 Rapid advances in the field of integrated circuit design has been advantageous from the point of view of cost and miniaturization. Although technology scaling is… (more)

Subjects/Keywords: Amplifiers; Biasing; filters; Inverters; PVT; SAR ADC

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APA (6th Edition):

Palani, R. K. (2015). Design of PVT Tolerant Inverter Based Circuits for Low Supply Voltages. (Doctoral Dissertation). University of Minnesota. Retrieved from http://hdl.handle.net/11299/190512

Chicago Manual of Style (16th Edition):

Palani, Rakesh Kumar. “Design of PVT Tolerant Inverter Based Circuits for Low Supply Voltages.” 2015. Doctoral Dissertation, University of Minnesota. Accessed September 23, 2019. http://hdl.handle.net/11299/190512.

MLA Handbook (7th Edition):

Palani, Rakesh Kumar. “Design of PVT Tolerant Inverter Based Circuits for Low Supply Voltages.” 2015. Web. 23 Sep 2019.

Vancouver:

Palani RK. Design of PVT Tolerant Inverter Based Circuits for Low Supply Voltages. [Internet] [Doctoral dissertation]. University of Minnesota; 2015. [cited 2019 Sep 23]. Available from: http://hdl.handle.net/11299/190512.

Council of Science Editors:

Palani RK. Design of PVT Tolerant Inverter Based Circuits for Low Supply Voltages. [Doctoral Dissertation]. University of Minnesota; 2015. Available from: http://hdl.handle.net/11299/190512

3. Lacruche, Marc. Caractérisation sécuritaire de circuits basse-consommation face aux attaques par laser : Security evaluation of low-power devices against laser fault attacks.

Degree: Docteur es, Micro et Nanoélectronique, 2016, Aix Marseille Université

La minimisation de la consommation d'énergie est primordiale lors de la conception de circuits. Cependant, il est nécessaire de s'assurer que cela ne compromette pas… (more)

Subjects/Keywords: Injection de fautes; Body biasing; Laser; Cryptographie; Basse consommation; Sécurité; Fault attacks; Body biasing; Laser; Cryptography; Low power; Security

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APA (6th Edition):

Lacruche, M. (2016). Caractérisation sécuritaire de circuits basse-consommation face aux attaques par laser : Security evaluation of low-power devices against laser fault attacks. (Doctoral Dissertation). Aix Marseille Université. Retrieved from http://www.theses.fr/2016AIXM4331

Chicago Manual of Style (16th Edition):

Lacruche, Marc. “Caractérisation sécuritaire de circuits basse-consommation face aux attaques par laser : Security evaluation of low-power devices against laser fault attacks.” 2016. Doctoral Dissertation, Aix Marseille Université. Accessed September 23, 2019. http://www.theses.fr/2016AIXM4331.

MLA Handbook (7th Edition):

Lacruche, Marc. “Caractérisation sécuritaire de circuits basse-consommation face aux attaques par laser : Security evaluation of low-power devices against laser fault attacks.” 2016. Web. 23 Sep 2019.

Vancouver:

Lacruche M. Caractérisation sécuritaire de circuits basse-consommation face aux attaques par laser : Security evaluation of low-power devices against laser fault attacks. [Internet] [Doctoral dissertation]. Aix Marseille Université 2016. [cited 2019 Sep 23]. Available from: http://www.theses.fr/2016AIXM4331.

Council of Science Editors:

Lacruche M. Caractérisation sécuritaire de circuits basse-consommation face aux attaques par laser : Security evaluation of low-power devices against laser fault attacks. [Doctoral Dissertation]. Aix Marseille Université 2016. Available from: http://www.theses.fr/2016AIXM4331

4. Kheirallah, Rida. Etude statistique de l’énergie dans les circuits intégrés CMOS-FDSOI : caractérisation et optimisation : Statistical study of the energy in CMOS-FDSOI integrated circuits : characterization and optimization.

Degree: Docteur es, Systèmes automatiques et micro-électroniques, 2016, Montpellier

Pour les nœuds technologiques avancés, la consommation statique des circuits intégrés est devenue un facteur essentiel de l'industrie microélectronique. L'efficacité énergétique des circuits est mesurée… (more)

Subjects/Keywords: Énergie; Compromis Délai-Puissance; Technologie FDSOI; Variabilité de porocess; Body biasing; Energy; Power-Delay tradeoff; FDSOI Technology; Process variability; Body biasing

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APA (6th Edition):

Kheirallah, R. (2016). Etude statistique de l’énergie dans les circuits intégrés CMOS-FDSOI : caractérisation et optimisation : Statistical study of the energy in CMOS-FDSOI integrated circuits : characterization and optimization. (Doctoral Dissertation). Montpellier. Retrieved from http://www.theses.fr/2016MONTT342

Chicago Manual of Style (16th Edition):

Kheirallah, Rida. “Etude statistique de l’énergie dans les circuits intégrés CMOS-FDSOI : caractérisation et optimisation : Statistical study of the energy in CMOS-FDSOI integrated circuits : characterization and optimization.” 2016. Doctoral Dissertation, Montpellier. Accessed September 23, 2019. http://www.theses.fr/2016MONTT342.

MLA Handbook (7th Edition):

Kheirallah, Rida. “Etude statistique de l’énergie dans les circuits intégrés CMOS-FDSOI : caractérisation et optimisation : Statistical study of the energy in CMOS-FDSOI integrated circuits : characterization and optimization.” 2016. Web. 23 Sep 2019.

Vancouver:

Kheirallah R. Etude statistique de l’énergie dans les circuits intégrés CMOS-FDSOI : caractérisation et optimisation : Statistical study of the energy in CMOS-FDSOI integrated circuits : characterization and optimization. [Internet] [Doctoral dissertation]. Montpellier; 2016. [cited 2019 Sep 23]. Available from: http://www.theses.fr/2016MONTT342.

Council of Science Editors:

Kheirallah R. Etude statistique de l’énergie dans les circuits intégrés CMOS-FDSOI : caractérisation et optimisation : Statistical study of the energy in CMOS-FDSOI integrated circuits : characterization and optimization. [Doctoral Dissertation]. Montpellier; 2016. Available from: http://www.theses.fr/2016MONTT342


NSYSU

5. Liu, Yi-cheng. Mixed-Voltage-Tolerant I/O Cell With Dynamic Biasing and Sub 3ÃVDD Wide Range Mixed-Voltage-Tolerant I/O Cell.

Degree: Master, Electrical Engineering, 2009, NSYSU

 The thesis is composed of tow topics: a fully bidirectional mixed- voltage-tolerant I/O cell using a new output stage circuit and a sub-3ÃVDD wide range… (more)

Subjects/Keywords: I/O cell; Mixed-Voltage-Tolerant; Dynamic Biasing; Sub 3ÃVDD

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APA (6th Edition):

Liu, Y. (2009). Mixed-Voltage-Tolerant I/O Cell With Dynamic Biasing and Sub 3ÃVDD Wide Range Mixed-Voltage-Tolerant I/O Cell. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701109-205501

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Liu, Yi-cheng. “Mixed-Voltage-Tolerant I/O Cell With Dynamic Biasing and Sub 3ÃVDD Wide Range Mixed-Voltage-Tolerant I/O Cell.” 2009. Thesis, NSYSU. Accessed September 23, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701109-205501.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Liu, Yi-cheng. “Mixed-Voltage-Tolerant I/O Cell With Dynamic Biasing and Sub 3ÃVDD Wide Range Mixed-Voltage-Tolerant I/O Cell.” 2009. Web. 23 Sep 2019.

Vancouver:

Liu Y. Mixed-Voltage-Tolerant I/O Cell With Dynamic Biasing and Sub 3ÃVDD Wide Range Mixed-Voltage-Tolerant I/O Cell. [Internet] [Thesis]. NSYSU; 2009. [cited 2019 Sep 23]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701109-205501.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Liu Y. Mixed-Voltage-Tolerant I/O Cell With Dynamic Biasing and Sub 3ÃVDD Wide Range Mixed-Voltage-Tolerant I/O Cell. [Thesis]. NSYSU; 2009. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0701109-205501

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Delft University of Technology

6. Christoforou, S. A zero-variance based scheme for Monte Carlo criticality simulations.

Degree: 2010, Delft University of Technology

 The ability of the Monte Carlo method to solve particle transport problems by simulating the particle behaviour makes it a very useful technique in nuclear… (more)

Subjects/Keywords: Monte Carlo; biasing; adjoint; criticality

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APA (6th Edition):

Christoforou, S. (2010). A zero-variance based scheme for Monte Carlo criticality simulations. (Doctoral Dissertation). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:8799a094-5a09-4670-853a-4bd1626fce74 ; urn:NBN:nl:ui:24-uuid:8799a094-5a09-4670-853a-4bd1626fce74 ; urn:NBN:nl:ui:24-uuid:8799a094-5a09-4670-853a-4bd1626fce74 ; http://resolver.tudelft.nl/uuid:8799a094-5a09-4670-853a-4bd1626fce74

Chicago Manual of Style (16th Edition):

Christoforou, S. “A zero-variance based scheme for Monte Carlo criticality simulations.” 2010. Doctoral Dissertation, Delft University of Technology. Accessed September 23, 2019. http://resolver.tudelft.nl/uuid:8799a094-5a09-4670-853a-4bd1626fce74 ; urn:NBN:nl:ui:24-uuid:8799a094-5a09-4670-853a-4bd1626fce74 ; urn:NBN:nl:ui:24-uuid:8799a094-5a09-4670-853a-4bd1626fce74 ; http://resolver.tudelft.nl/uuid:8799a094-5a09-4670-853a-4bd1626fce74.

MLA Handbook (7th Edition):

Christoforou, S. “A zero-variance based scheme for Monte Carlo criticality simulations.” 2010. Web. 23 Sep 2019.

Vancouver:

Christoforou S. A zero-variance based scheme for Monte Carlo criticality simulations. [Internet] [Doctoral dissertation]. Delft University of Technology; 2010. [cited 2019 Sep 23]. Available from: http://resolver.tudelft.nl/uuid:8799a094-5a09-4670-853a-4bd1626fce74 ; urn:NBN:nl:ui:24-uuid:8799a094-5a09-4670-853a-4bd1626fce74 ; urn:NBN:nl:ui:24-uuid:8799a094-5a09-4670-853a-4bd1626fce74 ; http://resolver.tudelft.nl/uuid:8799a094-5a09-4670-853a-4bd1626fce74.

Council of Science Editors:

Christoforou S. A zero-variance based scheme for Monte Carlo criticality simulations. [Doctoral Dissertation]. Delft University of Technology; 2010. Available from: http://resolver.tudelft.nl/uuid:8799a094-5a09-4670-853a-4bd1626fce74 ; urn:NBN:nl:ui:24-uuid:8799a094-5a09-4670-853a-4bd1626fce74 ; urn:NBN:nl:ui:24-uuid:8799a094-5a09-4670-853a-4bd1626fce74 ; http://resolver.tudelft.nl/uuid:8799a094-5a09-4670-853a-4bd1626fce74


Delft University of Technology

7. Adejumo, K.O. Investigation of the relation between growth mechanism and material properties of amorphous silicon solar cells:.

Degree: 2009, Delft University of Technology

 Thin film silicon solar cells are produced by using plasma deposition techniques. With this technique a thin film layer of silicon, most commonly amorphous silicon… (more)

Subjects/Keywords: amorphous growth mechanism; material properties; Pulse shaped biasing

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APA (6th Edition):

Adejumo, K. O. (2009). Investigation of the relation between growth mechanism and material properties of amorphous silicon solar cells:. (Masters Thesis). Delft University of Technology. Retrieved from http://resolver.tudelft.nl/uuid:c3e295b7-c9fa-4ebd-b61b-727bb4e14aee

Chicago Manual of Style (16th Edition):

Adejumo, K O. “Investigation of the relation between growth mechanism and material properties of amorphous silicon solar cells:.” 2009. Masters Thesis, Delft University of Technology. Accessed September 23, 2019. http://resolver.tudelft.nl/uuid:c3e295b7-c9fa-4ebd-b61b-727bb4e14aee.

MLA Handbook (7th Edition):

Adejumo, K O. “Investigation of the relation between growth mechanism and material properties of amorphous silicon solar cells:.” 2009. Web. 23 Sep 2019.

Vancouver:

Adejumo KO. Investigation of the relation between growth mechanism and material properties of amorphous silicon solar cells:. [Internet] [Masters thesis]. Delft University of Technology; 2009. [cited 2019 Sep 23]. Available from: http://resolver.tudelft.nl/uuid:c3e295b7-c9fa-4ebd-b61b-727bb4e14aee.

Council of Science Editors:

Adejumo KO. Investigation of the relation between growth mechanism and material properties of amorphous silicon solar cells:. [Masters Thesis]. Delft University of Technology; 2009. Available from: http://resolver.tudelft.nl/uuid:c3e295b7-c9fa-4ebd-b61b-727bb4e14aee


University of Illinois – Urbana-Champaign

8. Ryu, Sann Hee. Visuals, inferences, and consumers' biased information seeking.

Degree: PhD, Communications and Media, 2017, University of Illinois – Urbana-Champaign

 The purpose of this research is to investigate how varying product visuals affect consumers’ selective exposure, and whether inferences and attitudes toward a newly encountered… (more)

Subjects/Keywords: Visual biasing effects; Inferential beliefs; Brand attitudes; Confirmation bias; Selective exposure

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APA (6th Edition):

Ryu, S. H. (2017). Visuals, inferences, and consumers' biased information seeking. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/97728

Chicago Manual of Style (16th Edition):

Ryu, Sann Hee. “Visuals, inferences, and consumers' biased information seeking.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed September 23, 2019. http://hdl.handle.net/2142/97728.

MLA Handbook (7th Edition):

Ryu, Sann Hee. “Visuals, inferences, and consumers' biased information seeking.” 2017. Web. 23 Sep 2019.

Vancouver:

Ryu SH. Visuals, inferences, and consumers' biased information seeking. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2019 Sep 23]. Available from: http://hdl.handle.net/2142/97728.

Council of Science Editors:

Ryu SH. Visuals, inferences, and consumers' biased information seeking. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/97728


University of Utah

9. Ghosh, Amlan. Low-power operation of microprocessor systems in the presence of process variation.

Degree: PhD, Electrical & Computer Engineering;, 2010, University of Utah

 With the scaling of MOSFET dimensions and the performance enhancement features in the MOSFET, semiconductor manufacturing variation has also increased. Because of process variation and… (more)

Subjects/Keywords: Body biasing; Compensation; Design for manufacturing; Process variation; Slew rate; Within die variation; MOSFET

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APA (6th Edition):

Ghosh, A. (2010). Low-power operation of microprocessor systems in the presence of process variation. (Doctoral Dissertation). University of Utah. Retrieved from http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/2033/rec/721

Chicago Manual of Style (16th Edition):

Ghosh, Amlan. “Low-power operation of microprocessor systems in the presence of process variation.” 2010. Doctoral Dissertation, University of Utah. Accessed September 23, 2019. http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/2033/rec/721.

MLA Handbook (7th Edition):

Ghosh, Amlan. “Low-power operation of microprocessor systems in the presence of process variation.” 2010. Web. 23 Sep 2019.

Vancouver:

Ghosh A. Low-power operation of microprocessor systems in the presence of process variation. [Internet] [Doctoral dissertation]. University of Utah; 2010. [cited 2019 Sep 23]. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/2033/rec/721.

Council of Science Editors:

Ghosh A. Low-power operation of microprocessor systems in the presence of process variation. [Doctoral Dissertation]. University of Utah; 2010. Available from: http://content.lib.utah.edu/cdm/singleitem/collection/etd2/id/2033/rec/721


University of Florida

10. Harb, Shadi. Time Delay Measurement and Voltage Reference Circuits Compatible for Embedded Test in 3D Stacked ICs.

Degree: PhD, Electrical and Computer Engineering, 2010, University of Florida

 3D Technology is emerging as an attractive way to sustain Moore s law, by making it possible for highly integrated, high performance, cost effective compact… (more)

Subjects/Keywords: 3d; bandgap; biasing; bist; crosstalk; delay; embedded; gtl; integrity; reference; signal; stacked; test; time; tsv

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APA (6th Edition):

Harb, S. (2010). Time Delay Measurement and Voltage Reference Circuits Compatible for Embedded Test in 3D Stacked ICs. (Doctoral Dissertation). University of Florida. Retrieved from http://ufdc.ufl.edu/UFE0041423

Chicago Manual of Style (16th Edition):

Harb, Shadi. “Time Delay Measurement and Voltage Reference Circuits Compatible for Embedded Test in 3D Stacked ICs.” 2010. Doctoral Dissertation, University of Florida. Accessed September 23, 2019. http://ufdc.ufl.edu/UFE0041423.

MLA Handbook (7th Edition):

Harb, Shadi. “Time Delay Measurement and Voltage Reference Circuits Compatible for Embedded Test in 3D Stacked ICs.” 2010. Web. 23 Sep 2019.

Vancouver:

Harb S. Time Delay Measurement and Voltage Reference Circuits Compatible for Embedded Test in 3D Stacked ICs. [Internet] [Doctoral dissertation]. University of Florida; 2010. [cited 2019 Sep 23]. Available from: http://ufdc.ufl.edu/UFE0041423.

Council of Science Editors:

Harb S. Time Delay Measurement and Voltage Reference Circuits Compatible for Embedded Test in 3D Stacked ICs. [Doctoral Dissertation]. University of Florida; 2010. Available from: http://ufdc.ufl.edu/UFE0041423


University of Iowa

11. Griffioen, Amber Leigh. The irrational project: toward a different understanding of self-deception.

Degree: PhD, Philosophy, 2010, University of Iowa

  This dissertation focuses on questions regarding the metaphysical and psychological possibility of self-deception and attempts to show that self-deception is a phenomenon best characterized… (more)

Subjects/Keywords: biasing; intention; irrationality; partitioned-mind theories; philosophy of action; self-deception; Philosophy

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APA (6th Edition):

Griffioen, A. L. (2010). The irrational project: toward a different understanding of self-deception. (Doctoral Dissertation). University of Iowa. Retrieved from https://ir.uiowa.edu/etd/1461

Chicago Manual of Style (16th Edition):

Griffioen, Amber Leigh. “The irrational project: toward a different understanding of self-deception.” 2010. Doctoral Dissertation, University of Iowa. Accessed September 23, 2019. https://ir.uiowa.edu/etd/1461.

MLA Handbook (7th Edition):

Griffioen, Amber Leigh. “The irrational project: toward a different understanding of self-deception.” 2010. Web. 23 Sep 2019.

Vancouver:

Griffioen AL. The irrational project: toward a different understanding of self-deception. [Internet] [Doctoral dissertation]. University of Iowa; 2010. [cited 2019 Sep 23]. Available from: https://ir.uiowa.edu/etd/1461.

Council of Science Editors:

Griffioen AL. The irrational project: toward a different understanding of self-deception. [Doctoral Dissertation]. University of Iowa; 2010. Available from: https://ir.uiowa.edu/etd/1461


University of Edinburgh

12. Noorizadeh, Emad. Highly degenerate diffusions for sampling molecular systems.

Degree: PhD, 2010, University of Edinburgh

 This work is concerned with sampling and computation of rare events in molecular systems. In particular, we present new methods for sampling the canonical ensemble… (more)

Subjects/Keywords: 621; sampling; Boltzmann-Gibbs probability measure; degenerate diffusion; adaptive biasing force technique

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APA (6th Edition):

Noorizadeh, E. (2010). Highly degenerate diffusions for sampling molecular systems. (Doctoral Dissertation). University of Edinburgh. Retrieved from http://hdl.handle.net/1842/7584

Chicago Manual of Style (16th Edition):

Noorizadeh, Emad. “Highly degenerate diffusions for sampling molecular systems.” 2010. Doctoral Dissertation, University of Edinburgh. Accessed September 23, 2019. http://hdl.handle.net/1842/7584.

MLA Handbook (7th Edition):

Noorizadeh, Emad. “Highly degenerate diffusions for sampling molecular systems.” 2010. Web. 23 Sep 2019.

Vancouver:

Noorizadeh E. Highly degenerate diffusions for sampling molecular systems. [Internet] [Doctoral dissertation]. University of Edinburgh; 2010. [cited 2019 Sep 23]. Available from: http://hdl.handle.net/1842/7584.

Council of Science Editors:

Noorizadeh E. Highly degenerate diffusions for sampling molecular systems. [Doctoral Dissertation]. University of Edinburgh; 2010. Available from: http://hdl.handle.net/1842/7584


University of Arizona

13. Batel, Essa. The Effect of Sentence Contexts on Second Language Word Recognition .

Degree: 2019, University of Arizona

 This dissertation consists of three experiments testing various aspects of sentence processing in non-native English speakers. Experiment 1 tested the effect of constraining sentence context… (more)

Subjects/Keywords: Ambiguous Words; Biasing Context; First Language (L1); Reaction Times (RTs); Second Language (L2); Sentence Constraint

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APA (6th Edition):

Batel, E. (2019). The Effect of Sentence Contexts on Second Language Word Recognition . (Doctoral Dissertation). University of Arizona. Retrieved from http://hdl.handle.net/10150/631949

Chicago Manual of Style (16th Edition):

Batel, Essa. “The Effect of Sentence Contexts on Second Language Word Recognition .” 2019. Doctoral Dissertation, University of Arizona. Accessed September 23, 2019. http://hdl.handle.net/10150/631949.

MLA Handbook (7th Edition):

Batel, Essa. “The Effect of Sentence Contexts on Second Language Word Recognition .” 2019. Web. 23 Sep 2019.

Vancouver:

Batel E. The Effect of Sentence Contexts on Second Language Word Recognition . [Internet] [Doctoral dissertation]. University of Arizona; 2019. [cited 2019 Sep 23]. Available from: http://hdl.handle.net/10150/631949.

Council of Science Editors:

Batel E. The Effect of Sentence Contexts on Second Language Word Recognition . [Doctoral Dissertation]. University of Arizona; 2019. Available from: http://hdl.handle.net/10150/631949

14. Chitra, R Nayak. Studies on Chaos and Synchronization in ac-driven Josephson junctions.

Degree: Physics, 2008, Cochin University of Science and Technology

The main goal of this thesis is to study the dynamics of Josephson junction system in the presence of an external rf-biasing.A system of two… (more)

Subjects/Keywords: Chaos; Synchronization; Josephson junctions; ac biasing; Physics

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APA (6th Edition):

Chitra, R. N. (2008). Studies on Chaos and Synchronization in ac-driven Josephson junctions. (Thesis). Cochin University of Science and Technology. Retrieved from http://dyuthi.cusat.ac.in/purl/2904

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Chitra, R Nayak. “Studies on Chaos and Synchronization in ac-driven Josephson junctions.” 2008. Thesis, Cochin University of Science and Technology. Accessed September 23, 2019. http://dyuthi.cusat.ac.in/purl/2904.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Chitra, R Nayak. “Studies on Chaos and Synchronization in ac-driven Josephson junctions.” 2008. Web. 23 Sep 2019.

Vancouver:

Chitra RN. Studies on Chaos and Synchronization in ac-driven Josephson junctions. [Internet] [Thesis]. Cochin University of Science and Technology; 2008. [cited 2019 Sep 23]. Available from: http://dyuthi.cusat.ac.in/purl/2904.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Chitra RN. Studies on Chaos and Synchronization in ac-driven Josephson junctions. [Thesis]. Cochin University of Science and Technology; 2008. Available from: http://dyuthi.cusat.ac.in/purl/2904

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Purdue University

15. Mohammad, Imaduddin. Integrated DC-DC boost converters using CMOS silicon on Sapphire Technology.

Degree: MS, Electrical and Computer Engineering, 2014, Purdue University

  With the recent advancements in semiconductor manufacturing towards smaller, faster and more efficient microelectronic systems, the problems of increasing leakage current and reduced breakdown… (more)

Subjects/Keywords: Applied sciences; Dc-dc boost converter; Dynamic biasing; Fully-integrated; On-chip; Stacking; Transformerless; Electrical and Computer Engineering

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Mohammad, I. (2014). Integrated DC-DC boost converters using CMOS silicon on Sapphire Technology. (Thesis). Purdue University. Retrieved from http://docs.lib.purdue.edu/open_access_theses/456

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Mohammad, Imaduddin. “Integrated DC-DC boost converters using CMOS silicon on Sapphire Technology.” 2014. Thesis, Purdue University. Accessed September 23, 2019. http://docs.lib.purdue.edu/open_access_theses/456.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Mohammad, Imaduddin. “Integrated DC-DC boost converters using CMOS silicon on Sapphire Technology.” 2014. Web. 23 Sep 2019.

Vancouver:

Mohammad I. Integrated DC-DC boost converters using CMOS silicon on Sapphire Technology. [Internet] [Thesis]. Purdue University; 2014. [cited 2019 Sep 23]. Available from: http://docs.lib.purdue.edu/open_access_theses/456.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Mohammad I. Integrated DC-DC boost converters using CMOS silicon on Sapphire Technology. [Thesis]. Purdue University; 2014. Available from: http://docs.lib.purdue.edu/open_access_theses/456

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


University of Cincinnati

16. Ravi, Ajaay. Run-Time Active Leakage Control Mechanism based on a Light Threshold Voltage Hopping Technique (LITHE).

Degree: MS, Engineering and Applied Science: Computer Engineering, 2011, University of Cincinnati

  Leakage aware designs are an indispensable part of the design and manufacturing process in today’s deep sub-micron technologies. Technology scaling continues to be a… (more)

Subjects/Keywords: Computer Engineering; Leakage Power Reduction; Run-Time Active Leakage Control; Threshold Voltage Hopping; Substrate Biasing; LITHE; Steady state leakage current reduction

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Ravi, A. (2011). Run-Time Active Leakage Control Mechanism based on a Light Threshold Voltage Hopping Technique (LITHE). (Masters Thesis). University of Cincinnati. Retrieved from http://rave.ohiolink.edu/etdc/view?acc_num=ucin1302550444

Chicago Manual of Style (16th Edition):

Ravi, Ajaay. “Run-Time Active Leakage Control Mechanism based on a Light Threshold Voltage Hopping Technique (LITHE).” 2011. Masters Thesis, University of Cincinnati. Accessed September 23, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1302550444.

MLA Handbook (7th Edition):

Ravi, Ajaay. “Run-Time Active Leakage Control Mechanism based on a Light Threshold Voltage Hopping Technique (LITHE).” 2011. Web. 23 Sep 2019.

Vancouver:

Ravi A. Run-Time Active Leakage Control Mechanism based on a Light Threshold Voltage Hopping Technique (LITHE). [Internet] [Masters thesis]. University of Cincinnati; 2011. [cited 2019 Sep 23]. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1302550444.

Council of Science Editors:

Ravi A. Run-Time Active Leakage Control Mechanism based on a Light Threshold Voltage Hopping Technique (LITHE). [Masters Thesis]. University of Cincinnati; 2011. Available from: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1302550444


EPFL

17. Cojbasic, Radisav. Design of Digital SoC for Operation at High Temperatures.

Degree: 2014, EPFL

 There is a growing demand for Systems-on-Chip, integrating microprocessors, on-chip memories, data converters and a variety of sensors, which are capable of reliable operation at… (more)

Subjects/Keywords: High Temperatures; Reliability; SoC; SRAM; Digital Temperature Sensor; Flash ADC; Time-to-Digital Conversion; Adaptive Body-Biasing; Leakage Reduction Techniques; SOI

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APA (6th Edition):

Cojbasic, R. (2014). Design of Digital SoC for Operation at High Temperatures. (Thesis). EPFL. Retrieved from http://infoscience.epfl.ch/record/202013

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Cojbasic, Radisav. “Design of Digital SoC for Operation at High Temperatures.” 2014. Thesis, EPFL. Accessed September 23, 2019. http://infoscience.epfl.ch/record/202013.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Cojbasic, Radisav. “Design of Digital SoC for Operation at High Temperatures.” 2014. Web. 23 Sep 2019.

Vancouver:

Cojbasic R. Design of Digital SoC for Operation at High Temperatures. [Internet] [Thesis]. EPFL; 2014. [cited 2019 Sep 23]. Available from: http://infoscience.epfl.ch/record/202013.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Cojbasic R. Design of Digital SoC for Operation at High Temperatures. [Thesis]. EPFL; 2014. Available from: http://infoscience.epfl.ch/record/202013

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Université de Grenoble

18. Le Coz, Julien. Réduction de la consommation statique des circuits intégrés en technologie SOI 65 nm partiellement désertée : reseach on the reduction of the static power dissipation of integrated circuits in 65nm partially depleted Silicon_on_Insulator technology.

Degree: Docteur es, Sciences et technologie industrielles, 2011, Université de Grenoble

Les technologies SOI partiellement désertées (PD-SOI), permettent de gagner en performances ou en consommation dynamique, par rapport à leur équivalent sur substrat massif (BULK). Leur… (more)

Subjects/Keywords: SOI; Interrupteur de puissance; Basse consommation; Polarisation de body; SOi; Power switch; Low power; Body biasing

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Le Coz, J. (2011). Réduction de la consommation statique des circuits intégrés en technologie SOI 65 nm partiellement désertée : reseach on the reduction of the static power dissipation of integrated circuits in 65nm partially depleted Silicon_on_Insulator technology. (Doctoral Dissertation). Université de Grenoble. Retrieved from http://www.theses.fr/2011GRENT076

Chicago Manual of Style (16th Edition):

Le Coz, Julien. “Réduction de la consommation statique des circuits intégrés en technologie SOI 65 nm partiellement désertée : reseach on the reduction of the static power dissipation of integrated circuits in 65nm partially depleted Silicon_on_Insulator technology.” 2011. Doctoral Dissertation, Université de Grenoble. Accessed September 23, 2019. http://www.theses.fr/2011GRENT076.

MLA Handbook (7th Edition):

Le Coz, Julien. “Réduction de la consommation statique des circuits intégrés en technologie SOI 65 nm partiellement désertée : reseach on the reduction of the static power dissipation of integrated circuits in 65nm partially depleted Silicon_on_Insulator technology.” 2011. Web. 23 Sep 2019.

Vancouver:

Le Coz J. Réduction de la consommation statique des circuits intégrés en technologie SOI 65 nm partiellement désertée : reseach on the reduction of the static power dissipation of integrated circuits in 65nm partially depleted Silicon_on_Insulator technology. [Internet] [Doctoral dissertation]. Université de Grenoble; 2011. [cited 2019 Sep 23]. Available from: http://www.theses.fr/2011GRENT076.

Council of Science Editors:

Le Coz J. Réduction de la consommation statique des circuits intégrés en technologie SOI 65 nm partiellement désertée : reseach on the reduction of the static power dissipation of integrated circuits in 65nm partially depleted Silicon_on_Insulator technology. [Doctoral Dissertation]. Université de Grenoble; 2011. Available from: http://www.theses.fr/2011GRENT076


Penn State University

19. Zhu, Meng. ELECTRICAL TRANSPORT STUDIES OF MOLECULAR BEAM EPITAXY GROWN (GA,MN)AS EPILAYERS AND HETEROSTRUCTURES.

Degree: PhD, Physics, 2008, Penn State University

 Diluted magnetic semiconductors (DMS) grown by molecular beam epitaxy have been drawing attention in the context of emerging spintronics, which utilizes electron spins to develop… (more)

Subjects/Keywords: random telegraph noise; Molecular beam epitaxy; Mn)As; (Ga; Diluted magnetic semiconductor; exchange biasing; tunneling magnetoresistance

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zhu, M. (2008). ELECTRICAL TRANSPORT STUDIES OF MOLECULAR BEAM EPITAXY GROWN (GA,MN)AS EPILAYERS AND HETEROSTRUCTURES. (Doctoral Dissertation). Penn State University. Retrieved from https://etda.libraries.psu.edu/catalog/8870

Chicago Manual of Style (16th Edition):

Zhu, Meng. “ELECTRICAL TRANSPORT STUDIES OF MOLECULAR BEAM EPITAXY GROWN (GA,MN)AS EPILAYERS AND HETEROSTRUCTURES.” 2008. Doctoral Dissertation, Penn State University. Accessed September 23, 2019. https://etda.libraries.psu.edu/catalog/8870.

MLA Handbook (7th Edition):

Zhu, Meng. “ELECTRICAL TRANSPORT STUDIES OF MOLECULAR BEAM EPITAXY GROWN (GA,MN)AS EPILAYERS AND HETEROSTRUCTURES.” 2008. Web. 23 Sep 2019.

Vancouver:

Zhu M. ELECTRICAL TRANSPORT STUDIES OF MOLECULAR BEAM EPITAXY GROWN (GA,MN)AS EPILAYERS AND HETEROSTRUCTURES. [Internet] [Doctoral dissertation]. Penn State University; 2008. [cited 2019 Sep 23]. Available from: https://etda.libraries.psu.edu/catalog/8870.

Council of Science Editors:

Zhu M. ELECTRICAL TRANSPORT STUDIES OF MOLECULAR BEAM EPITAXY GROWN (GA,MN)AS EPILAYERS AND HETEROSTRUCTURES. [Doctoral Dissertation]. Penn State University; 2008. Available from: https://etda.libraries.psu.edu/catalog/8870

20. Berthier, Rémy. Development of characterization methods for in situ annealing and biasing of semiconductor devices in the TEM : Développement de méthodes de caractérisation pour le recuit et la polarisation in-situ de dispositifs semi-conducteur dans le microscope électronique à transmission.

Degree: Docteur es, Nanophysique, 2018, Grenoble Alpes

Dans cette thèse, nous abordons les défis rencontrés lors de la caractérisation des mémoires non volatiles par microscopie en transmission in situ. Les innovations récentes… (more)

Subjects/Keywords: Polarisation in situ; Microscopie électronique à transmission; Semi-Conducteurs; Dispositifs; In situ biasing; Transmission electron microscopy; Semiconductor; Device; 530

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Berthier, R. (2018). Development of characterization methods for in situ annealing and biasing of semiconductor devices in the TEM : Développement de méthodes de caractérisation pour le recuit et la polarisation in-situ de dispositifs semi-conducteur dans le microscope électronique à transmission. (Doctoral Dissertation). Grenoble Alpes. Retrieved from http://www.theses.fr/2018GREAY014

Chicago Manual of Style (16th Edition):

Berthier, Rémy. “Development of characterization methods for in situ annealing and biasing of semiconductor devices in the TEM : Développement de méthodes de caractérisation pour le recuit et la polarisation in-situ de dispositifs semi-conducteur dans le microscope électronique à transmission.” 2018. Doctoral Dissertation, Grenoble Alpes. Accessed September 23, 2019. http://www.theses.fr/2018GREAY014.

MLA Handbook (7th Edition):

Berthier, Rémy. “Development of characterization methods for in situ annealing and biasing of semiconductor devices in the TEM : Développement de méthodes de caractérisation pour le recuit et la polarisation in-situ de dispositifs semi-conducteur dans le microscope électronique à transmission.” 2018. Web. 23 Sep 2019.

Vancouver:

Berthier R. Development of characterization methods for in situ annealing and biasing of semiconductor devices in the TEM : Développement de méthodes de caractérisation pour le recuit et la polarisation in-situ de dispositifs semi-conducteur dans le microscope électronique à transmission. [Internet] [Doctoral dissertation]. Grenoble Alpes; 2018. [cited 2019 Sep 23]. Available from: http://www.theses.fr/2018GREAY014.

Council of Science Editors:

Berthier R. Development of characterization methods for in situ annealing and biasing of semiconductor devices in the TEM : Développement de méthodes de caractérisation pour le recuit et la polarisation in-situ de dispositifs semi-conducteur dans le microscope électronique à transmission. [Doctoral Dissertation]. Grenoble Alpes; 2018. Available from: http://www.theses.fr/2018GREAY014


University of Lund

21. Sherazi, Syed Muhammad Yasser. Design Space Exploration of Digital Circuits for Ultra-low Energy Dissipation.

Degree: 2013, University of Lund

 The ever expanding market of ultra portable electronic products is compelling the designer to invest major efforts in the development of small and low energy… (more)

Subjects/Keywords: Elektroteknik och elektronik; CMOS; ultra low-voltage; ultra low-energy; subthreshold (sub-VT); body biasing; pipelining; unfolding; half-band digital filter.

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Sherazi, S. M. Y. (2013). Design Space Exploration of Digital Circuits for Ultra-low Energy Dissipation. (Doctoral Dissertation). University of Lund. Retrieved from http://lup.lub.lu.se/record/4196433 ; http://portal.research.lu.se/ws/files/3439813/4196460.pdf

Chicago Manual of Style (16th Edition):

Sherazi, Syed Muhammad Yasser. “Design Space Exploration of Digital Circuits for Ultra-low Energy Dissipation.” 2013. Doctoral Dissertation, University of Lund. Accessed September 23, 2019. http://lup.lub.lu.se/record/4196433 ; http://portal.research.lu.se/ws/files/3439813/4196460.pdf.

MLA Handbook (7th Edition):

Sherazi, Syed Muhammad Yasser. “Design Space Exploration of Digital Circuits for Ultra-low Energy Dissipation.” 2013. Web. 23 Sep 2019.

Vancouver:

Sherazi SMY. Design Space Exploration of Digital Circuits for Ultra-low Energy Dissipation. [Internet] [Doctoral dissertation]. University of Lund; 2013. [cited 2019 Sep 23]. Available from: http://lup.lub.lu.se/record/4196433 ; http://portal.research.lu.se/ws/files/3439813/4196460.pdf.

Council of Science Editors:

Sherazi SMY. Design Space Exploration of Digital Circuits for Ultra-low Energy Dissipation. [Doctoral Dissertation]. University of Lund; 2013. Available from: http://lup.lub.lu.se/record/4196433 ; http://portal.research.lu.se/ws/files/3439813/4196460.pdf


Uppsala University

22. Viklund, Jonas. Developing of an ultra low noise bolometer biasing circuit.

Degree: Solid State Electronics, 2016, Uppsala University

  Noise in electronic circuits can sometimes cause problems. It is especially problematic in for example high sensitive sensors and high end audio and video… (more)

Subjects/Keywords: low noise; ultra low noise; bolometer; biasing; thermal; noise; filter; 1/f-noise; sensors; image sensor; DAC

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Viklund, J. (2016). Developing of an ultra low noise bolometer biasing circuit. (Thesis). Uppsala University. Retrieved from http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-296698

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Viklund, Jonas. “Developing of an ultra low noise bolometer biasing circuit.” 2016. Thesis, Uppsala University. Accessed September 23, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-296698.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Viklund, Jonas. “Developing of an ultra low noise bolometer biasing circuit.” 2016. Web. 23 Sep 2019.

Vancouver:

Viklund J. Developing of an ultra low noise bolometer biasing circuit. [Internet] [Thesis]. Uppsala University; 2016. [cited 2019 Sep 23]. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-296698.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Viklund J. Developing of an ultra low noise bolometer biasing circuit. [Thesis]. Uppsala University; 2016. Available from: http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-296698

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

23. Horký, Stanislav. Nízkošumový zesilovač pro pásmo UHF .

Degree: 2013, Brno University of Technology

 Tato bakalářská práce se zabývá popisem a návrhem nízkošumových vysokofrekvenčních zesilovačů. Dále se zaměřuje na návrh a simulaci zesilovače v programu Ansoft Designer. V práci… (more)

Subjects/Keywords: Zesilovač; šum; stabilita; přizpůsobení; pracovní bod; ATF 54143; filtr; Amplifier; noise; stability; matching; biasing; ATF 54143; filter

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Horký, S. (2013). Nízkošumový zesilovač pro pásmo UHF . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/25083

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Horký, Stanislav. “Nízkošumový zesilovač pro pásmo UHF .” 2013. Thesis, Brno University of Technology. Accessed September 23, 2019. http://hdl.handle.net/11012/25083.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Horký, Stanislav. “Nízkošumový zesilovač pro pásmo UHF .” 2013. Web. 23 Sep 2019.

Vancouver:

Horký S. Nízkošumový zesilovač pro pásmo UHF . [Internet] [Thesis]. Brno University of Technology; 2013. [cited 2019 Sep 23]. Available from: http://hdl.handle.net/11012/25083.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Horký S. Nízkošumový zesilovač pro pásmo UHF . [Thesis]. Brno University of Technology; 2013. Available from: http://hdl.handle.net/11012/25083

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rochester Institute of Technology

24. Amarchinta, Sumanth. High-performance subthreshold standard cell design and cell placement optimization.

Degree: Computer Engineering, 2009, Rochester Institute of Technology

Please see PDF for exact formulas. Advisors/Committee Members: Kudithipudi, Dhireesha, Moon, James, Hsu, Ken.

Subjects/Keywords: Charge boosting; CPM; ILP; Substrate biasing; Subthreshold; VLSI

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Amarchinta, S. (2009). High-performance subthreshold standard cell design and cell placement optimization. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/3167

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Amarchinta, Sumanth. “High-performance subthreshold standard cell design and cell placement optimization.” 2009. Thesis, Rochester Institute of Technology. Accessed September 23, 2019. https://scholarworks.rit.edu/theses/3167.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Amarchinta, Sumanth. “High-performance subthreshold standard cell design and cell placement optimization.” 2009. Web. 23 Sep 2019.

Vancouver:

Amarchinta S. High-performance subthreshold standard cell design and cell placement optimization. [Internet] [Thesis]. Rochester Institute of Technology; 2009. [cited 2019 Sep 23]. Available from: https://scholarworks.rit.edu/theses/3167.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Amarchinta S. High-performance subthreshold standard cell design and cell placement optimization. [Thesis]. Rochester Institute of Technology; 2009. Available from: https://scholarworks.rit.edu/theses/3167

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rochester Institute of Technology

25. Voyce, Kenneth. An Active FET Receiver Front End Mixer.

Degree: Electrical Engineering, 1969, Rochester Institute of Technology

  In many recent receiver designs, the front-end mixer determines the receiver's sensitivity and its susceptibility to distortion from large input signals. Two balanced FET… (more)

Subjects/Keywords: Bandwidth; Biasing; Circuit component; Frequency dependent; Mixer; Noise; Sensitivity

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APA (6th Edition):

Voyce, K. (1969). An Active FET Receiver Front End Mixer. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/1242

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Voyce, Kenneth. “An Active FET Receiver Front End Mixer.” 1969. Thesis, Rochester Institute of Technology. Accessed September 23, 2019. https://scholarworks.rit.edu/theses/1242.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Voyce, Kenneth. “An Active FET Receiver Front End Mixer.” 1969. Web. 23 Sep 2019.

Vancouver:

Voyce K. An Active FET Receiver Front End Mixer. [Internet] [Thesis]. Rochester Institute of Technology; 1969. [cited 2019 Sep 23]. Available from: https://scholarworks.rit.edu/theses/1242.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Voyce K. An Active FET Receiver Front End Mixer. [Thesis]. Rochester Institute of Technology; 1969. Available from: https://scholarworks.rit.edu/theses/1242

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Brno University of Technology

26. Horký, Stanislav. Nízkošumový zesilovač pro pásmo UHF .

Degree: 2013, Brno University of Technology

 Tato bakalářská práce se zabývá popisem a návrhem nízkošumových vysokofrekvenčních zesilovačů. Dále se zaměřuje na návrh a simulaci zesilovače v programu Ansoft Designer. V práci… (more)

Subjects/Keywords: Zesilovač; šum; stabilita; přizpůsobení; pracovní bod; ATF 54143; filtr; Amplifier; noise; stability; matching; biasing; ATF 54143; filter

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Horký, S. (2013). Nízkošumový zesilovač pro pásmo UHF . (Thesis). Brno University of Technology. Retrieved from http://hdl.handle.net/11012/71582

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Horký, Stanislav. “Nízkošumový zesilovač pro pásmo UHF .” 2013. Thesis, Brno University of Technology. Accessed September 23, 2019. http://hdl.handle.net/11012/71582.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Horký, Stanislav. “Nízkošumový zesilovač pro pásmo UHF .” 2013. Web. 23 Sep 2019.

Vancouver:

Horký S. Nízkošumový zesilovač pro pásmo UHF . [Internet] [Thesis]. Brno University of Technology; 2013. [cited 2019 Sep 23]. Available from: http://hdl.handle.net/11012/71582.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Horký S. Nízkošumový zesilovač pro pásmo UHF . [Thesis]. Brno University of Technology; 2013. Available from: http://hdl.handle.net/11012/71582

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Arizona State University

27. Magod Ramakrishna, Raveesh. Ultra-low Quiescent Current NMOS Low Dropout Regulator With Fast Transient response for Always-On Internet-of-Things Applications.

Degree: Electrical Engineering, 2018, Arizona State University

Subjects/Keywords: Electrical engineering; charge-pump; Dynamic biasing; Fast transient response; Hybrid biasing; NMOS LDO; Switched capacitor pole tracking compensation

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APA (6th Edition):

Magod Ramakrishna, R. (2018). Ultra-low Quiescent Current NMOS Low Dropout Regulator With Fast Transient response for Always-On Internet-of-Things Applications. (Doctoral Dissertation). Arizona State University. Retrieved from http://repository.asu.edu/items/50579

Chicago Manual of Style (16th Edition):

Magod Ramakrishna, Raveesh. “Ultra-low Quiescent Current NMOS Low Dropout Regulator With Fast Transient response for Always-On Internet-of-Things Applications.” 2018. Doctoral Dissertation, Arizona State University. Accessed September 23, 2019. http://repository.asu.edu/items/50579.

MLA Handbook (7th Edition):

Magod Ramakrishna, Raveesh. “Ultra-low Quiescent Current NMOS Low Dropout Regulator With Fast Transient response for Always-On Internet-of-Things Applications.” 2018. Web. 23 Sep 2019.

Vancouver:

Magod Ramakrishna R. Ultra-low Quiescent Current NMOS Low Dropout Regulator With Fast Transient response for Always-On Internet-of-Things Applications. [Internet] [Doctoral dissertation]. Arizona State University; 2018. [cited 2019 Sep 23]. Available from: http://repository.asu.edu/items/50579.

Council of Science Editors:

Magod Ramakrishna R. Ultra-low Quiescent Current NMOS Low Dropout Regulator With Fast Transient response for Always-On Internet-of-Things Applications. [Doctoral Dissertation]. Arizona State University; 2018. Available from: http://repository.asu.edu/items/50579

28. Held, Christopher M. Evaluation of strategies for repeat procurement.

Degree: PhD, Management, 2011, Georgia Tech

 For the past several decades, there has been a fundamental dispute between the appropriate mechanism for repeat procurement. On one hand, the supporters of Porter… (more)

Subjects/Keywords: Procurement; Incumbent biasing; Multi-sourcing; Operations management; Industrial procurement

…26 (Note not Released to Respondents: Incumbent Biasing) . . . . . . . 97 27… …includes all hypotheses and incorporates the impact of Incumbent Biasing… …isometric lines change as the biasing factor changes from 0. . 72 10 This figure shows how a… …procurement, with most suppliers opting for hybrid strategies such as Incumbent Biasing: a strategy… …Using this model, we find that Incumbent Biasing has an impact on procurement performance via… 

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APA (6th Edition):

Held, C. M. (2011). Evaluation of strategies for repeat procurement. (Doctoral Dissertation). Georgia Tech. Retrieved from http://hdl.handle.net/1853/43740

Chicago Manual of Style (16th Edition):

Held, Christopher M. “Evaluation of strategies for repeat procurement.” 2011. Doctoral Dissertation, Georgia Tech. Accessed September 23, 2019. http://hdl.handle.net/1853/43740.

MLA Handbook (7th Edition):

Held, Christopher M. “Evaluation of strategies for repeat procurement.” 2011. Web. 23 Sep 2019.

Vancouver:

Held CM. Evaluation of strategies for repeat procurement. [Internet] [Doctoral dissertation]. Georgia Tech; 2011. [cited 2019 Sep 23]. Available from: http://hdl.handle.net/1853/43740.

Council of Science Editors:

Held CM. Evaluation of strategies for repeat procurement. [Doctoral Dissertation]. Georgia Tech; 2011. Available from: http://hdl.handle.net/1853/43740

29. Zimmermann, Jonathan Thomas. Frequency Constraints on D.C. Biasing in Deep Submicron Technologies.

Degree: MS, Electrical Engineering, 2015, Rochester Institute of Technology

  The progression of technology has required smaller devices to achieve faster circuits and more power-efficient systems. However, with supply voltage and device intrinsic gain… (more)

Subjects/Keywords: 28nm; Biasing; CML buffer; Current source; Frequency response; Submicron

…vi 1 Introduction . . . . . . . . . . . . . . . . . . . . . 1.1 DC Biasing in Deep Sub… …micron Technologies . 1.2 Biasing Design . . . . . . . . . . . . . . . . . 1.3 Biasing of High… …6 2 Biasing Background . . . . . . . . . . . . . . . . . . . . . . 2.1 D.C. Current… …Feedback in Current Source Design . . . . . . . . Review of Feedback Techniques in Biasing Design… …Feedback . . . . . . . . . . . . . . . . . . 11 Traditional Biasing Analysis… 

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Zimmermann, J. T. (2015). Frequency Constraints on D.C. Biasing in Deep Submicron Technologies. (Masters Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/8636

Chicago Manual of Style (16th Edition):

Zimmermann, Jonathan Thomas. “Frequency Constraints on D.C. Biasing in Deep Submicron Technologies.” 2015. Masters Thesis, Rochester Institute of Technology. Accessed September 23, 2019. https://scholarworks.rit.edu/theses/8636.

MLA Handbook (7th Edition):

Zimmermann, Jonathan Thomas. “Frequency Constraints on D.C. Biasing in Deep Submicron Technologies.” 2015. Web. 23 Sep 2019.

Vancouver:

Zimmermann JT. Frequency Constraints on D.C. Biasing in Deep Submicron Technologies. [Internet] [Masters thesis]. Rochester Institute of Technology; 2015. [cited 2019 Sep 23]. Available from: https://scholarworks.rit.edu/theses/8636.

Council of Science Editors:

Zimmermann JT. Frequency Constraints on D.C. Biasing in Deep Submicron Technologies. [Masters Thesis]. Rochester Institute of Technology; 2015. Available from: https://scholarworks.rit.edu/theses/8636


California State University – Northridge

30. Parulkar, Shivani. Design of a Low Noise Amplifier.

Degree: MS, Department of Electrical and Computer Engineering., 6, California State University – Northridge

 The purpose of this master's project is to design a low noise amplifier with cascading different amplifier stages together for specific design conditions. The aim… (more)

Subjects/Keywords: DC biasing; Dissertations, Academic  – CSUN  – Engineering  – Electrical and Computer Engineering.

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Parulkar, S. (6). Design of a Low Noise Amplifier. (Masters Thesis). California State University – Northridge. Retrieved from http://hdl.handle.net/10211.3/171560

Chicago Manual of Style (16th Edition):

Parulkar, Shivani. “Design of a Low Noise Amplifier.” 6. Masters Thesis, California State University – Northridge. Accessed September 23, 2019. http://hdl.handle.net/10211.3/171560.

MLA Handbook (7th Edition):

Parulkar, Shivani. “Design of a Low Noise Amplifier.” 6. Web. 23 Sep 2019.

Vancouver:

Parulkar S. Design of a Low Noise Amplifier. [Internet] [Masters thesis]. California State University – Northridge; 6. [cited 2019 Sep 23]. Available from: http://hdl.handle.net/10211.3/171560.

Council of Science Editors:

Parulkar S. Design of a Low Noise Amplifier. [Masters Thesis]. California State University – Northridge; 6. Available from: http://hdl.handle.net/10211.3/171560

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