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You searched for subject:(barrier lowering). Showing records 1 – 4 of 4 total matches.

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Anna University

1. Balamurugan N B. Analytical modeling and simulation Of a fully depleted dual material Surrounding gate mosfets Considering short channel effects;.

Degree: Analytical modeling and simulation Of a fully depleted dual material Surrounding gate mosfets Considering short channel effects, 2014, Anna University

Silicon on insulator SOI technology has been the forerunner of newlinethe CMOS technology in the last decade offering superior CMOS devices newlinewith higher speed, higher… (more)

Subjects/Keywords: Drain induced barrier lowering; Dual Material Surrounding Gate; Shortchannel effects; Silicon on insulator

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APA (6th Edition):

B, B. N. (2014). Analytical modeling and simulation Of a fully depleted dual material Surrounding gate mosfets Considering short channel effects;. (Thesis). Anna University. Retrieved from http://shodhganga.inflibnet.ac.in/handle/10603/27996

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

B, Balamurugan N. “Analytical modeling and simulation Of a fully depleted dual material Surrounding gate mosfets Considering short channel effects;.” 2014. Thesis, Anna University. Accessed October 17, 2019. http://shodhganga.inflibnet.ac.in/handle/10603/27996.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

B, Balamurugan N. “Analytical modeling and simulation Of a fully depleted dual material Surrounding gate mosfets Considering short channel effects;.” 2014. Web. 17 Oct 2019.

Vancouver:

B BN. Analytical modeling and simulation Of a fully depleted dual material Surrounding gate mosfets Considering short channel effects;. [Internet] [Thesis]. Anna University; 2014. [cited 2019 Oct 17]. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/27996.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

B BN. Analytical modeling and simulation Of a fully depleted dual material Surrounding gate mosfets Considering short channel effects;. [Thesis]. Anna University; 2014. Available from: http://shodhganga.inflibnet.ac.in/handle/10603/27996

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


NSYSU

2. Tai, Chih-Hsuan. Investigate Short-Channel Effects and RF/analog Performance of A Highly Scaled-Down Novel Junctionless Vertical MOSFET.

Degree: Master, Electrical Engineering, 2011, NSYSU

 In this thesis, we carefully investigate the electrical characteristics of junctionless vertical MOSFET (JLVMOS) compared with the junctionless planar MOSFET (JLPMOS) and conversional junction vertical… (more)

Subjects/Keywords: SOI; junctionless; short-channel effects; Drain-Induced barrier lowering (DIBL); Subthreshold Swing (S.S.); double-gate

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APA (6th Edition):

Tai, C. (2011). Investigate Short-Channel Effects and RF/analog Performance of A Highly Scaled-Down Novel Junctionless Vertical MOSFET. (Thesis). NSYSU. Retrieved from http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0825111-213028

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Tai, Chih-Hsuan. “Investigate Short-Channel Effects and RF/analog Performance of A Highly Scaled-Down Novel Junctionless Vertical MOSFET.” 2011. Thesis, NSYSU. Accessed October 17, 2019. http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0825111-213028.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Tai, Chih-Hsuan. “Investigate Short-Channel Effects and RF/analog Performance of A Highly Scaled-Down Novel Junctionless Vertical MOSFET.” 2011. Web. 17 Oct 2019.

Vancouver:

Tai C. Investigate Short-Channel Effects and RF/analog Performance of A Highly Scaled-Down Novel Junctionless Vertical MOSFET. [Internet] [Thesis]. NSYSU; 2011. [cited 2019 Oct 17]. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0825111-213028.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Tai C. Investigate Short-Channel Effects and RF/analog Performance of A Highly Scaled-Down Novel Junctionless Vertical MOSFET. [Thesis]. NSYSU; 2011. Available from: http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0825111-213028

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


Rochester Institute of Technology

3. Singh, Siddhartha. Phosphorus implants for off-state improvement of SOI CMOS fabricated at low temperature.

Degree: Microelectronic Engineering, 2009, Rochester Institute of Technology

 A study on the influence of phosphorus implanted source/drain features on the off-state performance of transistors fabricated in thin-film crystalline silicon at low temperature is… (more)

Subjects/Keywords: Complementary metal oxide semiconductor; Drain induced barrier lowering; Gate induced drain leakage; Lightly doped drain; N-barrier implant; Silicon on insulator

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Singh, S. (2009). Phosphorus implants for off-state improvement of SOI CMOS fabricated at low temperature. (Thesis). Rochester Institute of Technology. Retrieved from https://scholarworks.rit.edu/theses/7123

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Singh, Siddhartha. “Phosphorus implants for off-state improvement of SOI CMOS fabricated at low temperature.” 2009. Thesis, Rochester Institute of Technology. Accessed October 17, 2019. https://scholarworks.rit.edu/theses/7123.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Singh, Siddhartha. “Phosphorus implants for off-state improvement of SOI CMOS fabricated at low temperature.” 2009. Web. 17 Oct 2019.

Vancouver:

Singh S. Phosphorus implants for off-state improvement of SOI CMOS fabricated at low temperature. [Internet] [Thesis]. Rochester Institute of Technology; 2009. [cited 2019 Oct 17]. Available from: https://scholarworks.rit.edu/theses/7123.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Singh S. Phosphorus implants for off-state improvement of SOI CMOS fabricated at low temperature. [Thesis]. Rochester Institute of Technology; 2009. Available from: https://scholarworks.rit.edu/theses/7123

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation


North Carolina State University

4. Tedesco, Joseph Leo. Electrical Characterization of Transition Metal Silicide Nanostructures Using Variable Temperature Scanning Probe Microscopy.

Degree: PhD, Physics, 2007, North Carolina State University

 Cobalt disilicide (CoSi2) islands have been formed on Si(111) and Si(100) through UHV deposition and annealing. Current-voltage (I-V) and temperature-dependent current-voltage (I-V-T) curves have been… (more)

Subjects/Keywords: CoSi2; titanium silicide; TiSi2; transition metal; silicide; scanning probe microscopy; Fermi level pinning; cobalt silicide; Si(100); Si(111); silicon; titanium; cobalt; electrical characterization; c-AFM; conducting atomic force microscopy; AFM; atomic force microscopy; STM; scanning tunneling microscopy; variable temperature; Schottky barrier; Coulomb blockade; I-V; variable temperature; Coulomb staircase; I-V-T; barrier lowering; single electron tunneling

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APA · Chicago · MLA · Vancouver · CSE | Export to Zotero / EndNote / Reference Manager

APA (6th Edition):

Tedesco, J. L. (2007). Electrical Characterization of Transition Metal Silicide Nanostructures Using Variable Temperature Scanning Probe Microscopy. (Doctoral Dissertation). North Carolina State University. Retrieved from http://www.lib.ncsu.edu/resolver/1840.16/4855

Chicago Manual of Style (16th Edition):

Tedesco, Joseph Leo. “Electrical Characterization of Transition Metal Silicide Nanostructures Using Variable Temperature Scanning Probe Microscopy.” 2007. Doctoral Dissertation, North Carolina State University. Accessed October 17, 2019. http://www.lib.ncsu.edu/resolver/1840.16/4855.

MLA Handbook (7th Edition):

Tedesco, Joseph Leo. “Electrical Characterization of Transition Metal Silicide Nanostructures Using Variable Temperature Scanning Probe Microscopy.” 2007. Web. 17 Oct 2019.

Vancouver:

Tedesco JL. Electrical Characterization of Transition Metal Silicide Nanostructures Using Variable Temperature Scanning Probe Microscopy. [Internet] [Doctoral dissertation]. North Carolina State University; 2007. [cited 2019 Oct 17]. Available from: http://www.lib.ncsu.edu/resolver/1840.16/4855.

Council of Science Editors:

Tedesco JL. Electrical Characterization of Transition Metal Silicide Nanostructures Using Variable Temperature Scanning Probe Microscopy. [Doctoral Dissertation]. North Carolina State University; 2007. Available from: http://www.lib.ncsu.edu/resolver/1840.16/4855

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