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You searched for subject:(Wear out). Showing records 1 – 8 of 8 total matches.

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1. Dabhoiwala, Mehernosh H. Online Nbti Wear-out Estimation.

Degree: MS, Electrical & Computer Engineering, 2013, University of Massachusetts

  CMOS feature size scaling has been a source of dramatic performance gains, but it has come at a cost of on-chip wear-out. Negative Bias… (more)

Subjects/Keywords: Online NBTI wear-out estimation; Computer Engineering; Electrical and Computer Engineering

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APA (6th Edition):

Dabhoiwala, M. H. (2013). Online Nbti Wear-out Estimation. (Masters Thesis). University of Massachusetts. Retrieved from https://scholarworks.umass.edu/theses/1117

Chicago Manual of Style (16th Edition):

Dabhoiwala, Mehernosh H. “Online Nbti Wear-out Estimation.” 2013. Masters Thesis, University of Massachusetts. Accessed March 04, 2021. https://scholarworks.umass.edu/theses/1117.

MLA Handbook (7th Edition):

Dabhoiwala, Mehernosh H. “Online Nbti Wear-out Estimation.” 2013. Web. 04 Mar 2021.

Vancouver:

Dabhoiwala MH. Online Nbti Wear-out Estimation. [Internet] [Masters thesis]. University of Massachusetts; 2013. [cited 2021 Mar 04]. Available from: https://scholarworks.umass.edu/theses/1117.

Council of Science Editors:

Dabhoiwala MH. Online Nbti Wear-out Estimation. [Masters Thesis]. University of Massachusetts; 2013. Available from: https://scholarworks.umass.edu/theses/1117


Cal Poly

2. Wilkinson, Gregory Ross. Digital Circuit Wear-out due to Electromigration in Semiconductor Metal Lines.

Degree: MS, Electrical Engineering, 2009, Cal Poly

 With the constant scaling of semiconductor devices, reliability of these devices is a huge concern. One of the biggest reliability issues is a phenomenon known… (more)

Subjects/Keywords: electromigration; reliability; wear-out; metal lines

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APA (6th Edition):

Wilkinson, G. R. (2009). Digital Circuit Wear-out due to Electromigration in Semiconductor Metal Lines. (Masters Thesis). Cal Poly. Retrieved from https://digitalcommons.calpoly.edu/theses/196 ; 10.15368/theses.2009.160

Chicago Manual of Style (16th Edition):

Wilkinson, Gregory Ross. “Digital Circuit Wear-out due to Electromigration in Semiconductor Metal Lines.” 2009. Masters Thesis, Cal Poly. Accessed March 04, 2021. https://digitalcommons.calpoly.edu/theses/196 ; 10.15368/theses.2009.160.

MLA Handbook (7th Edition):

Wilkinson, Gregory Ross. “Digital Circuit Wear-out due to Electromigration in Semiconductor Metal Lines.” 2009. Web. 04 Mar 2021.

Vancouver:

Wilkinson GR. Digital Circuit Wear-out due to Electromigration in Semiconductor Metal Lines. [Internet] [Masters thesis]. Cal Poly; 2009. [cited 2021 Mar 04]. Available from: https://digitalcommons.calpoly.edu/theses/196 ; 10.15368/theses.2009.160.

Council of Science Editors:

Wilkinson GR. Digital Circuit Wear-out due to Electromigration in Semiconductor Metal Lines. [Masters Thesis]. Cal Poly; 2009. Available from: https://digitalcommons.calpoly.edu/theses/196 ; 10.15368/theses.2009.160


University of New South Wales

3. Ihesiulor, Obinna. Wear reduction in modular taper-trunnion hip prostheses using straight cylindrical stems.

Degree: Engineering & Information Technology, 2018, University of New South Wales

 Evidence suggests that fretting wear at the taper-trunnion (head-stem) junction of modular metallic total hip replacement (THR) implants contributes to high rates of metallosis and… (more)

Subjects/Keywords: Tapered stems; Modular hip implants; Straight cylindrical stems; Interference fits; Pull-out forces; Volumetric wear

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APA (6th Edition):

Ihesiulor, O. (2018). Wear reduction in modular taper-trunnion hip prostheses using straight cylindrical stems. (Doctoral Dissertation). University of New South Wales. Retrieved from http://handle.unsw.edu.au/1959.4/60348 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51887/SOURCE2?view=true

Chicago Manual of Style (16th Edition):

Ihesiulor, Obinna. “Wear reduction in modular taper-trunnion hip prostheses using straight cylindrical stems.” 2018. Doctoral Dissertation, University of New South Wales. Accessed March 04, 2021. http://handle.unsw.edu.au/1959.4/60348 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51887/SOURCE2?view=true.

MLA Handbook (7th Edition):

Ihesiulor, Obinna. “Wear reduction in modular taper-trunnion hip prostheses using straight cylindrical stems.” 2018. Web. 04 Mar 2021.

Vancouver:

Ihesiulor O. Wear reduction in modular taper-trunnion hip prostheses using straight cylindrical stems. [Internet] [Doctoral dissertation]. University of New South Wales; 2018. [cited 2021 Mar 04]. Available from: http://handle.unsw.edu.au/1959.4/60348 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51887/SOURCE2?view=true.

Council of Science Editors:

Ihesiulor O. Wear reduction in modular taper-trunnion hip prostheses using straight cylindrical stems. [Doctoral Dissertation]. University of New South Wales; 2018. Available from: http://handle.unsw.edu.au/1959.4/60348 ; https://unsworks.unsw.edu.au/fapi/datastream/unsworks:51887/SOURCE2?view=true


University of Illinois – Urbana-Champaign

4. Karpuzcu, Rahmet. Novel many-core architectures for energy-efficiency.

Degree: PhD, 1200, 2012, University of Illinois – Urbana-Champaign

 Ideal CMOS device scaling relies on scaling voltages down with lithographic dimensions at every technology generation. This gives rise to faster circuits due to higher… (more)

Subjects/Keywords: Power constraints; Dark silicon; Near-threshold voltage; Many-core architectures; Process variations; Static random-access memory (SRAM) fault models; Wear-Out

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APA (6th Edition):

Karpuzcu, R. (2012). Novel many-core architectures for energy-efficiency. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/34560

Chicago Manual of Style (16th Edition):

Karpuzcu, Rahmet. “Novel many-core architectures for energy-efficiency.” 2012. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 04, 2021. http://hdl.handle.net/2142/34560.

MLA Handbook (7th Edition):

Karpuzcu, Rahmet. “Novel many-core architectures for energy-efficiency.” 2012. Web. 04 Mar 2021.

Vancouver:

Karpuzcu R. Novel many-core architectures for energy-efficiency. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2012. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/2142/34560.

Council of Science Editors:

Karpuzcu R. Novel many-core architectures for energy-efficiency. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2012. Available from: http://hdl.handle.net/2142/34560


Virginia Tech

5. Adler, W. Alexander III. Testing and Understanding Screwdriver Bit Wear.

Degree: MS, Mechanical Engineering, 1998, Virginia Tech

 This thesis is focused on gaining a better knowledge of how to design and test Phillips screwdriver bits. Wear is the primary concern in applications… (more)

Subjects/Keywords: Phillips; Screwdriver Bit; Cam-Out; Surface Contact; Tool Wear; User Emulation

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APA (6th Edition):

Adler, W. A. I. (1998). Testing and Understanding Screwdriver Bit Wear. (Masters Thesis). Virginia Tech. Retrieved from http://hdl.handle.net/10919/36701

Chicago Manual of Style (16th Edition):

Adler, W Alexander III. “Testing and Understanding Screwdriver Bit Wear.” 1998. Masters Thesis, Virginia Tech. Accessed March 04, 2021. http://hdl.handle.net/10919/36701.

MLA Handbook (7th Edition):

Adler, W Alexander III. “Testing and Understanding Screwdriver Bit Wear.” 1998. Web. 04 Mar 2021.

Vancouver:

Adler WAI. Testing and Understanding Screwdriver Bit Wear. [Internet] [Masters thesis]. Virginia Tech; 1998. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/10919/36701.

Council of Science Editors:

Adler WAI. Testing and Understanding Screwdriver Bit Wear. [Masters Thesis]. Virginia Tech; 1998. Available from: http://hdl.handle.net/10919/36701

6. Singh, Prashant. On-chip NBTI and Gate-Oxide-Degradation Sensing and Dynamic Management in VLSI Circuits.

Degree: PhD, Electrical Engineering, 2011, University of Michigan

 The VLSI industry has achieved advancement in technology by continuous process scaling which has resulted in large scale integration. However, scaling also poses new reliability… (more)

Subjects/Keywords: VLSI Circuit Reliability; Bias Temerature Instability (BTI); Gate-oxide Wear-out; Sensor; Dynamic Reliability Management; In Situ Sensing; Electrical Engineering; Engineering

…interconnects which exacerbates transistor degradation mechanism such as gate-oxide wear-out, Hot… …work we focused only on BTI and gate-oxide wear-out degradation mechanism. Other degradation… …degradation sensing techniques. In Chapter 5 we propose a method to do in situ gate-oxide wear-out… …detection which is capable of sensing the onset of gate-oxide wear-out of the actual core… …existing reliability management techniques to find out the most suitable of those for advanced… 

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APA (6th Edition):

Singh, P. (2011). On-chip NBTI and Gate-Oxide-Degradation Sensing and Dynamic Management in VLSI Circuits. (Doctoral Dissertation). University of Michigan. Retrieved from http://hdl.handle.net/2027.42/86281

Chicago Manual of Style (16th Edition):

Singh, Prashant. “On-chip NBTI and Gate-Oxide-Degradation Sensing and Dynamic Management in VLSI Circuits.” 2011. Doctoral Dissertation, University of Michigan. Accessed March 04, 2021. http://hdl.handle.net/2027.42/86281.

MLA Handbook (7th Edition):

Singh, Prashant. “On-chip NBTI and Gate-Oxide-Degradation Sensing and Dynamic Management in VLSI Circuits.” 2011. Web. 04 Mar 2021.

Vancouver:

Singh P. On-chip NBTI and Gate-Oxide-Degradation Sensing and Dynamic Management in VLSI Circuits. [Internet] [Doctoral dissertation]. University of Michigan; 2011. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/2027.42/86281.

Council of Science Editors:

Singh P. On-chip NBTI and Gate-Oxide-Degradation Sensing and Dynamic Management in VLSI Circuits. [Doctoral Dissertation]. University of Michigan; 2011. Available from: http://hdl.handle.net/2027.42/86281

7. Campbell, Keith A. Low-cost error detection through high-level synthesis.

Degree: MS, Electrical & Computer Engineering, 2015, University of Illinois – Urbana-Champaign

 System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling and complexity has resulted in a… (more)

Subjects/Keywords: High-level synthesis; Automation; error detection; scheduling; binding; compiler transformation; compiler optimization; pipelining; modulo arithmetic; logic optimization; state machine; datapath, control logic; shadow logic; low cost; high performance; electrical bugs; Aliasing; stuck-at faults; soft errors; timing errors; checkpointing; rollback; recovery; post-silicon validation; Accelerators; system on a chip; signature generation; execution signatures; execution hashing; logic bugs; nondeterministic bugs; masked errors; circuit reliability; hot spots; wear out; silent data corruption; observability; detection latency; mixed datapath; diversity; checkpoint corruption; error injection; error removal; Quick Error Detection (QED); Hybrid Quick Error Detection (H-QED); hybrid hardware/software; execution tracing; address conversion; undefined behavior; High-Level Synthesis (HLS) engine bugs; detection coverage

…transistors to wear out, resulting in longer gate propagation delays leading to timing errors after… …Wear Out Figure 1.1: The hazards inherent in designing custom hardware 3 For improved… …Wear Out Like mechanical systems, MOSFETs can wear out from prolonged, heavy use. High-energy… …at either a 0 or a 1. The more dramatic wear-out problems that cause permanent defects can… …3.1.2, such operations are optimized out by our high-level synthesis optimization passes. With… 

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APA (6th Edition):

Campbell, K. A. (2015). Low-cost error detection through high-level synthesis. (Thesis). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/89068

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Chicago Manual of Style (16th Edition):

Campbell, Keith A. “Low-cost error detection through high-level synthesis.” 2015. Thesis, University of Illinois – Urbana-Champaign. Accessed March 04, 2021. http://hdl.handle.net/2142/89068.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

MLA Handbook (7th Edition):

Campbell, Keith A. “Low-cost error detection through high-level synthesis.” 2015. Web. 04 Mar 2021.

Vancouver:

Campbell KA. Low-cost error detection through high-level synthesis. [Internet] [Thesis]. University of Illinois – Urbana-Champaign; 2015. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/2142/89068.

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

Council of Science Editors:

Campbell KA. Low-cost error detection through high-level synthesis. [Thesis]. University of Illinois – Urbana-Champaign; 2015. Available from: http://hdl.handle.net/2142/89068

Note: this citation may be lacking information needed for this citation format:
Not specified: Masters Thesis or Doctoral Dissertation

8. Campbell, Keith A. Robust and reliable hardware accelerator design through high-level synthesis.

Degree: PhD, Electrical & Computer Engr, 2017, University of Illinois – Urbana-Champaign

 System-on-chip design is becoming increasingly complex as technology scaling enables more and more functionality on a chip. This scaling-driven complexity has resulted in a variety… (more)

Subjects/Keywords: High-level synthesis (HLS); Automation; Error detection; Scheduling; Binding; Compiler transformation; Compiler optimization; Pipelining; Modulo arithmetic; Modulo-3; Logic optimization; State machine; Datapath; Control logic; Shadow datapath; Modulo datapath; Low cost; High performance; Electrical bug; Aliasing; Stuck-at fault; Soft error; Timing error; Checkpointing; Rollback; Recovery; Pre-silicon validation; Post-silicon validation; Pre-silicon debug; Post-silicon debug; Accelerator; System on a chip; Signature generation; Execution signature; Execution hash; Logic bug; Nondeterministic bug; Masked error; Circuit reliability; Hot spot; Wear out; Silent data corruption; Observability; Detection latency; Mixed datapath; Diversity; Checkpoint corruption; Error injection; Error removal; Quick Error Detection (QED); Hybrid Quick Error Detection (H-QED); Instrumentation; Hybrid co-simulation; Hardware/software; Integration testing; Hybrid tracing; Hybrid hashing; Source-code localization; Software debugging tool; Valgrind; Clang sanitizer; Clang static analyzer; Cppcheck; Root cause analysis; Execution tracing; Realtime error detection; Simulation trigger; Nonintrusive; Address conversion; Undefined behavior; High-level synthesis (HLS) bug; Detection coverage; Gate-level architecture; Mersenne modulus; Full adder; Half adder; Quarter adder; Wraparound; Modulo reducer; Modulo adder; Modulo multiplier; Modulo comparator; Cross-layer; Algorithm; Instruction; Architecture; Logic synthesis; Physical design; Algorithm-based fault tolerance (ABFT); Error detection by duplicated instructions (EDDI); Parity; Flip-flop hardening; Layout design through error-aware transistor positioning dual interlocked storage cell (LEAP-DICE); Cost-effective; Place-and-route; Field programmable gate array (FPGA) emulation; Application specific integrated circuit (ASIC); Field programmable gate array (FPGA); Energy; Area; Latency

…cause smaller transistors to wear out, resulting in longer gate propagation delays leading to… …Silicon Testing Soft Errors Permanent Faults Hardware Deployment Wear Out Figure 1.1: The… …unpredictable in nature. 1.1.5 Wear Out Like mechanical systems, MOSFETs can wear out from prolonged… …gate outputs being stuck at either a 0 or a 1. The more dramatic wear-out problems that cause… 

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APA (6th Edition):

Campbell, K. A. (2017). Robust and reliable hardware accelerator design through high-level synthesis. (Doctoral Dissertation). University of Illinois – Urbana-Champaign. Retrieved from http://hdl.handle.net/2142/99294

Chicago Manual of Style (16th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Doctoral Dissertation, University of Illinois – Urbana-Champaign. Accessed March 04, 2021. http://hdl.handle.net/2142/99294.

MLA Handbook (7th Edition):

Campbell, Keith A. “Robust and reliable hardware accelerator design through high-level synthesis.” 2017. Web. 04 Mar 2021.

Vancouver:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Internet] [Doctoral dissertation]. University of Illinois – Urbana-Champaign; 2017. [cited 2021 Mar 04]. Available from: http://hdl.handle.net/2142/99294.

Council of Science Editors:

Campbell KA. Robust and reliable hardware accelerator design through high-level synthesis. [Doctoral Dissertation]. University of Illinois – Urbana-Champaign; 2017. Available from: http://hdl.handle.net/2142/99294

.